VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 87477

Last change on this file since 87477 was 87477, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 PDM IOMMU code de-duplication and cleanup.
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  • Property svn:keywords set to Id Revision
File size: 68.9 KB
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1/* $Id: PDMInternal.h 87477 2021-01-29 11:43:09Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
19#define VMM_INCLUDED_SRC_include_PDMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/types.h>
25#include <VBox/param.h>
26#include <VBox/vmm/cfgm.h>
27#include <VBox/vmm/stam.h>
28#include <VBox/vusb.h>
29#include <VBox/vmm/iom.h>
30#include <VBox/vmm/pdmasynccompletion.h>
31#ifdef VBOX_WITH_NETSHAPER
32# include <VBox/vmm/pdmnetshaper.h>
33#endif
34#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
35# include <VBox/vmm/pdmasynccompletion.h>
36#endif
37#include <VBox/vmm/pdmblkcache.h>
38#include <VBox/vmm/pdmcommon.h>
39#include <VBox/vmm/pdmtask.h>
40#include <VBox/sup.h>
41#include <VBox/msi.h>
42#include <iprt/assert.h>
43#include <iprt/critsect.h>
44#ifdef IN_RING3
45# include <iprt/thread.h>
46#endif
47
48RT_C_DECLS_BEGIN
49
50
51/** @defgroup grp_pdm_int Internal
52 * @ingroup grp_pdm
53 * @internal
54 * @{
55 */
56
57/** @def PDM_WITH_R3R0_CRIT_SECT
58 * Enables or disabled ring-3/ring-0 critical sections. */
59#if defined(DOXYGEN_RUNNING) || 1
60# define PDM_WITH_R3R0_CRIT_SECT
61#endif
62
63/** @def PDMCRITSECT_STRICT
64 * Enables/disables PDM critsect strictness like deadlock detection. */
65#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
66 || defined(DOXYGEN_RUNNING)
67# define PDMCRITSECT_STRICT
68#endif
69
70/** @def PDMCRITSECT_STRICT
71 * Enables/disables PDM read/write critsect strictness like deadlock
72 * detection. */
73#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
74 || defined(DOXYGEN_RUNNING)
75# define PDMCRITSECTRW_STRICT
76#endif
77
78/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
79#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
80/** The maximum device instance (total) size, ring-3 only devices. */
81#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
82/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
83#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK PAGE_SIZE
84
85
86
87/*******************************************************************************
88* Structures and Typedefs *
89*******************************************************************************/
90
91/** Pointer to a PDM Device. */
92typedef struct PDMDEV *PPDMDEV;
93/** Pointer to a pointer to a PDM Device. */
94typedef PPDMDEV *PPPDMDEV;
95
96/** Pointer to a PDM USB Device. */
97typedef struct PDMUSB *PPDMUSB;
98/** Pointer to a pointer to a PDM USB Device. */
99typedef PPDMUSB *PPPDMUSB;
100
101/** Pointer to a PDM Driver. */
102typedef struct PDMDRV *PPDMDRV;
103/** Pointer to a pointer to a PDM Driver. */
104typedef PPDMDRV *PPPDMDRV;
105
106/** Pointer to a PDM Logical Unit. */
107typedef struct PDMLUN *PPDMLUN;
108/** Pointer to a pointer to a PDM Logical Unit. */
109typedef PPDMLUN *PPPDMLUN;
110
111/** Pointer to a DMAC instance. */
112typedef struct PDMDMAC *PPDMDMAC;
113/** Pointer to a RTC instance. */
114typedef struct PDMRTC *PPDMRTC;
115
116/** Pointer to an USB HUB registration record. */
117typedef struct PDMUSBHUB *PPDMUSBHUB;
118
119/**
120 * Supported asynchronous completion endpoint classes.
121 */
122typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
123{
124 /** File class. */
125 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
126 /** Number of supported classes. */
127 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
128 /** 32bit hack. */
129 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
130} PDMASYNCCOMPLETIONEPCLASSTYPE;
131
132
133/**
134 * MMIO/IO port registration tracking structure for DBGF tracing.
135 */
136typedef struct PDMDEVINSDBGFTRACK
137{
138 /** Flag whether this tracks a IO port or MMIO registration. */
139 bool fMmio;
140 /** Opaque user data passed during registration. */
141 void *pvUser;
142 /** Type dependent data. */
143 union
144 {
145 /** I/O port registration. */
146 struct
147 {
148 /** IOM I/O port handle. */
149 IOMIOPORTHANDLE hIoPorts;
150 /** Original OUT handler of the device. */
151 PFNIOMIOPORTNEWOUT pfnOut;
152 /** Original IN handler of the device. */
153 PFNIOMIOPORTNEWIN pfnIn;
154 /** Original string OUT handler of the device. */
155 PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
156 /** Original string IN handler of the device. */
157 PFNIOMIOPORTNEWINSTRING pfnInStr;
158 } IoPort;
159 /** MMIO registration. */
160 struct
161 {
162 /** IOM MMIO region handle. */
163 IOMMMIOHANDLE hMmioRegion;
164 /** Original MMIO write handler of the device. */
165 PFNIOMMMIONEWWRITE pfnWrite;
166 /** Original MMIO read handler of the device. */
167 PFNIOMMMIONEWREAD pfnRead;
168 /** Original MMIO fill handler of the device. */
169 PFNIOMMMIONEWFILL pfnFill;
170 } Mmio;
171 } u;
172} PDMDEVINSDBGFTRACK;
173/** Pointer to a MMIO/IO port registration tracking structure. */
174typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
175/** Pointer to a const MMIO/IO port registration tracking structure. */
176typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
177
178
179/**
180 * Private device instance data, ring-3.
181 */
182typedef struct PDMDEVINSINTR3
183{
184 /** Pointer to the next instance.
185 * (Head is pointed to by PDM::pDevInstances.) */
186 R3PTRTYPE(PPDMDEVINS) pNextR3;
187 /** Pointer to the next per device instance.
188 * (Head is pointed to by PDMDEV::pInstances.) */
189 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
190 /** Pointer to device structure. */
191 R3PTRTYPE(PPDMDEV) pDevR3;
192 /** Pointer to the list of logical units associated with the device. (FIFO) */
193 R3PTRTYPE(PPDMLUN) pLunsR3;
194 /** Pointer to the asynchronous notification callback set while in
195 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
196 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
197 /** Configuration handle to the instance node. */
198 R3PTRTYPE(PCFGMNODE) pCfgHandle;
199
200 /** R3 pointer to the VM this instance was created for. */
201 PVMR3 pVMR3;
202 /** DBGF trace event source handle if tracing is configured. */
203 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
204 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
205 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
206 /** Index of the next entry to use for tracking. */
207 uint32_t idxDbgfTraceTrackNext;
208 /** Maximum number of records fitting into the single page. */
209 uint32_t cDbgfTraceTrackMax;
210
211 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
212 uint32_t fIntFlags;
213 /** The last IRQ tag (for tracing it thru clearing). */
214 uint32_t uLastIrqTag;
215 /** The ring-0 device index (for making ring-0 calls). */
216 uint32_t idxR0Device;
217} PDMDEVINSINTR3;
218
219
220/**
221 * Private device instance data, ring-0.
222 */
223typedef struct PDMDEVINSINTR0
224{
225 /** Pointer to the VM this instance was created for. */
226 R0PTRTYPE(PGVM) pGVM;
227 /** Pointer to device structure. */
228 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
229 /** The ring-0 module reference. */
230 RTR0PTR hMod;
231 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
232 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
233 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
234 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
235 /** DBGF trace event source handle if tracing is configured. */
236 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
237 /** The device instance memory. */
238 RTR0MEMOBJ hMemObj;
239 /** The ring-3 mapping object. */
240 RTR0MEMOBJ hMapObj;
241 /** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
242 RTR0MEMOBJ hDbgfTraceObj;
243 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
244 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
245 /** Index of the next entry to use for tracking. */
246 uint32_t idxDbgfTraceTrackNext;
247 /** Maximum number of records fitting into the single page. */
248 uint32_t cDbgfTraceTrackMax;
249 /** Index into PDMR0PERVM::apDevInstances. */
250 uint32_t idxR0Device;
251} PDMDEVINSINTR0;
252
253
254/**
255 * Private device instance data, raw-mode
256 */
257typedef struct PDMDEVINSINTRC
258{
259 /** Pointer to the VM this instance was created for. */
260 RGPTRTYPE(PVM) pVMRC;
261} PDMDEVINSINTRC;
262
263
264/**
265 * Private device instance data.
266 */
267typedef struct PDMDEVINSINT
268{
269 /** Pointer to the next instance (HC Ptr).
270 * (Head is pointed to by PDM::pDevInstances.) */
271 R3PTRTYPE(PPDMDEVINS) pNextR3;
272 /** Pointer to the next per device instance (HC Ptr).
273 * (Head is pointed to by PDMDEV::pInstances.) */
274 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
275 /** Pointer to device structure - HC Ptr. */
276 R3PTRTYPE(PPDMDEV) pDevR3;
277 /** Pointer to the list of logical units associated with the device. (FIFO) */
278 R3PTRTYPE(PPDMLUN) pLunsR3;
279 /** Pointer to the asynchronous notification callback set while in
280 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
281 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
282 /** Configuration handle to the instance node. */
283 R3PTRTYPE(PCFGMNODE) pCfgHandle;
284
285 /** R3 pointer to the VM this instance was created for. */
286 PVMR3 pVMR3;
287
288 /** R0 pointer to the VM this instance was created for. */
289 R0PTRTYPE(PVMCC) pVMR0;
290
291 /** RC pointer to the VM this instance was created for. */
292 PVMRC pVMRC;
293
294 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
295 uint32_t fIntFlags;
296 /** The last IRQ tag (for tracing it thru clearing). */
297 uint32_t uLastIrqTag;
298} PDMDEVINSINT;
299
300/** @name PDMDEVINSINT::fIntFlags
301 * @{ */
302/** Used by pdmR3Load to mark device instances it found in the saved state. */
303#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
304/** Indicates that the device hasn't been powered on or resumed.
305 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
306 * to make sure each device gets exactly one notification for each of those
307 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
308 * a failure (already resumed/powered-on devices are suspended).
309 * PDMR3PowerOff resets this flag once before going through the devices to make sure
310 * every device gets the power off notification even if it was suspended before with
311 * PDMR3Suspend.
312 */
313#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
314/** Indicates that the device has been reset already. Used by PDMR3Reset. */
315#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
316#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
317#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
318/** Set if we've called the ring-0 constructor. */
319#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
320/** Set if using non-default critical section. */
321#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
322/** @} */
323
324
325/**
326 * Private USB device instance data.
327 */
328typedef struct PDMUSBINSINT
329{
330 /** The UUID of this instance. */
331 RTUUID Uuid;
332 /** Pointer to the next instance.
333 * (Head is pointed to by PDM::pUsbInstances.) */
334 R3PTRTYPE(PPDMUSBINS) pNext;
335 /** Pointer to the next per USB device instance.
336 * (Head is pointed to by PDMUSB::pInstances.) */
337 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
338
339 /** Pointer to device structure. */
340 R3PTRTYPE(PPDMUSB) pUsbDev;
341
342 /** Pointer to the VM this instance was created for. */
343 PVMR3 pVM;
344 /** Pointer to the list of logical units associated with the device. (FIFO) */
345 R3PTRTYPE(PPDMLUN) pLuns;
346 /** The per instance device configuration. */
347 R3PTRTYPE(PCFGMNODE) pCfg;
348 /** Same as pCfg if the configuration should be deleted when detaching the device. */
349 R3PTRTYPE(PCFGMNODE) pCfgDelete;
350 /** The global device configuration. */
351 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
352
353 /** Pointer to the USB hub this device is attached to.
354 * This is NULL if the device isn't connected to any HUB. */
355 R3PTRTYPE(PPDMUSBHUB) pHub;
356 /** The port number that we're connected to. */
357 uint32_t iPort;
358 /** Indicates that the USB device hasn't been powered on or resumed.
359 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
360 bool fVMSuspended;
361 /** Indicates that the USB device has been reset. */
362 bool fVMReset;
363 /** Pointer to the asynchronous notification callback set while in
364 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
365 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
366} PDMUSBINSINT;
367
368
369/**
370 * Private driver instance data.
371 */
372typedef struct PDMDRVINSINT
373{
374 /** Pointer to the driver instance above.
375 * This is NULL for the topmost drive. */
376 R3PTRTYPE(PPDMDRVINS) pUp;
377 /** Pointer to the driver instance below.
378 * This is NULL for the bottommost driver. */
379 R3PTRTYPE(PPDMDRVINS) pDown;
380 /** Pointer to the logical unit this driver chained on. */
381 R3PTRTYPE(PPDMLUN) pLun;
382 /** Pointer to driver structure from which this was instantiated. */
383 R3PTRTYPE(PPDMDRV) pDrv;
384 /** Pointer to the VM this instance was created for, ring-3 context. */
385 PVMR3 pVMR3;
386 /** Pointer to the VM this instance was created for, ring-0 context. */
387 R0PTRTYPE(PVMCC) pVMR0;
388 /** Pointer to the VM this instance was created for, raw-mode context. */
389 PVMRC pVMRC;
390 /** Flag indicating that the driver is being detached and destroyed.
391 * (Helps detect potential recursive detaching.) */
392 bool fDetaching;
393 /** Indicates that the driver hasn't been powered on or resumed.
394 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
395 bool fVMSuspended;
396 /** Indicates that the driver has been reset already. */
397 bool fVMReset;
398 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
399 bool fHyperHeap;
400 /** Pointer to the asynchronous notification callback set while in
401 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
402 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
403 /** Configuration handle to the instance node. */
404 R3PTRTYPE(PCFGMNODE) pCfgHandle;
405 /** Pointer to the ring-0 request handler function. */
406 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
407} PDMDRVINSINT;
408
409
410/**
411 * Private critical section data.
412 */
413typedef struct PDMCRITSECTINT
414{
415 /** The critical section core which is shared with IPRT.
416 * @note The semaphore is a SUPSEMEVENT. */
417 RTCRITSECT Core;
418 /** Pointer to the next critical section.
419 * This chain is used for relocating pVMRC and device cleanup. */
420 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
421 /** Owner identifier.
422 * This is pDevIns if the owner is a device. Similarly for a driver or service.
423 * PDMR3CritSectInit() sets this to point to the critsect itself. */
424 RTR3PTR pvKey;
425 /** Pointer to the VM - R3Ptr. */
426 PVMR3 pVMR3;
427 /** Pointer to the VM - R0Ptr. */
428 R0PTRTYPE(PVMCC) pVMR0;
429 /** Pointer to the VM - GCPtr. */
430 PVMRC pVMRC;
431 /** Set if this critical section is the automatically created default
432 * section of a device. */
433 bool fAutomaticDefaultCritsect;
434 /** Set if the critical section is used by a timer or similar.
435 * See PDMR3DevGetCritSect. */
436 bool fUsedByTimerOrSimilar;
437 /** Alignment padding. */
438 bool afPadding[2];
439 /** Support driver event semaphore that is scheduled to be signaled upon leaving
440 * the critical section. This is only for Ring-3 and Ring-0. */
441 SUPSEMEVENT hEventToSignal;
442 /** The lock name. */
443 R3PTRTYPE(const char *) pszName;
444 /** R0/RC lock contention. */
445 STAMCOUNTER StatContentionRZLock;
446 /** R0/RC unlock contention. */
447 STAMCOUNTER StatContentionRZUnlock;
448 /** R3 lock contention. */
449 STAMCOUNTER StatContentionR3;
450 /** Profiling the time the section is locked. */
451 STAMPROFILEADV StatLocked;
452} PDMCRITSECTINT;
453AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
454/** Pointer to private critical section data. */
455typedef PDMCRITSECTINT *PPDMCRITSECTINT;
456
457/** Indicates that the critical section is queued for unlock.
458 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
459#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
460
461
462/**
463 * Private critical section data.
464 */
465typedef struct PDMCRITSECTRWINT
466{
467 /** The read/write critical section core which is shared with IPRT.
468 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
469 RTCRITSECTRW Core;
470
471 /** Pointer to the next critical section.
472 * This chain is used for relocating pVMRC and device cleanup. */
473 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
474 /** Owner identifier.
475 * This is pDevIns if the owner is a device. Similarly for a driver or service.
476 * PDMR3CritSectInit() sets this to point to the critsect itself. */
477 RTR3PTR pvKey;
478 /** Pointer to the VM - R3Ptr. */
479 PVMR3 pVMR3;
480 /** Pointer to the VM - R0Ptr. */
481 R0PTRTYPE(PVMCC) pVMR0;
482 /** Pointer to the VM - GCPtr. */
483 PVMRC pVMRC;
484#if HC_ARCH_BITS == 64
485 /** Alignment padding. */
486 RTRCPTR RCPtrPadding;
487#endif
488 /** The lock name. */
489 R3PTRTYPE(const char *) pszName;
490 /** R0/RC write lock contention. */
491 STAMCOUNTER StatContentionRZEnterExcl;
492 /** R0/RC write unlock contention. */
493 STAMCOUNTER StatContentionRZLeaveExcl;
494 /** R0/RC read lock contention. */
495 STAMCOUNTER StatContentionRZEnterShared;
496 /** R0/RC read unlock contention. */
497 STAMCOUNTER StatContentionRZLeaveShared;
498 /** R0/RC writes. */
499 STAMCOUNTER StatRZEnterExcl;
500 /** R0/RC reads. */
501 STAMCOUNTER StatRZEnterShared;
502 /** R3 write lock contention. */
503 STAMCOUNTER StatContentionR3EnterExcl;
504 /** R3 read lock contention. */
505 STAMCOUNTER StatContentionR3EnterShared;
506 /** R3 writes. */
507 STAMCOUNTER StatR3EnterExcl;
508 /** R3 reads. */
509 STAMCOUNTER StatR3EnterShared;
510 /** Profiling the time the section is write locked. */
511 STAMPROFILEADV StatWriteLocked;
512} PDMCRITSECTRWINT;
513AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
514AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u64State, 8);
515/** Pointer to private critical section data. */
516typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
517
518
519
520/**
521 * The usual device/driver/internal/external stuff.
522 */
523typedef enum
524{
525 /** The usual invalid entry. */
526 PDMTHREADTYPE_INVALID = 0,
527 /** Device type. */
528 PDMTHREADTYPE_DEVICE,
529 /** USB Device type. */
530 PDMTHREADTYPE_USB,
531 /** Driver type. */
532 PDMTHREADTYPE_DRIVER,
533 /** Internal type. */
534 PDMTHREADTYPE_INTERNAL,
535 /** External type. */
536 PDMTHREADTYPE_EXTERNAL,
537 /** The usual 32-bit hack. */
538 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
539} PDMTHREADTYPE;
540
541
542/**
543 * The internal structure for the thread.
544 */
545typedef struct PDMTHREADINT
546{
547 /** The VM pointer. */
548 PVMR3 pVM;
549 /** The event semaphore the thread blocks on when not running. */
550 RTSEMEVENTMULTI BlockEvent;
551 /** The event semaphore the thread sleeps on while running. */
552 RTSEMEVENTMULTI SleepEvent;
553 /** Pointer to the next thread. */
554 R3PTRTYPE(struct PDMTHREAD *) pNext;
555 /** The thread type. */
556 PDMTHREADTYPE enmType;
557} PDMTHREADINT;
558
559
560
561/* Must be included after PDMDEVINSINT is defined. */
562#define PDMDEVINSINT_DECLARED
563#define PDMUSBINSINT_DECLARED
564#define PDMDRVINSINT_DECLARED
565#define PDMCRITSECTINT_DECLARED
566#define PDMCRITSECTRWINT_DECLARED
567#define PDMTHREADINT_DECLARED
568#ifdef ___VBox_pdm_h
569# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
570#endif
571RT_C_DECLS_END
572#include <VBox/vmm/pdm.h>
573RT_C_DECLS_BEGIN
574
575/**
576 * PDM Logical Unit.
577 *
578 * This typically the representation of a physical port on a
579 * device, like for instance the PS/2 keyboard port on the
580 * keyboard controller device. The LUNs are chained on the
581 * device they belong to (PDMDEVINSINT::pLunsR3).
582 */
583typedef struct PDMLUN
584{
585 /** The LUN - The Logical Unit Number. */
586 RTUINT iLun;
587 /** Pointer to the next LUN. */
588 PPDMLUN pNext;
589 /** Pointer to the top driver in the driver chain. */
590 PPDMDRVINS pTop;
591 /** Pointer to the bottom driver in the driver chain. */
592 PPDMDRVINS pBottom;
593 /** Pointer to the device instance which the LUN belongs to.
594 * Either this is set or pUsbIns is set. Both is never set at the same time. */
595 PPDMDEVINS pDevIns;
596 /** Pointer to the USB device instance which the LUN belongs to. */
597 PPDMUSBINS pUsbIns;
598 /** Pointer to the device base interface. */
599 PPDMIBASE pBase;
600 /** Description of this LUN. */
601 const char *pszDesc;
602} PDMLUN;
603
604
605/**
606 * PDM Device, ring-3.
607 */
608typedef struct PDMDEV
609{
610 /** Pointer to the next device (R3 Ptr). */
611 R3PTRTYPE(PPDMDEV) pNext;
612 /** Device name length. (search optimization) */
613 uint32_t cchName;
614 /** Registration structure. */
615 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
616 /** Number of instances. */
617 uint32_t cInstances;
618 /** Pointer to chain of instances (R3 Ptr). */
619 PPDMDEVINSR3 pInstances;
620 /** The search path for raw-mode context modules (';' as separator). */
621 char *pszRCSearchPath;
622 /** The search path for ring-0 context modules (';' as separator). */
623 char *pszR0SearchPath;
624} PDMDEV;
625
626
627#if 0
628/**
629 * PDM Device, ring-0.
630 */
631typedef struct PDMDEVR0
632{
633 /** Pointer to the next device. */
634 R0PTRTYPE(PPDMDEVR0) pNext;
635 /** Device name length. (search optimization) */
636 uint32_t cchName;
637 /** Registration structure. */
638 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
639 /** Number of instances. */
640 uint32_t cInstances;
641 /** Pointer to chain of instances. */
642 PPDMDEVINSR0 pInstances;
643} PDMDEVR0;
644#endif
645
646
647/**
648 * PDM USB Device.
649 */
650typedef struct PDMUSB
651{
652 /** Pointer to the next device (R3 Ptr). */
653 R3PTRTYPE(PPDMUSB) pNext;
654 /** Device name length. (search optimization) */
655 RTUINT cchName;
656 /** Registration structure. */
657 R3PTRTYPE(const struct PDMUSBREG *) pReg;
658 /** Next instance number. */
659 uint32_t iNextInstance;
660 /** Pointer to chain of instances (R3 Ptr). */
661 R3PTRTYPE(PPDMUSBINS) pInstances;
662} PDMUSB;
663
664
665/**
666 * PDM Driver.
667 */
668typedef struct PDMDRV
669{
670 /** Pointer to the next device. */
671 PPDMDRV pNext;
672 /** Registration structure. */
673 const struct PDMDRVREG * pReg;
674 /** Current number of instances. */
675 uint32_t cInstances;
676 /** The next instance number. */
677 uint32_t iNextInstance;
678 /** The search path for raw-mode context modules (';' as separator). */
679 char *pszRCSearchPath;
680 /** The search path for ring-0 context modules (';' as separator). */
681 char *pszR0SearchPath;
682} PDMDRV;
683
684
685/**
686 * PDM registered IOMMU device.
687 */
688typedef struct PDMIOMMU
689{
690 /** IOMMU index. */
691 uint32_t idxIommu;
692 uint32_t uPadding0; /**< Alignment padding.*/
693
694 /** Pointer to the IOMMU device instance - R3. */
695 PPDMDEVINSR3 pDevInsR3;
696 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
697 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbAccess,
698 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
699 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
700 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
701 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
702 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
703 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
704} PDMIOMMU;
705/** Pointer to a PDM IOMMU instance. */
706typedef PDMIOMMU *PPDMIOMMU;
707/** Pointer to a const PDM IOMMU instance. */
708typedef const PDMIOMMU *PCPDMIOMMU;
709
710
711/**
712 * Ring-0 PDM IOMMU instance data.
713 */
714typedef struct PDMIOMMUR0
715{
716 /** IOMMU index. */
717 uint32_t idxIommu;
718 uint32_t uPadding0; /**< Alignment padding.*/
719
720 /** Pointer to IOMMU device instance. */
721 PPDMDEVINSR0 pDevInsR0;
722 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
723 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbAccess,
724 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
725 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
726 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
727 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
728 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
729 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
730} PDMIOMMUR0;
731/** Pointer to a ring-0 IOMMU data. */
732typedef PDMIOMMUR0 *PPDMIOMMUR0;
733/** Pointer to a const ring-0 IOMMU data. */
734typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
735
736
737/**
738 * PDM registered PIC device.
739 */
740typedef struct PDMPIC
741{
742 /** Pointer to the PIC device instance - R3. */
743 PPDMDEVINSR3 pDevInsR3;
744 /** @copydoc PDMPICREG::pfnSetIrq */
745 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
746 /** @copydoc PDMPICREG::pfnGetInterrupt */
747 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
748
749 /** Pointer to the PIC device instance - R0. */
750 PPDMDEVINSR0 pDevInsR0;
751 /** @copydoc PDMPICREG::pfnSetIrq */
752 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
753 /** @copydoc PDMPICREG::pfnGetInterrupt */
754 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
755
756 /** Pointer to the PIC device instance - RC. */
757 PPDMDEVINSRC pDevInsRC;
758 /** @copydoc PDMPICREG::pfnSetIrq */
759 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
760 /** @copydoc PDMPICREG::pfnGetInterrupt */
761 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
762 /** Alignment padding. */
763 RTRCPTR RCPtrPadding;
764} PDMPIC;
765
766
767/**
768 * PDM registered APIC device.
769 */
770typedef struct PDMAPIC
771{
772 /** Pointer to the APIC device instance - R3 Ptr. */
773 PPDMDEVINSR3 pDevInsR3;
774 /** Pointer to the APIC device instance - R0 Ptr. */
775 PPDMDEVINSR0 pDevInsR0;
776 /** Pointer to the APIC device instance - RC Ptr. */
777 PPDMDEVINSRC pDevInsRC;
778 uint8_t Alignment[4];
779} PDMAPIC;
780
781
782/**
783 * PDM registered I/O APIC device.
784 */
785typedef struct PDMIOAPIC
786{
787 /** Pointer to the APIC device instance - R3 Ptr. */
788 PPDMDEVINSR3 pDevInsR3;
789 /** @copydoc PDMIOAPICREG::pfnSetIrq */
790 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
791 /** @copydoc PDMIOAPICREG::pfnSendMsi */
792 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
793 /** @copydoc PDMIOAPICREG::pfnSetEoi */
794 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
795
796 /** Pointer to the PIC device instance - R0. */
797 PPDMDEVINSR0 pDevInsR0;
798 /** @copydoc PDMIOAPICREG::pfnSetIrq */
799 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
800 /** @copydoc PDMIOAPICREG::pfnSendMsi */
801 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
802 /** @copydoc PDMIOAPICREG::pfnSetEoi */
803 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
804
805 /** Pointer to the APIC device instance - RC Ptr. */
806 PPDMDEVINSRC pDevInsRC;
807 /** @copydoc PDMIOAPICREG::pfnSetIrq */
808 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
809 /** @copydoc PDMIOAPICREG::pfnSendMsi */
810 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
811 /** @copydoc PDMIOAPICREG::pfnSendMsi */
812 DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
813} PDMIOAPIC;
814
815/** Maximum number of PCI busses for a VM. */
816#define PDM_PCI_BUSSES_MAX 8
817/** Maximum number of IOMMUs (at most one per PCI bus). */
818#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
819
820
821#ifdef IN_RING3
822/**
823 * PDM registered firmware device.
824 */
825typedef struct PDMFW
826{
827 /** Pointer to the firmware device instance. */
828 PPDMDEVINSR3 pDevIns;
829 /** Copy of the registration structure. */
830 PDMFWREG Reg;
831} PDMFW;
832/** Pointer to a firmware instance. */
833typedef PDMFW *PPDMFW;
834#endif
835
836
837/**
838 * PDM PCI bus instance.
839 */
840typedef struct PDMPCIBUS
841{
842 /** PCI bus number. */
843 uint32_t iBus;
844 uint32_t uPadding0; /**< Alignment padding.*/
845
846 /** Pointer to PCI bus device instance. */
847 PPDMDEVINSR3 pDevInsR3;
848 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
849 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
850
851 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
852 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
853 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
854 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
855 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
856 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
857 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
858 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
859 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
860 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
861 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
862 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
863 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
864 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
865 uint32_t uAddress, unsigned cb, uint32_t u32Value));
866 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
867 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
868 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
869} PDMPCIBUS;
870/** Pointer to a PDM PCI Bus instance. */
871typedef PDMPCIBUS *PPDMPCIBUS;
872/** Pointer to a const PDM PCI Bus instance. */
873typedef const PDMPCIBUS *PCPDMPCIBUS;
874
875
876/**
877 * Ring-0 PDM PCI bus instance data.
878 */
879typedef struct PDMPCIBUSR0
880{
881 /** PCI bus number. */
882 uint32_t iBus;
883 uint32_t uPadding0; /**< Alignment padding.*/
884 /** Pointer to PCI bus device instance. */
885 PPDMDEVINSR0 pDevInsR0;
886 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
887 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
888} PDMPCIBUSR0;
889/** Pointer to the ring-0 PCI bus data. */
890typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
891/** Pointer to the const ring-0 PCI bus data. */
892typedef const PDMPCIBUSR0 *PCPDMPCIBUSR0;
893
894
895#ifdef IN_RING3
896/**
897 * PDM registered DMAC (DMA Controller) device.
898 */
899typedef struct PDMDMAC
900{
901 /** Pointer to the DMAC device instance. */
902 PPDMDEVINSR3 pDevIns;
903 /** Copy of the registration structure. */
904 PDMDMACREG Reg;
905} PDMDMAC;
906
907
908/**
909 * PDM registered RTC (Real Time Clock) device.
910 */
911typedef struct PDMRTC
912{
913 /** Pointer to the RTC device instance. */
914 PPDMDEVINSR3 pDevIns;
915 /** Copy of the registration structure. */
916 PDMRTCREG Reg;
917} PDMRTC;
918
919#endif /* IN_RING3 */
920
921/**
922 * Module type.
923 */
924typedef enum PDMMODTYPE
925{
926 /** Raw-mode (RC) context module. */
927 PDMMOD_TYPE_RC,
928 /** Ring-0 (host) context module. */
929 PDMMOD_TYPE_R0,
930 /** Ring-3 (host) context module. */
931 PDMMOD_TYPE_R3
932} PDMMODTYPE;
933
934
935/** The module name length including the terminator. */
936#define PDMMOD_NAME_LEN 32
937
938/**
939 * Loaded module instance.
940 */
941typedef struct PDMMOD
942{
943 /** Module name. This is used for referring to
944 * the module internally, sort of like a handle. */
945 char szName[PDMMOD_NAME_LEN];
946 /** Module type. */
947 PDMMODTYPE eType;
948 /** Loader module handle. Not used for R0 modules. */
949 RTLDRMOD hLdrMod;
950 /** Loaded address.
951 * This is the 'handle' for R0 modules. */
952 RTUINTPTR ImageBase;
953 /** Old loaded address.
954 * This is used during relocation of GC modules. Not used for R0 modules. */
955 RTUINTPTR OldImageBase;
956 /** Where the R3 HC bits are stored.
957 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
958 void *pvBits;
959
960 /** Pointer to next module. */
961 struct PDMMOD *pNext;
962 /** Module filename. */
963 char szFilename[1];
964} PDMMOD;
965/** Pointer to loaded module instance. */
966typedef PDMMOD *PPDMMOD;
967
968
969
970/** Extra space in the free array. */
971#define PDMQUEUE_FREE_SLACK 16
972
973/**
974 * Queue type.
975 */
976typedef enum PDMQUEUETYPE
977{
978 /** Device consumer. */
979 PDMQUEUETYPE_DEV = 1,
980 /** Driver consumer. */
981 PDMQUEUETYPE_DRV,
982 /** Internal consumer. */
983 PDMQUEUETYPE_INTERNAL,
984 /** External consumer. */
985 PDMQUEUETYPE_EXTERNAL
986} PDMQUEUETYPE;
987
988/** Pointer to a PDM Queue. */
989typedef struct PDMQUEUE *PPDMQUEUE;
990
991/**
992 * PDM Queue.
993 */
994typedef struct PDMQUEUE
995{
996 /** Pointer to the next queue in the list. */
997 R3PTRTYPE(PPDMQUEUE) pNext;
998 /** Type specific data. */
999 union
1000 {
1001 /** PDMQUEUETYPE_DEV */
1002 struct
1003 {
1004 /** Pointer to consumer function. */
1005 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1006 /** Pointer to the device instance owning the queue. */
1007 R3PTRTYPE(PPDMDEVINS) pDevIns;
1008 } Dev;
1009 /** PDMQUEUETYPE_DRV */
1010 struct
1011 {
1012 /** Pointer to consumer function. */
1013 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1014 /** Pointer to the driver instance owning the queue. */
1015 R3PTRTYPE(PPDMDRVINS) pDrvIns;
1016 } Drv;
1017 /** PDMQUEUETYPE_INTERNAL */
1018 struct
1019 {
1020 /** Pointer to consumer function. */
1021 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1022 } Int;
1023 /** PDMQUEUETYPE_EXTERNAL */
1024 struct
1025 {
1026 /** Pointer to consumer function. */
1027 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1028 /** Pointer to user argument. */
1029 R3PTRTYPE(void *) pvUser;
1030 } Ext;
1031 } u;
1032 /** Queue type. */
1033 PDMQUEUETYPE enmType;
1034 /** The interval between checking the queue for events.
1035 * The realtime timer below is used to do the waiting.
1036 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1037 uint32_t cMilliesInterval;
1038 /** Interval timer. Only used if cMilliesInterval is non-zero. */
1039 PTMTIMERR3 pTimer;
1040 /** Pointer to the VM - R3. */
1041 PVMR3 pVMR3;
1042 /** LIFO of pending items - R3. */
1043 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR3;
1044 /** Pointer to the VM - R0. */
1045 PVMR0 pVMR0;
1046 /** LIFO of pending items - R0. */
1047 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR0;
1048 /** Pointer to the GC VM and indicator for GC enabled queue.
1049 * If this is NULL, the queue cannot be used in GC.
1050 */
1051 PVMRC pVMRC;
1052 /** LIFO of pending items - GC. */
1053 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingRC;
1054
1055 /** Item size (bytes). */
1056 uint32_t cbItem;
1057 /** Number of items in the queue. */
1058 uint32_t cItems;
1059 /** Index to the free head (where we insert). */
1060 uint32_t volatile iFreeHead;
1061 /** Index to the free tail (where we remove). */
1062 uint32_t volatile iFreeTail;
1063
1064 /** Unique queue name. */
1065 R3PTRTYPE(const char *) pszName;
1066#if HC_ARCH_BITS == 32
1067 RTR3PTR Alignment1;
1068#endif
1069 /** Stat: Times PDMQueueAlloc fails. */
1070 STAMCOUNTER StatAllocFailures;
1071 /** Stat: PDMQueueInsert calls. */
1072 STAMCOUNTER StatInsert;
1073 /** Stat: Queue flushes. */
1074 STAMCOUNTER StatFlush;
1075 /** Stat: Queue flushes with pending items left over. */
1076 STAMCOUNTER StatFlushLeftovers;
1077#ifdef VBOX_WITH_STATISTICS
1078 /** State: Profiling the flushing. */
1079 STAMPROFILE StatFlushPrf;
1080 /** State: Pending items. */
1081 uint32_t volatile cStatPending;
1082 uint32_t volatile cAlignment;
1083#endif
1084
1085 /** Array of pointers to free items. Variable size. */
1086 struct PDMQUEUEFREEITEM
1087 {
1088 /** Pointer to the free item - HC Ptr. */
1089 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR3;
1090 /** Pointer to the free item - HC Ptr. */
1091 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR0;
1092 /** Pointer to the free item - GC Ptr. */
1093 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pItemRC;
1094#if HC_ARCH_BITS == 64
1095 RTRCPTR Alignment0;
1096#endif
1097 } aFreeItems[1];
1098} PDMQUEUE;
1099
1100/** @name PDM::fQueueFlushing
1101 * @{ */
1102/** Used to make sure only one EMT will flush the queues.
1103 * Set when an EMT is flushing queues, clear otherwise. */
1104#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1105/** Indicating there are queues with items pending.
1106 * This is make sure we don't miss inserts happening during flushing. The FF
1107 * cannot be used for this since it has to be cleared immediately to prevent
1108 * other EMTs from spinning. */
1109#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1110/** @} */
1111
1112
1113/** @name PDM task structures.
1114 * @{ */
1115
1116/**
1117 * A asynchronous user mode task.
1118 */
1119typedef struct PDMTASK
1120{
1121 /** Task owner type. */
1122 PDMTASKTYPE volatile enmType;
1123 /** Queue flags. */
1124 uint32_t volatile fFlags;
1125 /** User argument for the callback. */
1126 R3PTRTYPE(void *) volatile pvUser;
1127 /** The callback (will be cast according to enmType before callout). */
1128 R3PTRTYPE(PFNRT) volatile pfnCallback;
1129 /** The owner identifier. */
1130 R3PTRTYPE(void *) volatile pvOwner;
1131 /** Task name. */
1132 R3PTRTYPE(const char *) pszName;
1133 /** Number of times already triggered when PDMTaskTrigger was called. */
1134 uint32_t volatile cAlreadyTrigged;
1135 /** Number of runs. */
1136 uint32_t cRuns;
1137} PDMTASK;
1138/** Pointer to a PDM task. */
1139typedef PDMTASK *PPDMTASK;
1140
1141/**
1142 * A task set.
1143 *
1144 * This is served by one task executor thread.
1145 */
1146typedef struct PDMTASKSET
1147{
1148 /** Magic value (PDMTASKSET_MAGIC). */
1149 uint32_t u32Magic;
1150 /** Set if this task set works for ring-0 and raw-mode. */
1151 bool fRZEnabled;
1152 /** Number of allocated taks. */
1153 uint8_t volatile cAllocated;
1154 /** Base handle value for this set. */
1155 uint16_t uHandleBase;
1156 /** The task executor thread. */
1157 R3PTRTYPE(RTTHREAD) hThread;
1158 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1159 SUPSEMEVENT hEventR0;
1160 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1161 R3PTRTYPE(RTSEMEVENT) hEventR3;
1162 /** The VM pointer. */
1163 PVM pVM;
1164 /** Padding so fTriggered is in its own cacheline. */
1165 uint64_t au64Padding2[3];
1166
1167 /** Bitmask of triggered tasks. */
1168 uint64_t volatile fTriggered;
1169 /** Shutdown thread indicator. */
1170 bool volatile fShutdown;
1171 /** Padding. */
1172 bool volatile afPadding3[3];
1173 /** Task currently running, UINT32_MAX if idle. */
1174 uint32_t volatile idxRunning;
1175 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1176 uint64_t volatile au64Padding3[6];
1177
1178 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1179 PDMTASK aTasks[64];
1180} PDMTASKSET;
1181AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1182AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1183/** Magic value for PDMTASKSET::u32Magic. */
1184#define PDMTASKSET_MAGIC UINT32_C(0x19320314)
1185/** Pointer to a task set. */
1186typedef PDMTASKSET *PPDMTASKSET;
1187
1188/** @} */
1189
1190
1191/**
1192 * Queue device helper task operation.
1193 */
1194typedef enum PDMDEVHLPTASKOP
1195{
1196 /** The usual invalid 0 entry. */
1197 PDMDEVHLPTASKOP_INVALID = 0,
1198 /** ISASetIrq */
1199 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1200 /** PCISetIrq */
1201 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1202 /** PCISetIrq */
1203 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1204 /** The usual 32-bit hack. */
1205 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1206} PDMDEVHLPTASKOP;
1207
1208/**
1209 * Queued Device Helper Task.
1210 */
1211typedef struct PDMDEVHLPTASK
1212{
1213 /** The queue item core (don't touch). */
1214 PDMQUEUEITEMCORE Core;
1215 /** Pointer to the device instance (R3 Ptr). */
1216 PPDMDEVINSR3 pDevInsR3;
1217 /** This operation to perform. */
1218 PDMDEVHLPTASKOP enmOp;
1219#if HC_ARCH_BITS == 64
1220 uint32_t Alignment0;
1221#endif
1222 /** Parameters to the operation. */
1223 union PDMDEVHLPTASKPARAMS
1224 {
1225 /**
1226 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1227 */
1228 struct PDMDEVHLPTASKISASETIRQ
1229 {
1230 /** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1231 PCIBDF uBusDevFn;
1232 /** The IRQ */
1233 int iIrq;
1234 /** The new level. */
1235 int iLevel;
1236 /** The IRQ tag and source. */
1237 uint32_t uTagSrc;
1238 } IsaSetIRQ, IoApicSetIRQ;
1239
1240 /**
1241 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1242 */
1243 struct PDMDEVHLPTASKPCISETIRQ
1244 {
1245 /** Pointer to the PCI device (R3 Ptr). */
1246 R3PTRTYPE(PPDMPCIDEV) pPciDevR3;
1247 /** The IRQ */
1248 int iIrq;
1249 /** The new level. */
1250 int iLevel;
1251 /** The IRQ tag and source. */
1252 uint32_t uTagSrc;
1253 } PciSetIRQ;
1254
1255 /** Expanding the structure. */
1256 uint64_t au64[3];
1257 } u;
1258} PDMDEVHLPTASK;
1259/** Pointer to a queued Device Helper Task. */
1260typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1261/** Pointer to a const queued Device Helper Task. */
1262typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1263
1264
1265
1266/**
1267 * An USB hub registration record.
1268 */
1269typedef struct PDMUSBHUB
1270{
1271 /** The USB versions this hub support.
1272 * Note that 1.1 hubs can take on 2.0 devices. */
1273 uint32_t fVersions;
1274 /** The number of ports on the hub. */
1275 uint32_t cPorts;
1276 /** The number of available ports (0..cPorts). */
1277 uint32_t cAvailablePorts;
1278 /** The driver instance of the hub. */
1279 PPDMDRVINS pDrvIns;
1280 /** Copy of the to the registration structure. */
1281 PDMUSBHUBREG Reg;
1282
1283 /** Pointer to the next hub in the list. */
1284 struct PDMUSBHUB *pNext;
1285} PDMUSBHUB;
1286
1287/** Pointer to a const USB HUB registration record. */
1288typedef const PDMUSBHUB *PCPDMUSBHUB;
1289
1290/** Pointer to a PDM Async I/O template. */
1291typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1292
1293/** Pointer to the main PDM Async completion endpoint class. */
1294typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1295
1296/** Pointer to the global block cache structure. */
1297typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1298
1299/**
1300 * PDM VMCPU Instance data.
1301 * Changes to this must checked against the padding of the pdm union in VMCPU!
1302 */
1303typedef struct PDMCPU
1304{
1305 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1306 * in use. */
1307 uint32_t cQueuedCritSectLeaves;
1308 uint32_t uPadding0; /**< Alignment padding.*/
1309 /** Critical sections queued in RC/R0 because of contention preventing leave to
1310 * complete. (R3 Ptrs)
1311 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1312 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1313
1314 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1315 * currently in use. */
1316 uint32_t cQueuedCritSectRwExclLeaves;
1317 uint32_t uPadding1; /**< Alignment padding.*/
1318 /** Read/write critical sections queued in RC/R0 because of contention
1319 * preventing exclusive leave to complete. (R3 Ptrs)
1320 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1321 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1322
1323 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1324 * currently in use. */
1325 uint32_t cQueuedCritSectRwShrdLeaves;
1326 uint32_t uPadding2; /**< Alignment padding.*/
1327 /** Read/write critical sections queued in RC/R0 because of contention
1328 * preventing shared leave to complete. (R3 Ptrs)
1329 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1330 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1331} PDMCPU;
1332
1333
1334/**
1335 * PDM VM Instance data.
1336 * Changes to this must checked against the padding of the cfgm union in VM!
1337 */
1338typedef struct PDM
1339{
1340 /** The PDM lock.
1341 * This is used to protect everything that deals with interrupts, i.e.
1342 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1343 PDMCRITSECT CritSect;
1344 /** The NOP critical section.
1345 * This is a dummy critical section that will not do any thread
1346 * serialization but instead let all threads enter immediately and
1347 * concurrently. */
1348 PDMCRITSECT NopCritSect;
1349
1350 /** The ring-0 capable task sets (max 128). */
1351 PDMTASKSET aTaskSets[2];
1352 /** Pointer to task sets (max 512). */
1353 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1354
1355 /** PCI Buses. */
1356 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1357 /** IOMMU devices. */
1358 PDMIOMMU aIommus[PDM_IOMMUS_MAX];
1359 /** The register PIC device. */
1360 PDMPIC Pic;
1361 /** The registered APIC device. */
1362 PDMAPIC Apic;
1363 /** The registered I/O APIC device. */
1364 PDMIOAPIC IoApic;
1365 /** The registered HPET device. */
1366 PPDMDEVINSR3 pHpet;
1367
1368 /** List of registered devices. (FIFO) */
1369 R3PTRTYPE(PPDMDEV) pDevs;
1370 /** List of devices instances. (FIFO) */
1371 R3PTRTYPE(PPDMDEVINS) pDevInstances;
1372 /** List of registered USB devices. (FIFO) */
1373 R3PTRTYPE(PPDMUSB) pUsbDevs;
1374 /** List of USB devices instances. (FIFO) */
1375 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1376 /** List of registered drivers. (FIFO) */
1377 R3PTRTYPE(PPDMDRV) pDrvs;
1378 /** The registered firmware device (can be NULL). */
1379 R3PTRTYPE(PPDMFW) pFirmware;
1380 /** The registered DMAC device. */
1381 R3PTRTYPE(PPDMDMAC) pDmac;
1382 /** The registered RTC device. */
1383 R3PTRTYPE(PPDMRTC) pRtc;
1384 /** The registered USB HUBs. (FIFO) */
1385 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1386
1387 /** @name Queues
1388 * @{ */
1389 /** Queue in which devhlp tasks are queued for R3 execution - R3 Ptr. */
1390 R3PTRTYPE(PPDMQUEUE) pDevHlpQueueR3;
1391 /** Queue in which devhlp tasks are queued for R3 execution - R0 Ptr. */
1392 R0PTRTYPE(PPDMQUEUE) pDevHlpQueueR0;
1393 /** Queue in which devhlp tasks are queued for R3 execution - RC Ptr. */
1394 RCPTRTYPE(PPDMQUEUE) pDevHlpQueueRC;
1395 /** Pointer to the queue which should be manually flushed - RC Ptr.
1396 * Only touched by EMT. */
1397 RCPTRTYPE(struct PDMQUEUE *) pQueueFlushRC;
1398 /** Pointer to the queue which should be manually flushed - R0 Ptr.
1399 * Only touched by EMT. */
1400 R0PTRTYPE(struct PDMQUEUE *) pQueueFlushR0;
1401 /** Bitmask controlling the queue flushing.
1402 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1403 uint32_t volatile fQueueFlushing;
1404 /** @} */
1405
1406 /** The current IRQ tag (tracing purposes). */
1407 uint32_t volatile uIrqTag;
1408
1409 /** Pending reset flags (PDMVMRESET_F_XXX). */
1410 uint32_t volatile fResetFlags;
1411
1412 /** Set by pdmR3LoadExec for use in assertions. */
1413 bool fStateLoaded;
1414 /** Alignment padding. */
1415 bool afPadding[3];
1416
1417 /** The tracing ID of the next device instance.
1418 *
1419 * @remarks We keep the device tracing ID seperate from the rest as these are
1420 * then more likely to end up with the same ID from one run to
1421 * another, making analysis somewhat easier. Drivers and USB devices
1422 * are more volatile and can be changed at runtime, thus these are much
1423 * less likely to remain stable, so just heap them all together. */
1424 uint32_t idTracingDev;
1425 /** The tracing ID of the next driver instance, USB device instance or other
1426 * PDM entity requiring an ID. */
1427 uint32_t idTracingOther;
1428
1429 /** @name VMM device heap
1430 * @{ */
1431 /** The heap size. */
1432 uint32_t cbVMMDevHeap;
1433 /** Free space. */
1434 uint32_t cbVMMDevHeapLeft;
1435 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1436 RTR3PTR pvVMMDevHeap;
1437 /** Ring-3 mapping/unmapping notification callback for the user. */
1438 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1439 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1440 RTGCPHYS GCPhysVMMDevHeap;
1441 /** @} */
1442
1443 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1444 STAMCOUNTER StatQueuedCritSectLeaves;
1445} PDM;
1446AssertCompileMemberAlignment(PDM, CritSect, 8);
1447AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1448AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1449AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1450/** Pointer to PDM VM instance data. */
1451typedef PDM *PPDM;
1452
1453
1454/**
1455 * PDM data kept in the ring-0 GVM.
1456 */
1457typedef struct PDMR0PERVM
1458{
1459 /** PCI Buses, ring-0 data. */
1460 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1461 /** IOMMUs, ring-0 data. */
1462 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1463 /** Number of valid ring-0 device instances (apDevInstances). */
1464 uint32_t cDevInstances;
1465 uint32_t u32Padding;
1466 /** Pointer to ring-0 device instances. */
1467 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[190];
1468} PDMR0PERVM;
1469
1470
1471/**
1472 * PDM data kept in the UVM.
1473 */
1474typedef struct PDMUSERPERVM
1475{
1476 /** @todo move more stuff over here. */
1477
1478 /** Linked list of timer driven PDM queues.
1479 * Currently serialized by PDM::CritSect. */
1480 R3PTRTYPE(struct PDMQUEUE *) pQueuesTimer;
1481 /** Linked list of force action driven PDM queues.
1482 * Currently serialized by PDM::CritSect. */
1483 R3PTRTYPE(struct PDMQUEUE *) pQueuesForced;
1484
1485 /** Lock protecting the lists below it. */
1486 RTCRITSECT ListCritSect;
1487 /** Pointer to list of loaded modules. */
1488 PPDMMOD pModules;
1489 /** List of initialized critical sections. (LIFO) */
1490 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1491 /** List of initialized read/write critical sections. (LIFO) */
1492 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1493 /** Head of the PDM Thread list. (singly linked) */
1494 R3PTRTYPE(PPDMTHREAD) pThreads;
1495 /** Tail of the PDM Thread list. (singly linked) */
1496 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1497
1498 /** @name PDM Async Completion
1499 * @{ */
1500 /** Pointer to the array of supported endpoint classes. */
1501 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1502 /** Head of the templates. Singly linked, protected by ListCritSect. */
1503 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1504 /** @} */
1505
1506 /** Global block cache data. */
1507 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1508#ifdef VBOX_WITH_NETSHAPER
1509 /** Pointer to network shaper instance. */
1510 R3PTRTYPE(PPDMNETSHAPER) pNetShaper;
1511#endif /* VBOX_WITH_NETSHAPER */
1512
1513} PDMUSERPERVM;
1514/** Pointer to the PDM data kept in the UVM. */
1515typedef PDMUSERPERVM *PPDMUSERPERVM;
1516
1517
1518
1519/*******************************************************************************
1520* Global Variables *
1521*******************************************************************************/
1522#ifdef IN_RING3
1523extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1524extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1525# ifdef VBOX_WITH_DBGF_TRACING
1526extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1527# endif
1528extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1529extern const PDMPICHLP g_pdmR3DevPicHlp;
1530extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1531extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1532extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1533extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1534extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1535extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1536extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1537extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1538#endif
1539
1540
1541/*******************************************************************************
1542* Defined Constants And Macros *
1543*******************************************************************************/
1544/** @def PDMDEV_ASSERT_DEVINS
1545 * Asserts the validity of the device instance.
1546 */
1547#ifdef VBOX_STRICT
1548# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1549 do { \
1550 AssertPtr(pDevIns); \
1551 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1552 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1553 } while (0)
1554#else
1555# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1556#endif
1557
1558/** @def PDMDRV_ASSERT_DRVINS
1559 * Asserts the validity of the driver instance.
1560 */
1561#ifdef VBOX_STRICT
1562# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1563 do { \
1564 AssertPtr(pDrvIns); \
1565 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1566 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1567 } while (0)
1568#else
1569# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1570#endif
1571
1572
1573/*******************************************************************************
1574* Internal Functions *
1575*******************************************************************************/
1576#ifdef IN_RING3
1577bool pdmR3IsValidName(const char *pszName);
1578
1579int pdmR3CritSectBothInitStats(PVM pVM);
1580void pdmR3CritSectBothRelocate(PVM pVM);
1581int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1582int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1583int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1584 const char *pszNameFmt, va_list va);
1585int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1586 const char *pszNameFmt, ...);
1587int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1588 const char *pszNameFmt, ...);
1589int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1590 const char *pszNameFmt, va_list va);
1591int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1592 const char *pszNameFmt, ...);
1593int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1594 const char *pszNameFmt, ...);
1595
1596int pdmR3DevInit(PVM pVM);
1597int pdmR3DevInitComplete(PVM pVM);
1598PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1599int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1600DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1601
1602int pdmR3UsbLoadModules(PVM pVM);
1603int pdmR3UsbInstantiateDevices(PVM pVM);
1604PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1605int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1606int pdmR3UsbVMInitComplete(PVM pVM);
1607
1608int pdmR3DrvInit(PVM pVM);
1609int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1610 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1611int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1612void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1613PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1614
1615int pdmR3LdrInitU(PUVM pUVM);
1616void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1617char *pdmR3FileR3(const char *pszFile, bool fShared);
1618int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1619
1620void pdmR3QueueRelocate(PVM pVM, RTGCINTPTR offDelta);
1621
1622int pdmR3TaskInit(PVM pVM);
1623void pdmR3TaskTerm(PVM pVM);
1624
1625int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1626 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1627int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1628 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1629int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1630 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1631int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1632int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1633int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1634void pdmR3ThreadDestroyAll(PVM pVM);
1635int pdmR3ThreadResumeAll(PVM pVM);
1636int pdmR3ThreadSuspendAll(PVM pVM);
1637
1638#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1639int pdmR3AsyncCompletionInit(PVM pVM);
1640int pdmR3AsyncCompletionTerm(PVM pVM);
1641void pdmR3AsyncCompletionResume(PVM pVM);
1642int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1643int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1644 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1645int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1646int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1647int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1648int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1649#endif
1650
1651#ifdef VBOX_WITH_NETSHAPER
1652int pdmR3NetShaperInit(PVM pVM);
1653int pdmR3NetShaperTerm(PVM pVM);
1654#endif
1655
1656int pdmR3BlkCacheInit(PVM pVM);
1657void pdmR3BlkCacheTerm(PVM pVM);
1658int pdmR3BlkCacheResume(PVM pVM);
1659
1660#endif /* IN_RING3 */
1661
1662void pdmLock(PVMCC pVM);
1663int pdmLockEx(PVMCC pVM, int rc);
1664void pdmUnlock(PVMCC pVM);
1665
1666#ifdef VBOX_WITH_IOMMU_AMD
1667int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1668int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1669int pdmIommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock);
1670int pdmIommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock);
1671int pdmIommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks);
1672int pdmIommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks);
1673int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t uDeviceId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut);
1674#endif
1675
1676#if defined(IN_RING3) || defined(IN_RING0)
1677void pdmCritSectRwLeaveSharedQueued(PPDMCRITSECTRW pThis);
1678void pdmCritSectRwLeaveExclQueued(PPDMCRITSECTRW pThis);
1679#endif
1680
1681#ifdef IN_RING0
1682DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1683#endif
1684
1685#ifdef VBOX_WITH_DBGF_TRACING
1686# ifdef IN_RING3
1687DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1688 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1689 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1690 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1691DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1692DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1693DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1694 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1695 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1696 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion);
1697DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1698DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1699DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1700DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1701DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1702DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1703DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1704DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1705DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1706DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1707# elif defined(IN_RING0)
1708DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1709 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1710 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1711 void *pvUser);
1712DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1713 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1714DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1715DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1716DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1717DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1718DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1719DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1720DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1721DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1722# else
1723# error "Invalid environment selected"
1724# endif
1725#endif
1726
1727
1728/** @} */
1729
1730RT_C_DECLS_END
1731
1732#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1733
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