VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 54763

Last change on this file since 54763 was 52670, checked in by vboxsync, 10 years ago

VMM, Devices: Add interface to query the APIC frequency from the APIC device.
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File size: 53.9 KB
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1/* $Id: PDMInternal.h 52670 2014-09-10 11:04:10Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PDMInternal_h
19#define ___PDMInternal_h
20
21#include <VBox/types.h>
22#include <VBox/param.h>
23#include <VBox/vmm/cfgm.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vusb.h>
26#include <VBox/vmm/pdmasynccompletion.h>
27#ifdef VBOX_WITH_NETSHAPER
28# include <VBox/vmm/pdmnetshaper.h>
29#endif
30#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
31# include <VBox/vmm/pdmasynccompletion.h>
32#endif
33#include <VBox/vmm/pdmblkcache.h>
34#include <VBox/vmm/pdmcommon.h>
35#include <VBox/sup.h>
36#include <iprt/assert.h>
37#include <iprt/critsect.h>
38#ifdef IN_RING3
39# include <iprt/thread.h>
40#endif
41
42RT_C_DECLS_BEGIN
43
44
45/** @defgroup grp_pdm_int Internal
46 * @ingroup grp_pdm
47 * @internal
48 * @{
49 */
50
51/** @def PDM_WITH_R3R0_CRIT_SECT
52 * Enables or disabled ring-3/ring-0 critical sections. */
53#if defined(DOXYGEN_RUNNING) || 1
54# define PDM_WITH_R3R0_CRIT_SECT
55#endif
56
57/** @def PDMCRITSECT_STRICT
58 * Enables/disables PDM critsect strictness like deadlock detection. */
59#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(IEM_VERIFICATION_MODE) && !defined(PDMCRITSECT_STRICT)) \
60 || defined(DOXYGEN_RUNNING)
61# define PDMCRITSECT_STRICT
62#endif
63
64/** @def PDMCRITSECT_STRICT
65 * Enables/disables PDM read/write critsect strictness like deadlock
66 * detection. */
67#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(IEM_VERIFICATION_MODE) && !defined(PDMCRITSECTRW_STRICT)) \
68 || defined(DOXYGEN_RUNNING)
69# define PDMCRITSECTRW_STRICT
70#endif
71
72
73/*******************************************************************************
74* Structures and Typedefs *
75*******************************************************************************/
76
77/** Pointer to a PDM Device. */
78typedef struct PDMDEV *PPDMDEV;
79/** Pointer to a pointer to a PDM Device. */
80typedef PPDMDEV *PPPDMDEV;
81
82/** Pointer to a PDM USB Device. */
83typedef struct PDMUSB *PPDMUSB;
84/** Pointer to a pointer to a PDM USB Device. */
85typedef PPDMUSB *PPPDMUSB;
86
87/** Pointer to a PDM Driver. */
88typedef struct PDMDRV *PPDMDRV;
89/** Pointer to a pointer to a PDM Driver. */
90typedef PPDMDRV *PPPDMDRV;
91
92/** Pointer to a PDM Logical Unit. */
93typedef struct PDMLUN *PPDMLUN;
94/** Pointer to a pointer to a PDM Logical Unit. */
95typedef PPDMLUN *PPPDMLUN;
96
97/** Pointer to a PDM PCI Bus instance. */
98typedef struct PDMPCIBUS *PPDMPCIBUS;
99/** Pointer to a DMAC instance. */
100typedef struct PDMDMAC *PPDMDMAC;
101/** Pointer to a RTC instance. */
102typedef struct PDMRTC *PPDMRTC;
103
104/** Pointer to an USB HUB registration record. */
105typedef struct PDMUSBHUB *PPDMUSBHUB;
106
107/**
108 * Supported asynchronous completion endpoint classes.
109 */
110typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
111{
112 /** File class. */
113 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
114 /** Number of supported classes. */
115 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
116 /** 32bit hack. */
117 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
118} PDMASYNCCOMPLETIONEPCLASSTYPE;
119
120/**
121 * Private device instance data.
122 */
123typedef struct PDMDEVINSINT
124{
125 /** Pointer to the next instance (HC Ptr).
126 * (Head is pointed to by PDM::pDevInstances.) */
127 R3PTRTYPE(PPDMDEVINS) pNextR3;
128 /** Pointer to the next per device instance (HC Ptr).
129 * (Head is pointed to by PDMDEV::pInstances.) */
130 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
131 /** Pointer to device structure - HC Ptr. */
132 R3PTRTYPE(PPDMDEV) pDevR3;
133 /** Pointer to the list of logical units associated with the device. (FIFO) */
134 R3PTRTYPE(PPDMLUN) pLunsR3;
135 /** Pointer to the asynchronous notification callback set while in
136 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
137 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
138 /** Configuration handle to the instance node. */
139 R3PTRTYPE(PCFGMNODE) pCfgHandle;
140
141 /** R3 pointer to the VM this instance was created for. */
142 PVMR3 pVMR3;
143 /** R3 pointer to associated PCI device structure. */
144 R3PTRTYPE(struct PCIDevice *) pPciDeviceR3;
145 /** R3 pointer to associated PCI bus structure. */
146 R3PTRTYPE(PPDMPCIBUS) pPciBusR3;
147
148 /** R0 pointer to the VM this instance was created for. */
149 PVMR0 pVMR0;
150 /** R0 pointer to associated PCI device structure. */
151 R0PTRTYPE(struct PCIDevice *) pPciDeviceR0;
152 /** R0 pointer to associated PCI bus structure. */
153 R0PTRTYPE(PPDMPCIBUS) pPciBusR0;
154
155 /** RC pointer to the VM this instance was created for. */
156 PVMRC pVMRC;
157 /** RC pointer to associated PCI device structure. */
158 RCPTRTYPE(struct PCIDevice *) pPciDeviceRC;
159 /** RC pointer to associated PCI bus structure. */
160 RCPTRTYPE(PPDMPCIBUS) pPciBusRC;
161
162 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
163 uint32_t fIntFlags;
164 /** The last IRQ tag (for tracing it thru clearing). */
165 uint32_t uLastIrqTag;
166 /** Size padding. */
167 uint32_t u32Padding;
168} PDMDEVINSINT;
169
170/** @name PDMDEVINSINT::fIntFlags
171 * @{ */
172/** Used by pdmR3Load to mark device instances it found in the saved state. */
173#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
174/** Indicates that the device hasn't been powered on or resumed.
175 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
176 * to make sure each device gets exactly one notification for each of those
177 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
178 * a failure (already resumed/powered-on devices are suspended). */
179#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
180/** Indicates that the device has been reset already. Used by PDMR3Reset. */
181#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
182/** @} */
183
184
185/**
186 * Private USB device instance data.
187 */
188typedef struct PDMUSBINSINT
189{
190 /** The UUID of this instance. */
191 RTUUID Uuid;
192 /** Pointer to the next instance.
193 * (Head is pointed to by PDM::pUsbInstances.) */
194 R3PTRTYPE(PPDMUSBINS) pNext;
195 /** Pointer to the next per USB device instance.
196 * (Head is pointed to by PDMUSB::pInstances.) */
197 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
198
199 /** Pointer to device structure. */
200 R3PTRTYPE(PPDMUSB) pUsbDev;
201
202 /** Pointer to the VM this instance was created for. */
203 PVMR3 pVM;
204 /** Pointer to the list of logical units associated with the device. (FIFO) */
205 R3PTRTYPE(PPDMLUN) pLuns;
206 /** The per instance device configuration. */
207 R3PTRTYPE(PCFGMNODE) pCfg;
208 /** Same as pCfg if the configuration should be deleted when detaching the device. */
209 R3PTRTYPE(PCFGMNODE) pCfgDelete;
210 /** The global device configuration. */
211 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
212
213 /** Pointer to the USB hub this device is attached to.
214 * This is NULL if the device isn't connected to any HUB. */
215 R3PTRTYPE(PPDMUSBHUB) pHub;
216 /** The port number that we're connected to. */
217 uint32_t iPort;
218 /** Indicates that the USB device hasn't been powered on or resumed.
219 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
220 bool fVMSuspended;
221 /** Indicates that the USB device has been reset. */
222 bool fVMReset;
223 /** Pointer to the asynchronous notification callback set while in
224 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
225 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
226} PDMUSBINSINT;
227
228
229/**
230 * Private driver instance data.
231 */
232typedef struct PDMDRVINSINT
233{
234 /** Pointer to the driver instance above.
235 * This is NULL for the topmost drive. */
236 R3PTRTYPE(PPDMDRVINS) pUp;
237 /** Pointer to the driver instance below.
238 * This is NULL for the bottommost driver. */
239 R3PTRTYPE(PPDMDRVINS) pDown;
240 /** Pointer to the logical unit this driver chained on. */
241 R3PTRTYPE(PPDMLUN) pLun;
242 /** Pointer to driver structure from which this was instantiated. */
243 R3PTRTYPE(PPDMDRV) pDrv;
244 /** Pointer to the VM this instance was created for, ring-3 context. */
245 PVMR3 pVMR3;
246 /** Pointer to the VM this instance was created for, ring-0 context. */
247 PVMR0 pVMR0;
248 /** Pointer to the VM this instance was created for, raw-mode context. */
249 PVMRC pVMRC;
250 /** Flag indicating that the driver is being detached and destroyed.
251 * (Helps detect potential recursive detaching.) */
252 bool fDetaching;
253 /** Indicates that the driver hasn't been powered on or resumed.
254 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
255 bool fVMSuspended;
256 /** Indicates that the driver has been reset already. */
257 bool fVMReset;
258 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
259 bool fHyperHeap;
260 /** Pointer to the asynchronous notification callback set while in
261 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
262 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
263 /** Configuration handle to the instance node. */
264 R3PTRTYPE(PCFGMNODE) pCfgHandle;
265 /** Pointer to the ring-0 request handler function. */
266 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
267} PDMDRVINSINT;
268
269
270/**
271 * Private critical section data.
272 */
273typedef struct PDMCRITSECTINT
274{
275 /** The critical section core which is shared with IPRT.
276 * @note The semaphore is a SUPSEMEVENT. */
277 RTCRITSECT Core;
278 /** Pointer to the next critical section.
279 * This chain is used for relocating pVMRC and device cleanup. */
280 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
281 /** Owner identifier.
282 * This is pDevIns if the owner is a device. Similarly for a driver or service.
283 * PDMR3CritSectInit() sets this to point to the critsect itself. */
284 RTR3PTR pvKey;
285 /** Pointer to the VM - R3Ptr. */
286 PVMR3 pVMR3;
287 /** Pointer to the VM - R0Ptr. */
288 PVMR0 pVMR0;
289 /** Pointer to the VM - GCPtr. */
290 PVMRC pVMRC;
291 /** Set if this critical section is the automatically created default
292 * section of a device.. */
293 bool fAutomaticDefaultCritsect;
294 /** Set if the critical section is used by a timer or similar.
295 * See PDMR3DevGetCritSect. */
296 bool fUsedByTimerOrSimilar;
297 /** Alignment padding. */
298 bool afPadding[2];
299 /** Event semaphore that is scheduled to be signaled upon leaving the
300 * critical section. This is Ring-3 only of course. */
301 RTSEMEVENT EventToSignal;
302 /** The lock name. */
303 R3PTRTYPE(const char *) pszName;
304 /** R0/RC lock contention. */
305 STAMCOUNTER StatContentionRZLock;
306 /** R0/RC unlock contention. */
307 STAMCOUNTER StatContentionRZUnlock;
308 /** R3 lock contention. */
309 STAMCOUNTER StatContentionR3;
310 /** Profiling the time the section is locked. */
311 STAMPROFILEADV StatLocked;
312} PDMCRITSECTINT;
313AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
314/** Pointer to private critical section data. */
315typedef PDMCRITSECTINT *PPDMCRITSECTINT;
316
317/** Indicates that the critical section is queued for unlock.
318 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
319#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
320
321
322/**
323 * Private critical section data.
324 */
325typedef struct PDMCRITSECTRWINT
326{
327 /** The read/write critical section core which is shared with IPRT.
328 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
329 RTCRITSECTRW Core;
330
331 /** Pointer to the next critical section.
332 * This chain is used for relocating pVMRC and device cleanup. */
333 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
334 /** Owner identifier.
335 * This is pDevIns if the owner is a device. Similarly for a driver or service.
336 * PDMR3CritSectInit() sets this to point to the critsect itself. */
337 RTR3PTR pvKey;
338 /** Pointer to the VM - R3Ptr. */
339 PVMR3 pVMR3;
340 /** Pointer to the VM - R0Ptr. */
341 PVMR0 pVMR0;
342 /** Pointer to the VM - GCPtr. */
343 PVMRC pVMRC;
344#if HC_ARCH_BITS == 64
345 /** Alignment padding. */
346 RTRCPTR RCPtrPadding;
347#endif
348 /** The lock name. */
349 R3PTRTYPE(const char *) pszName;
350 /** R0/RC write lock contention. */
351 STAMCOUNTER StatContentionRZEnterExcl;
352 /** R0/RC write unlock contention. */
353 STAMCOUNTER StatContentionRZLeaveExcl;
354 /** R0/RC read lock contention. */
355 STAMCOUNTER StatContentionRZEnterShared;
356 /** R0/RC read unlock contention. */
357 STAMCOUNTER StatContentionRZLeaveShared;
358 /** R0/RC writes. */
359 STAMCOUNTER StatRZEnterExcl;
360 /** R0/RC reads. */
361 STAMCOUNTER StatRZEnterShared;
362 /** R3 write lock contention. */
363 STAMCOUNTER StatContentionR3EnterExcl;
364 /** R3 read lock contention. */
365 STAMCOUNTER StatContentionR3EnterShared;
366 /** R3 writes. */
367 STAMCOUNTER StatR3EnterExcl;
368 /** R3 reads. */
369 STAMCOUNTER StatR3EnterShared;
370 /** Profiling the time the section is write locked. */
371 STAMPROFILEADV StatWriteLocked;
372} PDMCRITSECTRWINT;
373AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
374AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u64State, 8);
375/** Pointer to private critical section data. */
376typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
377
378
379
380/**
381 * The usual device/driver/internal/external stuff.
382 */
383typedef enum
384{
385 /** The usual invalid entry. */
386 PDMTHREADTYPE_INVALID = 0,
387 /** Device type. */
388 PDMTHREADTYPE_DEVICE,
389 /** USB Device type. */
390 PDMTHREADTYPE_USB,
391 /** Driver type. */
392 PDMTHREADTYPE_DRIVER,
393 /** Internal type. */
394 PDMTHREADTYPE_INTERNAL,
395 /** External type. */
396 PDMTHREADTYPE_EXTERNAL,
397 /** The usual 32-bit hack. */
398 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
399} PDMTHREADTYPE;
400
401
402/**
403 * The internal structure for the thread.
404 */
405typedef struct PDMTHREADINT
406{
407 /** The VM pointer. */
408 PVMR3 pVM;
409 /** The event semaphore the thread blocks on when not running. */
410 RTSEMEVENTMULTI BlockEvent;
411 /** The event semaphore the thread sleeps on while running. */
412 RTSEMEVENTMULTI SleepEvent;
413 /** Pointer to the next thread. */
414 R3PTRTYPE(struct PDMTHREAD *) pNext;
415 /** The thread type. */
416 PDMTHREADTYPE enmType;
417} PDMTHREADINT;
418
419
420
421/* Must be included after PDMDEVINSINT is defined. */
422#define PDMDEVINSINT_DECLARED
423#define PDMUSBINSINT_DECLARED
424#define PDMDRVINSINT_DECLARED
425#define PDMCRITSECTINT_DECLARED
426#define PDMCRITSECTRWINT_DECLARED
427#define PDMTHREADINT_DECLARED
428#ifdef ___VBox_pdm_h
429# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
430#endif
431RT_C_DECLS_END
432#include <VBox/vmm/pdm.h>
433RT_C_DECLS_BEGIN
434
435/**
436 * PDM Logical Unit.
437 *
438 * This typically the representation of a physical port on a
439 * device, like for instance the PS/2 keyboard port on the
440 * keyboard controller device. The LUNs are chained on the
441 * device the belong to (PDMDEVINSINT::pLunsR3).
442 */
443typedef struct PDMLUN
444{
445 /** The LUN - The Logical Unit Number. */
446 RTUINT iLun;
447 /** Pointer to the next LUN. */
448 PPDMLUN pNext;
449 /** Pointer to the top driver in the driver chain. */
450 PPDMDRVINS pTop;
451 /** Pointer to the bottom driver in the driver chain. */
452 PPDMDRVINS pBottom;
453 /** Pointer to the device instance which the LUN belongs to.
454 * Either this is set or pUsbIns is set. Both is never set at the same time. */
455 PPDMDEVINS pDevIns;
456 /** Pointer to the USB device instance which the LUN belongs to. */
457 PPDMUSBINS pUsbIns;
458 /** Pointer to the device base interface. */
459 PPDMIBASE pBase;
460 /** Description of this LUN. */
461 const char *pszDesc;
462} PDMLUN;
463
464
465/**
466 * PDM Device.
467 */
468typedef struct PDMDEV
469{
470 /** Pointer to the next device (R3 Ptr). */
471 R3PTRTYPE(PPDMDEV) pNext;
472 /** Device name length. (search optimization) */
473 RTUINT cchName;
474 /** Registration structure. */
475 R3PTRTYPE(const struct PDMDEVREG *) pReg;
476 /** Number of instances. */
477 uint32_t cInstances;
478 /** Pointer to chain of instances (R3 Ptr). */
479 PPDMDEVINSR3 pInstances;
480 /** The search path for raw-mode context modules (';' as separator). */
481 char *pszRCSearchPath;
482 /** The search path for ring-0 context modules (';' as separator). */
483 char *pszR0SearchPath;
484} PDMDEV;
485
486
487/**
488 * PDM USB Device.
489 */
490typedef struct PDMUSB
491{
492 /** Pointer to the next device (R3 Ptr). */
493 R3PTRTYPE(PPDMUSB) pNext;
494 /** Device name length. (search optimization) */
495 RTUINT cchName;
496 /** Registration structure. */
497 R3PTRTYPE(const struct PDMUSBREG *) pReg;
498 /** Next instance number. */
499 uint32_t iNextInstance;
500 /** Pointer to chain of instances (R3 Ptr). */
501 R3PTRTYPE(PPDMUSBINS) pInstances;
502} PDMUSB;
503
504
505/**
506 * PDM Driver.
507 */
508typedef struct PDMDRV
509{
510 /** Pointer to the next device. */
511 PPDMDRV pNext;
512 /** Registration structure. */
513 const struct PDMDRVREG * pReg;
514 /** Current number of instances. */
515 uint32_t cInstances;
516 /** The next instance number. */
517 uint32_t iNextInstance;
518 /** The search path for raw-mode context modules (';' as separator). */
519 char *pszRCSearchPath;
520 /** The search path for ring-0 context modules (';' as separator). */
521 char *pszR0SearchPath;
522} PDMDRV;
523
524
525/**
526 * PDM registered PIC device.
527 */
528typedef struct PDMPIC
529{
530 /** Pointer to the PIC device instance - R3. */
531 PPDMDEVINSR3 pDevInsR3;
532 /** @copydoc PDMPICREG::pfnSetIrqR3 */
533 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
534 /** @copydoc PDMPICREG::pfnGetInterruptR3 */
535 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
536
537 /** Pointer to the PIC device instance - R0. */
538 PPDMDEVINSR0 pDevInsR0;
539 /** @copydoc PDMPICREG::pfnSetIrqR3 */
540 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
541 /** @copydoc PDMPICREG::pfnGetInterruptR3 */
542 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
543
544 /** Pointer to the PIC device instance - RC. */
545 PPDMDEVINSRC pDevInsRC;
546 /** @copydoc PDMPICREG::pfnSetIrqR3 */
547 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
548 /** @copydoc PDMPICREG::pfnGetInterruptR3 */
549 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
550 /** Alignment padding. */
551 RTRCPTR RCPtrPadding;
552} PDMPIC;
553
554
555/**
556 * PDM registered APIC device.
557 */
558typedef struct PDMAPIC
559{
560 /** Pointer to the APIC device instance - R3 Ptr. */
561 PPDMDEVINSR3 pDevInsR3;
562 /** @copydoc PDMAPICREG::pfnGetInterruptR3 */
563 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc));
564 /** @copydoc PDMAPICREG::pfnHasPendingIrqR3 */
565 DECLR3CALLBACKMEMBER(bool, pfnHasPendingIrqR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t *pu8PendingIrq));
566 /** @copydoc PDMAPICREG::pfnSetBaseR3 */
567 DECLR3CALLBACKMEMBER(void, pfnSetBaseR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base));
568 /** @copydoc PDMAPICREG::pfnGetBaseR3 */
569 DECLR3CALLBACKMEMBER(uint64_t, pfnGetBaseR3,(PPDMDEVINS pDevIns, VMCPUID idCpu));
570 /** @copydoc PDMAPICREG::pfnSetTPRR3 */
571 DECLR3CALLBACKMEMBER(void, pfnSetTPRR3,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t u8TPR));
572 /** @copydoc PDMAPICREG::pfnGetTPRR3 */
573 DECLR3CALLBACKMEMBER(uint8_t, pfnGetTPRR3,(PPDMDEVINS pDevIns, VMCPUID idCpu));
574 /** @copydoc PDMAPICREG::pfnWriteMSRR3 */
575 DECLR3CALLBACKMEMBER(int, pfnWriteMSRR3, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value));
576 /** @copydoc PDMAPICREG::pfnReadMSRR3 */
577 DECLR3CALLBACKMEMBER(int, pfnReadMSRR3, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value));
578 /** @copydoc PDMAPICREG::pfnBusDeliverR3 */
579 DECLR3CALLBACKMEMBER(int, pfnBusDeliverR3,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
580 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
581 /** @copydoc PDMAPICREG::pfnLocalInterruptR3 */
582 DECLR3CALLBACKMEMBER(int, pfnLocalInterruptR3,(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level));
583 /** @copydoc PDMAPICREG::pfnGetTimerFreqR3 */
584 DECLR3CALLBACKMEMBER(uint64_t, pfnGetTimerFreqR3,(PPDMDEVINS pDevIns));
585
586 /** Pointer to the APIC device instance - R0 Ptr. */
587 PPDMDEVINSR0 pDevInsR0;
588 /** @copydoc PDMAPICREG::pfnGetInterruptR3 */
589 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc));
590 /** @copydoc PDMAPICREG::pfnHasPendingIrqR3 */
591 DECLR0CALLBACKMEMBER(bool, pfnHasPendingIrqR0,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t *pu8PendingIrq));
592 /** @copydoc PDMAPICREG::pfnSetBaseR3 */
593 DECLR0CALLBACKMEMBER(void, pfnSetBaseR0,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base));
594 /** @copydoc PDMAPICREG::pfnGetBaseR3 */
595 DECLR0CALLBACKMEMBER(uint64_t, pfnGetBaseR0,(PPDMDEVINS pDevIns, VMCPUID idCpu));
596 /** @copydoc PDMAPICREG::pfnSetTPRR3 */
597 DECLR0CALLBACKMEMBER(void, pfnSetTPRR0,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t u8TPR));
598 /** @copydoc PDMAPICREG::pfnGetTPRR3 */
599 DECLR0CALLBACKMEMBER(uint8_t, pfnGetTPRR0,(PPDMDEVINS pDevIns, VMCPUID idCpu));
600 /** @copydoc PDMAPICREG::pfnWriteMSRR3 */
601 DECLR0CALLBACKMEMBER(uint32_t, pfnWriteMSRR0, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value));
602 /** @copydoc PDMAPICREG::pfnReadMSRR3 */
603 DECLR0CALLBACKMEMBER(uint32_t, pfnReadMSRR0, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value));
604 /** @copydoc PDMAPICREG::pfnBusDeliverR3 */
605 DECLR0CALLBACKMEMBER(int, pfnBusDeliverR0,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
606 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
607 /** @copydoc PDMAPICREG::pfnLocalInterruptR3 */
608 DECLR0CALLBACKMEMBER(int, pfnLocalInterruptR0,(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level));
609 /** @copydoc PDMAPICREG::pfnGetTimerFreqR3 */
610 DECLR0CALLBACKMEMBER(uint64_t, pfnGetTimerFreqR0,(PPDMDEVINS pDevIns));
611
612 /** Pointer to the APIC device instance - RC Ptr. */
613 PPDMDEVINSRC pDevInsRC;
614 /** @copydoc PDMAPICREG::pfnGetInterruptR3 */
615 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc));
616 /** @copydoc PDMAPICREG::pfnHasPendingIrqR3 */
617 DECLRCCALLBACKMEMBER(bool, pfnHasPendingIrqRC,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t *pu8PendingIrq));
618 /** @copydoc PDMAPICREG::pfnSetBaseR3 */
619 DECLRCCALLBACKMEMBER(void, pfnSetBaseRC,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t u64Base));
620 /** @copydoc PDMAPICREG::pfnGetBaseR3 */
621 DECLRCCALLBACKMEMBER(uint64_t, pfnGetBaseRC,(PPDMDEVINS pDevIns, VMCPUID idCpu));
622 /** @copydoc PDMAPICREG::pfnSetTPRR3 */
623 DECLRCCALLBACKMEMBER(void, pfnSetTPRRC,(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t u8TPR));
624 /** @copydoc PDMAPICREG::pfnGetTPRR3 */
625 DECLRCCALLBACKMEMBER(uint8_t, pfnGetTPRRC,(PPDMDEVINS pDevIns, VMCPUID idCpu));
626 /** @copydoc PDMAPICREG::pfnWriteMSRR3 */
627 DECLRCCALLBACKMEMBER(uint32_t, pfnWriteMSRRC, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value));
628 /** @copydoc PDMAPICREG::pfnReadMSRR3 */
629 DECLRCCALLBACKMEMBER(uint32_t, pfnReadMSRRC, (PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value));
630 /** @copydoc PDMAPICREG::pfnBusDeliverR3 */
631 DECLRCCALLBACKMEMBER(int, pfnBusDeliverRC,(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
632 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc));
633 /** @copydoc PDMAPICREG::pfnLocalInterruptR3 */
634 DECLRCCALLBACKMEMBER(int, pfnLocalInterruptRC,(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level));
635 /** @copydoc PDMAPICREG::pfnGetTimerFreqR3 */
636 DECLRCCALLBACKMEMBER(uint64_t, pfnGetTimerFreqRC,(PPDMDEVINS pDevIns));
637} PDMAPIC;
638
639
640/**
641 * PDM registered I/O APIC device.
642 */
643typedef struct PDMIOAPIC
644{
645 /** Pointer to the APIC device instance - R3 Ptr. */
646 PPDMDEVINSR3 pDevInsR3;
647 /** @copydoc PDMIOAPICREG::pfnSetIrqR3 */
648 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
649 /** @copydoc PDMIOAPICREG::pfnSendMsiR3 */
650 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
651
652 /** Pointer to the PIC device instance - R0. */
653 PPDMDEVINSR0 pDevInsR0;
654 /** @copydoc PDMIOAPICREG::pfnSetIrqR3 */
655 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
656 /** @copydoc PDMIOAPICREG::pfnSendMsiR3 */
657 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
658
659 /** Pointer to the APIC device instance - RC Ptr. */
660 PPDMDEVINSRC pDevInsRC;
661 /** @copydoc PDMIOAPICREG::pfnSetIrqR3 */
662 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
663 /** @copydoc PDMIOAPICREG::pfnSendMsiR3 */
664 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
665
666 uint8_t Alignment[4];
667} PDMIOAPIC;
668
669/** Maximum number of PCI busses for a VM. */
670#define PDM_PCI_BUSSES_MAX 8
671
672/**
673 * PDM PCI Bus instance.
674 */
675typedef struct PDMPCIBUS
676{
677 /** PCI bus number. */
678 RTUINT iBus;
679 RTUINT uPadding0; /**< Alignment padding.*/
680
681 /** Pointer to PCI Bus device instance. */
682 PPDMDEVINSR3 pDevInsR3;
683 /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */
684 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
685 /** @copydoc PDMPCIBUSREG::pfnRegisterR3 */
686 DECLR3CALLBACKMEMBER(int, pfnRegisterR3,(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev));
687 /** @copydoc PDMPCIBUSREG::pfnPCIRegisterMsiR3 */
688 DECLR3CALLBACKMEMBER(int, pfnRegisterMsiR3,(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PPDMMSIREG pMsiReg));
689 /** @copydoc PDMPCIBUSREG::pfnIORegionRegisterR3 */
690 DECLR3CALLBACKMEMBER(int, pfnIORegionRegisterR3,(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion,
691 PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback));
692 /** @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3 */
693 DECLR3CALLBACKMEMBER(void, pfnSetConfigCallbacksR3,(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead,
694 PPFNPCICONFIGREAD ppfnReadOld, PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld));
695 /** @copydoc PDMPCIBUSREG::pfnFakePCIBIOSR3 */
696 DECLR3CALLBACKMEMBER(int, pfnFakePCIBIOSR3,(PPDMDEVINS pDevIns));
697
698 /** Pointer to the PIC device instance - R0. */
699 R0PTRTYPE(PPDMDEVINS) pDevInsR0;
700 /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */
701 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
702
703 /** Pointer to PCI Bus device instance. */
704 PPDMDEVINSRC pDevInsRC;
705 /** @copydoc PDMPCIBUSREG::pfnSetIrqR3 */
706 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
707} PDMPCIBUS;
708
709
710#ifdef IN_RING3
711/**
712 * PDM registered DMAC (DMA Controller) device.
713 */
714typedef struct PDMDMAC
715{
716 /** Pointer to the DMAC device instance. */
717 PPDMDEVINSR3 pDevIns;
718 /** Copy of the registration structure. */
719 PDMDMACREG Reg;
720} PDMDMAC;
721
722
723/**
724 * PDM registered RTC (Real Time Clock) device.
725 */
726typedef struct PDMRTC
727{
728 /** Pointer to the RTC device instance. */
729 PPDMDEVINSR3 pDevIns;
730 /** Copy of the registration structure. */
731 PDMRTCREG Reg;
732} PDMRTC;
733
734#endif /* IN_RING3 */
735
736/**
737 * Module type.
738 */
739typedef enum PDMMODTYPE
740{
741 /** Raw-mode (RC) context module. */
742 PDMMOD_TYPE_RC,
743 /** Ring-0 (host) context module. */
744 PDMMOD_TYPE_R0,
745 /** Ring-3 (host) context module. */
746 PDMMOD_TYPE_R3
747} PDMMODTYPE;
748
749
750/** The module name length including the terminator. */
751#define PDMMOD_NAME_LEN 32
752
753/**
754 * Loaded module instance.
755 */
756typedef struct PDMMOD
757{
758 /** Module name. This is used for referring to
759 * the module internally, sort of like a handle. */
760 char szName[PDMMOD_NAME_LEN];
761 /** Module type. */
762 PDMMODTYPE eType;
763 /** Loader module handle. Not used for R0 modules. */
764 RTLDRMOD hLdrMod;
765 /** Loaded address.
766 * This is the 'handle' for R0 modules. */
767 RTUINTPTR ImageBase;
768 /** Old loaded address.
769 * This is used during relocation of GC modules. Not used for R0 modules. */
770 RTUINTPTR OldImageBase;
771 /** Where the R3 HC bits are stored.
772 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
773 void *pvBits;
774
775 /** Pointer to next module. */
776 struct PDMMOD *pNext;
777 /** Module filename. */
778 char szFilename[1];
779} PDMMOD;
780/** Pointer to loaded module instance. */
781typedef PDMMOD *PPDMMOD;
782
783
784
785/** Extra space in the free array. */
786#define PDMQUEUE_FREE_SLACK 16
787
788/**
789 * Queue type.
790 */
791typedef enum PDMQUEUETYPE
792{
793 /** Device consumer. */
794 PDMQUEUETYPE_DEV = 1,
795 /** Driver consumer. */
796 PDMQUEUETYPE_DRV,
797 /** Internal consumer. */
798 PDMQUEUETYPE_INTERNAL,
799 /** External consumer. */
800 PDMQUEUETYPE_EXTERNAL
801} PDMQUEUETYPE;
802
803/** Pointer to a PDM Queue. */
804typedef struct PDMQUEUE *PPDMQUEUE;
805
806/**
807 * PDM Queue.
808 */
809typedef struct PDMQUEUE
810{
811 /** Pointer to the next queue in the list. */
812 R3PTRTYPE(PPDMQUEUE) pNext;
813 /** Type specific data. */
814 union
815 {
816 /** PDMQUEUETYPE_DEV */
817 struct
818 {
819 /** Pointer to consumer function. */
820 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
821 /** Pointer to the device instance owning the queue. */
822 R3PTRTYPE(PPDMDEVINS) pDevIns;
823 } Dev;
824 /** PDMQUEUETYPE_DRV */
825 struct
826 {
827 /** Pointer to consumer function. */
828 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
829 /** Pointer to the driver instance owning the queue. */
830 R3PTRTYPE(PPDMDRVINS) pDrvIns;
831 } Drv;
832 /** PDMQUEUETYPE_INTERNAL */
833 struct
834 {
835 /** Pointer to consumer function. */
836 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
837 } Int;
838 /** PDMQUEUETYPE_EXTERNAL */
839 struct
840 {
841 /** Pointer to consumer function. */
842 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
843 /** Pointer to user argument. */
844 R3PTRTYPE(void *) pvUser;
845 } Ext;
846 } u;
847 /** Queue type. */
848 PDMQUEUETYPE enmType;
849 /** The interval between checking the queue for events.
850 * The realtime timer below is used to do the waiting.
851 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
852 uint32_t cMilliesInterval;
853 /** Interval timer. Only used if cMilliesInterval is non-zero. */
854 PTMTIMERR3 pTimer;
855 /** Pointer to the VM - R3. */
856 PVMR3 pVMR3;
857 /** LIFO of pending items - R3. */
858 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR3;
859 /** Pointer to the VM - R0. */
860 PVMR0 pVMR0;
861 /** LIFO of pending items - R0. */
862 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR0;
863 /** Pointer to the GC VM and indicator for GC enabled queue.
864 * If this is NULL, the queue cannot be used in GC.
865 */
866 PVMRC pVMRC;
867 /** LIFO of pending items - GC. */
868 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingRC;
869
870 /** Item size (bytes). */
871 uint32_t cbItem;
872 /** Number of items in the queue. */
873 uint32_t cItems;
874 /** Index to the free head (where we insert). */
875 uint32_t volatile iFreeHead;
876 /** Index to the free tail (where we remove). */
877 uint32_t volatile iFreeTail;
878
879 /** Unique queue name. */
880 R3PTRTYPE(const char *) pszName;
881#if HC_ARCH_BITS == 32
882 RTR3PTR Alignment1;
883#endif
884 /** Stat: Times PDMQueueAlloc fails. */
885 STAMCOUNTER StatAllocFailures;
886 /** Stat: PDMQueueInsert calls. */
887 STAMCOUNTER StatInsert;
888 /** Stat: Queue flushes. */
889 STAMCOUNTER StatFlush;
890 /** Stat: Queue flushes with pending items left over. */
891 STAMCOUNTER StatFlushLeftovers;
892#ifdef VBOX_WITH_STATISTICS
893 /** State: Profiling the flushing. */
894 STAMPROFILE StatFlushPrf;
895 /** State: Pending items. */
896 uint32_t volatile cStatPending;
897 uint32_t volatile cAlignment;
898#endif
899
900 /** Array of pointers to free items. Variable size. */
901 struct PDMQUEUEFREEITEM
902 {
903 /** Pointer to the free item - HC Ptr. */
904 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR3;
905 /** Pointer to the free item - HC Ptr. */
906 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR0;
907 /** Pointer to the free item - GC Ptr. */
908 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pItemRC;
909#if HC_ARCH_BITS == 64
910 RTRCPTR Alignment0;
911#endif
912 } aFreeItems[1];
913} PDMQUEUE;
914
915/** @name PDM::fQueueFlushing
916 * @{ */
917/** Used to make sure only one EMT will flush the queues.
918 * Set when an EMT is flushing queues, clear otherwise. */
919#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
920/** Indicating there are queues with items pending.
921 * This is make sure we don't miss inserts happening during flushing. The FF
922 * cannot be used for this since it has to be cleared immediately to prevent
923 * other EMTs from spinning. */
924#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
925/** }@ */
926
927
928/**
929 * Queue device helper task operation.
930 */
931typedef enum PDMDEVHLPTASKOP
932{
933 /** The usual invalid 0 entry. */
934 PDMDEVHLPTASKOP_INVALID = 0,
935 /** ISASetIrq */
936 PDMDEVHLPTASKOP_ISA_SET_IRQ,
937 /** PCISetIrq */
938 PDMDEVHLPTASKOP_PCI_SET_IRQ,
939 /** PCISetIrq */
940 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
941 /** The usual 32-bit hack. */
942 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
943} PDMDEVHLPTASKOP;
944
945/**
946 * Queued Device Helper Task.
947 */
948typedef struct PDMDEVHLPTASK
949{
950 /** The queue item core (don't touch). */
951 PDMQUEUEITEMCORE Core;
952 /** Pointer to the device instance (R3 Ptr). */
953 PPDMDEVINSR3 pDevInsR3;
954 /** This operation to perform. */
955 PDMDEVHLPTASKOP enmOp;
956#if HC_ARCH_BITS == 64
957 uint32_t Alignment0;
958#endif
959 /** Parameters to the operation. */
960 union PDMDEVHLPTASKPARAMS
961 {
962 /**
963 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_PCI_SET_IRQ.
964 */
965 struct PDMDEVHLPTASKSETIRQ
966 {
967 /** The IRQ */
968 int iIrq;
969 /** The new level. */
970 int iLevel;
971 /** The IRQ tag and source. */
972 uint32_t uTagSrc;
973 } SetIRQ;
974
975 /** Expanding the structure.. */
976 uint64_t au64[2];
977 } u;
978} PDMDEVHLPTASK;
979/** Pointer to a queued Device Helper Task. */
980typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
981/** Pointer to a const queued Device Helper Task. */
982typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
983
984
985
986/**
987 * An USB hub registration record.
988 */
989typedef struct PDMUSBHUB
990{
991 /** The USB versions this hub support.
992 * Note that 1.1 hubs can take on 2.0 devices. */
993 uint32_t fVersions;
994 /** The number of ports on the hub. */
995 uint32_t cPorts;
996 /** The number of available ports (0..cPorts). */
997 uint32_t cAvailablePorts;
998 /** The driver instance of the hub. */
999 PPDMDRVINS pDrvIns;
1000 /** Copy of the to the registration structure. */
1001 PDMUSBHUBREG Reg;
1002
1003 /** Pointer to the next hub in the list. */
1004 struct PDMUSBHUB *pNext;
1005} PDMUSBHUB;
1006
1007/** Pointer to a const USB HUB registration record. */
1008typedef const PDMUSBHUB *PCPDMUSBHUB;
1009
1010/** Pointer to a PDM Async I/O template. */
1011typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1012
1013/** Pointer to the main PDM Async completion endpoint class. */
1014typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1015
1016/** Pointer to the global block cache structure. */
1017typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1018
1019/**
1020 * PDM VMCPU Instance data.
1021 * Changes to this must checked against the padding of the pdm union in VMCPU!
1022 */
1023typedef struct PDMCPU
1024{
1025 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1026 * in use. */
1027 uint32_t cQueuedCritSectLeaves;
1028 uint32_t uPadding0; /**< Alignment padding.*/
1029 /** Critical sections queued in RC/R0 because of contention preventing leave to
1030 * complete. (R3 Ptrs)
1031 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1032 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1033
1034 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1035 * currently in use. */
1036 uint32_t cQueuedCritSectRwExclLeaves;
1037 uint32_t uPadding1; /**< Alignment padding.*/
1038 /** Read/write critical sections queued in RC/R0 because of contention
1039 * preventing exclusive leave to complete. (R3 Ptrs)
1040 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1041 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1042
1043 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1044 * currently in use. */
1045 uint32_t cQueuedCritSectRwShrdLeaves;
1046 uint32_t uPadding2; /**< Alignment padding.*/
1047 /** Read/write critical sections queued in RC/R0 because of contention
1048 * preventing shared leave to complete. (R3 Ptrs)
1049 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1050 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1051} PDMCPU;
1052
1053
1054/**
1055 * PDM VM Instance data.
1056 * Changes to this must checked against the padding of the cfgm union in VM!
1057 */
1058typedef struct PDM
1059{
1060 /** The PDM lock.
1061 * This is used to protect everything that deals with interrupts, i.e.
1062 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1063 PDMCRITSECT CritSect;
1064 /** The NOP critical section.
1065 * This is a dummy critical section that will not do any thread
1066 * serialization but instead let all threads enter immediately and
1067 * concurrently. */
1068 PDMCRITSECT NopCritSect;
1069
1070 /** List of registered devices. (FIFO) */
1071 R3PTRTYPE(PPDMDEV) pDevs;
1072 /** List of devices instances. (FIFO) */
1073 R3PTRTYPE(PPDMDEVINS) pDevInstances;
1074 /** List of registered USB devices. (FIFO) */
1075 R3PTRTYPE(PPDMUSB) pUsbDevs;
1076 /** List of USB devices instances. (FIFO) */
1077 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1078 /** List of registered drivers. (FIFO) */
1079 R3PTRTYPE(PPDMDRV) pDrvs;
1080 /** PCI Buses. */
1081 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1082 /** The register PIC device. */
1083 PDMPIC Pic;
1084 /** The registered APIC device. */
1085 PDMAPIC Apic;
1086 /** The registered I/O APIC device. */
1087 PDMIOAPIC IoApic;
1088 /** The registered DMAC device. */
1089 R3PTRTYPE(PPDMDMAC) pDmac;
1090 /** The registered RTC device. */
1091 R3PTRTYPE(PPDMRTC) pRtc;
1092 /** The registered USB HUBs. (FIFO) */
1093 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1094
1095 /** Queue in which devhlp tasks are queued for R3 execution - R3 Ptr. */
1096 R3PTRTYPE(PPDMQUEUE) pDevHlpQueueR3;
1097 /** Queue in which devhlp tasks are queued for R3 execution - R0 Ptr. */
1098 R0PTRTYPE(PPDMQUEUE) pDevHlpQueueR0;
1099 /** Queue in which devhlp tasks are queued for R3 execution - RC Ptr. */
1100 RCPTRTYPE(PPDMQUEUE) pDevHlpQueueRC;
1101 /** Pointer to the queue which should be manually flushed - RC Ptr.
1102 * Only touched by EMT. */
1103 RCPTRTYPE(struct PDMQUEUE *) pQueueFlushRC;
1104 /** Pointer to the queue which should be manually flushed - R0 Ptr.
1105 * Only touched by EMT. */
1106 R0PTRTYPE(struct PDMQUEUE *) pQueueFlushR0;
1107 /** Bitmask controlling the queue flushing.
1108 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1109 uint32_t volatile fQueueFlushing;
1110
1111 /** The current IRQ tag (tracing purposes). */
1112 uint32_t volatile uIrqTag;
1113
1114 /** The tracing ID of the next device instance.
1115 *
1116 * @remarks We keep the device tracing ID seperate from the rest as these are
1117 * then more likely to end up with the same ID from one run to
1118 * another, making analysis somewhat easier. Drivers and USB devices
1119 * are more volatile and can be changed at runtime, thus these are much
1120 * less likely to remain stable, so just heap them all together. */
1121 uint32_t idTracingDev;
1122 /** The tracing ID of the next driver instance, USB device instance or other
1123 * PDM entity requiring an ID. */
1124 uint32_t idTracingOther;
1125
1126 /** @name VMM device heap
1127 * @{ */
1128 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1129 RTR3PTR pvVMMDevHeap;
1130 /** The heap size. */
1131 uint32_t cbVMMDevHeap;
1132 /** Free space. */
1133 uint32_t cbVMMDevHeapLeft;
1134 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1135 RTGCPHYS GCPhysVMMDevHeap;
1136 /** @} */
1137
1138 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1139 STAMCOUNTER StatQueuedCritSectLeaves;
1140} PDM;
1141AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1142AssertCompileMemberAlignment(PDM, CritSect, 8);
1143AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1144/** Pointer to PDM VM instance data. */
1145typedef PDM *PPDM;
1146
1147
1148
1149/**
1150 * PDM data kept in the UVM.
1151 */
1152typedef struct PDMUSERPERVM
1153{
1154 /** @todo move more stuff over here. */
1155
1156 /** Linked list of timer driven PDM queues.
1157 * Currently serialized by PDM::CritSect. */
1158 R3PTRTYPE(struct PDMQUEUE *) pQueuesTimer;
1159 /** Linked list of force action driven PDM queues.
1160 * Currently serialized by PDM::CritSect. */
1161 R3PTRTYPE(struct PDMQUEUE *) pQueuesForced;
1162
1163 /** Lock protecting the lists below it. */
1164 RTCRITSECT ListCritSect;
1165 /** Pointer to list of loaded modules. */
1166 PPDMMOD pModules;
1167 /** List of initialized critical sections. (LIFO) */
1168 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1169 /** List of initialized read/write critical sections. (LIFO) */
1170 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1171 /** Head of the PDM Thread list. (singly linked) */
1172 R3PTRTYPE(PPDMTHREAD) pThreads;
1173 /** Tail of the PDM Thread list. (singly linked) */
1174 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1175
1176 /** @name PDM Async Completion
1177 * @{ */
1178 /** Pointer to the array of supported endpoint classes. */
1179 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1180 /** Head of the templates. Singly linked, protected by ListCritSect. */
1181 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1182 /** @} */
1183
1184 /** Global block cache data. */
1185 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1186#ifdef VBOX_WITH_NETSHAPER
1187 /** Pointer to network shaper instance. */
1188 R3PTRTYPE(PPDMNETSHAPER) pNetShaper;
1189#endif /* VBOX_WITH_NETSHAPER */
1190
1191} PDMUSERPERVM;
1192/** Pointer to the PDM data kept in the UVM. */
1193typedef PDMUSERPERVM *PPDMUSERPERVM;
1194
1195
1196
1197/*******************************************************************************
1198* Global Variables *
1199*******************************************************************************/
1200#ifdef IN_RING3
1201extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1202extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1203extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1204extern const PDMPICHLPR3 g_pdmR3DevPicHlp;
1205extern const PDMAPICHLPR3 g_pdmR3DevApicHlp;
1206extern const PDMIOAPICHLPR3 g_pdmR3DevIoApicHlp;
1207extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1208extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1209extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1210extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1211extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1212#endif
1213
1214
1215/*******************************************************************************
1216* Defined Constants And Macros *
1217*******************************************************************************/
1218/** @def PDMDEV_ASSERT_DEVINS
1219 * Asserts the validity of the device instance.
1220 */
1221#ifdef VBOX_STRICT
1222# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1223 do { \
1224 AssertPtr(pDevIns); \
1225 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1226 Assert(pDevIns->CTX_SUFF(pvInstanceData) == (void *)&pDevIns->achInstanceData[0]); \
1227 } while (0)
1228#else
1229# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1230#endif
1231
1232/** @def PDMDRV_ASSERT_DRVINS
1233 * Asserts the validity of the driver instance.
1234 */
1235#ifdef VBOX_STRICT
1236# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1237 do { \
1238 AssertPtr(pDrvIns); \
1239 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1240 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1241 } while (0)
1242#else
1243# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1244#endif
1245
1246
1247/*******************************************************************************
1248* Internal Functions *
1249*******************************************************************************/
1250#ifdef IN_RING3
1251bool pdmR3IsValidName(const char *pszName);
1252
1253int pdmR3CritSectBothInitStats(PVM pVM);
1254void pdmR3CritSectBothRelocate(PVM pVM);
1255int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1256int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1257int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1258 const char *pszNameFmt, va_list va);
1259int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1260 const char *pszNameFmt, ...);
1261int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1262 const char *pszNameFmt, ...);
1263int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1264 const char *pszNameFmt, va_list va);
1265int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1266 const char *pszNameFmt, ...);
1267int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1268 const char *pszNameFmt, ...);
1269
1270int pdmR3DevInit(PVM pVM);
1271PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1272int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1273DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1274
1275int pdmR3UsbLoadModules(PVM pVM);
1276int pdmR3UsbInstantiateDevices(PVM pVM);
1277PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1278int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1279int pdmR3UsbVMInitComplete(PVM pVM);
1280
1281int pdmR3DrvInit(PVM pVM);
1282int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1283 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1284int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1285void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1286PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1287
1288int pdmR3LdrInitU(PUVM pUVM);
1289void pdmR3LdrTermU(PUVM pUVM);
1290char *pdmR3FileR3(const char *pszFile, bool fShared);
1291int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1292
1293void pdmR3QueueRelocate(PVM pVM, RTGCINTPTR offDelta);
1294
1295int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1296 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1297int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1298 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1299int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1300 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1301int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1302int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1303int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1304void pdmR3ThreadDestroyAll(PVM pVM);
1305int pdmR3ThreadResumeAll(PVM pVM);
1306int pdmR3ThreadSuspendAll(PVM pVM);
1307
1308#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1309int pdmR3AsyncCompletionInit(PVM pVM);
1310int pdmR3AsyncCompletionTerm(PVM pVM);
1311void pdmR3AsyncCompletionResume(PVM pVM);
1312int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1313int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1314 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1315int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1316int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1317int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1318int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1319#endif
1320
1321#ifdef VBOX_WITH_NETSHAPER
1322int pdmR3NetShaperInit(PVM pVM);
1323int pdmR3NetShaperTerm(PVM pVM);
1324#endif
1325
1326int pdmR3BlkCacheInit(PVM pVM);
1327void pdmR3BlkCacheTerm(PVM pVM);
1328int pdmR3BlkCacheResume(PVM pVM);
1329
1330#endif /* IN_RING3 */
1331
1332void pdmLock(PVM pVM);
1333int pdmLockEx(PVM pVM, int rc);
1334void pdmUnlock(PVM pVM);
1335
1336#if defined(IN_RING3) || defined(IN_RING0)
1337void pdmCritSectRwLeaveSharedQueued(PPDMCRITSECTRW pThis);
1338void pdmCritSectRwLeaveExclQueued(PPDMCRITSECTRW pThis);
1339#endif
1340
1341/** @} */
1342
1343RT_C_DECLS_END
1344
1345#endif
1346
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