VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 107044

Last change on this file since 107044 was 106061, checked in by vboxsync, 2 months ago

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1/* $Id: PDMInternal.h 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
29#define VMM_INCLUDED_SRC_include_PDMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/param.h>
36#include <VBox/vmm/cfgm.h>
37#include <VBox/vmm/stam.h>
38#include <VBox/vusb.h>
39#include <VBox/vmm/iom.h>
40#include <VBox/vmm/pdmasynccompletion.h>
41#ifdef VBOX_WITH_NETSHAPER
42# include <VBox/vmm/pdmnetshaper.h>
43#endif
44#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
45# include <VBox/vmm/pdmasynccompletion.h>
46#endif
47#include <VBox/vmm/pdmblkcache.h>
48#include <VBox/vmm/pdmcommon.h>
49#include <VBox/vmm/pdmtask.h>
50#include <VBox/sup.h>
51#include <VBox/msi.h>
52#include <iprt/assert.h>
53#include <iprt/critsect.h>
54#ifdef IN_RING3
55# include <iprt/thread.h>
56#endif
57
58RT_C_DECLS_BEGIN
59
60
61/** @defgroup grp_pdm_int Internal
62 * @ingroup grp_pdm
63 * @internal
64 * @{
65 */
66
67/** @def PDM_WITH_R3R0_CRIT_SECT
68 * Enables or disabled ring-3/ring-0 critical sections. */
69#if defined(DOXYGEN_RUNNING) || 1
70# define PDM_WITH_R3R0_CRIT_SECT
71#endif
72
73/** @def PDMCRITSECT_STRICT
74 * Enables/disables PDM critsect strictness like deadlock detection. */
75#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
76 || defined(DOXYGEN_RUNNING)
77# define PDMCRITSECT_STRICT
78#endif
79
80/** @def PDMCRITSECT_STRICT
81 * Enables/disables PDM read/write critsect strictness like deadlock
82 * detection. */
83#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
84 || defined(DOXYGEN_RUNNING)
85# define PDMCRITSECTRW_STRICT
86#endif
87
88/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
89#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
90/** The maximum device instance (total) size, ring-3 only devices. */
91#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
92/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
93#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK HOST_PAGE_SIZE
94
95
96
97/*******************************************************************************
98* Structures and Typedefs *
99*******************************************************************************/
100
101/** Pointer to a PDM Device. */
102typedef struct PDMDEV *PPDMDEV;
103/** Pointer to a pointer to a PDM Device. */
104typedef PPDMDEV *PPPDMDEV;
105
106/** Pointer to a PDM USB Device. */
107typedef struct PDMUSB *PPDMUSB;
108/** Pointer to a pointer to a PDM USB Device. */
109typedef PPDMUSB *PPPDMUSB;
110
111/** Pointer to a PDM Driver. */
112typedef struct PDMDRV *PPDMDRV;
113/** Pointer to a pointer to a PDM Driver. */
114typedef PPDMDRV *PPPDMDRV;
115
116/** Pointer to a PDM Logical Unit. */
117typedef struct PDMLUN *PPDMLUN;
118/** Pointer to a pointer to a PDM Logical Unit. */
119typedef PPDMLUN *PPPDMLUN;
120
121/** Pointer to a DMAC instance. */
122typedef struct PDMDMAC *PPDMDMAC;
123/** Pointer to a RTC instance. */
124typedef struct PDMRTC *PPDMRTC;
125
126/** Pointer to an USB HUB registration record. */
127typedef struct PDMUSBHUB *PPDMUSBHUB;
128
129/**
130 * Supported asynchronous completion endpoint classes.
131 */
132typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
133{
134 /** File class. */
135 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
136 /** Number of supported classes. */
137 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
138 /** 32bit hack. */
139 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
140} PDMASYNCCOMPLETIONEPCLASSTYPE;
141
142
143/**
144 * MMIO/IO port registration tracking structure for DBGF tracing.
145 */
146typedef struct PDMDEVINSDBGFTRACK
147{
148 /** Flag whether this tracks a IO port or MMIO registration. */
149 bool fMmio;
150 /** Opaque user data passed during registration. */
151 void *pvUser;
152 /** Type dependent data. */
153 union
154 {
155 /** I/O port registration. */
156 struct
157 {
158 /** IOM I/O port handle. */
159 IOMIOPORTHANDLE hIoPorts;
160 /** Original OUT handler of the device. */
161 PFNIOMIOPORTNEWOUT pfnOut;
162 /** Original IN handler of the device. */
163 PFNIOMIOPORTNEWIN pfnIn;
164 /** Original string OUT handler of the device. */
165 PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
166 /** Original string IN handler of the device. */
167 PFNIOMIOPORTNEWINSTRING pfnInStr;
168 } IoPort;
169 /** MMIO registration. */
170 struct
171 {
172 /** IOM MMIO region handle. */
173 IOMMMIOHANDLE hMmioRegion;
174 /** Original MMIO write handler of the device. */
175 PFNIOMMMIONEWWRITE pfnWrite;
176 /** Original MMIO read handler of the device. */
177 PFNIOMMMIONEWREAD pfnRead;
178 /** Original MMIO fill handler of the device. */
179 PFNIOMMMIONEWFILL pfnFill;
180 } Mmio;
181 } u;
182} PDMDEVINSDBGFTRACK;
183/** Pointer to a MMIO/IO port registration tracking structure. */
184typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
185/** Pointer to a const MMIO/IO port registration tracking structure. */
186typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
187
188
189/**
190 * Private device instance data, ring-3.
191 */
192typedef struct PDMDEVINSINTR3
193{
194 /** Pointer to the next instance.
195 * (Head is pointed to by PDM::pDevInstances.) */
196 R3PTRTYPE(PPDMDEVINS) pNextR3;
197 /** Pointer to the next per device instance.
198 * (Head is pointed to by PDMDEV::pInstances.) */
199 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
200 /** Pointer to device structure. */
201 R3PTRTYPE(PPDMDEV) pDevR3;
202 /** Pointer to the list of logical units associated with the device. (FIFO) */
203 R3PTRTYPE(PPDMLUN) pLunsR3;
204 /** Pointer to the asynchronous notification callback set while in
205 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
206 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
207 /** Configuration handle to the instance node. */
208 R3PTRTYPE(PCFGMNODE) pCfgHandle;
209
210 /** R3 pointer to the VM this instance was created for. */
211 PVMR3 pVMR3;
212 /** DBGF trace event source handle if tracing is configured. */
213 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
214 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
215 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
216 /** Index of the next entry to use for tracking. */
217 uint32_t idxDbgfTraceTrackNext;
218 /** Maximum number of records fitting into the single page. */
219 uint32_t cDbgfTraceTrackMax;
220
221 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
222 uint32_t fIntFlags;
223 /** The last IRQ tag (for tracing it thru clearing). */
224 uint32_t uLastIrqTag;
225 /** The ring-0 device index (for making ring-0 calls). */
226 uint32_t idxR0Device;
227} PDMDEVINSINTR3;
228
229
230/**
231 * Private device instance data, ring-0.
232 */
233typedef struct PDMDEVINSINTR0
234{
235 /** Pointer to the VM this instance was created for. */
236 R0PTRTYPE(PGVM) pGVM;
237 /** Pointer to device structure. */
238 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
239 /** The ring-0 module reference. */
240 RTR0PTR hMod;
241 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
242 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
243 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
244 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
245 /** DBGF trace event source handle if tracing is configured. */
246 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
247 /** The device instance memory. */
248 RTR0MEMOBJ hMemObj;
249 /** The ring-3 mapping object. */
250 RTR0MEMOBJ hMapObj;
251 /** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
252 RTR0MEMOBJ hDbgfTraceObj;
253 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
254 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
255 /** Index of the next entry to use for tracking. */
256 uint32_t idxDbgfTraceTrackNext;
257 /** Maximum number of records fitting into the single page. */
258 uint32_t cDbgfTraceTrackMax;
259 /** Index into PDMR0PERVM::apDevInstances. */
260 uint32_t idxR0Device;
261} PDMDEVINSINTR0;
262
263
264/**
265 * Private device instance data, raw-mode
266 */
267typedef struct PDMDEVINSINTRC
268{
269 /** Pointer to the VM this instance was created for. */
270 RGPTRTYPE(PVM) pVMRC;
271} PDMDEVINSINTRC;
272
273
274/**
275 * Private device instance data.
276 */
277typedef struct PDMDEVINSINT
278{
279 /** Pointer to the next instance (HC Ptr).
280 * (Head is pointed to by PDM::pDevInstances.) */
281 R3PTRTYPE(PPDMDEVINS) pNextR3;
282 /** Pointer to the next per device instance (HC Ptr).
283 * (Head is pointed to by PDMDEV::pInstances.) */
284 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
285 /** Pointer to device structure - HC Ptr. */
286 R3PTRTYPE(PPDMDEV) pDevR3;
287 /** Pointer to the list of logical units associated with the device. (FIFO) */
288 R3PTRTYPE(PPDMLUN) pLunsR3;
289 /** Pointer to the asynchronous notification callback set while in
290 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
291 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
292 /** Configuration handle to the instance node. */
293 R3PTRTYPE(PCFGMNODE) pCfgHandle;
294
295 /** R3 pointer to the VM this instance was created for. */
296 PVMR3 pVMR3;
297
298 /** R0 pointer to the VM this instance was created for. */
299 R0PTRTYPE(PVMCC) pVMR0;
300
301 /** RC pointer to the VM this instance was created for. */
302 PVMRC pVMRC;
303
304 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
305 uint32_t fIntFlags;
306 /** The last IRQ tag (for tracing it thru clearing). */
307 uint32_t uLastIrqTag;
308} PDMDEVINSINT;
309
310/** @name PDMDEVINSINT::fIntFlags
311 * @{ */
312/** Used by pdmR3Load to mark device instances it found in the saved state. */
313#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
314/** Indicates that the device hasn't been powered on or resumed.
315 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
316 * to make sure each device gets exactly one notification for each of those
317 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
318 * a failure (already resumed/powered-on devices are suspended).
319 * PDMR3PowerOff resets this flag once before going through the devices to make sure
320 * every device gets the power off notification even if it was suspended before with
321 * PDMR3Suspend.
322 */
323#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
324/** Indicates that the device has been reset already. Used by PDMR3Reset. */
325#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
326#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
327#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
328/** Set if we've called the ring-0 constructor. */
329#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
330/** Set if using non-default critical section. */
331#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
332/** @} */
333
334
335/**
336 * Private USB device instance data.
337 */
338typedef struct PDMUSBINSINT
339{
340 /** The UUID of this instance. */
341 RTUUID Uuid;
342 /** Pointer to the next instance.
343 * (Head is pointed to by PDM::pUsbInstances.) */
344 R3PTRTYPE(PPDMUSBINS) pNext;
345 /** Pointer to the next per USB device instance.
346 * (Head is pointed to by PDMUSB::pInstances.) */
347 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
348
349 /** Pointer to device structure. */
350 R3PTRTYPE(PPDMUSB) pUsbDev;
351
352 /** Pointer to the VM this instance was created for. */
353 PVMR3 pVM;
354 /** Pointer to the list of logical units associated with the device. (FIFO) */
355 R3PTRTYPE(PPDMLUN) pLuns;
356 /** The per instance device configuration. */
357 R3PTRTYPE(PCFGMNODE) pCfg;
358 /** Same as pCfg if the configuration should be deleted when detaching the device. */
359 R3PTRTYPE(PCFGMNODE) pCfgDelete;
360 /** The global device configuration. */
361 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
362
363 /** Pointer to the USB hub this device is attached to.
364 * This is NULL if the device isn't connected to any HUB. */
365 R3PTRTYPE(PPDMUSBHUB) pHub;
366 /** The port number that we're connected to. */
367 uint32_t iPort;
368 /** Indicates that the USB device hasn't been powered on or resumed.
369 * See PDMDEVINSINT_FLAGS_SUSPENDED.
370 * @note Runtime attached USB devices gets a pfnHotPlugged callback rather than
371 * a pfnVMResume one. */
372 bool fVMSuspended;
373 /** Indicates that the USB device has been reset. */
374 bool fVMReset;
375 /** Pointer to the asynchronous notification callback set while in
376 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
377 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
378} PDMUSBINSINT;
379
380
381/**
382 * Private driver instance data.
383 */
384typedef struct PDMDRVINSINT
385{
386 /** Pointer to the driver instance above.
387 * This is NULL for the topmost drive. */
388 R3PTRTYPE(PPDMDRVINS) pUp;
389 /** Pointer to the driver instance below.
390 * This is NULL for the bottommost driver. */
391 R3PTRTYPE(PPDMDRVINS) pDown;
392 /** Pointer to the logical unit this driver chained on. */
393 R3PTRTYPE(PPDMLUN) pLun;
394 /** Pointer to driver structure from which this was instantiated. */
395 R3PTRTYPE(PPDMDRV) pDrv;
396 /** Pointer to the VM this instance was created for, ring-3 context. */
397 PVMR3 pVMR3;
398 /** Pointer to the VM this instance was created for, ring-0 context. */
399 R0PTRTYPE(PVMCC) pVMR0;
400 /** Pointer to the VM this instance was created for, raw-mode context. */
401 PVMRC pVMRC;
402 /** Flag indicating that the driver is being detached and destroyed.
403 * (Helps detect potential recursive detaching.) */
404 bool fDetaching;
405 /** Indicates that the driver hasn't been powered on or resumed.
406 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
407 bool fVMSuspended;
408 /** Indicates that the driver has been reset already. */
409 bool fVMReset;
410 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
411 bool fHyperHeap;
412 /** Pointer to the asynchronous notification callback set while in
413 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
414 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
415 /** Configuration handle to the instance node. */
416 R3PTRTYPE(PCFGMNODE) pCfgHandle;
417 /** Pointer to the ring-0 request handler function. */
418 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
419 /** Pointer to the next instance (starts at PDMDRV::pInstances). */
420 R3PTRTYPE(PPDMDRVINS) pNext;
421} PDMDRVINSINT;
422
423
424/**
425 * Private critical section data.
426 */
427typedef struct PDMCRITSECTINT
428{
429 /** The critical section core which is shared with IPRT.
430 * @note The semaphore is a SUPSEMEVENT. */
431 RTCRITSECT Core;
432 /** Pointer to the next critical section.
433 * This chain is used for device cleanup and the dbgf info item. */
434 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
435 /** Owner identifier.
436 * This is pDevIns if the owner is a device. Similarly for a driver or service.
437 * PDMR3CritSectInit() sets this to point to the critsect itself. */
438 RTR3PTR pvKey;
439 /** Set if this critical section is the automatically created default
440 * section of a device. */
441 bool fAutomaticDefaultCritsect;
442 /** Set if the critical section is used by a timer or similar.
443 * See PDMR3DevGetCritSect. */
444 bool fUsedByTimerOrSimilar;
445 /** Alignment padding. */
446 bool afPadding[2+4];
447 /** Support driver event semaphore that is scheduled to be signaled upon leaving
448 * the critical section. This is only for Ring-3 and Ring-0. */
449 SUPSEMEVENT volatile hEventToSignal;
450 /** The lock name. */
451 R3PTRTYPE(const char *) pszName;
452 /** The ring-3 pointer to this critical section, for leave queueing. */
453 R3PTRTYPE(PPDMCRITSECT) pSelfR3;
454 /** R0/RC lock contention. */
455 STAMCOUNTER StatContentionRZLock;
456 /** R0/RC lock contention: returning rcBusy or VERR_SEM_BUSY (try). */
457 STAMCOUNTER StatContentionRZLockBusy;
458 /** R0/RC lock contention: Profiling waiting time. */
459 STAMPROFILE StatContentionRZWait;
460 /** R0/RC unlock contention. */
461 STAMCOUNTER StatContentionRZUnlock;
462 /** R3 lock contention. */
463 STAMCOUNTER StatContentionR3;
464 /** R3 lock contention: Profiling waiting time. */
465 STAMPROFILE StatContentionR3Wait;
466 /** Profiling the time the section is locked. */
467 STAMPROFILEADV StatLocked;
468} PDMCRITSECTINT;
469AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
470/** Pointer to private critical section data. */
471typedef PDMCRITSECTINT *PPDMCRITSECTINT;
472
473/** Special magic value set when we failed to abort entering in ring-0 due to a
474 * timeout, interruption or pending thread termination. */
475#define PDMCRITSECT_MAGIC_FAILED_ABORT UINT32_C(0x0bad0326)
476/** Special magic value set if we detected data/state corruption. */
477#define PDMCRITSECT_MAGIC_CORRUPTED UINT32_C(0x0bad2603)
478
479/** Indicates that the critical section is queued for unlock.
480 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
481#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
482
483
484/**
485 * Private critical section data.
486 */
487typedef struct PDMCRITSECTRWINT
488{
489 /** The read/write critical section core which is shared with IPRT.
490 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
491 RTCRITSECTRW Core;
492
493 /** Pointer to the next critical section.
494 * This chain is used for device cleanup and the dbgf info item. */
495 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
496 /** Self pointer. */
497 R3PTRTYPE(PPDMCRITSECTRW) pSelfR3;
498 /** Owner identifier.
499 * This is pDevIns if the owner is a device. Similarly for a driver or service.
500 * PDMR3CritSectRwInit() sets this to point to the critsect itself. */
501 RTR3PTR pvKey;
502 /** The lock name. */
503 R3PTRTYPE(const char *) pszName;
504
505 /** R0/RC write lock contention. */
506 STAMCOUNTER StatContentionRZEnterExcl;
507 /** R0/RC write unlock contention. */
508 STAMCOUNTER StatContentionRZLeaveExcl;
509 /** R0/RC read lock contention. */
510 STAMCOUNTER StatContentionRZEnterShared;
511 /** R0/RC read unlock contention. */
512 STAMCOUNTER StatContentionRZLeaveShared;
513 /** R0/RC writes. */
514 STAMCOUNTER StatRZEnterExcl;
515 /** R0/RC reads. */
516 STAMCOUNTER StatRZEnterShared;
517 /** R3 write lock contention. */
518 STAMCOUNTER StatContentionR3EnterExcl;
519 /** R3 write unlock contention. */
520 STAMCOUNTER StatContentionR3LeaveExcl;
521 /** R3 read lock contention. */
522 STAMCOUNTER StatContentionR3EnterShared;
523 /** R3 writes. */
524 STAMCOUNTER StatR3EnterExcl;
525 /** R3 reads. */
526 STAMCOUNTER StatR3EnterShared;
527 /** Profiling the time the section is write locked. */
528 STAMPROFILEADV StatWriteLocked;
529} PDMCRITSECTRWINT;
530AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
531AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u, 16);
532AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u.s.u64State, 8);
533/** Pointer to private critical section data. */
534typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
535
536/** Special magic value we set the structure has become corrupted. */
537#define PDMCRITSECTRW_MAGIC_CORRUPT UINT32_C(0x0bad0620)
538
539
540/**
541 * The usual device/driver/internal/external stuff.
542 */
543typedef enum
544{
545 /** The usual invalid entry. */
546 PDMTHREADTYPE_INVALID = 0,
547 /** Device type. */
548 PDMTHREADTYPE_DEVICE,
549 /** USB Device type. */
550 PDMTHREADTYPE_USB,
551 /** Driver type. */
552 PDMTHREADTYPE_DRIVER,
553 /** Internal type. */
554 PDMTHREADTYPE_INTERNAL,
555 /** External type. */
556 PDMTHREADTYPE_EXTERNAL,
557 /** The usual 32-bit hack. */
558 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
559} PDMTHREADTYPE;
560
561
562/**
563 * The internal structure for the thread.
564 */
565typedef struct PDMTHREADINT
566{
567 /** The VM pointer. */
568 PVMR3 pVM;
569 /** The event semaphore the thread blocks on when not running. */
570 RTSEMEVENTMULTI BlockEvent;
571 /** The event semaphore the thread sleeps on while running. */
572 RTSEMEVENTMULTI SleepEvent;
573 /** Pointer to the next thread. */
574 R3PTRTYPE(struct PDMTHREAD *) pNext;
575 /** The thread type. */
576 PDMTHREADTYPE enmType;
577} PDMTHREADINT;
578
579
580
581/* Must be included after PDMDEVINSINT is defined. */
582#define PDMDEVINSINT_DECLARED
583#define PDMUSBINSINT_DECLARED
584#define PDMDRVINSINT_DECLARED
585#define PDMCRITSECTINT_DECLARED
586#define PDMCRITSECTRWINT_DECLARED
587#define PDMTHREADINT_DECLARED
588#ifdef ___VBox_pdm_h
589# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
590#endif
591RT_C_DECLS_END
592#include <VBox/vmm/pdm.h>
593RT_C_DECLS_BEGIN
594
595/**
596 * PDM Logical Unit.
597 *
598 * This typically the representation of a physical port on a
599 * device, like for instance the PS/2 keyboard port on the
600 * keyboard controller device. The LUNs are chained on the
601 * device they belong to (PDMDEVINSINT::pLunsR3).
602 */
603typedef struct PDMLUN
604{
605 /** The LUN - The Logical Unit Number. */
606 RTUINT iLun;
607 /** Pointer to the next LUN. */
608 PPDMLUN pNext;
609 /** Pointer to the top driver in the driver chain. */
610 PPDMDRVINS pTop;
611 /** Pointer to the bottom driver in the driver chain. */
612 PPDMDRVINS pBottom;
613 /** Pointer to the device instance which the LUN belongs to.
614 * Either this is set or pUsbIns is set. Both are never set at the same time. */
615 PPDMDEVINS pDevIns;
616 /** Pointer to the USB device instance which the LUN belongs to. */
617 PPDMUSBINS pUsbIns;
618 /** Pointer to the device base interface. */
619 PPDMIBASE pBase;
620 /** Description of this LUN. */
621 const char *pszDesc;
622} PDMLUN;
623
624
625/**
626 * PDM Device, ring-3.
627 */
628typedef struct PDMDEV
629{
630 /** Pointer to the next device (R3 Ptr). */
631 R3PTRTYPE(PPDMDEV) pNext;
632 /** Device name length. (search optimization) */
633 uint32_t cchName;
634 /** Registration structure. */
635 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
636 /** Number of instances. */
637 uint32_t cInstances;
638 /** Pointer to chain of instances (R3 Ptr). */
639 PPDMDEVINSR3 pInstances;
640 /** The search path for raw-mode context modules (';' as separator). */
641 char *pszRCSearchPath;
642 /** The search path for ring-0 context modules (';' as separator). */
643 char *pszR0SearchPath;
644} PDMDEV;
645
646
647#if 0
648/**
649 * PDM Device, ring-0.
650 */
651typedef struct PDMDEVR0
652{
653 /** Pointer to the next device. */
654 R0PTRTYPE(PPDMDEVR0) pNext;
655 /** Device name length. (search optimization) */
656 uint32_t cchName;
657 /** Registration structure. */
658 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
659 /** Number of instances. */
660 uint32_t cInstances;
661 /** Pointer to chain of instances. */
662 PPDMDEVINSR0 pInstances;
663} PDMDEVR0;
664#endif
665
666
667/**
668 * PDM USB Device.
669 */
670typedef struct PDMUSB
671{
672 /** Pointer to the next device (R3 Ptr). */
673 R3PTRTYPE(PPDMUSB) pNext;
674 /** Device name length. (search optimization) */
675 RTUINT cchName;
676 /** Registration structure. */
677 R3PTRTYPE(const struct PDMUSBREG *) pReg;
678 /** Next instance number. */
679 uint32_t iNextInstance;
680 /** Pointer to chain of instances (R3 Ptr). */
681 R3PTRTYPE(PPDMUSBINS) pInstances;
682} PDMUSB;
683
684
685/**
686 * PDM Driver.
687 */
688typedef struct PDMDRV
689{
690 /** Pointer to the next device. */
691 PPDMDRV pNext;
692 /** Registration structure. */
693 const struct PDMDRVREG * pReg;
694 /** Current number of instances. */
695 uint32_t cInstances;
696 /** The next instance number. */
697 uint32_t iNextInstance;
698 /** The search path for raw-mode context modules (';' as separator). */
699 char *pszRCSearchPath;
700 /** The search path for ring-0 context modules (';' as separator). */
701 char *pszR0SearchPath;
702 /** Pointer to chain of instances. */
703 PPDMDRVINSR3 pInstances;
704} PDMDRV;
705
706
707/**
708 * PDM IOMMU, shared ring-3.
709 */
710typedef struct PDMIOMMUR3
711{
712 /** IOMMU index. */
713 uint32_t idxIommu;
714 uint32_t uPadding0; /**< Alignment padding.*/
715
716 /** Pointer to the IOMMU device instance - R3. */
717 PPDMDEVINSR3 pDevInsR3;
718 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
719 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
720 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
721 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
722 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
723 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
724 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
725 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
726} PDMIOMMUR3;
727/** Pointer to a PDM IOMMU instance. */
728typedef PDMIOMMUR3 *PPDMIOMMUR3;
729/** Pointer to a const PDM IOMMU instance. */
730typedef const PDMIOMMUR3 *PCPDMIOMMUR3;
731
732
733/**
734 * PDM IOMMU, ring-0.
735 */
736typedef struct PDMIOMMUR0
737{
738 /** IOMMU index. */
739 uint32_t idxIommu;
740 uint32_t uPadding0; /**< Alignment padding.*/
741
742 /** Pointer to IOMMU device instance. */
743 PPDMDEVINSR0 pDevInsR0;
744 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
745 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
746 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
747 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
748 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
749 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
750 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
751 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
752} PDMIOMMUR0;
753/** Pointer to a ring-0 IOMMU data. */
754typedef PDMIOMMUR0 *PPDMIOMMUR0;
755/** Pointer to a const ring-0 IOMMU data. */
756typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
757
758/** Pointer to a PDM IOMMU for the current context. */
759#ifdef IN_RING3
760typedef PPDMIOMMUR3 PPDMIOMMU;
761#else
762typedef PPDMIOMMUR0 PPDMIOMMU;
763#endif
764
765
766/**
767 * PDM registered PIC device.
768 */
769typedef struct PDMPIC
770{
771 /** Pointer to the PIC device instance - R3. */
772 PPDMDEVINSR3 pDevInsR3;
773 /** @copydoc PDMPICREG::pfnSetIrq */
774 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
775 /** @copydoc PDMPICREG::pfnGetInterrupt */
776 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
777
778 /** Pointer to the PIC device instance - R0. */
779 PPDMDEVINSR0 pDevInsR0;
780 /** @copydoc PDMPICREG::pfnSetIrq */
781 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
782 /** @copydoc PDMPICREG::pfnGetInterrupt */
783 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
784
785 /** Pointer to the PIC device instance - RC. */
786 PPDMDEVINSRC pDevInsRC;
787 /** @copydoc PDMPICREG::pfnSetIrq */
788 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
789 /** @copydoc PDMPICREG::pfnGetInterrupt */
790 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
791 /** Alignment padding. */
792 RTRCPTR RCPtrPadding;
793} PDMPIC;
794
795
796/**
797 * PDM registered APIC device.
798 */
799typedef struct PDMAPIC
800{
801 /** Pointer to the APIC device instance - R3 Ptr. */
802 PPDMDEVINSR3 pDevInsR3;
803 /** Pointer to the APIC device instance - R0 Ptr. */
804 PPDMDEVINSR0 pDevInsR0;
805 /** Pointer to the APIC device instance - RC Ptr. */
806 PPDMDEVINSRC pDevInsRC;
807 uint8_t Alignment[4];
808} PDMAPIC;
809
810
811/**
812 * PDM registered I/O APIC device.
813 */
814typedef struct PDMIOAPIC
815{
816 /** Pointer to the I/O APIC device instance - R3 Ptr. */
817 PPDMDEVINSR3 pDevInsR3;
818 /** @copydoc PDMIOAPICREG::pfnSetIrq */
819 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
820 /** @copydoc PDMIOAPICREG::pfnSendMsi */
821 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
822 /** @copydoc PDMIOAPICREG::pfnSetEoi */
823 DECLR3CALLBACKMEMBER(void, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
824
825 /** Pointer to the I/O APIC device instance - R0. */
826 PPDMDEVINSR0 pDevInsR0;
827 /** @copydoc PDMIOAPICREG::pfnSetIrq */
828 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
829 /** @copydoc PDMIOAPICREG::pfnSendMsi */
830 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
831 /** @copydoc PDMIOAPICREG::pfnSetEoi */
832 DECLR0CALLBACKMEMBER(void, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
833
834 /** Pointer to the I/O APIC device instance - RC Ptr. */
835 PPDMDEVINSRC pDevInsRC;
836 /** @copydoc PDMIOAPICREG::pfnSetIrq */
837 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
838 /** @copydoc PDMIOAPICREG::pfnSendMsi */
839 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
840 /** @copydoc PDMIOAPICREG::pfnSendMsi */
841 DECLRCCALLBACKMEMBER(void, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
842} PDMIOAPIC;
843/** Pointer to a PDM IOAPIC instance. */
844typedef PDMIOAPIC *PPDMIOAPIC;
845/** Pointer to a const PDM IOAPIC instance. */
846typedef PDMIOAPIC const *PCPDMIOAPIC;
847
848/** Maximum number of PCI busses for a VM. */
849#define PDM_PCI_BUSSES_MAX 8
850/** Maximum number of IOMMUs (at most one per PCI bus). */
851#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
852
853
854#ifdef IN_RING3
855/**
856 * PDM registered firmware device.
857 */
858typedef struct PDMFW
859{
860 /** Pointer to the firmware device instance. */
861 PPDMDEVINSR3 pDevIns;
862 /** Copy of the registration structure. */
863 PDMFWREG Reg;
864} PDMFW;
865/** Pointer to a firmware instance. */
866typedef PDMFW *PPDMFW;
867#endif
868
869
870/**
871 * PDM PCI bus instance.
872 */
873typedef struct PDMPCIBUS
874{
875 /** PCI bus number. */
876 uint32_t iBus;
877 uint32_t uPadding0; /**< Alignment padding.*/
878
879 /** Pointer to PCI bus device instance. */
880 PPDMDEVINSR3 pDevInsR3;
881 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
882 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
883
884 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
885 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
886 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
887 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
888 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
889 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
890 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
891 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
892 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
893 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
894 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
895 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
896 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
897 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
898 uint32_t uAddress, unsigned cb, uint32_t u32Value));
899 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
900 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
901 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
902} PDMPCIBUS;
903/** Pointer to a PDM PCI Bus instance. */
904typedef PDMPCIBUS *PPDMPCIBUS;
905/** Pointer to a const PDM PCI Bus instance. */
906typedef const PDMPCIBUS *PCPDMPCIBUS;
907
908
909/**
910 * Ring-0 PDM PCI bus instance data.
911 */
912typedef struct PDMPCIBUSR0
913{
914 /** PCI bus number. */
915 uint32_t iBus;
916 uint32_t uPadding0; /**< Alignment padding.*/
917 /** Pointer to PCI bus device instance. */
918 PPDMDEVINSR0 pDevInsR0;
919 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
920 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
921} PDMPCIBUSR0;
922/** Pointer to the ring-0 PCI bus data. */
923typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
924/** Pointer to the const ring-0 PCI bus data. */
925typedef const PDMPCIBUSR0 *PCPDMPCIBUSR0;
926
927
928#ifdef IN_RING3
929/**
930 * PDM registered DMAC (DMA Controller) device.
931 */
932typedef struct PDMDMAC
933{
934 /** Pointer to the DMAC device instance. */
935 PPDMDEVINSR3 pDevIns;
936 /** Copy of the registration structure. */
937 PDMDMACREG Reg;
938} PDMDMAC;
939
940
941/**
942 * PDM registered RTC (Real Time Clock) device.
943 */
944typedef struct PDMRTC
945{
946 /** Pointer to the RTC device instance. */
947 PPDMDEVINSR3 pDevIns;
948 /** Copy of the registration structure. */
949 PDMRTCREG Reg;
950} PDMRTC;
951
952#endif /* IN_RING3 */
953
954/**
955 * Module type.
956 */
957typedef enum PDMMODTYPE
958{
959 /** Raw-mode (RC) context module. */
960 PDMMOD_TYPE_RC,
961 /** Ring-0 (host) context module. */
962 PDMMOD_TYPE_R0,
963 /** Ring-3 (host) context module. */
964 PDMMOD_TYPE_R3
965} PDMMODTYPE;
966
967
968/** The module name length including the terminator. */
969#define PDMMOD_NAME_LEN 32
970
971/**
972 * Loaded module instance.
973 */
974typedef struct PDMMOD
975{
976 /** Module name. This is used for referring to
977 * the module internally, sort of like a handle. */
978 char szName[PDMMOD_NAME_LEN];
979 /** Module type. */
980 PDMMODTYPE eType;
981 /** Loader module handle. Not used for R0 modules. */
982 RTLDRMOD hLdrMod;
983 /** Loaded address.
984 * This is the 'handle' for R0 modules. */
985 RTUINTPTR ImageBase;
986 /** Old loaded address.
987 * This is used during relocation of GC modules. Not used for R0 modules. */
988 RTUINTPTR OldImageBase;
989 /** Where the R3 HC bits are stored.
990 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
991 void *pvBits;
992
993 /** Pointer to next module. */
994 struct PDMMOD *pNext;
995 /** Module filename. */
996 char szFilename[1];
997} PDMMOD;
998/** Pointer to loaded module instance. */
999typedef PDMMOD *PPDMMOD;
1000
1001
1002
1003/** Max number of items in a queue. */
1004#define PDMQUEUE_MAX_ITEMS _16K
1005/** Max item size. */
1006#define PDMQUEUE_MAX_ITEM_SIZE _1M
1007/** Max total queue item size for ring-0 capable queues. */
1008#define PDMQUEUE_MAX_TOTAL_SIZE_R0 _8M
1009/** Max total queue item size for ring-3 only queues. */
1010#define PDMQUEUE_MAX_TOTAL_SIZE_R3 _32M
1011
1012/**
1013 * Queue type.
1014 */
1015typedef enum PDMQUEUETYPE
1016{
1017 /** Device consumer. */
1018 PDMQUEUETYPE_DEV = 1,
1019 /** Driver consumer. */
1020 PDMQUEUETYPE_DRV,
1021 /** Internal consumer. */
1022 PDMQUEUETYPE_INTERNAL,
1023 /** External consumer. */
1024 PDMQUEUETYPE_EXTERNAL
1025} PDMQUEUETYPE;
1026
1027/**
1028 * PDM Queue.
1029 */
1030typedef struct PDMQUEUE
1031{
1032 /** Magic value (PDMQUEUE_MAGIC). */
1033 uint32_t u32Magic;
1034 /** Item size (bytes). */
1035 uint32_t cbItem;
1036 /** Number of items in the queue. */
1037 uint32_t cItems;
1038 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1039 uint32_t offItems;
1040
1041 /** Interval timer. Only used if cMilliesInterval is non-zero. */
1042 TMTIMERHANDLE hTimer;
1043 /** The interval between checking the queue for events.
1044 * The realtime timer below is used to do the waiting.
1045 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1046 uint32_t cMilliesInterval;
1047
1048 /** This is VINF_SUCCESS if the queue is okay, error status if not. */
1049 int32_t rcOkay;
1050 uint32_t u32Padding;
1051
1052 /** Queue type. */
1053 PDMQUEUETYPE enmType;
1054 /** Type specific data. */
1055 union
1056 {
1057 /** PDMQUEUETYPE_DEV */
1058 struct
1059 {
1060 /** Pointer to consumer function. */
1061 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1062 /** Pointer to the device instance owning the queue. */
1063 R3PTRTYPE(PPDMDEVINS) pDevIns;
1064 } Dev;
1065 /** PDMQUEUETYPE_DRV */
1066 struct
1067 {
1068 /** Pointer to consumer function. */
1069 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1070 /** Pointer to the driver instance owning the queue. */
1071 R3PTRTYPE(PPDMDRVINS) pDrvIns;
1072 } Drv;
1073 /** PDMQUEUETYPE_INTERNAL */
1074 struct
1075 {
1076 /** Pointer to consumer function. */
1077 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1078 } Int;
1079 /** PDMQUEUETYPE_EXTERNAL */
1080 struct
1081 {
1082 /** Pointer to consumer function. */
1083 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1084 /** Pointer to user argument. */
1085 R3PTRTYPE(void *) pvUser;
1086 } Ext;
1087 struct
1088 {
1089 /** Generic callback pointer. */
1090 RTR3PTR pfnCallback;
1091 /** Generic owner pointer. */
1092 RTR3PTR pvOwner;
1093 } Gen;
1094 } u;
1095
1096 /** Unique queue name. */
1097 char szName[40];
1098
1099 /** LIFO of pending items (item index), UINT32_MAX if empty. */
1100 uint32_t volatile iPending;
1101
1102 /** State: Pending items. */
1103 uint32_t volatile cStatPending;
1104 /** Stat: Times PDMQueueAlloc fails. */
1105 STAMCOUNTER StatAllocFailures;
1106 /** Stat: PDMQueueInsert calls. */
1107 STAMCOUNTER StatInsert;
1108 /** Stat: Queue flushes. */
1109 STAMCOUNTER StatFlush;
1110 /** Stat: Queue flushes with pending items left over. */
1111 STAMCOUNTER StatFlushLeftovers;
1112 /** State: Profiling the flushing. */
1113 STAMPROFILE StatFlushPrf;
1114 uint64_t au64Padding[3];
1115
1116 /** Allocation bitmap: Set bits means free, clear means allocated. */
1117 RT_FLEXIBLE_ARRAY_EXTENSION
1118 uint64_t bmAlloc[RT_FLEXIBLE_ARRAY];
1119 /* The items follows after the end of the bitmap */
1120} PDMQUEUE;
1121AssertCompileMemberAlignment(PDMQUEUE, bmAlloc, 64);
1122/** Pointer to a PDM Queue. */
1123typedef struct PDMQUEUE *PPDMQUEUE;
1124
1125/** Magic value PDMQUEUE::u32Magic (Bud Powell). */
1126#define PDMQUEUE_MAGIC UINT32_C(0x19240927)
1127/** Magic value PDMQUEUE::u32Magic after destroy. */
1128#define PDMQUEUE_MAGIC_DEAD UINT32_C(0x19660731)
1129
1130/** @name PDM::fQueueFlushing
1131 * @{ */
1132/** Used to make sure only one EMT will flush the queues.
1133 * Set when an EMT is flushing queues, clear otherwise. */
1134#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1135/** Indicating there are queues with items pending.
1136 * This is make sure we don't miss inserts happening during flushing. The FF
1137 * cannot be used for this since it has to be cleared immediately to prevent
1138 * other EMTs from spinning. */
1139#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1140/** @} */
1141
1142/**
1143 * Ring-0 queue
1144 *
1145 * @author bird (2022-02-04)
1146 */
1147typedef struct PDMQUEUER0
1148{
1149 /** Pointer to the shared queue data. */
1150 R0PTRTYPE(PPDMQUEUE) pQueue;
1151 /** The memory allocation. */
1152 RTR0MEMOBJ hMemObj;
1153 /** The ring-3 mapping object. */
1154 RTR0MEMOBJ hMapObj;
1155 /** The owner pointer. This is NULL if not allocated. */
1156 RTR0PTR pvOwner;
1157 /** Queue item size. */
1158 uint32_t cbItem;
1159 /** Number of queue items. */
1160 uint32_t cItems;
1161 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1162 uint32_t offItems;
1163 uint32_t u32Reserved;
1164} PDMQUEUER0;
1165
1166
1167/** @name PDM task structures.
1168 * @{ */
1169
1170/**
1171 * A asynchronous user mode task.
1172 */
1173typedef struct PDMTASK
1174{
1175 /** Task owner type. */
1176 PDMTASKTYPE volatile enmType;
1177 /** Queue flags. */
1178 uint32_t volatile fFlags;
1179 /** User argument for the callback. */
1180 R3PTRTYPE(void *) volatile pvUser;
1181 /** The callback (will be cast according to enmType before callout). */
1182 R3PTRTYPE(PFNRT) volatile pfnCallback;
1183 /** The owner identifier. */
1184 R3PTRTYPE(void *) volatile pvOwner;
1185 /** Task name. */
1186 R3PTRTYPE(const char *) pszName;
1187 /** Number of times already triggered when PDMTaskTrigger was called. */
1188 uint32_t volatile cAlreadyTrigged;
1189 /** Number of runs. */
1190 uint32_t cRuns;
1191} PDMTASK;
1192/** Pointer to a PDM task. */
1193typedef PDMTASK *PPDMTASK;
1194
1195/**
1196 * A task set.
1197 *
1198 * This is served by one task executor thread.
1199 */
1200typedef struct PDMTASKSET
1201{
1202 /** Magic value (PDMTASKSET_MAGIC). */
1203 uint32_t u32Magic;
1204 /** Set if this task set works for ring-0 and raw-mode. */
1205 bool fRZEnabled;
1206 /** Number of allocated taks. */
1207 uint8_t volatile cAllocated;
1208 /** Base handle value for this set. */
1209 uint16_t uHandleBase;
1210 /** The task executor thread. */
1211 R3PTRTYPE(RTTHREAD) hThread;
1212 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1213 SUPSEMEVENT hEventR0;
1214 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1215 R3PTRTYPE(RTSEMEVENT) hEventR3;
1216 /** The VM pointer. */
1217 PVM pVM;
1218 /** Padding so fTriggered is in its own cacheline. */
1219 uint64_t au64Padding2[3];
1220
1221 /** Bitmask of triggered tasks. */
1222 uint64_t volatile fTriggered;
1223 /** Shutdown thread indicator. */
1224 bool volatile fShutdown;
1225 /** Padding. */
1226 bool volatile afPadding3[3];
1227 /** Task currently running, UINT32_MAX if idle. */
1228 uint32_t volatile idxRunning;
1229 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1230 uint64_t volatile au64Padding3[6];
1231
1232 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1233 PDMTASK aTasks[64];
1234} PDMTASKSET;
1235AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1236AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1237/** Magic value for PDMTASKSET::u32Magic (Quincy Delight Jones Jr.). */
1238#define PDMTASKSET_MAGIC UINT32_C(0x19330314)
1239/** Pointer to a task set. */
1240typedef PDMTASKSET *PPDMTASKSET;
1241
1242/** @} */
1243
1244
1245/** @name PDM Network Shaper
1246 * @{ */
1247
1248/**
1249 * Bandwidth group.
1250 */
1251typedef struct PDMNSBWGROUP
1252{
1253 /** Critical section protecting all members below. */
1254 PDMCRITSECT Lock;
1255 /** List of filters in this group (PDMNSFILTER). */
1256 RTLISTANCHORR3 FilterList;
1257 /** Reference counter - How many filters are associated with this group. */
1258 volatile uint32_t cRefs;
1259 uint32_t uPadding1;
1260 /** The group name. */
1261 char szName[PDM_NET_SHAPER_MAX_NAME_LEN + 1];
1262 /** Maximum number of bytes filters are allowed to transfer. */
1263 volatile uint64_t cbPerSecMax;
1264 /** Number of bytes we are allowed to transfer in one burst. */
1265 volatile uint32_t cbBucket;
1266 /** Number of bytes we were allowed to transfer at the last update. */
1267 volatile uint32_t cbTokensLast;
1268 /** Timestamp of the last update */
1269 volatile uint64_t tsUpdatedLast;
1270 /** Number of times a filter was choked. */
1271 volatile uint64_t cTotalChokings;
1272 /** Pad the structure to a multiple of 64 bytes. */
1273 uint64_t au64Padding[1];
1274} PDMNSBWGROUP;
1275AssertCompileSizeAlignment(PDMNSBWGROUP, 64);
1276/** Pointer to a bandwidth group. */
1277typedef PDMNSBWGROUP *PPDMNSBWGROUP;
1278
1279/** @} */
1280
1281
1282/**
1283 * Queue device helper task operation.
1284 */
1285typedef enum PDMDEVHLPTASKOP
1286{
1287 /** The usual invalid 0 entry. */
1288 PDMDEVHLPTASKOP_INVALID = 0,
1289 /** IsaSetIrq, IoApicSetIrq */
1290 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1291 /** PciSetIrq */
1292 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1293 /** PciSetIrq */
1294 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1295 /** IoApicSendMsi */
1296 PDMDEVHLPTASKOP_IOAPIC_SEND_MSI,
1297 /** IoApicSettEoi */
1298 PDMDEVHLPTASKOP_IOAPIC_SET_EOI,
1299 /** The usual 32-bit hack. */
1300 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1301} PDMDEVHLPTASKOP;
1302
1303/**
1304 * Queued Device Helper Task.
1305 */
1306typedef struct PDMDEVHLPTASK
1307{
1308 /** The queue item core (don't touch). */
1309 PDMQUEUEITEMCORE Core;
1310 /** Pointer to the device instance (R3 Ptr). */
1311 PPDMDEVINSR3 pDevInsR3;
1312 /** This operation to perform. */
1313 PDMDEVHLPTASKOP enmOp;
1314#if HC_ARCH_BITS == 64
1315 uint32_t Alignment0;
1316#endif
1317 /** Parameters to the operation. */
1318 union PDMDEVHLPTASKPARAMS
1319 {
1320 /**
1321 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1322 */
1323 struct PDMDEVHLPTASKISASETIRQ
1324 {
1325 /** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1326 PCIBDF uBusDevFn;
1327 /** The IRQ */
1328 int iIrq;
1329 /** The new level. */
1330 int iLevel;
1331 /** The IRQ tag and source. */
1332 uint32_t uTagSrc;
1333 } IsaSetIrq, IoApicSetIrq;
1334
1335 /**
1336 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1337 */
1338 struct PDMDEVHLPTASKPCISETIRQ
1339 {
1340 /** Index of the PCI device (into PDMDEVINSR3::apPciDevs). */
1341 uint32_t idxPciDev;
1342 /** The IRQ */
1343 int32_t iIrq;
1344 /** The new level. */
1345 int32_t iLevel;
1346 /** The IRQ tag and source. */
1347 uint32_t uTagSrc;
1348 } PciSetIrq;
1349
1350 /**
1351 * PDMDEVHLPTASKOP_IOAPIC_SEND_MSI
1352 */
1353 struct PDMDEVHLPTASKIOAPICSENDMSI
1354 {
1355 /** The bus:device:function of the device sending the MSI. */
1356 PCIBDF uBusDevFn;
1357 /** The MSI. */
1358 MSIMSG Msi;
1359 /** The IRQ tag and source. */
1360 uint32_t uTagSrc;
1361 } IoApicSendMsi;
1362
1363 /**
1364 * PDMDEVHLPTASKOP_IOAPIC_SET_EOI
1365 */
1366 struct PDMDEVHLPTASKIOAPICSETEOI
1367 {
1368 /** The vector corresponding to the EOI. */
1369 uint8_t uVector;
1370 } IoApicSetEoi;
1371
1372 /** Expanding the structure. */
1373 uint64_t au64[3];
1374 } u;
1375} PDMDEVHLPTASK;
1376/** Pointer to a queued Device Helper Task. */
1377typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1378/** Pointer to a const queued Device Helper Task. */
1379typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1380
1381
1382
1383/**
1384 * An USB hub registration record.
1385 */
1386typedef struct PDMUSBHUB
1387{
1388 /** The USB versions this hub support.
1389 * Note that 1.1 hubs can take on 2.0 devices. */
1390 uint32_t fVersions;
1391 /** The number of ports on the hub. */
1392 uint32_t cPorts;
1393 /** The number of available ports (0..cPorts). */
1394 uint32_t cAvailablePorts;
1395 /** The driver instance of the hub. */
1396 PPDMDRVINS pDrvIns;
1397 /** Copy of the to the registration structure. */
1398 PDMUSBHUBREG Reg;
1399
1400 /** Pointer to the next hub in the list. */
1401 struct PDMUSBHUB *pNext;
1402} PDMUSBHUB;
1403
1404/** Pointer to a const USB HUB registration record. */
1405typedef const PDMUSBHUB *PCPDMUSBHUB;
1406
1407/** Pointer to a PDM Async I/O template. */
1408typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1409
1410/** Pointer to the main PDM Async completion endpoint class. */
1411typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1412
1413/** Pointer to the global block cache structure. */
1414typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1415
1416/**
1417 * PDM VMCPU Instance data.
1418 * Changes to this must checked against the padding of the pdm union in VMCPU!
1419 */
1420typedef struct PDMCPU
1421{
1422 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1423 * in use. */
1424 uint32_t cQueuedCritSectLeaves;
1425 uint32_t uPadding0; /**< Alignment padding.*/
1426 /** Critical sections queued in RC/R0 because of contention preventing leave to
1427 * complete. (R3 Ptrs)
1428 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1429 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1430
1431 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1432 * currently in use. */
1433 uint32_t cQueuedCritSectRwExclLeaves;
1434 uint32_t uPadding1; /**< Alignment padding.*/
1435 /** Read/write critical sections queued in RC/R0 because of contention
1436 * preventing exclusive leave to complete. (R3 Ptrs)
1437 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1438 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1439
1440 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1441 * currently in use. */
1442 uint32_t cQueuedCritSectRwShrdLeaves;
1443 uint32_t uPadding2; /**< Alignment padding.*/
1444 /** Read/write critical sections queued in RC/R0 because of contention
1445 * preventing shared leave to complete. (R3 Ptrs)
1446 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1447 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1448} PDMCPU;
1449
1450
1451/** Max number of ring-0 device instances. */
1452#define PDM_MAX_RING0_DEVICE_INSTANCES 190
1453
1454
1455/**
1456 * PDM VM Instance data.
1457 * Changes to this must checked against the padding of the cfgm union in VM!
1458 */
1459typedef struct PDM
1460{
1461 /** The PDM lock.
1462 * This is used to protect everything that deals with interrupts, i.e.
1463 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1464 PDMCRITSECT CritSect;
1465 /** The NOP critical section.
1466 * This is a dummy critical section that will not do any thread
1467 * serialization but instead let all threads enter immediately and
1468 * concurrently. */
1469 PDMCRITSECT NopCritSect;
1470 /** Critical read/write section protecting the core list: devices,
1471 * usb devices, drivers.
1472 * @note The PDMUSERPERVM::ListCritSect lock covers queues and the stuff in
1473 * PDMUSERPERVM. */
1474 RTCRITSECTRW CoreListCritSectRw;
1475
1476 /** The ring-0 capable task sets (max 128). */
1477 PDMTASKSET aTaskSets[2];
1478 /** Pointer to task sets (max 512). */
1479 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1480
1481 /** PCI Buses. */
1482 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1483 /** IOMMU devices. */
1484 PDMIOMMUR3 aIommus[PDM_IOMMUS_MAX];
1485 /** The register PIC device. */
1486 PDMPIC Pic;
1487 /** The registered APIC device. */
1488 PDMAPIC Apic;
1489 /** The registered I/O APIC device. */
1490 PDMIOAPIC IoApic;
1491 /** The registered HPET device. */
1492 PPDMDEVINSR3 pHpet;
1493
1494 /** List of registered devices. (FIFO) */
1495 R3PTRTYPE(PPDMDEV) pDevs;
1496 /** List of devices instances. (FIFO) */
1497 PPDMDEVINSR3 pDevInstances;
1498 /** This runs parallel to PDMR0PERVM::apDevInstances and is used with
1499 * physical access handlers to get the ring-3 device instance for passing down
1500 * as uUser. */
1501 PPDMDEVINSR3 apDevRing0Instances[PDM_MAX_RING0_DEVICE_INSTANCES];
1502
1503 /** List of registered USB devices. (FIFO) */
1504 R3PTRTYPE(PPDMUSB) pUsbDevs;
1505 /** List of USB devices instances. (FIFO) */
1506 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1507 /** List of registered drivers. (FIFO) */
1508 R3PTRTYPE(PPDMDRV) pDrvs;
1509 /** The registered firmware device (can be NULL). */
1510 R3PTRTYPE(PPDMFW) pFirmware;
1511 /** The registered DMAC device. */
1512 R3PTRTYPE(PPDMDMAC) pDmac;
1513 /** The registered RTC device. */
1514 R3PTRTYPE(PPDMRTC) pRtc;
1515 /** The registered USB HUBs. (FIFO)
1516 * @note Protected by CoreListCritSectRw. */
1517 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1518
1519 /** @name Queues
1520 * @note Protected by PDMUSERPERVM::ListCritSect.
1521 * @{ */
1522 /** Number of ring-0 capable queues in apQueues. */
1523 uint32_t cRing0Queues;
1524 uint32_t u32Padding1;
1525 /** Array of ring-0 capable queues running in parallel to PDMR0PERVM::aQueues. */
1526 R3PTRTYPE(PPDMQUEUE) apRing0Queues[16];
1527
1528 /** Number of ring-3 only queues.
1529 * PDMUSERPERVM::ListCritSect protects this and the next two members. */
1530 uint32_t cRing3Queues;
1531 /** The allocation size of the ring-3 queue handle table. */
1532 uint32_t cRing3QueuesAlloc;
1533 /** Handle table for the ring-3 only queues. */
1534 R3PTRTYPE(PPDMQUEUE *) papRing3Queues;
1535
1536 /** Queue in which devhlp tasks are queued for R3 execution. */
1537 PDMQUEUEHANDLE hDevHlpQueue;
1538 /** Bitmask controlling the queue flushing.
1539 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1540 uint32_t volatile fQueueFlushing;
1541 /** @} */
1542
1543 /** The current IRQ tag (tracing purposes). */
1544 uint32_t volatile uIrqTag;
1545
1546 /** Pending reset flags (PDMVMRESET_F_XXX). */
1547 uint32_t volatile fResetFlags;
1548
1549 /** Set by pdmR3LoadExec for use in assertions. */
1550 bool fStateLoaded;
1551 /** Alignment padding. */
1552 bool afPadding1[3];
1553
1554 /** The tracing ID of the next device instance.
1555 *
1556 * @remarks We keep the device tracing ID seperate from the rest as these are
1557 * then more likely to end up with the same ID from one run to
1558 * another, making analysis somewhat easier. Drivers and USB devices
1559 * are more volatile and can be changed at runtime, thus these are much
1560 * less likely to remain stable, so just heap them all together. */
1561 uint32_t idTracingDev;
1562 /** The tracing ID of the next driver instance, USB device instance or other
1563 * PDM entity requiring an ID. */
1564 uint32_t idTracingOther;
1565
1566 /** @name VMM device heap
1567 * @{ */
1568 /** The heap size. */
1569 uint32_t cbVMMDevHeap;
1570 /** Free space. */
1571 uint32_t cbVMMDevHeapLeft;
1572 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1573 RTR3PTR pvVMMDevHeap;
1574 /** Ring-3 mapping/unmapping notification callback for the user. */
1575 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1576 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1577 RTGCPHYS GCPhysVMMDevHeap;
1578 /** @} */
1579
1580 /** @name Network Shaper
1581 * @{ */
1582 /** Thread that processes choked filter drivers after
1583 * the a PDM_NETSHAPER_MAX_LATENCY period has elapsed. */
1584 PPDMTHREAD pNsUnchokeThread;
1585 /** Semaphore that the TX thread waits on. */
1586 RTSEMEVENT hNsUnchokeEvt;
1587 /** Timer handle for waking up pNsUnchokeThread. */
1588 TMTIMERHANDLE hNsUnchokeTimer;
1589 /** Indicates whether the unchoke timer has been armed already or not. */
1590 bool volatile fNsUnchokeTimerArmed;
1591 /** Align aNsGroups on a cacheline. */
1592 bool afPadding2[19+16];
1593 /** Number of network shaper groups.
1594 * @note Marked volatile to prevent re-reading after validation. */
1595 uint32_t volatile cNsGroups;
1596 /** The network shaper groups. */
1597 PDMNSBWGROUP aNsGroups[PDM_NET_SHAPER_MAX_GROUPS];
1598 /** Critical section protecting attaching, detaching and unchoking.
1599 * This helps making sure pNsTxThread can do unchoking w/o needing to lock the
1600 * individual groups and cause unnecessary contention. */
1601 RTCRITSECT NsLock;
1602 /** @} */
1603
1604 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1605 STAMCOUNTER StatQueuedCritSectLeaves;
1606 /** Number of times we've successfully aborted a wait in ring-0. */
1607 STAMCOUNTER StatAbortedCritSectEnters;
1608 /** Number of times we've got the critical section ownership while trying to
1609 * abort a wait due to VERR_INTERRUPTED. */
1610 STAMCOUNTER StatCritSectEntersWhileAborting;
1611 STAMCOUNTER StatCritSectVerrTimeout;
1612 STAMCOUNTER StatCritSectVerrInterrupted;
1613 STAMCOUNTER StatCritSectNonInterruptibleWaits;
1614
1615 STAMCOUNTER StatCritSectRwExclVerrTimeout;
1616 STAMCOUNTER StatCritSectRwExclVerrInterrupted;
1617 STAMCOUNTER StatCritSectRwExclNonInterruptibleWaits;
1618
1619 STAMCOUNTER StatCritSectRwEnterSharedWhileAborting;
1620 STAMCOUNTER StatCritSectRwSharedVerrTimeout;
1621 STAMCOUNTER StatCritSectRwSharedVerrInterrupted;
1622 STAMCOUNTER StatCritSectRwSharedNonInterruptibleWaits;
1623} PDM;
1624AssertCompileMemberAlignment(PDM, CritSect, 8);
1625AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1626AssertCompileMemberAlignment(PDM, aNsGroups, 8);
1627AssertCompileMemberAlignment(PDM, aNsGroups, 16);
1628AssertCompileMemberAlignment(PDM, aNsGroups, 32);
1629AssertCompileMemberAlignment(PDM, aNsGroups, 64);
1630AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1631AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1632/** Pointer to PDM VM instance data. */
1633typedef PDM *PPDM;
1634
1635
1636/**
1637 * PDM data kept in the ring-0 GVM.
1638 */
1639typedef struct PDMR0PERVM
1640{
1641 /** PCI Buses, ring-0 data. */
1642 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1643 /** IOMMUs, ring-0 data. */
1644 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1645 /** Number of valid ring-0 device instances (apDevInstances). */
1646 uint32_t cDevInstances;
1647 uint32_t u32Padding1;
1648 /** Pointer to ring-0 device instances. */
1649 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[PDM_MAX_RING0_DEVICE_INSTANCES];
1650 /** Number of valid ring-0 queue instances (aQueues). */
1651 uint32_t cQueues;
1652 uint32_t u32Padding2;
1653 /** Array of ring-0 queues. */
1654 PDMQUEUER0 aQueues[16];
1655} PDMR0PERVM;
1656
1657
1658/**
1659 * PDM data kept in the UVM.
1660 */
1661typedef struct PDMUSERPERVM
1662{
1663 /** @todo move more stuff over here. */
1664
1665 /** Lock protecting the lists below it and the queue list (in PDM). */
1666 RTCRITSECT ListCritSect;
1667 /** Pointer to list of loaded modules. */
1668 PPDMMOD pModules;
1669 /** List of initialized critical sections. (LIFO) */
1670 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1671 /** List of initialized read/write critical sections. (LIFO) */
1672 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1673 /** Head of the PDM Thread list. (singly linked) */
1674 R3PTRTYPE(PPDMTHREAD) pThreads;
1675 /** Tail of the PDM Thread list. (singly linked) */
1676 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1677
1678 /** @name PDM Async Completion
1679 * @{ */
1680 /** Pointer to the array of supported endpoint classes. */
1681 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1682 /** Head of the templates. Singly linked, protected by ListCritSect. */
1683 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1684 /** @} */
1685
1686 /** Global block cache data. */
1687 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1688} PDMUSERPERVM;
1689/** Pointer to the PDM data kept in the UVM. */
1690typedef PDMUSERPERVM *PPDMUSERPERVM;
1691
1692
1693
1694/*******************************************************************************
1695* Global Variables *
1696*******************************************************************************/
1697#ifdef IN_RING3
1698extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1699extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1700# ifdef VBOX_WITH_DBGF_TRACING
1701extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1702# endif
1703extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1704extern const PDMPICHLP g_pdmR3DevPicHlp;
1705extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1706extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1707extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1708extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1709extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1710extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1711extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1712extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1713#endif
1714
1715
1716/*******************************************************************************
1717* Defined Constants And Macros *
1718*******************************************************************************/
1719/** @def PDMDEV_ASSERT_DEVINS
1720 * Asserts the validity of the device instance.
1721 */
1722#ifdef VBOX_STRICT
1723# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1724 do { \
1725 AssertPtr(pDevIns); \
1726 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1727 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1728 } while (0)
1729#else
1730# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1731#endif
1732
1733/** @def PDMDRV_ASSERT_DRVINS
1734 * Asserts the validity of the driver instance.
1735 */
1736#ifdef VBOX_STRICT
1737# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1738 do { \
1739 AssertPtr(pDrvIns); \
1740 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1741 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1742 } while (0)
1743#else
1744# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1745#endif
1746
1747
1748/*******************************************************************************
1749* Internal Functions *
1750*******************************************************************************/
1751#ifdef IN_RING3
1752bool pdmR3IsValidName(const char *pszName);
1753
1754int pdmR3CritSectBothInitStatsAndInfo(PVM pVM);
1755int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1756int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1757int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1758 const char *pszNameFmt, va_list va);
1759int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1760 const char *pszNameFmt, ...);
1761int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1762 const char *pszNameFmt, ...);
1763int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1764 const char *pszNameFmt, va_list va);
1765int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1766 const char *pszNameFmt, ...);
1767int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1768 const char *pszNameFmt, ...);
1769
1770int pdmR3DevInit(PVM pVM);
1771int pdmR3DevInitComplete(PVM pVM);
1772PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1773int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1774DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1775
1776int pdmR3UsbLoadModules(PVM pVM);
1777int pdmR3UsbInstantiateDevices(PVM pVM);
1778PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1779int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1780int pdmR3UsbVMInitComplete(PVM pVM);
1781
1782int pdmR3DrvInit(PVM pVM);
1783int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1784 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1785int pdmR3DrvDetach(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fFlags);
1786void pdmR3DrvDestroyChain(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fFlags);
1787PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1788
1789int pdmR3LdrInitU(PUVM pUVM);
1790void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1791char *pdmR3FileR3(const char *pszFile, bool fShared);
1792int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1793#endif /* IN_RING3 */
1794
1795void pdmQueueInit(PPDMQUEUE pQueue, uint32_t cbBitmap, uint32_t cbItem, uint32_t cItems,
1796 const char *pszName, PDMQUEUETYPE enmType, RTR3PTR pfnCallback, RTR3PTR pvOwner);
1797
1798#ifdef IN_RING3
1799int pdmR3TaskInit(PVM pVM);
1800void pdmR3TaskTerm(PVM pVM);
1801
1802int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1803 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1804int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1805 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1806int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1807 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1808int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1809int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1810int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1811void pdmR3ThreadDestroyAll(PVM pVM);
1812int pdmR3ThreadResumeAll(PVM pVM);
1813int pdmR3ThreadSuspendAll(PVM pVM);
1814
1815# ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1816int pdmR3AsyncCompletionInit(PVM pVM);
1817int pdmR3AsyncCompletionTerm(PVM pVM);
1818void pdmR3AsyncCompletionResume(PVM pVM);
1819int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1820int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1821 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1822int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1823int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1824int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1825int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1826# endif
1827
1828# ifdef VBOX_WITH_NETSHAPER
1829int pdmR3NetShaperInit(PVM pVM);
1830void pdmR3NetShaperTerm(PVM pVM);
1831# endif
1832
1833int pdmR3BlkCacheInit(PVM pVM);
1834void pdmR3BlkCacheTerm(PVM pVM);
1835int pdmR3BlkCacheResume(PVM pVM);
1836
1837DECLHIDDEN(void) pdmR3QueueTerm(PVM pVM);
1838#endif /* IN_RING3 */
1839
1840void pdmLock(PVMCC pVM);
1841int pdmLockEx(PVMCC pVM, int rcBusy);
1842void pdmUnlock(PVMCC pVM);
1843bool pdmLockIsOwner(PVMCC pVM);
1844
1845#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1846bool pdmIommuIsPresent(PPDMDEVINS pDevIns);
1847int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut);
1848int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1849int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1850# ifdef IN_RING3
1851int pdmR3IommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock);
1852int pdmR3IommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock);
1853int pdmR3IommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks);
1854int pdmR3IommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks);
1855# endif
1856#endif
1857
1858#if defined(IN_RING3) || defined(IN_RING0)
1859void pdmCritSectRwLeaveSharedQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1860void pdmCritSectRwLeaveExclQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1861#endif
1862
1863#ifdef IN_RING0
1864DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1865DECLHIDDEN(void) pdmR0QueueDestroy(PGVM pGVM, uint32_t iQueue);
1866
1867#endif
1868
1869#ifdef VBOX_WITH_DBGF_TRACING
1870# ifdef IN_RING3
1871DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1872 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1873 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1874 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1875DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1876DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1877DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1878 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1879 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1880 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion);
1881DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1882DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1883DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1884DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1885DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1886DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1887DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1888DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1889DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1890DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1891# elif defined(IN_RING0)
1892DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1893 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1894 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1895 void *pvUser);
1896DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1897 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1898DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1899DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1900DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1901DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1902DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1903DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1904DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1905DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1906# else
1907# error "Invalid environment selected"
1908# endif
1909#endif
1910
1911
1912/** @} */
1913
1914RT_C_DECLS_END
1915
1916#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1917
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