VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 97405

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1/* $Id: PDMInternal.h 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
29#define VMM_INCLUDED_SRC_include_PDMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/param.h>
36#include <VBox/vmm/cfgm.h>
37#include <VBox/vmm/stam.h>
38#include <VBox/vusb.h>
39#include <VBox/vmm/iom.h>
40#include <VBox/vmm/pdmasynccompletion.h>
41#ifdef VBOX_WITH_NETSHAPER
42# include <VBox/vmm/pdmnetshaper.h>
43#endif
44#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
45# include <VBox/vmm/pdmasynccompletion.h>
46#endif
47#include <VBox/vmm/pdmblkcache.h>
48#include <VBox/vmm/pdmcommon.h>
49#include <VBox/vmm/pdmtask.h>
50#include <VBox/sup.h>
51#include <VBox/msi.h>
52#include <iprt/assert.h>
53#include <iprt/critsect.h>
54#ifdef IN_RING3
55# include <iprt/thread.h>
56#endif
57
58RT_C_DECLS_BEGIN
59
60
61/** @defgroup grp_pdm_int Internal
62 * @ingroup grp_pdm
63 * @internal
64 * @{
65 */
66
67/** @def PDM_WITH_R3R0_CRIT_SECT
68 * Enables or disabled ring-3/ring-0 critical sections. */
69#if defined(DOXYGEN_RUNNING) || 1
70# define PDM_WITH_R3R0_CRIT_SECT
71#endif
72
73/** @def PDMCRITSECT_STRICT
74 * Enables/disables PDM critsect strictness like deadlock detection. */
75#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
76 || defined(DOXYGEN_RUNNING)
77# define PDMCRITSECT_STRICT
78#endif
79
80/** @def PDMCRITSECT_STRICT
81 * Enables/disables PDM read/write critsect strictness like deadlock
82 * detection. */
83#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
84 || defined(DOXYGEN_RUNNING)
85# define PDMCRITSECTRW_STRICT
86#endif
87
88/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
89#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
90/** The maximum device instance (total) size, ring-3 only devices. */
91#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
92/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
93#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK HOST_PAGE_SIZE
94
95
96
97/*******************************************************************************
98* Structures and Typedefs *
99*******************************************************************************/
100
101/** Pointer to a PDM Device. */
102typedef struct PDMDEV *PPDMDEV;
103/** Pointer to a pointer to a PDM Device. */
104typedef PPDMDEV *PPPDMDEV;
105
106/** Pointer to a PDM USB Device. */
107typedef struct PDMUSB *PPDMUSB;
108/** Pointer to a pointer to a PDM USB Device. */
109typedef PPDMUSB *PPPDMUSB;
110
111/** Pointer to a PDM Driver. */
112typedef struct PDMDRV *PPDMDRV;
113/** Pointer to a pointer to a PDM Driver. */
114typedef PPDMDRV *PPPDMDRV;
115
116/** Pointer to a PDM Logical Unit. */
117typedef struct PDMLUN *PPDMLUN;
118/** Pointer to a pointer to a PDM Logical Unit. */
119typedef PPDMLUN *PPPDMLUN;
120
121/** Pointer to a DMAC instance. */
122typedef struct PDMDMAC *PPDMDMAC;
123/** Pointer to a RTC instance. */
124typedef struct PDMRTC *PPDMRTC;
125
126/** Pointer to an USB HUB registration record. */
127typedef struct PDMUSBHUB *PPDMUSBHUB;
128
129/**
130 * Supported asynchronous completion endpoint classes.
131 */
132typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
133{
134 /** File class. */
135 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
136 /** Number of supported classes. */
137 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
138 /** 32bit hack. */
139 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
140} PDMASYNCCOMPLETIONEPCLASSTYPE;
141
142
143/**
144 * MMIO/IO port registration tracking structure for DBGF tracing.
145 */
146typedef struct PDMDEVINSDBGFTRACK
147{
148 /** Flag whether this tracks a IO port or MMIO registration. */
149 bool fMmio;
150 /** Opaque user data passed during registration. */
151 void *pvUser;
152 /** Type dependent data. */
153 union
154 {
155 /** I/O port registration. */
156 struct
157 {
158 /** IOM I/O port handle. */
159 IOMIOPORTHANDLE hIoPorts;
160 /** Original OUT handler of the device. */
161 PFNIOMIOPORTNEWOUT pfnOut;
162 /** Original IN handler of the device. */
163 PFNIOMIOPORTNEWIN pfnIn;
164 /** Original string OUT handler of the device. */
165 PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
166 /** Original string IN handler of the device. */
167 PFNIOMIOPORTNEWINSTRING pfnInStr;
168 } IoPort;
169 /** MMIO registration. */
170 struct
171 {
172 /** IOM MMIO region handle. */
173 IOMMMIOHANDLE hMmioRegion;
174 /** Original MMIO write handler of the device. */
175 PFNIOMMMIONEWWRITE pfnWrite;
176 /** Original MMIO read handler of the device. */
177 PFNIOMMMIONEWREAD pfnRead;
178 /** Original MMIO fill handler of the device. */
179 PFNIOMMMIONEWFILL pfnFill;
180 } Mmio;
181 } u;
182} PDMDEVINSDBGFTRACK;
183/** Pointer to a MMIO/IO port registration tracking structure. */
184typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
185/** Pointer to a const MMIO/IO port registration tracking structure. */
186typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
187
188
189/**
190 * Private device instance data, ring-3.
191 */
192typedef struct PDMDEVINSINTR3
193{
194 /** Pointer to the next instance.
195 * (Head is pointed to by PDM::pDevInstances.) */
196 R3PTRTYPE(PPDMDEVINS) pNextR3;
197 /** Pointer to the next per device instance.
198 * (Head is pointed to by PDMDEV::pInstances.) */
199 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
200 /** Pointer to device structure. */
201 R3PTRTYPE(PPDMDEV) pDevR3;
202 /** Pointer to the list of logical units associated with the device. (FIFO) */
203 R3PTRTYPE(PPDMLUN) pLunsR3;
204 /** Pointer to the asynchronous notification callback set while in
205 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
206 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
207 /** Configuration handle to the instance node. */
208 R3PTRTYPE(PCFGMNODE) pCfgHandle;
209
210 /** R3 pointer to the VM this instance was created for. */
211 PVMR3 pVMR3;
212 /** DBGF trace event source handle if tracing is configured. */
213 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
214 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
215 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
216 /** Index of the next entry to use for tracking. */
217 uint32_t idxDbgfTraceTrackNext;
218 /** Maximum number of records fitting into the single page. */
219 uint32_t cDbgfTraceTrackMax;
220
221 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
222 uint32_t fIntFlags;
223 /** The last IRQ tag (for tracing it thru clearing). */
224 uint32_t uLastIrqTag;
225 /** The ring-0 device index (for making ring-0 calls). */
226 uint32_t idxR0Device;
227} PDMDEVINSINTR3;
228
229
230/**
231 * Private device instance data, ring-0.
232 */
233typedef struct PDMDEVINSINTR0
234{
235 /** Pointer to the VM this instance was created for. */
236 R0PTRTYPE(PGVM) pGVM;
237 /** Pointer to device structure. */
238 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
239 /** The ring-0 module reference. */
240 RTR0PTR hMod;
241 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
242 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
243 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
244 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
245 /** DBGF trace event source handle if tracing is configured. */
246 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
247 /** The device instance memory. */
248 RTR0MEMOBJ hMemObj;
249 /** The ring-3 mapping object. */
250 RTR0MEMOBJ hMapObj;
251 /** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
252 RTR0MEMOBJ hDbgfTraceObj;
253 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
254 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
255 /** Index of the next entry to use for tracking. */
256 uint32_t idxDbgfTraceTrackNext;
257 /** Maximum number of records fitting into the single page. */
258 uint32_t cDbgfTraceTrackMax;
259 /** Index into PDMR0PERVM::apDevInstances. */
260 uint32_t idxR0Device;
261} PDMDEVINSINTR0;
262
263
264/**
265 * Private device instance data, raw-mode
266 */
267typedef struct PDMDEVINSINTRC
268{
269 /** Pointer to the VM this instance was created for. */
270 RGPTRTYPE(PVM) pVMRC;
271} PDMDEVINSINTRC;
272
273
274/**
275 * Private device instance data.
276 */
277typedef struct PDMDEVINSINT
278{
279 /** Pointer to the next instance (HC Ptr).
280 * (Head is pointed to by PDM::pDevInstances.) */
281 R3PTRTYPE(PPDMDEVINS) pNextR3;
282 /** Pointer to the next per device instance (HC Ptr).
283 * (Head is pointed to by PDMDEV::pInstances.) */
284 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
285 /** Pointer to device structure - HC Ptr. */
286 R3PTRTYPE(PPDMDEV) pDevR3;
287 /** Pointer to the list of logical units associated with the device. (FIFO) */
288 R3PTRTYPE(PPDMLUN) pLunsR3;
289 /** Pointer to the asynchronous notification callback set while in
290 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
291 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
292 /** Configuration handle to the instance node. */
293 R3PTRTYPE(PCFGMNODE) pCfgHandle;
294
295 /** R3 pointer to the VM this instance was created for. */
296 PVMR3 pVMR3;
297
298 /** R0 pointer to the VM this instance was created for. */
299 R0PTRTYPE(PVMCC) pVMR0;
300
301 /** RC pointer to the VM this instance was created for. */
302 PVMRC pVMRC;
303
304 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
305 uint32_t fIntFlags;
306 /** The last IRQ tag (for tracing it thru clearing). */
307 uint32_t uLastIrqTag;
308} PDMDEVINSINT;
309
310/** @name PDMDEVINSINT::fIntFlags
311 * @{ */
312/** Used by pdmR3Load to mark device instances it found in the saved state. */
313#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
314/** Indicates that the device hasn't been powered on or resumed.
315 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
316 * to make sure each device gets exactly one notification for each of those
317 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
318 * a failure (already resumed/powered-on devices are suspended).
319 * PDMR3PowerOff resets this flag once before going through the devices to make sure
320 * every device gets the power off notification even if it was suspended before with
321 * PDMR3Suspend.
322 */
323#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
324/** Indicates that the device has been reset already. Used by PDMR3Reset. */
325#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
326#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
327#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
328/** Set if we've called the ring-0 constructor. */
329#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
330/** Set if using non-default critical section. */
331#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
332/** @} */
333
334
335/**
336 * Private USB device instance data.
337 */
338typedef struct PDMUSBINSINT
339{
340 /** The UUID of this instance. */
341 RTUUID Uuid;
342 /** Pointer to the next instance.
343 * (Head is pointed to by PDM::pUsbInstances.) */
344 R3PTRTYPE(PPDMUSBINS) pNext;
345 /** Pointer to the next per USB device instance.
346 * (Head is pointed to by PDMUSB::pInstances.) */
347 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
348
349 /** Pointer to device structure. */
350 R3PTRTYPE(PPDMUSB) pUsbDev;
351
352 /** Pointer to the VM this instance was created for. */
353 PVMR3 pVM;
354 /** Pointer to the list of logical units associated with the device. (FIFO) */
355 R3PTRTYPE(PPDMLUN) pLuns;
356 /** The per instance device configuration. */
357 R3PTRTYPE(PCFGMNODE) pCfg;
358 /** Same as pCfg if the configuration should be deleted when detaching the device. */
359 R3PTRTYPE(PCFGMNODE) pCfgDelete;
360 /** The global device configuration. */
361 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
362
363 /** Pointer to the USB hub this device is attached to.
364 * This is NULL if the device isn't connected to any HUB. */
365 R3PTRTYPE(PPDMUSBHUB) pHub;
366 /** The port number that we're connected to. */
367 uint32_t iPort;
368 /** Indicates that the USB device hasn't been powered on or resumed.
369 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
370 bool fVMSuspended;
371 /** Indicates that the USB device has been reset. */
372 bool fVMReset;
373 /** Pointer to the asynchronous notification callback set while in
374 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
375 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
376} PDMUSBINSINT;
377
378
379/**
380 * Private driver instance data.
381 */
382typedef struct PDMDRVINSINT
383{
384 /** Pointer to the driver instance above.
385 * This is NULL for the topmost drive. */
386 R3PTRTYPE(PPDMDRVINS) pUp;
387 /** Pointer to the driver instance below.
388 * This is NULL for the bottommost driver. */
389 R3PTRTYPE(PPDMDRVINS) pDown;
390 /** Pointer to the logical unit this driver chained on. */
391 R3PTRTYPE(PPDMLUN) pLun;
392 /** Pointer to driver structure from which this was instantiated. */
393 R3PTRTYPE(PPDMDRV) pDrv;
394 /** Pointer to the VM this instance was created for, ring-3 context. */
395 PVMR3 pVMR3;
396 /** Pointer to the VM this instance was created for, ring-0 context. */
397 R0PTRTYPE(PVMCC) pVMR0;
398 /** Pointer to the VM this instance was created for, raw-mode context. */
399 PVMRC pVMRC;
400 /** Flag indicating that the driver is being detached and destroyed.
401 * (Helps detect potential recursive detaching.) */
402 bool fDetaching;
403 /** Indicates that the driver hasn't been powered on or resumed.
404 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
405 bool fVMSuspended;
406 /** Indicates that the driver has been reset already. */
407 bool fVMReset;
408 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
409 bool fHyperHeap;
410 /** Pointer to the asynchronous notification callback set while in
411 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
412 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
413 /** Configuration handle to the instance node. */
414 R3PTRTYPE(PCFGMNODE) pCfgHandle;
415 /** Pointer to the ring-0 request handler function. */
416 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
417} PDMDRVINSINT;
418
419
420/**
421 * Private critical section data.
422 */
423typedef struct PDMCRITSECTINT
424{
425 /** The critical section core which is shared with IPRT.
426 * @note The semaphore is a SUPSEMEVENT. */
427 RTCRITSECT Core;
428 /** Pointer to the next critical section.
429 * This chain is used for device cleanup and the dbgf info item. */
430 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
431 /** Owner identifier.
432 * This is pDevIns if the owner is a device. Similarly for a driver or service.
433 * PDMR3CritSectInit() sets this to point to the critsect itself. */
434 RTR3PTR pvKey;
435 /** Set if this critical section is the automatically created default
436 * section of a device. */
437 bool fAutomaticDefaultCritsect;
438 /** Set if the critical section is used by a timer or similar.
439 * See PDMR3DevGetCritSect. */
440 bool fUsedByTimerOrSimilar;
441 /** Alignment padding. */
442 bool afPadding[2+4];
443 /** Support driver event semaphore that is scheduled to be signaled upon leaving
444 * the critical section. This is only for Ring-3 and Ring-0. */
445 SUPSEMEVENT volatile hEventToSignal;
446 /** The lock name. */
447 R3PTRTYPE(const char *) pszName;
448 /** The ring-3 pointer to this critical section, for leave queueing. */
449 R3PTRTYPE(PPDMCRITSECT) pSelfR3;
450 /** R0/RC lock contention. */
451 STAMCOUNTER StatContentionRZLock;
452 /** R0/RC lock contention: returning rcBusy or VERR_SEM_BUSY (try). */
453 STAMCOUNTER StatContentionRZLockBusy;
454 /** R0/RC lock contention: Profiling waiting time. */
455 STAMPROFILE StatContentionRZWait;
456 /** R0/RC unlock contention. */
457 STAMCOUNTER StatContentionRZUnlock;
458 /** R3 lock contention. */
459 STAMCOUNTER StatContentionR3;
460 /** R3 lock contention: Profiling waiting time. */
461 STAMPROFILE StatContentionR3Wait;
462 /** Profiling the time the section is locked. */
463 STAMPROFILEADV StatLocked;
464} PDMCRITSECTINT;
465AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
466/** Pointer to private critical section data. */
467typedef PDMCRITSECTINT *PPDMCRITSECTINT;
468
469/** Special magic value set when we failed to abort entering in ring-0 due to a
470 * timeout, interruption or pending thread termination. */
471#define PDMCRITSECT_MAGIC_FAILED_ABORT UINT32_C(0x0bad0326)
472/** Special magic value set if we detected data/state corruption. */
473#define PDMCRITSECT_MAGIC_CORRUPTED UINT32_C(0x0bad2603)
474
475/** Indicates that the critical section is queued for unlock.
476 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
477#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
478
479
480/**
481 * Private critical section data.
482 */
483typedef struct PDMCRITSECTRWINT
484{
485 /** The read/write critical section core which is shared with IPRT.
486 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
487 RTCRITSECTRW Core;
488
489 /** Pointer to the next critical section.
490 * This chain is used for device cleanup and the dbgf info item. */
491 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
492 /** Self pointer. */
493 R3PTRTYPE(PPDMCRITSECTRW) pSelfR3;
494 /** Owner identifier.
495 * This is pDevIns if the owner is a device. Similarly for a driver or service.
496 * PDMR3CritSectRwInit() sets this to point to the critsect itself. */
497 RTR3PTR pvKey;
498 /** The lock name. */
499 R3PTRTYPE(const char *) pszName;
500
501 /** R0/RC write lock contention. */
502 STAMCOUNTER StatContentionRZEnterExcl;
503 /** R0/RC write unlock contention. */
504 STAMCOUNTER StatContentionRZLeaveExcl;
505 /** R0/RC read lock contention. */
506 STAMCOUNTER StatContentionRZEnterShared;
507 /** R0/RC read unlock contention. */
508 STAMCOUNTER StatContentionRZLeaveShared;
509 /** R0/RC writes. */
510 STAMCOUNTER StatRZEnterExcl;
511 /** R0/RC reads. */
512 STAMCOUNTER StatRZEnterShared;
513 /** R3 write lock contention. */
514 STAMCOUNTER StatContentionR3EnterExcl;
515 /** R3 write unlock contention. */
516 STAMCOUNTER StatContentionR3LeaveExcl;
517 /** R3 read lock contention. */
518 STAMCOUNTER StatContentionR3EnterShared;
519 /** R3 writes. */
520 STAMCOUNTER StatR3EnterExcl;
521 /** R3 reads. */
522 STAMCOUNTER StatR3EnterShared;
523 /** Profiling the time the section is write locked. */
524 STAMPROFILEADV StatWriteLocked;
525} PDMCRITSECTRWINT;
526AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
527AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u, 16);
528AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u.s.u64State, 8);
529/** Pointer to private critical section data. */
530typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
531
532/** Special magic value we set the structure has become corrupted. */
533#define PDMCRITSECTRW_MAGIC_CORRUPT UINT32_C(0x0bad0620)
534
535
536/**
537 * The usual device/driver/internal/external stuff.
538 */
539typedef enum
540{
541 /** The usual invalid entry. */
542 PDMTHREADTYPE_INVALID = 0,
543 /** Device type. */
544 PDMTHREADTYPE_DEVICE,
545 /** USB Device type. */
546 PDMTHREADTYPE_USB,
547 /** Driver type. */
548 PDMTHREADTYPE_DRIVER,
549 /** Internal type. */
550 PDMTHREADTYPE_INTERNAL,
551 /** External type. */
552 PDMTHREADTYPE_EXTERNAL,
553 /** The usual 32-bit hack. */
554 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
555} PDMTHREADTYPE;
556
557
558/**
559 * The internal structure for the thread.
560 */
561typedef struct PDMTHREADINT
562{
563 /** The VM pointer. */
564 PVMR3 pVM;
565 /** The event semaphore the thread blocks on when not running. */
566 RTSEMEVENTMULTI BlockEvent;
567 /** The event semaphore the thread sleeps on while running. */
568 RTSEMEVENTMULTI SleepEvent;
569 /** Pointer to the next thread. */
570 R3PTRTYPE(struct PDMTHREAD *) pNext;
571 /** The thread type. */
572 PDMTHREADTYPE enmType;
573} PDMTHREADINT;
574
575
576
577/* Must be included after PDMDEVINSINT is defined. */
578#define PDMDEVINSINT_DECLARED
579#define PDMUSBINSINT_DECLARED
580#define PDMDRVINSINT_DECLARED
581#define PDMCRITSECTINT_DECLARED
582#define PDMCRITSECTRWINT_DECLARED
583#define PDMTHREADINT_DECLARED
584#ifdef ___VBox_pdm_h
585# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
586#endif
587RT_C_DECLS_END
588#include <VBox/vmm/pdm.h>
589RT_C_DECLS_BEGIN
590
591/**
592 * PDM Logical Unit.
593 *
594 * This typically the representation of a physical port on a
595 * device, like for instance the PS/2 keyboard port on the
596 * keyboard controller device. The LUNs are chained on the
597 * device they belong to (PDMDEVINSINT::pLunsR3).
598 */
599typedef struct PDMLUN
600{
601 /** The LUN - The Logical Unit Number. */
602 RTUINT iLun;
603 /** Pointer to the next LUN. */
604 PPDMLUN pNext;
605 /** Pointer to the top driver in the driver chain. */
606 PPDMDRVINS pTop;
607 /** Pointer to the bottom driver in the driver chain. */
608 PPDMDRVINS pBottom;
609 /** Pointer to the device instance which the LUN belongs to.
610 * Either this is set or pUsbIns is set. Both is never set at the same time. */
611 PPDMDEVINS pDevIns;
612 /** Pointer to the USB device instance which the LUN belongs to. */
613 PPDMUSBINS pUsbIns;
614 /** Pointer to the device base interface. */
615 PPDMIBASE pBase;
616 /** Description of this LUN. */
617 const char *pszDesc;
618} PDMLUN;
619
620
621/**
622 * PDM Device, ring-3.
623 */
624typedef struct PDMDEV
625{
626 /** Pointer to the next device (R3 Ptr). */
627 R3PTRTYPE(PPDMDEV) pNext;
628 /** Device name length. (search optimization) */
629 uint32_t cchName;
630 /** Registration structure. */
631 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
632 /** Number of instances. */
633 uint32_t cInstances;
634 /** Pointer to chain of instances (R3 Ptr). */
635 PPDMDEVINSR3 pInstances;
636 /** The search path for raw-mode context modules (';' as separator). */
637 char *pszRCSearchPath;
638 /** The search path for ring-0 context modules (';' as separator). */
639 char *pszR0SearchPath;
640} PDMDEV;
641
642
643#if 0
644/**
645 * PDM Device, ring-0.
646 */
647typedef struct PDMDEVR0
648{
649 /** Pointer to the next device. */
650 R0PTRTYPE(PPDMDEVR0) pNext;
651 /** Device name length. (search optimization) */
652 uint32_t cchName;
653 /** Registration structure. */
654 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
655 /** Number of instances. */
656 uint32_t cInstances;
657 /** Pointer to chain of instances. */
658 PPDMDEVINSR0 pInstances;
659} PDMDEVR0;
660#endif
661
662
663/**
664 * PDM USB Device.
665 */
666typedef struct PDMUSB
667{
668 /** Pointer to the next device (R3 Ptr). */
669 R3PTRTYPE(PPDMUSB) pNext;
670 /** Device name length. (search optimization) */
671 RTUINT cchName;
672 /** Registration structure. */
673 R3PTRTYPE(const struct PDMUSBREG *) pReg;
674 /** Next instance number. */
675 uint32_t iNextInstance;
676 /** Pointer to chain of instances (R3 Ptr). */
677 R3PTRTYPE(PPDMUSBINS) pInstances;
678} PDMUSB;
679
680
681/**
682 * PDM Driver.
683 */
684typedef struct PDMDRV
685{
686 /** Pointer to the next device. */
687 PPDMDRV pNext;
688 /** Registration structure. */
689 const struct PDMDRVREG * pReg;
690 /** Current number of instances. */
691 uint32_t cInstances;
692 /** The next instance number. */
693 uint32_t iNextInstance;
694 /** The search path for raw-mode context modules (';' as separator). */
695 char *pszRCSearchPath;
696 /** The search path for ring-0 context modules (';' as separator). */
697 char *pszR0SearchPath;
698} PDMDRV;
699
700
701/**
702 * PDM IOMMU, shared ring-3.
703 */
704typedef struct PDMIOMMUR3
705{
706 /** IOMMU index. */
707 uint32_t idxIommu;
708 uint32_t uPadding0; /**< Alignment padding.*/
709
710 /** Pointer to the IOMMU device instance - R3. */
711 PPDMDEVINSR3 pDevInsR3;
712 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
713 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
714 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
715 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
716 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
717 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
718 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
719 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
720} PDMIOMMUR3;
721/** Pointer to a PDM IOMMU instance. */
722typedef PDMIOMMUR3 *PPDMIOMMUR3;
723/** Pointer to a const PDM IOMMU instance. */
724typedef const PDMIOMMUR3 *PCPDMIOMMUR3;
725
726
727/**
728 * PDM IOMMU, ring-0.
729 */
730typedef struct PDMIOMMUR0
731{
732 /** IOMMU index. */
733 uint32_t idxIommu;
734 uint32_t uPadding0; /**< Alignment padding.*/
735
736 /** Pointer to IOMMU device instance. */
737 PPDMDEVINSR0 pDevInsR0;
738 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
739 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
740 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
741 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
742 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
743 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
744 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
745 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
746} PDMIOMMUR0;
747/** Pointer to a ring-0 IOMMU data. */
748typedef PDMIOMMUR0 *PPDMIOMMUR0;
749/** Pointer to a const ring-0 IOMMU data. */
750typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
751
752/** Pointer to a PDM IOMMU for the current context. */
753#ifdef IN_RING3
754typedef PPDMIOMMUR3 PPDMIOMMU;
755#else
756typedef PPDMIOMMUR0 PPDMIOMMU;
757#endif
758
759
760/**
761 * PDM registered PIC device.
762 */
763typedef struct PDMPIC
764{
765 /** Pointer to the PIC device instance - R3. */
766 PPDMDEVINSR3 pDevInsR3;
767 /** @copydoc PDMPICREG::pfnSetIrq */
768 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
769 /** @copydoc PDMPICREG::pfnGetInterrupt */
770 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
771
772 /** Pointer to the PIC device instance - R0. */
773 PPDMDEVINSR0 pDevInsR0;
774 /** @copydoc PDMPICREG::pfnSetIrq */
775 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
776 /** @copydoc PDMPICREG::pfnGetInterrupt */
777 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
778
779 /** Pointer to the PIC device instance - RC. */
780 PPDMDEVINSRC pDevInsRC;
781 /** @copydoc PDMPICREG::pfnSetIrq */
782 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
783 /** @copydoc PDMPICREG::pfnGetInterrupt */
784 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
785 /** Alignment padding. */
786 RTRCPTR RCPtrPadding;
787} PDMPIC;
788
789
790/**
791 * PDM registered APIC device.
792 */
793typedef struct PDMAPIC
794{
795 /** Pointer to the APIC device instance - R3 Ptr. */
796 PPDMDEVINSR3 pDevInsR3;
797 /** Pointer to the APIC device instance - R0 Ptr. */
798 PPDMDEVINSR0 pDevInsR0;
799 /** Pointer to the APIC device instance - RC Ptr. */
800 PPDMDEVINSRC pDevInsRC;
801 uint8_t Alignment[4];
802} PDMAPIC;
803
804
805/**
806 * PDM registered I/O APIC device.
807 */
808typedef struct PDMIOAPIC
809{
810 /** Pointer to the I/O APIC device instance - R3 Ptr. */
811 PPDMDEVINSR3 pDevInsR3;
812 /** @copydoc PDMIOAPICREG::pfnSetIrq */
813 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
814 /** @copydoc PDMIOAPICREG::pfnSendMsi */
815 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
816 /** @copydoc PDMIOAPICREG::pfnSetEoi */
817 DECLR3CALLBACKMEMBER(void, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
818
819 /** Pointer to the I/O APIC device instance - R0. */
820 PPDMDEVINSR0 pDevInsR0;
821 /** @copydoc PDMIOAPICREG::pfnSetIrq */
822 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
823 /** @copydoc PDMIOAPICREG::pfnSendMsi */
824 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
825 /** @copydoc PDMIOAPICREG::pfnSetEoi */
826 DECLR0CALLBACKMEMBER(void, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
827
828 /** Pointer to the I/O APIC device instance - RC Ptr. */
829 PPDMDEVINSRC pDevInsRC;
830 /** @copydoc PDMIOAPICREG::pfnSetIrq */
831 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
832 /** @copydoc PDMIOAPICREG::pfnSendMsi */
833 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
834 /** @copydoc PDMIOAPICREG::pfnSendMsi */
835 DECLRCCALLBACKMEMBER(void, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
836} PDMIOAPIC;
837/** Pointer to a PDM IOAPIC instance. */
838typedef PDMIOAPIC *PPDMIOAPIC;
839/** Pointer to a const PDM IOAPIC instance. */
840typedef PDMIOAPIC const *PCPDMIOAPIC;
841
842/** Maximum number of PCI busses for a VM. */
843#define PDM_PCI_BUSSES_MAX 8
844/** Maximum number of IOMMUs (at most one per PCI bus). */
845#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
846
847
848#ifdef IN_RING3
849/**
850 * PDM registered firmware device.
851 */
852typedef struct PDMFW
853{
854 /** Pointer to the firmware device instance. */
855 PPDMDEVINSR3 pDevIns;
856 /** Copy of the registration structure. */
857 PDMFWREG Reg;
858} PDMFW;
859/** Pointer to a firmware instance. */
860typedef PDMFW *PPDMFW;
861#endif
862
863
864/**
865 * PDM PCI bus instance.
866 */
867typedef struct PDMPCIBUS
868{
869 /** PCI bus number. */
870 uint32_t iBus;
871 uint32_t uPadding0; /**< Alignment padding.*/
872
873 /** Pointer to PCI bus device instance. */
874 PPDMDEVINSR3 pDevInsR3;
875 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
876 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
877
878 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
879 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
880 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
881 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
882 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
883 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
884 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
885 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
886 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
887 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
888 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
889 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
890 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
891 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
892 uint32_t uAddress, unsigned cb, uint32_t u32Value));
893 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
894 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
895 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
896} PDMPCIBUS;
897/** Pointer to a PDM PCI Bus instance. */
898typedef PDMPCIBUS *PPDMPCIBUS;
899/** Pointer to a const PDM PCI Bus instance. */
900typedef const PDMPCIBUS *PCPDMPCIBUS;
901
902
903/**
904 * Ring-0 PDM PCI bus instance data.
905 */
906typedef struct PDMPCIBUSR0
907{
908 /** PCI bus number. */
909 uint32_t iBus;
910 uint32_t uPadding0; /**< Alignment padding.*/
911 /** Pointer to PCI bus device instance. */
912 PPDMDEVINSR0 pDevInsR0;
913 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
914 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
915} PDMPCIBUSR0;
916/** Pointer to the ring-0 PCI bus data. */
917typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
918/** Pointer to the const ring-0 PCI bus data. */
919typedef const PDMPCIBUSR0 *PCPDMPCIBUSR0;
920
921
922#ifdef IN_RING3
923/**
924 * PDM registered DMAC (DMA Controller) device.
925 */
926typedef struct PDMDMAC
927{
928 /** Pointer to the DMAC device instance. */
929 PPDMDEVINSR3 pDevIns;
930 /** Copy of the registration structure. */
931 PDMDMACREG Reg;
932} PDMDMAC;
933
934
935/**
936 * PDM registered RTC (Real Time Clock) device.
937 */
938typedef struct PDMRTC
939{
940 /** Pointer to the RTC device instance. */
941 PPDMDEVINSR3 pDevIns;
942 /** Copy of the registration structure. */
943 PDMRTCREG Reg;
944} PDMRTC;
945
946#endif /* IN_RING3 */
947
948/**
949 * Module type.
950 */
951typedef enum PDMMODTYPE
952{
953 /** Raw-mode (RC) context module. */
954 PDMMOD_TYPE_RC,
955 /** Ring-0 (host) context module. */
956 PDMMOD_TYPE_R0,
957 /** Ring-3 (host) context module. */
958 PDMMOD_TYPE_R3
959} PDMMODTYPE;
960
961
962/** The module name length including the terminator. */
963#define PDMMOD_NAME_LEN 32
964
965/**
966 * Loaded module instance.
967 */
968typedef struct PDMMOD
969{
970 /** Module name. This is used for referring to
971 * the module internally, sort of like a handle. */
972 char szName[PDMMOD_NAME_LEN];
973 /** Module type. */
974 PDMMODTYPE eType;
975 /** Loader module handle. Not used for R0 modules. */
976 RTLDRMOD hLdrMod;
977 /** Loaded address.
978 * This is the 'handle' for R0 modules. */
979 RTUINTPTR ImageBase;
980 /** Old loaded address.
981 * This is used during relocation of GC modules. Not used for R0 modules. */
982 RTUINTPTR OldImageBase;
983 /** Where the R3 HC bits are stored.
984 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
985 void *pvBits;
986
987 /** Pointer to next module. */
988 struct PDMMOD *pNext;
989 /** Module filename. */
990 char szFilename[1];
991} PDMMOD;
992/** Pointer to loaded module instance. */
993typedef PDMMOD *PPDMMOD;
994
995
996
997/** Max number of items in a queue. */
998#define PDMQUEUE_MAX_ITEMS _16K
999/** Max item size. */
1000#define PDMQUEUE_MAX_ITEM_SIZE _1M
1001/** Max total queue item size for ring-0 capable queues. */
1002#define PDMQUEUE_MAX_TOTAL_SIZE_R0 _8M
1003/** Max total queue item size for ring-3 only queues. */
1004#define PDMQUEUE_MAX_TOTAL_SIZE_R3 _32M
1005
1006/**
1007 * Queue type.
1008 */
1009typedef enum PDMQUEUETYPE
1010{
1011 /** Device consumer. */
1012 PDMQUEUETYPE_DEV = 1,
1013 /** Driver consumer. */
1014 PDMQUEUETYPE_DRV,
1015 /** Internal consumer. */
1016 PDMQUEUETYPE_INTERNAL,
1017 /** External consumer. */
1018 PDMQUEUETYPE_EXTERNAL
1019} PDMQUEUETYPE;
1020
1021/**
1022 * PDM Queue.
1023 */
1024typedef struct PDMQUEUE
1025{
1026 /** Magic value (PDMQUEUE_MAGIC). */
1027 uint32_t u32Magic;
1028 /** Item size (bytes). */
1029 uint32_t cbItem;
1030 /** Number of items in the queue. */
1031 uint32_t cItems;
1032 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1033 uint32_t offItems;
1034
1035 /** Interval timer. Only used if cMilliesInterval is non-zero. */
1036 TMTIMERHANDLE hTimer;
1037 /** The interval between checking the queue for events.
1038 * The realtime timer below is used to do the waiting.
1039 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1040 uint32_t cMilliesInterval;
1041
1042 /** This is VINF_SUCCESS if the queue is okay, error status if not. */
1043 int32_t rcOkay;
1044 uint32_t u32Padding;
1045
1046 /** Queue type. */
1047 PDMQUEUETYPE enmType;
1048 /** Type specific data. */
1049 union
1050 {
1051 /** PDMQUEUETYPE_DEV */
1052 struct
1053 {
1054 /** Pointer to consumer function. */
1055 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1056 /** Pointer to the device instance owning the queue. */
1057 R3PTRTYPE(PPDMDEVINS) pDevIns;
1058 } Dev;
1059 /** PDMQUEUETYPE_DRV */
1060 struct
1061 {
1062 /** Pointer to consumer function. */
1063 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1064 /** Pointer to the driver instance owning the queue. */
1065 R3PTRTYPE(PPDMDRVINS) pDrvIns;
1066 } Drv;
1067 /** PDMQUEUETYPE_INTERNAL */
1068 struct
1069 {
1070 /** Pointer to consumer function. */
1071 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1072 } Int;
1073 /** PDMQUEUETYPE_EXTERNAL */
1074 struct
1075 {
1076 /** Pointer to consumer function. */
1077 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1078 /** Pointer to user argument. */
1079 R3PTRTYPE(void *) pvUser;
1080 } Ext;
1081 struct
1082 {
1083 /** Generic callback pointer. */
1084 RTR3PTR pfnCallback;
1085 /** Generic owner pointer. */
1086 RTR3PTR pvOwner;
1087 } Gen;
1088 } u;
1089
1090 /** Unique queue name. */
1091 char szName[40];
1092
1093 /** LIFO of pending items (item index), UINT32_MAX if empty. */
1094 uint32_t volatile iPending;
1095
1096 /** State: Pending items. */
1097 uint32_t volatile cStatPending;
1098 /** Stat: Times PDMQueueAlloc fails. */
1099 STAMCOUNTER StatAllocFailures;
1100 /** Stat: PDMQueueInsert calls. */
1101 STAMCOUNTER StatInsert;
1102 /** Stat: Queue flushes. */
1103 STAMCOUNTER StatFlush;
1104 /** Stat: Queue flushes with pending items left over. */
1105 STAMCOUNTER StatFlushLeftovers;
1106 /** State: Profiling the flushing. */
1107 STAMPROFILE StatFlushPrf;
1108 uint64_t au64Padding[3];
1109
1110 /** Allocation bitmap: Set bits means free, clear means allocated. */
1111 RT_FLEXIBLE_ARRAY_EXTENSION
1112 uint64_t bmAlloc[RT_FLEXIBLE_ARRAY];
1113 /* The items follows after the end of the bitmap */
1114} PDMQUEUE;
1115AssertCompileMemberAlignment(PDMQUEUE, bmAlloc, 64);
1116/** Pointer to a PDM Queue. */
1117typedef struct PDMQUEUE *PPDMQUEUE;
1118
1119/** Magic value PDMQUEUE::u32Magic (Bud Powell). */
1120#define PDMQUEUE_MAGIC UINT32_C(0x19240927)
1121/** Magic value PDMQUEUE::u32Magic after destroy. */
1122#define PDMQUEUE_MAGIC_DEAD UINT32_C(0x19660731)
1123
1124/** @name PDM::fQueueFlushing
1125 * @{ */
1126/** Used to make sure only one EMT will flush the queues.
1127 * Set when an EMT is flushing queues, clear otherwise. */
1128#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1129/** Indicating there are queues with items pending.
1130 * This is make sure we don't miss inserts happening during flushing. The FF
1131 * cannot be used for this since it has to be cleared immediately to prevent
1132 * other EMTs from spinning. */
1133#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1134/** @} */
1135
1136/**
1137 * Ring-0 queue
1138 *
1139 * @author bird (2022-02-04)
1140 */
1141typedef struct PDMQUEUER0
1142{
1143 /** Pointer to the shared queue data. */
1144 R0PTRTYPE(PPDMQUEUE) pQueue;
1145 /** The memory allocation. */
1146 RTR0MEMOBJ hMemObj;
1147 /** The ring-3 mapping object. */
1148 RTR0MEMOBJ hMapObj;
1149 /** The owner pointer. This is NULL if not allocated. */
1150 RTR0PTR pvOwner;
1151 /** Queue item size. */
1152 uint32_t cbItem;
1153 /** Number of queue items. */
1154 uint32_t cItems;
1155 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1156 uint32_t offItems;
1157 uint32_t u32Reserved;
1158} PDMQUEUER0;
1159
1160
1161/** @name PDM task structures.
1162 * @{ */
1163
1164/**
1165 * A asynchronous user mode task.
1166 */
1167typedef struct PDMTASK
1168{
1169 /** Task owner type. */
1170 PDMTASKTYPE volatile enmType;
1171 /** Queue flags. */
1172 uint32_t volatile fFlags;
1173 /** User argument for the callback. */
1174 R3PTRTYPE(void *) volatile pvUser;
1175 /** The callback (will be cast according to enmType before callout). */
1176 R3PTRTYPE(PFNRT) volatile pfnCallback;
1177 /** The owner identifier. */
1178 R3PTRTYPE(void *) volatile pvOwner;
1179 /** Task name. */
1180 R3PTRTYPE(const char *) pszName;
1181 /** Number of times already triggered when PDMTaskTrigger was called. */
1182 uint32_t volatile cAlreadyTrigged;
1183 /** Number of runs. */
1184 uint32_t cRuns;
1185} PDMTASK;
1186/** Pointer to a PDM task. */
1187typedef PDMTASK *PPDMTASK;
1188
1189/**
1190 * A task set.
1191 *
1192 * This is served by one task executor thread.
1193 */
1194typedef struct PDMTASKSET
1195{
1196 /** Magic value (PDMTASKSET_MAGIC). */
1197 uint32_t u32Magic;
1198 /** Set if this task set works for ring-0 and raw-mode. */
1199 bool fRZEnabled;
1200 /** Number of allocated taks. */
1201 uint8_t volatile cAllocated;
1202 /** Base handle value for this set. */
1203 uint16_t uHandleBase;
1204 /** The task executor thread. */
1205 R3PTRTYPE(RTTHREAD) hThread;
1206 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1207 SUPSEMEVENT hEventR0;
1208 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1209 R3PTRTYPE(RTSEMEVENT) hEventR3;
1210 /** The VM pointer. */
1211 PVM pVM;
1212 /** Padding so fTriggered is in its own cacheline. */
1213 uint64_t au64Padding2[3];
1214
1215 /** Bitmask of triggered tasks. */
1216 uint64_t volatile fTriggered;
1217 /** Shutdown thread indicator. */
1218 bool volatile fShutdown;
1219 /** Padding. */
1220 bool volatile afPadding3[3];
1221 /** Task currently running, UINT32_MAX if idle. */
1222 uint32_t volatile idxRunning;
1223 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1224 uint64_t volatile au64Padding3[6];
1225
1226 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1227 PDMTASK aTasks[64];
1228} PDMTASKSET;
1229AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1230AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1231/** Magic value for PDMTASKSET::u32Magic (Quincy Delight Jones Jr.). */
1232#define PDMTASKSET_MAGIC UINT32_C(0x19330314)
1233/** Pointer to a task set. */
1234typedef PDMTASKSET *PPDMTASKSET;
1235
1236/** @} */
1237
1238
1239/** @name PDM Network Shaper
1240 * @{ */
1241
1242/**
1243 * Bandwidth group.
1244 */
1245typedef struct PDMNSBWGROUP
1246{
1247 /** Critical section protecting all members below. */
1248 PDMCRITSECT Lock;
1249 /** List of filters in this group (PDMNSFILTER). */
1250 RTLISTANCHORR3 FilterList;
1251 /** Reference counter - How many filters are associated with this group. */
1252 volatile uint32_t cRefs;
1253 uint32_t uPadding1;
1254 /** The group name. */
1255 char szName[PDM_NET_SHAPER_MAX_NAME_LEN + 1];
1256 /** Maximum number of bytes filters are allowed to transfer. */
1257 volatile uint64_t cbPerSecMax;
1258 /** Number of bytes we are allowed to transfer in one burst. */
1259 volatile uint32_t cbBucket;
1260 /** Number of bytes we were allowed to transfer at the last update. */
1261 volatile uint32_t cbTokensLast;
1262 /** Timestamp of the last update */
1263 volatile uint64_t tsUpdatedLast;
1264 /** Number of times a filter was choked. */
1265 volatile uint64_t cTotalChokings;
1266 /** Pad the structure to a multiple of 64 bytes. */
1267 uint64_t au64Padding[1];
1268} PDMNSBWGROUP;
1269AssertCompileSizeAlignment(PDMNSBWGROUP, 64);
1270/** Pointer to a bandwidth group. */
1271typedef PDMNSBWGROUP *PPDMNSBWGROUP;
1272
1273/** @} */
1274
1275
1276/**
1277 * Queue device helper task operation.
1278 */
1279typedef enum PDMDEVHLPTASKOP
1280{
1281 /** The usual invalid 0 entry. */
1282 PDMDEVHLPTASKOP_INVALID = 0,
1283 /** IsaSetIrq, IoApicSetIrq */
1284 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1285 /** PciSetIrq */
1286 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1287 /** PciSetIrq */
1288 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1289 /** IoApicSendMsi */
1290 PDMDEVHLPTASKOP_IOAPIC_SEND_MSI,
1291 /** IoApicSettEoi */
1292 PDMDEVHLPTASKOP_IOAPIC_SET_EOI,
1293 /** The usual 32-bit hack. */
1294 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1295} PDMDEVHLPTASKOP;
1296
1297/**
1298 * Queued Device Helper Task.
1299 */
1300typedef struct PDMDEVHLPTASK
1301{
1302 /** The queue item core (don't touch). */
1303 PDMQUEUEITEMCORE Core;
1304 /** Pointer to the device instance (R3 Ptr). */
1305 PPDMDEVINSR3 pDevInsR3;
1306 /** This operation to perform. */
1307 PDMDEVHLPTASKOP enmOp;
1308#if HC_ARCH_BITS == 64
1309 uint32_t Alignment0;
1310#endif
1311 /** Parameters to the operation. */
1312 union PDMDEVHLPTASKPARAMS
1313 {
1314 /**
1315 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1316 */
1317 struct PDMDEVHLPTASKISASETIRQ
1318 {
1319 /** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1320 PCIBDF uBusDevFn;
1321 /** The IRQ */
1322 int iIrq;
1323 /** The new level. */
1324 int iLevel;
1325 /** The IRQ tag and source. */
1326 uint32_t uTagSrc;
1327 } IsaSetIrq, IoApicSetIrq;
1328
1329 /**
1330 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1331 */
1332 struct PDMDEVHLPTASKPCISETIRQ
1333 {
1334 /** Index of the PCI device (into PDMDEVINSR3::apPciDevs). */
1335 uint32_t idxPciDev;
1336 /** The IRQ */
1337 int32_t iIrq;
1338 /** The new level. */
1339 int32_t iLevel;
1340 /** The IRQ tag and source. */
1341 uint32_t uTagSrc;
1342 } PciSetIrq;
1343
1344 /**
1345 * PDMDEVHLPTASKOP_IOAPIC_SEND_MSI
1346 */
1347 struct PDMDEVHLPTASKIOAPICSENDMSI
1348 {
1349 /** The bus:device:function of the device sending the MSI. */
1350 PCIBDF uBusDevFn;
1351 /** The MSI. */
1352 MSIMSG Msi;
1353 /** The IRQ tag and source. */
1354 uint32_t uTagSrc;
1355 } IoApicSendMsi;
1356
1357 /**
1358 * PDMDEVHLPTASKOP_IOAPIC_SET_EOI
1359 */
1360 struct PDMDEVHLPTASKIOAPICSETEOI
1361 {
1362 /** The vector corresponding to the EOI. */
1363 uint8_t uVector;
1364 } IoApicSetEoi;
1365
1366 /** Expanding the structure. */
1367 uint64_t au64[3];
1368 } u;
1369} PDMDEVHLPTASK;
1370/** Pointer to a queued Device Helper Task. */
1371typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1372/** Pointer to a const queued Device Helper Task. */
1373typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1374
1375
1376
1377/**
1378 * An USB hub registration record.
1379 */
1380typedef struct PDMUSBHUB
1381{
1382 /** The USB versions this hub support.
1383 * Note that 1.1 hubs can take on 2.0 devices. */
1384 uint32_t fVersions;
1385 /** The number of ports on the hub. */
1386 uint32_t cPorts;
1387 /** The number of available ports (0..cPorts). */
1388 uint32_t cAvailablePorts;
1389 /** The driver instance of the hub. */
1390 PPDMDRVINS pDrvIns;
1391 /** Copy of the to the registration structure. */
1392 PDMUSBHUBREG Reg;
1393
1394 /** Pointer to the next hub in the list. */
1395 struct PDMUSBHUB *pNext;
1396} PDMUSBHUB;
1397
1398/** Pointer to a const USB HUB registration record. */
1399typedef const PDMUSBHUB *PCPDMUSBHUB;
1400
1401/** Pointer to a PDM Async I/O template. */
1402typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1403
1404/** Pointer to the main PDM Async completion endpoint class. */
1405typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1406
1407/** Pointer to the global block cache structure. */
1408typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1409
1410/**
1411 * PDM VMCPU Instance data.
1412 * Changes to this must checked against the padding of the pdm union in VMCPU!
1413 */
1414typedef struct PDMCPU
1415{
1416 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1417 * in use. */
1418 uint32_t cQueuedCritSectLeaves;
1419 uint32_t uPadding0; /**< Alignment padding.*/
1420 /** Critical sections queued in RC/R0 because of contention preventing leave to
1421 * complete. (R3 Ptrs)
1422 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1423 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1424
1425 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1426 * currently in use. */
1427 uint32_t cQueuedCritSectRwExclLeaves;
1428 uint32_t uPadding1; /**< Alignment padding.*/
1429 /** Read/write critical sections queued in RC/R0 because of contention
1430 * preventing exclusive leave to complete. (R3 Ptrs)
1431 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1432 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1433
1434 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1435 * currently in use. */
1436 uint32_t cQueuedCritSectRwShrdLeaves;
1437 uint32_t uPadding2; /**< Alignment padding.*/
1438 /** Read/write critical sections queued in RC/R0 because of contention
1439 * preventing shared leave to complete. (R3 Ptrs)
1440 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1441 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1442} PDMCPU;
1443
1444
1445/** Max number of ring-0 device instances. */
1446#define PDM_MAX_RING0_DEVICE_INSTANCES 190
1447
1448
1449/**
1450 * PDM VM Instance data.
1451 * Changes to this must checked against the padding of the cfgm union in VM!
1452 */
1453typedef struct PDM
1454{
1455 /** The PDM lock.
1456 * This is used to protect everything that deals with interrupts, i.e.
1457 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1458 PDMCRITSECT CritSect;
1459 /** The NOP critical section.
1460 * This is a dummy critical section that will not do any thread
1461 * serialization but instead let all threads enter immediately and
1462 * concurrently. */
1463 PDMCRITSECT NopCritSect;
1464
1465 /** The ring-0 capable task sets (max 128). */
1466 PDMTASKSET aTaskSets[2];
1467 /** Pointer to task sets (max 512). */
1468 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1469
1470 /** PCI Buses. */
1471 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1472 /** IOMMU devices. */
1473 PDMIOMMUR3 aIommus[PDM_IOMMUS_MAX];
1474 /** The register PIC device. */
1475 PDMPIC Pic;
1476 /** The registered APIC device. */
1477 PDMAPIC Apic;
1478 /** The registered I/O APIC device. */
1479 PDMIOAPIC IoApic;
1480 /** The registered HPET device. */
1481 PPDMDEVINSR3 pHpet;
1482
1483 /** List of registered devices. (FIFO) */
1484 R3PTRTYPE(PPDMDEV) pDevs;
1485 /** List of devices instances. (FIFO) */
1486 PPDMDEVINSR3 pDevInstances;
1487 /** This runs parallel to PDMR0PERVM::apDevInstances and is used with
1488 * physical access handlers to get the ring-3 device instance for passing down
1489 * as uUser. */
1490 PPDMDEVINSR3 apDevRing0Instances[PDM_MAX_RING0_DEVICE_INSTANCES];
1491
1492 /** List of registered USB devices. (FIFO) */
1493 R3PTRTYPE(PPDMUSB) pUsbDevs;
1494 /** List of USB devices instances. (FIFO) */
1495 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1496 /** List of registered drivers. (FIFO) */
1497 R3PTRTYPE(PPDMDRV) pDrvs;
1498 /** The registered firmware device (can be NULL). */
1499 R3PTRTYPE(PPDMFW) pFirmware;
1500 /** The registered DMAC device. */
1501 R3PTRTYPE(PPDMDMAC) pDmac;
1502 /** The registered RTC device. */
1503 R3PTRTYPE(PPDMRTC) pRtc;
1504 /** The registered USB HUBs. (FIFO) */
1505 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1506
1507 /** @name Queues
1508 * @{ */
1509 /** Number of ring-0 capable queues in apQueues. */
1510 uint32_t cRing0Queues;
1511 uint32_t u32Padding1;
1512 /** Array of ring-0 capable queues running in parallel to PDMR0PERVM::aQueues. */
1513 R3PTRTYPE(PPDMQUEUE) apRing0Queues[16];
1514 /** Number of ring-3 only queues */
1515 uint32_t cRing3Queues;
1516 /** The allocation size of the ring-3 queue handle table. */
1517 uint32_t cRing3QueuesAlloc;
1518 /** Handle table for the ring-3 only queues. */
1519 R3PTRTYPE(PPDMQUEUE *) papRing3Queues;
1520
1521 /** Queue in which devhlp tasks are queued for R3 execution. */
1522 PDMQUEUEHANDLE hDevHlpQueue;
1523 /** Bitmask controlling the queue flushing.
1524 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1525 uint32_t volatile fQueueFlushing;
1526 /** @} */
1527
1528 /** The current IRQ tag (tracing purposes). */
1529 uint32_t volatile uIrqTag;
1530
1531 /** Pending reset flags (PDMVMRESET_F_XXX). */
1532 uint32_t volatile fResetFlags;
1533
1534 /** Set by pdmR3LoadExec for use in assertions. */
1535 bool fStateLoaded;
1536 /** Alignment padding. */
1537 bool afPadding1[3];
1538
1539 /** The tracing ID of the next device instance.
1540 *
1541 * @remarks We keep the device tracing ID seperate from the rest as these are
1542 * then more likely to end up with the same ID from one run to
1543 * another, making analysis somewhat easier. Drivers and USB devices
1544 * are more volatile and can be changed at runtime, thus these are much
1545 * less likely to remain stable, so just heap them all together. */
1546 uint32_t idTracingDev;
1547 /** The tracing ID of the next driver instance, USB device instance or other
1548 * PDM entity requiring an ID. */
1549 uint32_t idTracingOther;
1550
1551 /** @name VMM device heap
1552 * @{ */
1553 /** The heap size. */
1554 uint32_t cbVMMDevHeap;
1555 /** Free space. */
1556 uint32_t cbVMMDevHeapLeft;
1557 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1558 RTR3PTR pvVMMDevHeap;
1559 /** Ring-3 mapping/unmapping notification callback for the user. */
1560 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1561 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1562 RTGCPHYS GCPhysVMMDevHeap;
1563 /** @} */
1564
1565 /** @name Network Shaper
1566 * @{ */
1567 /** Thread that processes choked filter drivers after
1568 * the a PDM_NETSHAPER_MAX_LATENCY period has elapsed. */
1569 PPDMTHREAD pNsUnchokeThread;
1570 /** Semaphore that the TX thread waits on. */
1571 RTSEMEVENT hNsUnchokeEvt;
1572 /** Timer handle for waking up pNsUnchokeThread. */
1573 TMTIMERHANDLE hNsUnchokeTimer;
1574 /** Indicates whether the unchoke timer has been armed already or not. */
1575 bool volatile fNsUnchokeTimerArmed;
1576 /** Align aNsGroups on a cacheline. */
1577 bool afPadding2[19+16];
1578 /** Number of network shaper groups.
1579 * @note Marked volatile to prevent re-reading after validation. */
1580 uint32_t volatile cNsGroups;
1581 /** The network shaper groups. */
1582 PDMNSBWGROUP aNsGroups[PDM_NET_SHAPER_MAX_GROUPS];
1583 /** Critical section protecting attaching, detaching and unchoking.
1584 * This helps making sure pNsTxThread can do unchoking w/o needing to lock the
1585 * individual groups and cause unnecessary contention. */
1586 RTCRITSECT NsLock;
1587 /** @} */
1588
1589 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1590 STAMCOUNTER StatQueuedCritSectLeaves;
1591 /** Number of times we've successfully aborted a wait in ring-0. */
1592 STAMCOUNTER StatAbortedCritSectEnters;
1593 /** Number of times we've got the critical section ownership while trying to
1594 * abort a wait due to VERR_INTERRUPTED. */
1595 STAMCOUNTER StatCritSectEntersWhileAborting;
1596 STAMCOUNTER StatCritSectVerrTimeout;
1597 STAMCOUNTER StatCritSectVerrInterrupted;
1598 STAMCOUNTER StatCritSectNonInterruptibleWaits;
1599
1600 STAMCOUNTER StatCritSectRwExclVerrTimeout;
1601 STAMCOUNTER StatCritSectRwExclVerrInterrupted;
1602 STAMCOUNTER StatCritSectRwExclNonInterruptibleWaits;
1603
1604 STAMCOUNTER StatCritSectRwEnterSharedWhileAborting;
1605 STAMCOUNTER StatCritSectRwSharedVerrTimeout;
1606 STAMCOUNTER StatCritSectRwSharedVerrInterrupted;
1607 STAMCOUNTER StatCritSectRwSharedNonInterruptibleWaits;
1608} PDM;
1609AssertCompileMemberAlignment(PDM, CritSect, 8);
1610AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1611AssertCompileMemberAlignment(PDM, aNsGroups, 8);
1612AssertCompileMemberAlignment(PDM, aNsGroups, 16);
1613AssertCompileMemberAlignment(PDM, aNsGroups, 32);
1614AssertCompileMemberAlignment(PDM, aNsGroups, 64);
1615AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1616AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1617/** Pointer to PDM VM instance data. */
1618typedef PDM *PPDM;
1619
1620
1621/**
1622 * PDM data kept in the ring-0 GVM.
1623 */
1624typedef struct PDMR0PERVM
1625{
1626 /** PCI Buses, ring-0 data. */
1627 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1628 /** IOMMUs, ring-0 data. */
1629 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1630 /** Number of valid ring-0 device instances (apDevInstances). */
1631 uint32_t cDevInstances;
1632 uint32_t u32Padding1;
1633 /** Pointer to ring-0 device instances. */
1634 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[PDM_MAX_RING0_DEVICE_INSTANCES];
1635 /** Number of valid ring-0 queue instances (aQueues). */
1636 uint32_t cQueues;
1637 uint32_t u32Padding2;
1638 /** Array of ring-0 queues. */
1639 PDMQUEUER0 aQueues[16];
1640} PDMR0PERVM;
1641
1642
1643/**
1644 * PDM data kept in the UVM.
1645 */
1646typedef struct PDMUSERPERVM
1647{
1648 /** @todo move more stuff over here. */
1649
1650 /** Lock protecting the lists below it. */
1651 RTCRITSECT ListCritSect;
1652 /** Pointer to list of loaded modules. */
1653 PPDMMOD pModules;
1654 /** List of initialized critical sections. (LIFO) */
1655 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1656 /** List of initialized read/write critical sections. (LIFO) */
1657 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1658 /** Head of the PDM Thread list. (singly linked) */
1659 R3PTRTYPE(PPDMTHREAD) pThreads;
1660 /** Tail of the PDM Thread list. (singly linked) */
1661 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1662
1663 /** @name PDM Async Completion
1664 * @{ */
1665 /** Pointer to the array of supported endpoint classes. */
1666 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1667 /** Head of the templates. Singly linked, protected by ListCritSect. */
1668 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1669 /** @} */
1670
1671 /** Global block cache data. */
1672 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1673} PDMUSERPERVM;
1674/** Pointer to the PDM data kept in the UVM. */
1675typedef PDMUSERPERVM *PPDMUSERPERVM;
1676
1677
1678
1679/*******************************************************************************
1680* Global Variables *
1681*******************************************************************************/
1682#ifdef IN_RING3
1683extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1684extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1685# ifdef VBOX_WITH_DBGF_TRACING
1686extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1687# endif
1688extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1689extern const PDMPICHLP g_pdmR3DevPicHlp;
1690extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1691extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1692extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1693extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1694extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1695extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1696extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1697extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1698#endif
1699
1700
1701/*******************************************************************************
1702* Defined Constants And Macros *
1703*******************************************************************************/
1704/** @def PDMDEV_ASSERT_DEVINS
1705 * Asserts the validity of the device instance.
1706 */
1707#ifdef VBOX_STRICT
1708# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1709 do { \
1710 AssertPtr(pDevIns); \
1711 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1712 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1713 } while (0)
1714#else
1715# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1716#endif
1717
1718/** @def PDMDRV_ASSERT_DRVINS
1719 * Asserts the validity of the driver instance.
1720 */
1721#ifdef VBOX_STRICT
1722# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1723 do { \
1724 AssertPtr(pDrvIns); \
1725 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1726 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1727 } while (0)
1728#else
1729# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1730#endif
1731
1732
1733/*******************************************************************************
1734* Internal Functions *
1735*******************************************************************************/
1736#ifdef IN_RING3
1737bool pdmR3IsValidName(const char *pszName);
1738
1739int pdmR3CritSectBothInitStatsAndInfo(PVM pVM);
1740int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1741int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1742int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1743 const char *pszNameFmt, va_list va);
1744int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1745 const char *pszNameFmt, ...);
1746int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1747 const char *pszNameFmt, ...);
1748int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1749 const char *pszNameFmt, va_list va);
1750int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1751 const char *pszNameFmt, ...);
1752int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1753 const char *pszNameFmt, ...);
1754
1755int pdmR3DevInit(PVM pVM);
1756int pdmR3DevInitComplete(PVM pVM);
1757PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1758int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1759DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1760
1761int pdmR3UsbLoadModules(PVM pVM);
1762int pdmR3UsbInstantiateDevices(PVM pVM);
1763PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1764int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1765int pdmR3UsbVMInitComplete(PVM pVM);
1766
1767int pdmR3DrvInit(PVM pVM);
1768int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1769 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1770int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1771void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1772PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1773
1774int pdmR3LdrInitU(PUVM pUVM);
1775void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1776char *pdmR3FileR3(const char *pszFile, bool fShared);
1777int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1778#endif /* IN_RING3 */
1779
1780void pdmQueueInit(PPDMQUEUE pQueue, uint32_t cbBitmap, uint32_t cbItem, uint32_t cItems,
1781 const char *pszName, PDMQUEUETYPE enmType, RTR3PTR pfnCallback, RTR3PTR pvOwner);
1782
1783#ifdef IN_RING3
1784int pdmR3TaskInit(PVM pVM);
1785void pdmR3TaskTerm(PVM pVM);
1786
1787int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1788 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1789int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1790 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1791int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1792 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1793int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1794int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1795int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1796void pdmR3ThreadDestroyAll(PVM pVM);
1797int pdmR3ThreadResumeAll(PVM pVM);
1798int pdmR3ThreadSuspendAll(PVM pVM);
1799
1800# ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1801int pdmR3AsyncCompletionInit(PVM pVM);
1802int pdmR3AsyncCompletionTerm(PVM pVM);
1803void pdmR3AsyncCompletionResume(PVM pVM);
1804int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1805int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1806 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1807int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1808int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1809int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1810int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1811# endif
1812
1813# ifdef VBOX_WITH_NETSHAPER
1814int pdmR3NetShaperInit(PVM pVM);
1815void pdmR3NetShaperTerm(PVM pVM);
1816# endif
1817
1818int pdmR3BlkCacheInit(PVM pVM);
1819void pdmR3BlkCacheTerm(PVM pVM);
1820int pdmR3BlkCacheResume(PVM pVM);
1821
1822DECLHIDDEN(void) pdmR3QueueTerm(PVM pVM);
1823#endif /* IN_RING3 */
1824
1825void pdmLock(PVMCC pVM);
1826int pdmLockEx(PVMCC pVM, int rcBusy);
1827void pdmUnlock(PVMCC pVM);
1828bool pdmLockIsOwner(PVMCC pVM);
1829
1830#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1831bool pdmIommuIsPresent(PPDMDEVINS pDevIns);
1832int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut);
1833int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1834int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1835# ifdef IN_RING3
1836int pdmR3IommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock);
1837int pdmR3IommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock);
1838int pdmR3IommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks);
1839int pdmR3IommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks);
1840# endif
1841#endif
1842
1843#if defined(IN_RING3) || defined(IN_RING0)
1844void pdmCritSectRwLeaveSharedQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1845void pdmCritSectRwLeaveExclQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1846#endif
1847
1848#ifdef IN_RING0
1849DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1850DECLHIDDEN(void) pdmR0QueueDestroy(PGVM pGVM, uint32_t iQueue);
1851
1852#endif
1853
1854#ifdef VBOX_WITH_DBGF_TRACING
1855# ifdef IN_RING3
1856DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1857 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1858 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1859 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1860DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1861DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1862DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1863 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1864 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1865 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion);
1866DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1867DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1868DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1869DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1870DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1871DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1872DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1873DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1874DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1875DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1876# elif defined(IN_RING0)
1877DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1878 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1879 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1880 void *pvUser);
1881DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1882 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1883DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1884DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1885DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1886DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1887DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1888DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1889DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1890DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1891# else
1892# error "Invalid environment selected"
1893# endif
1894#endif
1895
1896
1897/** @} */
1898
1899RT_C_DECLS_END
1900
1901#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1902
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