VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 107113

Last change on this file since 107113 was 107113, checked in by vboxsync, 3 months ago

VMM: bugref:10759 Restructure the APIC to allow different backends to be used.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 78.9 KB
Line 
1/* $Id: PDMInternal.h 107113 2024-11-22 10:48:00Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
29#define VMM_INCLUDED_SRC_include_PDMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/param.h>
36#include <VBox/vmm/cfgm.h>
37#include <VBox/vmm/stam.h>
38#include <VBox/vusb.h>
39#include <VBox/vmm/iom.h>
40#include <VBox/vmm/pdmasynccompletion.h>
41#ifdef VBOX_WITH_NETSHAPER
42# include <VBox/vmm/pdmnetshaper.h>
43#endif
44#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
45# include <VBox/vmm/pdmasynccompletion.h>
46#endif
47#include <VBox/vmm/pdmblkcache.h>
48#include <VBox/vmm/pdmcommon.h>
49#include <VBox/vmm/pdmtask.h>
50#include <VBox/vmm/pdmapic.h>
51#include <VBox/sup.h>
52#include <VBox/msi.h>
53#include <iprt/assert.h>
54#include <iprt/critsect.h>
55#ifdef IN_RING3
56# include <iprt/thread.h>
57#endif
58
59RT_C_DECLS_BEGIN
60
61
62/** @defgroup grp_pdm_int Internal
63 * @ingroup grp_pdm
64 * @internal
65 * @{
66 */
67
68/** @def PDM_WITH_R3R0_CRIT_SECT
69 * Enables or disabled ring-3/ring-0 critical sections. */
70#if defined(DOXYGEN_RUNNING) || 1
71# define PDM_WITH_R3R0_CRIT_SECT
72#endif
73
74/** @def PDMCRITSECT_STRICT
75 * Enables/disables PDM critsect strictness like deadlock detection. */
76#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
77 || defined(DOXYGEN_RUNNING)
78# define PDMCRITSECT_STRICT
79#endif
80
81/** @def PDMCRITSECT_STRICT
82 * Enables/disables PDM read/write critsect strictness like deadlock
83 * detection. */
84#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
85 || defined(DOXYGEN_RUNNING)
86# define PDMCRITSECTRW_STRICT
87#endif
88
89/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
90#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
91/** The maximum device instance (total) size, ring-3 only devices. */
92#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
93/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
94#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK HOST_PAGE_SIZE
95
96
97
98/*******************************************************************************
99* Structures and Typedefs *
100*******************************************************************************/
101
102/** Pointer to a PDM Device. */
103typedef struct PDMDEV *PPDMDEV;
104/** Pointer to a pointer to a PDM Device. */
105typedef PPDMDEV *PPPDMDEV;
106
107/** Pointer to a PDM USB Device. */
108typedef struct PDMUSB *PPDMUSB;
109/** Pointer to a pointer to a PDM USB Device. */
110typedef PPDMUSB *PPPDMUSB;
111
112/** Pointer to a PDM Driver. */
113typedef struct PDMDRV *PPDMDRV;
114/** Pointer to a pointer to a PDM Driver. */
115typedef PPDMDRV *PPPDMDRV;
116
117/** Pointer to a PDM Logical Unit. */
118typedef struct PDMLUN *PPDMLUN;
119/** Pointer to a pointer to a PDM Logical Unit. */
120typedef PPDMLUN *PPPDMLUN;
121
122/** Pointer to a DMAC instance. */
123typedef struct PDMDMAC *PPDMDMAC;
124/** Pointer to a RTC instance. */
125typedef struct PDMRTC *PPDMRTC;
126
127/** Pointer to an USB HUB registration record. */
128typedef struct PDMUSBHUB *PPDMUSBHUB;
129
130/**
131 * Supported asynchronous completion endpoint classes.
132 */
133typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
134{
135 /** File class. */
136 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
137 /** Number of supported classes. */
138 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
139 /** 32bit hack. */
140 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
141} PDMASYNCCOMPLETIONEPCLASSTYPE;
142
143
144/**
145 * MMIO/IO port registration tracking structure for DBGF tracing.
146 */
147typedef struct PDMDEVINSDBGFTRACK
148{
149 /** Flag whether this tracks a IO port or MMIO registration. */
150 bool fMmio;
151 /** Opaque user data passed during registration. */
152 void *pvUser;
153 /** Type dependent data. */
154 union
155 {
156 /** I/O port registration. */
157 struct
158 {
159 /** IOM I/O port handle. */
160 IOMIOPORTHANDLE hIoPorts;
161 /** Original OUT handler of the device. */
162 PFNIOMIOPORTNEWOUT pfnOut;
163 /** Original IN handler of the device. */
164 PFNIOMIOPORTNEWIN pfnIn;
165 /** Original string OUT handler of the device. */
166 PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
167 /** Original string IN handler of the device. */
168 PFNIOMIOPORTNEWINSTRING pfnInStr;
169 } IoPort;
170 /** MMIO registration. */
171 struct
172 {
173 /** IOM MMIO region handle. */
174 IOMMMIOHANDLE hMmioRegion;
175 /** Original MMIO write handler of the device. */
176 PFNIOMMMIONEWWRITE pfnWrite;
177 /** Original MMIO read handler of the device. */
178 PFNIOMMMIONEWREAD pfnRead;
179 /** Original MMIO fill handler of the device. */
180 PFNIOMMMIONEWFILL pfnFill;
181 } Mmio;
182 } u;
183} PDMDEVINSDBGFTRACK;
184/** Pointer to a MMIO/IO port registration tracking structure. */
185typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
186/** Pointer to a const MMIO/IO port registration tracking structure. */
187typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
188
189
190/**
191 * Private device instance data, ring-3.
192 */
193typedef struct PDMDEVINSINTR3
194{
195 /** Pointer to the next instance.
196 * (Head is pointed to by PDM::pDevInstances.) */
197 R3PTRTYPE(PPDMDEVINS) pNextR3;
198 /** Pointer to the next per device instance.
199 * (Head is pointed to by PDMDEV::pInstances.) */
200 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
201 /** Pointer to device structure. */
202 R3PTRTYPE(PPDMDEV) pDevR3;
203 /** Pointer to the list of logical units associated with the device. (FIFO) */
204 R3PTRTYPE(PPDMLUN) pLunsR3;
205 /** Pointer to the asynchronous notification callback set while in
206 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
207 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
208 /** Configuration handle to the instance node. */
209 R3PTRTYPE(PCFGMNODE) pCfgHandle;
210
211 /** R3 pointer to the VM this instance was created for. */
212 PVMR3 pVMR3;
213 /** DBGF trace event source handle if tracing is configured. */
214 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
215 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
216 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
217 /** Index of the next entry to use for tracking. */
218 uint32_t idxDbgfTraceTrackNext;
219 /** Maximum number of records fitting into the single page. */
220 uint32_t cDbgfTraceTrackMax;
221
222 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
223 uint32_t fIntFlags;
224 /** The last IRQ tag (for tracing it thru clearing). */
225 uint32_t uLastIrqTag;
226 /** The ring-0 device index (for making ring-0 calls). */
227 uint32_t idxR0Device;
228} PDMDEVINSINTR3;
229
230
231/**
232 * Private device instance data, ring-0.
233 */
234typedef struct PDMDEVINSINTR0
235{
236 /** Pointer to the VM this instance was created for. */
237 R0PTRTYPE(PGVM) pGVM;
238 /** Pointer to device structure. */
239 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
240 /** The ring-0 module reference. */
241 RTR0PTR hMod;
242 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
243 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
244 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
245 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
246 /** DBGF trace event source handle if tracing is configured. */
247 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
248 /** The device instance memory. */
249 RTR0MEMOBJ hMemObj;
250 /** The ring-3 mapping object. */
251 RTR0MEMOBJ hMapObj;
252 /** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
253 RTR0MEMOBJ hDbgfTraceObj;
254 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
255 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
256 /** Index of the next entry to use for tracking. */
257 uint32_t idxDbgfTraceTrackNext;
258 /** Maximum number of records fitting into the single page. */
259 uint32_t cDbgfTraceTrackMax;
260 /** Index into PDMR0PERVM::apDevInstances. */
261 uint32_t idxR0Device;
262} PDMDEVINSINTR0;
263
264
265/**
266 * Private device instance data, raw-mode
267 */
268typedef struct PDMDEVINSINTRC
269{
270 /** Pointer to the VM this instance was created for. */
271 RGPTRTYPE(PVM) pVMRC;
272} PDMDEVINSINTRC;
273
274
275/**
276 * Private device instance data.
277 */
278typedef struct PDMDEVINSINT
279{
280 /** Pointer to the next instance (HC Ptr).
281 * (Head is pointed to by PDM::pDevInstances.) */
282 R3PTRTYPE(PPDMDEVINS) pNextR3;
283 /** Pointer to the next per device instance (HC Ptr).
284 * (Head is pointed to by PDMDEV::pInstances.) */
285 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
286 /** Pointer to device structure - HC Ptr. */
287 R3PTRTYPE(PPDMDEV) pDevR3;
288 /** Pointer to the list of logical units associated with the device. (FIFO) */
289 R3PTRTYPE(PPDMLUN) pLunsR3;
290 /** Pointer to the asynchronous notification callback set while in
291 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
292 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
293 /** Configuration handle to the instance node. */
294 R3PTRTYPE(PCFGMNODE) pCfgHandle;
295
296 /** R3 pointer to the VM this instance was created for. */
297 PVMR3 pVMR3;
298
299 /** R0 pointer to the VM this instance was created for. */
300 R0PTRTYPE(PVMCC) pVMR0;
301
302 /** RC pointer to the VM this instance was created for. */
303 PVMRC pVMRC;
304
305 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
306 uint32_t fIntFlags;
307 /** The last IRQ tag (for tracing it thru clearing). */
308 uint32_t uLastIrqTag;
309} PDMDEVINSINT;
310
311/** @name PDMDEVINSINT::fIntFlags
312 * @{ */
313/** Used by pdmR3Load to mark device instances it found in the saved state. */
314#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
315/** Indicates that the device hasn't been powered on or resumed.
316 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
317 * to make sure each device gets exactly one notification for each of those
318 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
319 * a failure (already resumed/powered-on devices are suspended).
320 * PDMR3PowerOff resets this flag once before going through the devices to make sure
321 * every device gets the power off notification even if it was suspended before with
322 * PDMR3Suspend.
323 */
324#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
325/** Indicates that the device has been reset already. Used by PDMR3Reset. */
326#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
327#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
328#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
329/** Set if we've called the ring-0 constructor. */
330#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
331/** Set if using non-default critical section. */
332#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
333/** @} */
334
335
336/**
337 * Private USB device instance data.
338 */
339typedef struct PDMUSBINSINT
340{
341 /** The UUID of this instance. */
342 RTUUID Uuid;
343 /** Pointer to the next instance.
344 * (Head is pointed to by PDM::pUsbInstances.) */
345 R3PTRTYPE(PPDMUSBINS) pNext;
346 /** Pointer to the next per USB device instance.
347 * (Head is pointed to by PDMUSB::pInstances.) */
348 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
349
350 /** Pointer to device structure. */
351 R3PTRTYPE(PPDMUSB) pUsbDev;
352
353 /** Pointer to the VM this instance was created for. */
354 PVMR3 pVM;
355 /** Pointer to the list of logical units associated with the device. (FIFO) */
356 R3PTRTYPE(PPDMLUN) pLuns;
357 /** The per instance device configuration. */
358 R3PTRTYPE(PCFGMNODE) pCfg;
359 /** Same as pCfg if the configuration should be deleted when detaching the device. */
360 R3PTRTYPE(PCFGMNODE) pCfgDelete;
361 /** The global device configuration. */
362 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
363
364 /** Pointer to the USB hub this device is attached to.
365 * This is NULL if the device isn't connected to any HUB. */
366 R3PTRTYPE(PPDMUSBHUB) pHub;
367 /** The port number that we're connected to. */
368 uint32_t iPort;
369 /** Indicates that the USB device hasn't been powered on or resumed.
370 * See PDMDEVINSINT_FLAGS_SUSPENDED.
371 * @note Runtime attached USB devices gets a pfnHotPlugged callback rather than
372 * a pfnVMResume one. */
373 bool fVMSuspended;
374 /** Indicates that the USB device has been reset. */
375 bool fVMReset;
376 /** Pointer to the asynchronous notification callback set while in
377 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
378 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
379} PDMUSBINSINT;
380
381
382/**
383 * Private driver instance data.
384 */
385typedef struct PDMDRVINSINT
386{
387 /** Pointer to the driver instance above.
388 * This is NULL for the topmost drive. */
389 R3PTRTYPE(PPDMDRVINS) pUp;
390 /** Pointer to the driver instance below.
391 * This is NULL for the bottommost driver. */
392 R3PTRTYPE(PPDMDRVINS) pDown;
393 /** Pointer to the logical unit this driver chained on. */
394 R3PTRTYPE(PPDMLUN) pLun;
395 /** Pointer to driver structure from which this was instantiated. */
396 R3PTRTYPE(PPDMDRV) pDrv;
397 /** Pointer to the VM this instance was created for, ring-3 context. */
398 PVMR3 pVMR3;
399 /** Pointer to the VM this instance was created for, ring-0 context. */
400 R0PTRTYPE(PVMCC) pVMR0;
401 /** Pointer to the VM this instance was created for, raw-mode context. */
402 PVMRC pVMRC;
403 /** Flag indicating that the driver is being detached and destroyed.
404 * (Helps detect potential recursive detaching.) */
405 bool fDetaching;
406 /** Indicates that the driver hasn't been powered on or resumed.
407 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
408 bool fVMSuspended;
409 /** Indicates that the driver has been reset already. */
410 bool fVMReset;
411 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
412 bool fHyperHeap;
413 /** Pointer to the asynchronous notification callback set while in
414 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
415 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
416 /** Configuration handle to the instance node. */
417 R3PTRTYPE(PCFGMNODE) pCfgHandle;
418 /** Pointer to the ring-0 request handler function. */
419 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
420 /** Pointer to the next instance (starts at PDMDRV::pInstances). */
421 R3PTRTYPE(PPDMDRVINS) pNext;
422} PDMDRVINSINT;
423
424
425/**
426 * Private critical section data.
427 */
428typedef struct PDMCRITSECTINT
429{
430 /** The critical section core which is shared with IPRT.
431 * @note The semaphore is a SUPSEMEVENT. */
432 RTCRITSECT Core;
433 /** Pointer to the next critical section.
434 * This chain is used for device cleanup and the dbgf info item. */
435 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
436 /** Owner identifier.
437 * This is pDevIns if the owner is a device. Similarly for a driver or service.
438 * PDMR3CritSectInit() sets this to point to the critsect itself. */
439 RTR3PTR pvKey;
440 /** Set if this critical section is the automatically created default
441 * section of a device. */
442 bool fAutomaticDefaultCritsect;
443 /** Set if the critical section is used by a timer or similar.
444 * See PDMR3DevGetCritSect. */
445 bool fUsedByTimerOrSimilar;
446 /** Alignment padding. */
447 bool afPadding[2+4];
448 /** Support driver event semaphore that is scheduled to be signaled upon leaving
449 * the critical section. This is only for Ring-3 and Ring-0. */
450 SUPSEMEVENT volatile hEventToSignal;
451 /** The lock name. */
452 R3PTRTYPE(const char *) pszName;
453 /** The ring-3 pointer to this critical section, for leave queueing. */
454 R3PTRTYPE(PPDMCRITSECT) pSelfR3;
455 /** R0/RC lock contention. */
456 STAMCOUNTER StatContentionRZLock;
457 /** R0/RC lock contention: returning rcBusy or VERR_SEM_BUSY (try). */
458 STAMCOUNTER StatContentionRZLockBusy;
459 /** R0/RC lock contention: Profiling waiting time. */
460 STAMPROFILE StatContentionRZWait;
461 /** R0/RC unlock contention. */
462 STAMCOUNTER StatContentionRZUnlock;
463 /** R3 lock contention. */
464 STAMCOUNTER StatContentionR3;
465 /** R3 lock contention: Profiling waiting time. */
466 STAMPROFILE StatContentionR3Wait;
467 /** Profiling the time the section is locked. */
468 STAMPROFILEADV StatLocked;
469} PDMCRITSECTINT;
470AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
471/** Pointer to private critical section data. */
472typedef PDMCRITSECTINT *PPDMCRITSECTINT;
473
474/** Special magic value set when we failed to abort entering in ring-0 due to a
475 * timeout, interruption or pending thread termination. */
476#define PDMCRITSECT_MAGIC_FAILED_ABORT UINT32_C(0x0bad0326)
477/** Special magic value set if we detected data/state corruption. */
478#define PDMCRITSECT_MAGIC_CORRUPTED UINT32_C(0x0bad2603)
479
480/** Indicates that the critical section is queued for unlock.
481 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
482#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
483
484
485/**
486 * Private critical section data.
487 */
488typedef struct PDMCRITSECTRWINT
489{
490 /** The read/write critical section core which is shared with IPRT.
491 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
492 RTCRITSECTRW Core;
493
494 /** Pointer to the next critical section.
495 * This chain is used for device cleanup and the dbgf info item. */
496 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
497 /** Self pointer. */
498 R3PTRTYPE(PPDMCRITSECTRW) pSelfR3;
499 /** Owner identifier.
500 * This is pDevIns if the owner is a device. Similarly for a driver or service.
501 * PDMR3CritSectRwInit() sets this to point to the critsect itself. */
502 RTR3PTR pvKey;
503 /** The lock name. */
504 R3PTRTYPE(const char *) pszName;
505
506 /** R0/RC write lock contention. */
507 STAMCOUNTER StatContentionRZEnterExcl;
508 /** R0/RC write unlock contention. */
509 STAMCOUNTER StatContentionRZLeaveExcl;
510 /** R0/RC read lock contention. */
511 STAMCOUNTER StatContentionRZEnterShared;
512 /** R0/RC read unlock contention. */
513 STAMCOUNTER StatContentionRZLeaveShared;
514 /** R0/RC writes. */
515 STAMCOUNTER StatRZEnterExcl;
516 /** R0/RC reads. */
517 STAMCOUNTER StatRZEnterShared;
518 /** R3 write lock contention. */
519 STAMCOUNTER StatContentionR3EnterExcl;
520 /** R3 write unlock contention. */
521 STAMCOUNTER StatContentionR3LeaveExcl;
522 /** R3 read lock contention. */
523 STAMCOUNTER StatContentionR3EnterShared;
524 /** R3 writes. */
525 STAMCOUNTER StatR3EnterExcl;
526 /** R3 reads. */
527 STAMCOUNTER StatR3EnterShared;
528 /** Profiling the time the section is write locked. */
529 STAMPROFILEADV StatWriteLocked;
530} PDMCRITSECTRWINT;
531AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
532AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u, 16);
533AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u.s.u64State, 8);
534/** Pointer to private critical section data. */
535typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
536
537/** Special magic value we set the structure has become corrupted. */
538#define PDMCRITSECTRW_MAGIC_CORRUPT UINT32_C(0x0bad0620)
539
540
541/**
542 * The usual device/driver/internal/external stuff.
543 */
544typedef enum
545{
546 /** The usual invalid entry. */
547 PDMTHREADTYPE_INVALID = 0,
548 /** Device type. */
549 PDMTHREADTYPE_DEVICE,
550 /** USB Device type. */
551 PDMTHREADTYPE_USB,
552 /** Driver type. */
553 PDMTHREADTYPE_DRIVER,
554 /** Internal type. */
555 PDMTHREADTYPE_INTERNAL,
556 /** External type. */
557 PDMTHREADTYPE_EXTERNAL,
558 /** The usual 32-bit hack. */
559 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
560} PDMTHREADTYPE;
561
562
563/**
564 * The internal structure for the thread.
565 */
566typedef struct PDMTHREADINT
567{
568 /** The VM pointer. */
569 PVMR3 pVM;
570 /** The event semaphore the thread blocks on when not running. */
571 RTSEMEVENTMULTI BlockEvent;
572 /** The event semaphore the thread sleeps on while running. */
573 RTSEMEVENTMULTI SleepEvent;
574 /** Pointer to the next thread. */
575 R3PTRTYPE(struct PDMTHREAD *) pNext;
576 /** The thread type. */
577 PDMTHREADTYPE enmType;
578} PDMTHREADINT;
579
580
581
582/* Must be included after PDMDEVINSINT is defined. */
583#define PDMDEVINSINT_DECLARED
584#define PDMUSBINSINT_DECLARED
585#define PDMDRVINSINT_DECLARED
586#define PDMCRITSECTINT_DECLARED
587#define PDMCRITSECTRWINT_DECLARED
588#define PDMTHREADINT_DECLARED
589#ifdef ___VBox_pdm_h
590# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
591#endif
592RT_C_DECLS_END
593#include <VBox/vmm/pdm.h>
594RT_C_DECLS_BEGIN
595
596/**
597 * PDM Logical Unit.
598 *
599 * This typically the representation of a physical port on a
600 * device, like for instance the PS/2 keyboard port on the
601 * keyboard controller device. The LUNs are chained on the
602 * device they belong to (PDMDEVINSINT::pLunsR3).
603 */
604typedef struct PDMLUN
605{
606 /** The LUN - The Logical Unit Number. */
607 RTUINT iLun;
608 /** Pointer to the next LUN. */
609 PPDMLUN pNext;
610 /** Pointer to the top driver in the driver chain. */
611 PPDMDRVINS pTop;
612 /** Pointer to the bottom driver in the driver chain. */
613 PPDMDRVINS pBottom;
614 /** Pointer to the device instance which the LUN belongs to.
615 * Either this is set or pUsbIns is set. Both are never set at the same time. */
616 PPDMDEVINS pDevIns;
617 /** Pointer to the USB device instance which the LUN belongs to. */
618 PPDMUSBINS pUsbIns;
619 /** Pointer to the device base interface. */
620 PPDMIBASE pBase;
621 /** Description of this LUN. */
622 const char *pszDesc;
623} PDMLUN;
624
625
626/**
627 * PDM Device, ring-3.
628 */
629typedef struct PDMDEV
630{
631 /** Pointer to the next device (R3 Ptr). */
632 R3PTRTYPE(PPDMDEV) pNext;
633 /** Device name length. (search optimization) */
634 uint32_t cchName;
635 /** Registration structure. */
636 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
637 /** Number of instances. */
638 uint32_t cInstances;
639 /** Pointer to chain of instances (R3 Ptr). */
640 PPDMDEVINSR3 pInstances;
641 /** The search path for raw-mode context modules (';' as separator). */
642 char *pszRCSearchPath;
643 /** The search path for ring-0 context modules (';' as separator). */
644 char *pszR0SearchPath;
645} PDMDEV;
646
647
648#if 0
649/**
650 * PDM Device, ring-0.
651 */
652typedef struct PDMDEVR0
653{
654 /** Pointer to the next device. */
655 R0PTRTYPE(PPDMDEVR0) pNext;
656 /** Device name length. (search optimization) */
657 uint32_t cchName;
658 /** Registration structure. */
659 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
660 /** Number of instances. */
661 uint32_t cInstances;
662 /** Pointer to chain of instances. */
663 PPDMDEVINSR0 pInstances;
664} PDMDEVR0;
665#endif
666
667
668/**
669 * PDM USB Device.
670 */
671typedef struct PDMUSB
672{
673 /** Pointer to the next device (R3 Ptr). */
674 R3PTRTYPE(PPDMUSB) pNext;
675 /** Device name length. (search optimization) */
676 RTUINT cchName;
677 /** Registration structure. */
678 R3PTRTYPE(const struct PDMUSBREG *) pReg;
679 /** Next instance number. */
680 uint32_t iNextInstance;
681 /** Pointer to chain of instances (R3 Ptr). */
682 R3PTRTYPE(PPDMUSBINS) pInstances;
683} PDMUSB;
684
685
686/**
687 * PDM Driver.
688 */
689typedef struct PDMDRV
690{
691 /** Pointer to the next device. */
692 PPDMDRV pNext;
693 /** Registration structure. */
694 const struct PDMDRVREG * pReg;
695 /** Current number of instances. */
696 uint32_t cInstances;
697 /** The next instance number. */
698 uint32_t iNextInstance;
699 /** The search path for raw-mode context modules (';' as separator). */
700 char *pszRCSearchPath;
701 /** The search path for ring-0 context modules (';' as separator). */
702 char *pszR0SearchPath;
703 /** Pointer to chain of instances. */
704 PPDMDRVINSR3 pInstances;
705} PDMDRV;
706
707
708/**
709 * PDM IOMMU, shared ring-3.
710 */
711typedef struct PDMIOMMUR3
712{
713 /** IOMMU index. */
714 uint32_t idxIommu;
715 uint32_t uPadding0; /**< Alignment padding.*/
716
717 /** Pointer to the IOMMU device instance - R3. */
718 PPDMDEVINSR3 pDevInsR3;
719 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
720 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
721 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
722 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
723 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
724 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
725 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
726 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
727} PDMIOMMUR3;
728/** Pointer to a PDM IOMMU instance. */
729typedef PDMIOMMUR3 *PPDMIOMMUR3;
730/** Pointer to a const PDM IOMMU instance. */
731typedef const PDMIOMMUR3 *PCPDMIOMMUR3;
732
733
734/**
735 * PDM IOMMU, ring-0.
736 */
737typedef struct PDMIOMMUR0
738{
739 /** IOMMU index. */
740 uint32_t idxIommu;
741 uint32_t uPadding0; /**< Alignment padding.*/
742
743 /** Pointer to IOMMU device instance. */
744 PPDMDEVINSR0 pDevInsR0;
745 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
746 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
747 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
748 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
749 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
750 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
751 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
752 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
753} PDMIOMMUR0;
754/** Pointer to a ring-0 IOMMU data. */
755typedef PDMIOMMUR0 *PPDMIOMMUR0;
756/** Pointer to a const ring-0 IOMMU data. */
757typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
758
759/** Pointer to a PDM IOMMU for the current context. */
760#ifdef IN_RING3
761typedef PPDMIOMMUR3 PPDMIOMMU;
762#else
763typedef PPDMIOMMUR0 PPDMIOMMU;
764#endif
765
766
767/**
768 * PDM registered PIC device.
769 */
770typedef struct PDMPIC
771{
772 /** Pointer to the PIC device instance - R3. */
773 PPDMDEVINSR3 pDevInsR3;
774 /** @copydoc PDMPICREG::pfnSetIrq */
775 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
776 /** @copydoc PDMPICREG::pfnGetInterrupt */
777 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
778
779 /** Pointer to the PIC device instance - R0. */
780 PPDMDEVINSR0 pDevInsR0;
781 /** @copydoc PDMPICREG::pfnSetIrq */
782 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
783 /** @copydoc PDMPICREG::pfnGetInterrupt */
784 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
785
786 /** Pointer to the PIC device instance - RC. */
787 PPDMDEVINSRC pDevInsRC;
788 /** @copydoc PDMPICREG::pfnSetIrq */
789 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
790 /** @copydoc PDMPICREG::pfnGetInterrupt */
791 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
792 /** Alignment padding. */
793 RTRCPTR RCPtrPadding;
794} PDMPIC;
795
796
797/**
798 * PDM IC (Interrupt Controller), shared ring-3.
799 */
800typedef struct PDMICR3
801{
802 /** Pointer to the interrupt controller instance - R3 Ptr. */
803 PPDMDEVINSR3 pDevInsR3;
804#ifndef VBOX_VMM_TARGET_ARMV8
805 /** The type of APIC backend. */
806 PDMAPICBACKENDTYPE enmKind;
807 uint32_t uPadding;
808 /** The APIC backend. */
809 PDMAPICBACKENDR3 ApicBackend;
810#else
811 /** @todo The GIC backend. Currently the padding helps keep alignment common
812 * between x86 and arm. */
813 uint8_t auPadding[4+4+232];
814#endif
815} PDMICR3;
816AssertCompileSizeAlignment(PDMICR3, 8);
817
818/**
819 * PDM IC (Interrupt Controller), ring-0.
820 */
821typedef struct PDMICR0
822{
823 /** Pointer to the interrupt controller instance - R0 Ptr. */
824 PPDMDEVINSR0 pDevInsR0;
825#ifndef VBOX_VMM_TARGET_ARMV8
826 /** The APIC backend. */
827 PDMAPICBACKENDR0 ApicBackend;
828#else
829 /** @todo The GIC backend. Currently the padding helps keep alignment common
830 * between x86 and arm. */
831 uint8_t auPadding[232];
832#endif
833} PDMICR0;
834AssertCompileSizeAlignment(PDMICR0, 8);
835
836/**
837 * PDM IC (Interrupt Controller), raw-mode context.
838 */
839typedef struct PDMICRC
840{
841 /** Pointer to the interrupt controller instance - R0 Ptr. */
842 PPDMDEVINSRC pDevInsR0;
843 RTRCPTR avPadding;
844#ifndef VBOX_VMM_TARGET_ARMV8
845 /** The APIC backend. */
846 PDMAPICBACKENDRC ApicBackend;
847#else
848 /** @todo The GIC backend. Currently the padding helps keep alignment common
849 * between x86 and arm. */
850 uint8_t auPadding[232];
851#endif
852} PDMICRC;
853AssertCompileSizeAlignment(PDMICRC, 8);
854
855/**
856 * PDM registered I/O APIC device.
857 */
858typedef struct PDMIOAPIC
859{
860 /** Pointer to the I/O APIC device instance - R3 Ptr. */
861 PPDMDEVINSR3 pDevInsR3;
862 /** @copydoc PDMIOAPICREG::pfnSetIrq */
863 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
864 /** @copydoc PDMIOAPICREG::pfnSendMsi */
865 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
866 /** @copydoc PDMIOAPICREG::pfnSetEoi */
867 DECLR3CALLBACKMEMBER(void, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
868
869 /** Pointer to the I/O APIC device instance - R0. */
870 PPDMDEVINSR0 pDevInsR0;
871 /** @copydoc PDMIOAPICREG::pfnSetIrq */
872 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
873 /** @copydoc PDMIOAPICREG::pfnSendMsi */
874 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
875 /** @copydoc PDMIOAPICREG::pfnSetEoi */
876 DECLR0CALLBACKMEMBER(void, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
877
878 /** Pointer to the I/O APIC device instance - RC Ptr. */
879 PPDMDEVINSRC pDevInsRC;
880 /** @copydoc PDMIOAPICREG::pfnSetIrq */
881 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
882 /** @copydoc PDMIOAPICREG::pfnSendMsi */
883 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
884 /** @copydoc PDMIOAPICREG::pfnSendMsi */
885 DECLRCCALLBACKMEMBER(void, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
886} PDMIOAPIC;
887/** Pointer to a PDM IOAPIC instance. */
888typedef PDMIOAPIC *PPDMIOAPIC;
889/** Pointer to a const PDM IOAPIC instance. */
890typedef PDMIOAPIC const *PCPDMIOAPIC;
891
892/** Maximum number of PCI busses for a VM. */
893#define PDM_PCI_BUSSES_MAX 8
894/** Maximum number of IOMMUs (at most one per PCI bus). */
895#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
896
897
898#ifdef IN_RING3
899/**
900 * PDM registered firmware device.
901 */
902typedef struct PDMFW
903{
904 /** Pointer to the firmware device instance. */
905 PPDMDEVINSR3 pDevIns;
906 /** Copy of the registration structure. */
907 PDMFWREG Reg;
908} PDMFW;
909/** Pointer to a firmware instance. */
910typedef PDMFW *PPDMFW;
911#endif
912
913
914/**
915 * PDM PCI bus instance.
916 */
917typedef struct PDMPCIBUS
918{
919 /** PCI bus number. */
920 uint32_t iBus;
921 uint32_t uPadding0; /**< Alignment padding.*/
922
923 /** Pointer to PCI bus device instance. */
924 PPDMDEVINSR3 pDevInsR3;
925 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
926 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
927
928 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
929 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
930 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
931 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
932 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
933 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
934 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
935 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
936 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
937 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
938 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
939 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
940 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
941 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
942 uint32_t uAddress, unsigned cb, uint32_t u32Value));
943 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
944 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
945 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
946} PDMPCIBUS;
947/** Pointer to a PDM PCI Bus instance. */
948typedef PDMPCIBUS *PPDMPCIBUS;
949/** Pointer to a const PDM PCI Bus instance. */
950typedef const PDMPCIBUS *PCPDMPCIBUS;
951
952
953/**
954 * Ring-0 PDM PCI bus instance data.
955 */
956typedef struct PDMPCIBUSR0
957{
958 /** PCI bus number. */
959 uint32_t iBus;
960 uint32_t uPadding0; /**< Alignment padding.*/
961 /** Pointer to PCI bus device instance. */
962 PPDMDEVINSR0 pDevInsR0;
963 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
964 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
965} PDMPCIBUSR0;
966/** Pointer to the ring-0 PCI bus data. */
967typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
968/** Pointer to the const ring-0 PCI bus data. */
969typedef const PDMPCIBUSR0 *PCPDMPCIBUSR0;
970
971
972#ifdef IN_RING3
973/**
974 * PDM registered DMAC (DMA Controller) device.
975 */
976typedef struct PDMDMAC
977{
978 /** Pointer to the DMAC device instance. */
979 PPDMDEVINSR3 pDevIns;
980 /** Copy of the registration structure. */
981 PDMDMACREG Reg;
982} PDMDMAC;
983
984
985/**
986 * PDM registered RTC (Real Time Clock) device.
987 */
988typedef struct PDMRTC
989{
990 /** Pointer to the RTC device instance. */
991 PPDMDEVINSR3 pDevIns;
992 /** Copy of the registration structure. */
993 PDMRTCREG Reg;
994} PDMRTC;
995
996#endif /* IN_RING3 */
997
998/**
999 * Module type.
1000 */
1001typedef enum PDMMODTYPE
1002{
1003 /** Raw-mode (RC) context module. */
1004 PDMMOD_TYPE_RC,
1005 /** Ring-0 (host) context module. */
1006 PDMMOD_TYPE_R0,
1007 /** Ring-3 (host) context module. */
1008 PDMMOD_TYPE_R3
1009} PDMMODTYPE;
1010
1011
1012/** The module name length including the terminator. */
1013#define PDMMOD_NAME_LEN 32
1014
1015/**
1016 * Loaded module instance.
1017 */
1018typedef struct PDMMOD
1019{
1020 /** Module name. This is used for referring to
1021 * the module internally, sort of like a handle. */
1022 char szName[PDMMOD_NAME_LEN];
1023 /** Module type. */
1024 PDMMODTYPE eType;
1025 /** Loader module handle. Not used for R0 modules. */
1026 RTLDRMOD hLdrMod;
1027 /** Loaded address.
1028 * This is the 'handle' for R0 modules. */
1029 RTUINTPTR ImageBase;
1030 /** Old loaded address.
1031 * This is used during relocation of GC modules. Not used for R0 modules. */
1032 RTUINTPTR OldImageBase;
1033 /** Where the R3 HC bits are stored.
1034 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
1035 void *pvBits;
1036
1037 /** Pointer to next module. */
1038 struct PDMMOD *pNext;
1039 /** Module filename. */
1040 char szFilename[1];
1041} PDMMOD;
1042/** Pointer to loaded module instance. */
1043typedef PDMMOD *PPDMMOD;
1044
1045
1046
1047/** Max number of items in a queue. */
1048#define PDMQUEUE_MAX_ITEMS _16K
1049/** Max item size. */
1050#define PDMQUEUE_MAX_ITEM_SIZE _1M
1051/** Max total queue item size for ring-0 capable queues. */
1052#define PDMQUEUE_MAX_TOTAL_SIZE_R0 _8M
1053/** Max total queue item size for ring-3 only queues. */
1054#define PDMQUEUE_MAX_TOTAL_SIZE_R3 _32M
1055
1056/**
1057 * Queue type.
1058 */
1059typedef enum PDMQUEUETYPE
1060{
1061 /** Device consumer. */
1062 PDMQUEUETYPE_DEV = 1,
1063 /** Driver consumer. */
1064 PDMQUEUETYPE_DRV,
1065 /** Internal consumer. */
1066 PDMQUEUETYPE_INTERNAL,
1067 /** External consumer. */
1068 PDMQUEUETYPE_EXTERNAL
1069} PDMQUEUETYPE;
1070
1071/**
1072 * PDM Queue.
1073 */
1074typedef struct PDMQUEUE
1075{
1076 /** Magic value (PDMQUEUE_MAGIC). */
1077 uint32_t u32Magic;
1078 /** Item size (bytes). */
1079 uint32_t cbItem;
1080 /** Number of items in the queue. */
1081 uint32_t cItems;
1082 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1083 uint32_t offItems;
1084
1085 /** Interval timer. Only used if cMilliesInterval is non-zero. */
1086 TMTIMERHANDLE hTimer;
1087 /** The interval between checking the queue for events.
1088 * The realtime timer below is used to do the waiting.
1089 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1090 uint32_t cMilliesInterval;
1091
1092 /** This is VINF_SUCCESS if the queue is okay, error status if not. */
1093 int32_t rcOkay;
1094 uint32_t u32Padding;
1095
1096 /** Queue type. */
1097 PDMQUEUETYPE enmType;
1098 /** Type specific data. */
1099 union
1100 {
1101 /** PDMQUEUETYPE_DEV */
1102 struct
1103 {
1104 /** Pointer to consumer function. */
1105 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1106 /** Pointer to the device instance owning the queue. */
1107 R3PTRTYPE(PPDMDEVINS) pDevIns;
1108 } Dev;
1109 /** PDMQUEUETYPE_DRV */
1110 struct
1111 {
1112 /** Pointer to consumer function. */
1113 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1114 /** Pointer to the driver instance owning the queue. */
1115 R3PTRTYPE(PPDMDRVINS) pDrvIns;
1116 } Drv;
1117 /** PDMQUEUETYPE_INTERNAL */
1118 struct
1119 {
1120 /** Pointer to consumer function. */
1121 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1122 } Int;
1123 /** PDMQUEUETYPE_EXTERNAL */
1124 struct
1125 {
1126 /** Pointer to consumer function. */
1127 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1128 /** Pointer to user argument. */
1129 R3PTRTYPE(void *) pvUser;
1130 } Ext;
1131 struct
1132 {
1133 /** Generic callback pointer. */
1134 RTR3PTR pfnCallback;
1135 /** Generic owner pointer. */
1136 RTR3PTR pvOwner;
1137 } Gen;
1138 } u;
1139
1140 /** Unique queue name. */
1141 char szName[40];
1142
1143 /** LIFO of pending items (item index), UINT32_MAX if empty. */
1144 uint32_t volatile iPending;
1145
1146 /** State: Pending items. */
1147 uint32_t volatile cStatPending;
1148 /** Stat: Times PDMQueueAlloc fails. */
1149 STAMCOUNTER StatAllocFailures;
1150 /** Stat: PDMQueueInsert calls. */
1151 STAMCOUNTER StatInsert;
1152 /** Stat: Queue flushes. */
1153 STAMCOUNTER StatFlush;
1154 /** Stat: Queue flushes with pending items left over. */
1155 STAMCOUNTER StatFlushLeftovers;
1156 /** State: Profiling the flushing. */
1157 STAMPROFILE StatFlushPrf;
1158 uint64_t au64Padding[3];
1159
1160 /** Allocation bitmap: Set bits means free, clear means allocated. */
1161 RT_FLEXIBLE_ARRAY_EXTENSION
1162 uint64_t bmAlloc[RT_FLEXIBLE_ARRAY];
1163 /* The items follows after the end of the bitmap */
1164} PDMQUEUE;
1165AssertCompileMemberAlignment(PDMQUEUE, bmAlloc, 64);
1166/** Pointer to a PDM Queue. */
1167typedef struct PDMQUEUE *PPDMQUEUE;
1168
1169/** Magic value PDMQUEUE::u32Magic (Bud Powell). */
1170#define PDMQUEUE_MAGIC UINT32_C(0x19240927)
1171/** Magic value PDMQUEUE::u32Magic after destroy. */
1172#define PDMQUEUE_MAGIC_DEAD UINT32_C(0x19660731)
1173
1174/** @name PDM::fQueueFlushing
1175 * @{ */
1176/** Used to make sure only one EMT will flush the queues.
1177 * Set when an EMT is flushing queues, clear otherwise. */
1178#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1179/** Indicating there are queues with items pending.
1180 * This is make sure we don't miss inserts happening during flushing. The FF
1181 * cannot be used for this since it has to be cleared immediately to prevent
1182 * other EMTs from spinning. */
1183#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1184/** @} */
1185
1186/**
1187 * Ring-0 queue
1188 *
1189 * @author bird (2022-02-04)
1190 */
1191typedef struct PDMQUEUER0
1192{
1193 /** Pointer to the shared queue data. */
1194 R0PTRTYPE(PPDMQUEUE) pQueue;
1195 /** The memory allocation. */
1196 RTR0MEMOBJ hMemObj;
1197 /** The ring-3 mapping object. */
1198 RTR0MEMOBJ hMapObj;
1199 /** The owner pointer. This is NULL if not allocated. */
1200 RTR0PTR pvOwner;
1201 /** Queue item size. */
1202 uint32_t cbItem;
1203 /** Number of queue items. */
1204 uint32_t cItems;
1205 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1206 uint32_t offItems;
1207 uint32_t u32Reserved;
1208} PDMQUEUER0;
1209
1210
1211/** @name PDM task structures.
1212 * @{ */
1213
1214/**
1215 * A asynchronous user mode task.
1216 */
1217typedef struct PDMTASK
1218{
1219 /** Task owner type. */
1220 PDMTASKTYPE volatile enmType;
1221 /** Queue flags. */
1222 uint32_t volatile fFlags;
1223 /** User argument for the callback. */
1224 R3PTRTYPE(void *) volatile pvUser;
1225 /** The callback (will be cast according to enmType before callout). */
1226 R3PTRTYPE(PFNRT) volatile pfnCallback;
1227 /** The owner identifier. */
1228 R3PTRTYPE(void *) volatile pvOwner;
1229 /** Task name. */
1230 R3PTRTYPE(const char *) pszName;
1231 /** Number of times already triggered when PDMTaskTrigger was called. */
1232 uint32_t volatile cAlreadyTrigged;
1233 /** Number of runs. */
1234 uint32_t cRuns;
1235} PDMTASK;
1236/** Pointer to a PDM task. */
1237typedef PDMTASK *PPDMTASK;
1238
1239/**
1240 * A task set.
1241 *
1242 * This is served by one task executor thread.
1243 */
1244typedef struct PDMTASKSET
1245{
1246 /** Magic value (PDMTASKSET_MAGIC). */
1247 uint32_t u32Magic;
1248 /** Set if this task set works for ring-0 and raw-mode. */
1249 bool fRZEnabled;
1250 /** Number of allocated taks. */
1251 uint8_t volatile cAllocated;
1252 /** Base handle value for this set. */
1253 uint16_t uHandleBase;
1254 /** The task executor thread. */
1255 R3PTRTYPE(RTTHREAD) hThread;
1256 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1257 SUPSEMEVENT hEventR0;
1258 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1259 R3PTRTYPE(RTSEMEVENT) hEventR3;
1260 /** The VM pointer. */
1261 PVM pVM;
1262 /** Padding so fTriggered is in its own cacheline. */
1263 uint64_t au64Padding2[3];
1264
1265 /** Bitmask of triggered tasks. */
1266 uint64_t volatile fTriggered;
1267 /** Shutdown thread indicator. */
1268 bool volatile fShutdown;
1269 /** Padding. */
1270 bool volatile afPadding3[3];
1271 /** Task currently running, UINT32_MAX if idle. */
1272 uint32_t volatile idxRunning;
1273 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1274 uint64_t volatile au64Padding3[6];
1275
1276 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1277 PDMTASK aTasks[64];
1278} PDMTASKSET;
1279AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1280AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1281/** Magic value for PDMTASKSET::u32Magic (Quincy Delight Jones Jr.). */
1282#define PDMTASKSET_MAGIC UINT32_C(0x19330314)
1283/** Pointer to a task set. */
1284typedef PDMTASKSET *PPDMTASKSET;
1285
1286/** @} */
1287
1288
1289/** @name PDM Network Shaper
1290 * @{ */
1291
1292/**
1293 * Bandwidth group.
1294 */
1295typedef struct PDMNSBWGROUP
1296{
1297 /** Critical section protecting all members below. */
1298 PDMCRITSECT Lock;
1299 /** List of filters in this group (PDMNSFILTER). */
1300 RTLISTANCHORR3 FilterList;
1301 /** Reference counter - How many filters are associated with this group. */
1302 volatile uint32_t cRefs;
1303 uint32_t uPadding1;
1304 /** The group name. */
1305 char szName[PDM_NET_SHAPER_MAX_NAME_LEN + 1];
1306 /** Maximum number of bytes filters are allowed to transfer. */
1307 volatile uint64_t cbPerSecMax;
1308 /** Number of bytes we are allowed to transfer in one burst. */
1309 volatile uint32_t cbBucket;
1310 /** Number of bytes we were allowed to transfer at the last update. */
1311 volatile uint32_t cbTokensLast;
1312 /** Timestamp of the last update */
1313 volatile uint64_t tsUpdatedLast;
1314 /** Number of times a filter was choked. */
1315 volatile uint64_t cTotalChokings;
1316 /** Pad the structure to a multiple of 64 bytes. */
1317 uint64_t au64Padding[1];
1318} PDMNSBWGROUP;
1319AssertCompileSizeAlignment(PDMNSBWGROUP, 64);
1320/** Pointer to a bandwidth group. */
1321typedef PDMNSBWGROUP *PPDMNSBWGROUP;
1322
1323/** @} */
1324
1325
1326/**
1327 * Queue device helper task operation.
1328 */
1329typedef enum PDMDEVHLPTASKOP
1330{
1331 /** The usual invalid 0 entry. */
1332 PDMDEVHLPTASKOP_INVALID = 0,
1333 /** IsaSetIrq, IoApicSetIrq */
1334 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1335 /** PciSetIrq */
1336 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1337 /** PciSetIrq */
1338 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1339 /** IoApicSendMsi */
1340 PDMDEVHLPTASKOP_IOAPIC_SEND_MSI,
1341 /** IoApicSettEoi */
1342 PDMDEVHLPTASKOP_IOAPIC_SET_EOI,
1343 /** The usual 32-bit hack. */
1344 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1345} PDMDEVHLPTASKOP;
1346
1347/**
1348 * Queued Device Helper Task.
1349 */
1350typedef struct PDMDEVHLPTASK
1351{
1352 /** The queue item core (don't touch). */
1353 PDMQUEUEITEMCORE Core;
1354 /** Pointer to the device instance (R3 Ptr). */
1355 PPDMDEVINSR3 pDevInsR3;
1356 /** This operation to perform. */
1357 PDMDEVHLPTASKOP enmOp;
1358#if HC_ARCH_BITS == 64
1359 uint32_t Alignment0;
1360#endif
1361 /** Parameters to the operation. */
1362 union PDMDEVHLPTASKPARAMS
1363 {
1364 /**
1365 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1366 */
1367 struct PDMDEVHLPTASKISASETIRQ
1368 {
1369 /** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1370 PCIBDF uBusDevFn;
1371 /** The IRQ */
1372 int iIrq;
1373 /** The new level. */
1374 int iLevel;
1375 /** The IRQ tag and source. */
1376 uint32_t uTagSrc;
1377 } IsaSetIrq, IoApicSetIrq;
1378
1379 /**
1380 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1381 */
1382 struct PDMDEVHLPTASKPCISETIRQ
1383 {
1384 /** Index of the PCI device (into PDMDEVINSR3::apPciDevs). */
1385 uint32_t idxPciDev;
1386 /** The IRQ */
1387 int32_t iIrq;
1388 /** The new level. */
1389 int32_t iLevel;
1390 /** The IRQ tag and source. */
1391 uint32_t uTagSrc;
1392 } PciSetIrq;
1393
1394 /**
1395 * PDMDEVHLPTASKOP_IOAPIC_SEND_MSI
1396 */
1397 struct PDMDEVHLPTASKIOAPICSENDMSI
1398 {
1399 /** The bus:device:function of the device sending the MSI. */
1400 PCIBDF uBusDevFn;
1401 /** The MSI. */
1402 MSIMSG Msi;
1403 /** The IRQ tag and source. */
1404 uint32_t uTagSrc;
1405 } IoApicSendMsi;
1406
1407 /**
1408 * PDMDEVHLPTASKOP_IOAPIC_SET_EOI
1409 */
1410 struct PDMDEVHLPTASKIOAPICSETEOI
1411 {
1412 /** The vector corresponding to the EOI. */
1413 uint8_t uVector;
1414 } IoApicSetEoi;
1415
1416 /** Expanding the structure. */
1417 uint64_t au64[3];
1418 } u;
1419} PDMDEVHLPTASK;
1420/** Pointer to a queued Device Helper Task. */
1421typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1422/** Pointer to a const queued Device Helper Task. */
1423typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1424
1425
1426
1427/**
1428 * An USB hub registration record.
1429 */
1430typedef struct PDMUSBHUB
1431{
1432 /** The USB versions this hub support.
1433 * Note that 1.1 hubs can take on 2.0 devices. */
1434 uint32_t fVersions;
1435 /** The number of ports on the hub. */
1436 uint32_t cPorts;
1437 /** The number of available ports (0..cPorts). */
1438 uint32_t cAvailablePorts;
1439 /** The driver instance of the hub. */
1440 PPDMDRVINS pDrvIns;
1441 /** Copy of the to the registration structure. */
1442 PDMUSBHUBREG Reg;
1443
1444 /** Pointer to the next hub in the list. */
1445 struct PDMUSBHUB *pNext;
1446} PDMUSBHUB;
1447
1448/** Pointer to a const USB HUB registration record. */
1449typedef const PDMUSBHUB *PCPDMUSBHUB;
1450
1451/** Pointer to a PDM Async I/O template. */
1452typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1453
1454/** Pointer to the main PDM Async completion endpoint class. */
1455typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1456
1457/** Pointer to the global block cache structure. */
1458typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1459
1460/**
1461 * PDM VMCPU Instance data.
1462 * Changes to this must checked against the padding of the pdm union in VMCPU!
1463 */
1464typedef struct PDMCPU
1465{
1466 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1467 * in use. */
1468 uint32_t cQueuedCritSectLeaves;
1469 uint32_t uPadding0; /**< Alignment padding.*/
1470 /** Critical sections queued in RC/R0 because of contention preventing leave to
1471 * complete. (R3 Ptrs)
1472 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1473 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1474
1475 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1476 * currently in use. */
1477 uint32_t cQueuedCritSectRwExclLeaves;
1478 uint32_t uPadding1; /**< Alignment padding.*/
1479 /** Read/write critical sections queued in RC/R0 because of contention
1480 * preventing exclusive leave to complete. (R3 Ptrs)
1481 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1482 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1483
1484 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1485 * currently in use. */
1486 uint32_t cQueuedCritSectRwShrdLeaves;
1487 uint32_t uPadding2; /**< Alignment padding.*/
1488 /** Read/write critical sections queued in RC/R0 because of contention
1489 * preventing shared leave to complete. (R3 Ptrs)
1490 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1491 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1492} PDMCPU;
1493
1494
1495/** Max number of ring-0 device instances. */
1496#define PDM_MAX_RING0_DEVICE_INSTANCES 190
1497
1498
1499/**
1500 * PDM VM Instance data.
1501 * Changes to this must checked against the padding of the cfgm union in VM!
1502 */
1503typedef struct PDM
1504{
1505 /** The PDM lock.
1506 * This is used to protect everything that deals with interrupts, i.e.
1507 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1508 PDMCRITSECT CritSect;
1509 /** The NOP critical section.
1510 * This is a dummy critical section that will not do any thread
1511 * serialization but instead let all threads enter immediately and
1512 * concurrently. */
1513 PDMCRITSECT NopCritSect;
1514 /** Critical read/write section protecting the core list: devices,
1515 * usb devices, drivers.
1516 * @note The PDMUSERPERVM::ListCritSect lock covers queues and the stuff in
1517 * PDMUSERPERVM. */
1518 RTCRITSECTRW CoreListCritSectRw;
1519
1520 /** The ring-0 capable task sets (max 128). */
1521 PDMTASKSET aTaskSets[2];
1522 /** Pointer to task sets (max 512). */
1523 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1524
1525 /** PCI Buses. */
1526 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1527 /** IOMMU devices. */
1528 PDMIOMMUR3 aIommus[PDM_IOMMUS_MAX];
1529 /** The register PIC device. */
1530 PDMPIC Pic;
1531 /** The registered IC device. */
1532 PDMICR3 Ic;
1533 /** The registered I/O APIC device. */
1534 PDMIOAPIC IoApic;
1535 /** The registered HPET device. */
1536 PPDMDEVINSR3 pHpet;
1537
1538 /** List of registered devices. (FIFO) */
1539 R3PTRTYPE(PPDMDEV) pDevs;
1540 /** List of devices instances. (FIFO) */
1541 PPDMDEVINSR3 pDevInstances;
1542 /** This runs parallel to PDMR0PERVM::apDevInstances and is used with
1543 * physical access handlers to get the ring-3 device instance for passing down
1544 * as uUser. */
1545 PPDMDEVINSR3 apDevRing0Instances[PDM_MAX_RING0_DEVICE_INSTANCES];
1546
1547 /** List of registered USB devices. (FIFO) */
1548 R3PTRTYPE(PPDMUSB) pUsbDevs;
1549 /** List of USB devices instances. (FIFO) */
1550 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1551 /** List of registered drivers. (FIFO) */
1552 R3PTRTYPE(PPDMDRV) pDrvs;
1553 /** The registered firmware device (can be NULL). */
1554 R3PTRTYPE(PPDMFW) pFirmware;
1555 /** The registered DMAC device. */
1556 R3PTRTYPE(PPDMDMAC) pDmac;
1557 /** The registered RTC device. */
1558 R3PTRTYPE(PPDMRTC) pRtc;
1559 /** The registered USB HUBs. (FIFO)
1560 * @note Protected by CoreListCritSectRw. */
1561 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1562
1563 /** @name Queues
1564 * @note Protected by PDMUSERPERVM::ListCritSect.
1565 * @{ */
1566 /** Number of ring-0 capable queues in apQueues. */
1567 uint32_t cRing0Queues;
1568 uint32_t u32Padding1;
1569 /** Array of ring-0 capable queues running in parallel to PDMR0PERVM::aQueues. */
1570 R3PTRTYPE(PPDMQUEUE) apRing0Queues[16];
1571
1572 /** Number of ring-3 only queues.
1573 * PDMUSERPERVM::ListCritSect protects this and the next two members. */
1574 uint32_t cRing3Queues;
1575 /** The allocation size of the ring-3 queue handle table. */
1576 uint32_t cRing3QueuesAlloc;
1577 /** Handle table for the ring-3 only queues. */
1578 R3PTRTYPE(PPDMQUEUE *) papRing3Queues;
1579
1580 /** Queue in which devhlp tasks are queued for R3 execution. */
1581 PDMQUEUEHANDLE hDevHlpQueue;
1582 /** Bitmask controlling the queue flushing.
1583 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1584 uint32_t volatile fQueueFlushing;
1585 /** @} */
1586
1587 /** The current IRQ tag (tracing purposes). */
1588 uint32_t volatile uIrqTag;
1589
1590 /** Pending reset flags (PDMVMRESET_F_XXX). */
1591 uint32_t volatile fResetFlags;
1592
1593 /** Set by pdmR3LoadExec for use in assertions. */
1594 bool fStateLoaded;
1595 /** Alignment padding. */
1596 bool afPadding1[3];
1597
1598 /** The tracing ID of the next device instance.
1599 *
1600 * @remarks We keep the device tracing ID seperate from the rest as these are
1601 * then more likely to end up with the same ID from one run to
1602 * another, making analysis somewhat easier. Drivers and USB devices
1603 * are more volatile and can be changed at runtime, thus these are much
1604 * less likely to remain stable, so just heap them all together. */
1605 uint32_t idTracingDev;
1606 /** The tracing ID of the next driver instance, USB device instance or other
1607 * PDM entity requiring an ID. */
1608 uint32_t idTracingOther;
1609
1610 /** @name VMM device heap
1611 * @{ */
1612 /** The heap size. */
1613 uint32_t cbVMMDevHeap;
1614 /** Free space. */
1615 uint32_t cbVMMDevHeapLeft;
1616 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1617 RTR3PTR pvVMMDevHeap;
1618 /** Ring-3 mapping/unmapping notification callback for the user. */
1619 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1620 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1621 RTGCPHYS GCPhysVMMDevHeap;
1622 /** @} */
1623
1624 /** @name Network Shaper
1625 * @{ */
1626 /** Thread that processes choked filter drivers after
1627 * the a PDM_NETSHAPER_MAX_LATENCY period has elapsed. */
1628 PPDMTHREAD pNsUnchokeThread;
1629 /** Semaphore that the TX thread waits on. */
1630 RTSEMEVENT hNsUnchokeEvt;
1631 /** Timer handle for waking up pNsUnchokeThread. */
1632 TMTIMERHANDLE hNsUnchokeTimer;
1633 /** Indicates whether the unchoke timer has been armed already or not. */
1634 bool volatile fNsUnchokeTimerArmed;
1635 /** Align aNsGroups on a cacheline. */
1636 bool afPadding2[19+16+25];
1637 /** Number of network shaper groups.
1638 * @note Marked volatile to prevent re-reading after validation. */
1639 uint32_t volatile cNsGroups;
1640 /** The network shaper groups. */
1641 PDMNSBWGROUP aNsGroups[PDM_NET_SHAPER_MAX_GROUPS];
1642 /** Critical section protecting attaching, detaching and unchoking.
1643 * This helps making sure pNsTxThread can do unchoking w/o needing to lock the
1644 * individual groups and cause unnecessary contention. */
1645 RTCRITSECT NsLock;
1646 /** @} */
1647
1648 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1649 STAMCOUNTER StatQueuedCritSectLeaves;
1650 /** Number of times we've successfully aborted a wait in ring-0. */
1651 STAMCOUNTER StatAbortedCritSectEnters;
1652 /** Number of times we've got the critical section ownership while trying to
1653 * abort a wait due to VERR_INTERRUPTED. */
1654 STAMCOUNTER StatCritSectEntersWhileAborting;
1655 STAMCOUNTER StatCritSectVerrTimeout;
1656 STAMCOUNTER StatCritSectVerrInterrupted;
1657 STAMCOUNTER StatCritSectNonInterruptibleWaits;
1658
1659 STAMCOUNTER StatCritSectRwExclVerrTimeout;
1660 STAMCOUNTER StatCritSectRwExclVerrInterrupted;
1661 STAMCOUNTER StatCritSectRwExclNonInterruptibleWaits;
1662
1663 STAMCOUNTER StatCritSectRwEnterSharedWhileAborting;
1664 STAMCOUNTER StatCritSectRwSharedVerrTimeout;
1665 STAMCOUNTER StatCritSectRwSharedVerrInterrupted;
1666 STAMCOUNTER StatCritSectRwSharedNonInterruptibleWaits;
1667} PDM;
1668AssertCompileMemberAlignment(PDM, CritSect, 8);
1669AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1670AssertCompileMemberAlignment(PDM, aNsGroups, 8);
1671AssertCompileMemberAlignment(PDM, aNsGroups, 16);
1672AssertCompileMemberAlignment(PDM, aNsGroups, 32);
1673AssertCompileMemberAlignment(PDM, aNsGroups, 64);
1674AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1675AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1676/** Pointer to PDM VM instance data. */
1677typedef PDM *PPDM;
1678
1679
1680/**
1681 * PDM data kept in the ring-0 GVM.
1682 */
1683typedef struct PDMR0PERVM
1684{
1685 /** PCI Buses, ring-0 data. */
1686 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1687 /** IOMMUs, ring-0 data. */
1688 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1689 /** Number of valid ring-0 device instances (apDevInstances). */
1690 uint32_t cDevInstances;
1691 uint32_t u32Padding1;
1692 /** Pointer to ring-0 device instances. */
1693 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[PDM_MAX_RING0_DEVICE_INSTANCES];
1694 /** Number of valid ring-0 queue instances (aQueues). */
1695 uint32_t cQueues;
1696 uint32_t u32Padding2;
1697 /** Array of ring-0 queues. */
1698 PDMQUEUER0 aQueues[16];
1699 /** The interrupt-controller, ring-0 data. */
1700 PDMICR0 Ic;
1701} PDMR0PERVM;
1702
1703
1704/**
1705 * PDM data kept in the UVM.
1706 */
1707typedef struct PDMUSERPERVM
1708{
1709 /** @todo move more stuff over here. */
1710
1711 /** Lock protecting the lists below it and the queue list (in PDM). */
1712 RTCRITSECT ListCritSect;
1713 /** Pointer to list of loaded modules. */
1714 PPDMMOD pModules;
1715 /** List of initialized critical sections. (LIFO) */
1716 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1717 /** List of initialized read/write critical sections. (LIFO) */
1718 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1719 /** Head of the PDM Thread list. (singly linked) */
1720 R3PTRTYPE(PPDMTHREAD) pThreads;
1721 /** Tail of the PDM Thread list. (singly linked) */
1722 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1723
1724 /** @name PDM Async Completion
1725 * @{ */
1726 /** Pointer to the array of supported endpoint classes. */
1727 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1728 /** Head of the templates. Singly linked, protected by ListCritSect. */
1729 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1730 /** @} */
1731
1732 /** Global block cache data. */
1733 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1734} PDMUSERPERVM;
1735/** Pointer to the PDM data kept in the UVM. */
1736typedef PDMUSERPERVM *PPDMUSERPERVM;
1737
1738
1739
1740/*******************************************************************************
1741* Global Variables *
1742*******************************************************************************/
1743#ifdef IN_RING3
1744extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1745extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1746# ifdef VBOX_WITH_DBGF_TRACING
1747extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1748# endif
1749extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1750extern const PDMPICHLP g_pdmR3DevPicHlp;
1751extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1752extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1753extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1754extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1755extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1756extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1757extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1758extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1759#endif
1760
1761
1762/*******************************************************************************
1763* Defined Constants And Macros *
1764*******************************************************************************/
1765/** @def PDMDEV_ASSERT_DEVINS
1766 * Asserts the validity of the device instance.
1767 */
1768#ifdef VBOX_STRICT
1769# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1770 do { \
1771 AssertPtr(pDevIns); \
1772 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1773 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1774 } while (0)
1775#else
1776# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1777#endif
1778
1779/** @def PDMDRV_ASSERT_DRVINS
1780 * Asserts the validity of the driver instance.
1781 */
1782#ifdef VBOX_STRICT
1783# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1784 do { \
1785 AssertPtr(pDrvIns); \
1786 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1787 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1788 } while (0)
1789#else
1790# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1791#endif
1792
1793#ifndef VBOX_VMM_TARGET_ARMV8
1794/** @def PDM_TO_APICBACKEND
1795 * Gets the APIC backend given the VM cross-context structure.
1796 */
1797/** @def PDMCPU_TO_APICBACKEND
1798 * Gets the APIC backend given VMCPU cross-context structure.
1799 */
1800# ifdef IN_RING3
1801# define PDM_TO_APICBACKEND(a_pVM) (&((a_pVM)->pdm.s.Ic.ApicBackend))
1802# define PDMCPU_TO_APICBACKEND(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->pdm.s.Ic.ApicBackend))
1803#else
1804# define PDM_TO_APICBACKEND(a_pVM) (&((a_pVM)->pdmr0.s.Ic.ApicBackend))
1805# define PDMCPU_TO_APICBACKEND(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->pdmr0.s.Ic.ApicBackend))
1806#endif
1807#else
1808/** @todo GIC backend. */
1809#endif
1810
1811/*******************************************************************************
1812* Internal Functions *
1813*******************************************************************************/
1814#ifdef IN_RING3
1815bool pdmR3IsValidName(const char *pszName);
1816
1817int pdmR3CritSectBothInitStatsAndInfo(PVM pVM);
1818int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1819int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1820int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1821 const char *pszNameFmt, va_list va);
1822int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1823 const char *pszNameFmt, ...);
1824int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1825 const char *pszNameFmt, ...);
1826int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1827 const char *pszNameFmt, va_list va);
1828int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1829 const char *pszNameFmt, ...);
1830int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1831 const char *pszNameFmt, ...);
1832
1833int pdmR3DevInit(PVM pVM);
1834int pdmR3DevInitComplete(PVM pVM);
1835PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1836int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1837DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1838
1839int pdmR3UsbLoadModules(PVM pVM);
1840int pdmR3UsbInstantiateDevices(PVM pVM);
1841PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1842int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1843int pdmR3UsbVMInitComplete(PVM pVM);
1844
1845int pdmR3DrvInit(PVM pVM);
1846int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1847 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1848int pdmR3DrvDetach(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fFlags);
1849void pdmR3DrvDestroyChain(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fFlags);
1850PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1851
1852int pdmR3LdrInitU(PUVM pUVM);
1853void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1854char *pdmR3FileR3(const char *pszFile, bool fShared);
1855int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1856#endif /* IN_RING3 */
1857
1858void pdmQueueInit(PPDMQUEUE pQueue, uint32_t cbBitmap, uint32_t cbItem, uint32_t cItems,
1859 const char *pszName, PDMQUEUETYPE enmType, RTR3PTR pfnCallback, RTR3PTR pvOwner);
1860
1861#ifdef IN_RING3
1862int pdmR3TaskInit(PVM pVM);
1863void pdmR3TaskTerm(PVM pVM);
1864
1865int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1866 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1867int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1868 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1869int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1870 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1871int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1872int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1873int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1874void pdmR3ThreadDestroyAll(PVM pVM);
1875int pdmR3ThreadResumeAll(PVM pVM);
1876int pdmR3ThreadSuspendAll(PVM pVM);
1877
1878# ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1879int pdmR3AsyncCompletionInit(PVM pVM);
1880int pdmR3AsyncCompletionTerm(PVM pVM);
1881void pdmR3AsyncCompletionResume(PVM pVM);
1882int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1883int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1884 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1885int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1886int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1887int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1888int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1889# endif
1890
1891# ifdef VBOX_WITH_NETSHAPER
1892int pdmR3NetShaperInit(PVM pVM);
1893void pdmR3NetShaperTerm(PVM pVM);
1894# endif
1895
1896int pdmR3BlkCacheInit(PVM pVM);
1897void pdmR3BlkCacheTerm(PVM pVM);
1898int pdmR3BlkCacheResume(PVM pVM);
1899
1900DECLHIDDEN(void) pdmR3QueueTerm(PVM pVM);
1901#endif /* IN_RING3 */
1902
1903void pdmLock(PVMCC pVM);
1904int pdmLockEx(PVMCC pVM, int rcBusy);
1905void pdmUnlock(PVMCC pVM);
1906bool pdmLockIsOwner(PVMCC pVM);
1907
1908#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1909bool pdmIommuIsPresent(PPDMDEVINS pDevIns);
1910int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut);
1911int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1912int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1913# ifdef IN_RING3
1914int pdmR3IommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock);
1915int pdmR3IommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock);
1916int pdmR3IommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks);
1917int pdmR3IommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks);
1918# endif
1919#endif
1920
1921#if defined(IN_RING3) || defined(IN_RING0)
1922void pdmCritSectRwLeaveSharedQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1923void pdmCritSectRwLeaveExclQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1924#endif
1925
1926#ifdef IN_RING0
1927DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1928DECLHIDDEN(void) pdmR0QueueDestroy(PGVM pGVM, uint32_t iQueue);
1929
1930#endif
1931
1932#ifdef VBOX_WITH_DBGF_TRACING
1933# ifdef IN_RING3
1934DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1935 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1936 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1937 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1938DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1939DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1940DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1941 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1942 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1943 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion);
1944DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1945DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1946DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1947DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1948DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1949DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1950DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1951DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1952DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1953DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1954# elif defined(IN_RING0)
1955DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1956 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1957 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1958 void *pvUser);
1959DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1960 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1961DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1962DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1963DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1964DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1965DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1966DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1967DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1968DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1969# else
1970# error "Invalid environment selected"
1971# endif
1972#endif
1973
1974
1975/** @} */
1976
1977RT_C_DECLS_END
1978
1979#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1980
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