IEMOpHlp.h@ 104626

Last change on this file since 104626 was 104272, checked in by vboxsync, 8 months ago
VMM: bugref:9898 VEX.W opcode decoding helper and its usage for vtestp[s\|d] instructions.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 26.0 KB

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1	/* $Id: IEMOpHlp.h 104272 2024-04-10 10:44:58Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager - Opcode Helpers.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMOpHlp_h
29	#define VMM_INCLUDED_SRC_include_IEMOpHlp_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	/** @name Common opcode decoders.
35	* @{
36	*/
37	void iemOpStubMsg2(PVMCPUCC pVCpu) RT_NOEXCEPT;
38
39	/**
40	* Complains about a stub.
41	*
42	* Providing two versions of this macro, one for daily use and one for use when
43	* working on IEM.
44	*/
45	#if 0
46	# define IEMOP_BITCH_ABOUT_STUB() \
47	do { \
48	RTAssertMsg1(NULL, __LINE__, __FILE__, __FUNCTION__); \
49	iemOpStubMsg2(pVCpu); \
50	RTAssertPanic(); \
51	} while (0)
52	#else
53	# define IEMOP_BITCH_ABOUT_STUB() Log(("Stub: %s (line %d)\n", __FUNCTION__, __LINE__));
54	#endif
55
56	/** Stubs an opcode. */
57	#define FNIEMOP_STUB(a_Name) \
58	FNIEMOP_DEF(a_Name) \
59	{ \
60	RT_NOREF_PV(pVCpu); \
61	IEMOP_BITCH_ABOUT_STUB(); \
62	return VERR_IEM_INSTR_NOT_IMPLEMENTED; \
63	} \
64	typedef int ignore_semicolon
65
66	/** Stubs an opcode. */
67	#define FNIEMOP_STUB_1(a_Name, a_Type0, a_Name0) \
68	FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
69	{ \
70	RT_NOREF_PV(pVCpu); \
71	RT_NOREF_PV(a_Name0); \
72	IEMOP_BITCH_ABOUT_STUB(); \
73	return VERR_IEM_INSTR_NOT_IMPLEMENTED; \
74	} \
75	typedef int ignore_semicolon
76
77	/** Stubs an opcode which currently should raise \#UD. */
78	#define FNIEMOP_UD_STUB(a_Name) \
79	FNIEMOP_DEF(a_Name) \
80	{ \
81	Log(("Unsupported instruction %Rfn\n", __FUNCTION__)); \
82	IEMOP_RAISE_INVALID_OPCODE_RET(); \
83	} \
84	typedef int ignore_semicolon
85
86	/** Stubs an opcode which currently should raise \#UD. */
87	#define FNIEMOP_UD_STUB_1(a_Name, a_Type0, a_Name0) \
88	FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
89	{ \
90	RT_NOREF_PV(pVCpu); \
91	RT_NOREF_PV(a_Name0); \
92	Log(("Unsupported instruction %Rfn\n", __FUNCTION__)); \
93	IEMOP_RAISE_INVALID_OPCODE_RET(); \
94	} \
95	typedef int ignore_semicolon
96
97	/** @} */
98
99
100	/** @name Opcode Debug Helpers.
101	* @{
102	*/
103	#ifdef VBOX_WITH_STATISTICS
104	# ifdef IN_RING3
105	# define IEMOP_INC_STATS(a_Stats) do { pVCpu->iem.s.StatsR3.a_Stats += 1; } while (0)
106	# else
107	# define IEMOP_INC_STATS(a_Stats) do { pVCpu->iem.s.StatsRZ.a_Stats += 1; } while (0)
108	# endif
109	#else
110	# define IEMOP_INC_STATS(a_Stats) do { } while (0)
111	#endif
112
113	#ifdef DEBUG
114	# define IEMOP_MNEMONIC(a_Stats, a_szMnemonic) \
115	do { \
116	IEMOP_INC_STATS(a_Stats); \
117	Log4(("decode - %04x:%RGv %s%s [#%u]\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, \
118	pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK ? "lock " : "", a_szMnemonic, pVCpu->iem.s.cInstructions)); \
119	} while (0)
120
121	# define IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) \
122	do { \
123	IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
124	(void)RT_CONCAT(IEMOPFORM_, a_Form); \
125	(void)RT_CONCAT(OP_,a_Upper); \
126	(void)(a_fDisHints); \
127	(void)(a_fIemHints); \
128	} while (0)
129
130	# define IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) \
131	do { \
132	IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
133	(void)RT_CONCAT(IEMOPFORM_, a_Form); \
134	(void)RT_CONCAT(OP_,a_Upper); \
135	(void)RT_CONCAT(OP_PARM_,a_Op1); \
136	(void)(a_fDisHints); \
137	(void)(a_fIemHints); \
138	} while (0)
139
140	# define IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \
141	do { \
142	IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
143	(void)RT_CONCAT(IEMOPFORM_, a_Form); \
144	(void)RT_CONCAT(OP_,a_Upper); \
145	(void)RT_CONCAT(OP_PARM_,a_Op1); \
146	(void)RT_CONCAT(OP_PARM_,a_Op2); \
147	(void)(a_fDisHints); \
148	(void)(a_fIemHints); \
149	} while (0)
150
151	# define IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \
152	do { \
153	IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
154	(void)RT_CONCAT(IEMOPFORM_, a_Form); \
155	(void)RT_CONCAT(OP_,a_Upper); \
156	(void)RT_CONCAT(OP_PARM_,a_Op1); \
157	(void)RT_CONCAT(OP_PARM_,a_Op2); \
158	(void)RT_CONCAT(OP_PARM_,a_Op3); \
159	(void)(a_fDisHints); \
160	(void)(a_fIemHints); \
161	} while (0)
162
163	# define IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \
164	do { \
165	IEMOP_MNEMONIC(a_Stats, a_szMnemonic); \
166	(void)RT_CONCAT(IEMOPFORM_, a_Form); \
167	(void)RT_CONCAT(OP_,a_Upper); \
168	(void)RT_CONCAT(OP_PARM_,a_Op1); \
169	(void)RT_CONCAT(OP_PARM_,a_Op2); \
170	(void)RT_CONCAT(OP_PARM_,a_Op3); \
171	(void)RT_CONCAT(OP_PARM_,a_Op4); \
172	(void)(a_fDisHints); \
173	(void)(a_fIemHints); \
174	} while (0)
175
176	#else
177	# define IEMOP_MNEMONIC(a_Stats, a_szMnemonic) IEMOP_INC_STATS(a_Stats)
178
179	# define IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) \
180	IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
181	# define IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) \
182	IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
183	# define IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \
184	IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
185	# define IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \
186	IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
187	# define IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \
188	IEMOP_MNEMONIC(a_Stats, a_szMnemonic)
189
190	#endif
191
192	#define IEMOP_MNEMONIC0(a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) \
193	IEMOP_MNEMONIC0EX(a_Lower, \
194	#a_Lower, \
195	a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints)
196	#define IEMOP_MNEMONIC1(a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) \
197	IEMOP_MNEMONIC1EX(RT_CONCAT3(a_Lower,_,a_Op1), \
198	#a_Lower " " #a_Op1, \
199	a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints)
200	#define IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \
201	IEMOP_MNEMONIC2EX(RT_CONCAT5(a_Lower,_,a_Op1,_,a_Op2), \
202	#a_Lower " " #a_Op1 "," #a_Op2, \
203	a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints)
204	#define IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \
205	IEMOP_MNEMONIC3EX(RT_CONCAT7(a_Lower,_,a_Op1,_,a_Op2,_,a_Op3), \
206	#a_Lower " " #a_Op1 "," #a_Op2 "," #a_Op3, \
207	a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints)
208	#define IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \
209	IEMOP_MNEMONIC4EX(RT_CONCAT9(a_Lower,_,a_Op1,_,a_Op2,_,a_Op3,_,a_Op4), \
210	#a_Lower " " #a_Op1 "," #a_Op2 "," #a_Op3 "," #a_Op4, \
211	a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints)
212
213	/** @} */
214
215
216	/** @name Opcode Helpers.
217	* @{
218	*/
219
220	#ifdef IN_RING3
221	# define IEMOP_HLP_MIN_CPU(a_uMinCpu, a_fOnlyIf) \
222	do { \
223	if (IEM_GET_TARGET_CPU(pVCpu) >= (a_uMinCpu) \|\| !(a_fOnlyIf)) { } \
224	else \
225	{ \
226	(void)DBGFSTOP(pVCpu->CTX_SUFF(pVM)); \
227	IEMOP_RAISE_INVALID_OPCODE_RET(); \
228	} \
229	} while (0)
230	#else
231	# define IEMOP_HLP_MIN_CPU(a_uMinCpu, a_fOnlyIf) \
232	do { \
233	if (IEM_GET_TARGET_CPU(pVCpu) >= (a_uMinCpu) \|\| !(a_fOnlyIf)) { } \
234	else IEMOP_RAISE_INVALID_OPCODE_RET(); \
235	} while (0)
236	#endif
237
238	/** The instruction requires a 186 or later. */
239	#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_186
240	# define IEMOP_HLP_MIN_186() do { } while (0)
241	#else
242	# define IEMOP_HLP_MIN_186() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_186, true)
243	#endif
244
245	/** The instruction requires a 286 or later. */
246	#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_286
247	# define IEMOP_HLP_MIN_286() do { } while (0)
248	#else
249	# define IEMOP_HLP_MIN_286() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_286, true)
250	#endif
251
252	/** The instruction requires a 386 or later. */
253	#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_386
254	# define IEMOP_HLP_MIN_386() do { } while (0)
255	#else
256	# define IEMOP_HLP_MIN_386() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_386, true)
257	#endif
258
259	/** The instruction requires a 386 or later if the given expression is true. */
260	#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_386
261	# define IEMOP_HLP_MIN_386_EX(a_fOnlyIf) do { } while (0)
262	#else
263	# define IEMOP_HLP_MIN_386_EX(a_fOnlyIf) IEMOP_HLP_MIN_CPU(IEMTARGETCPU_386, a_fOnlyIf)
264	#endif
265
266	/** The instruction requires a 486 or later. */
267	#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_486
268	# define IEMOP_HLP_MIN_486() do { } while (0)
269	#else
270	# define IEMOP_HLP_MIN_486() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_486, true)
271	#endif
272
273	/** The instruction requires a Pentium (586) or later. */
274	#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_PENTIUM
275	# define IEMOP_HLP_MIN_586() do { } while (0)
276	#else
277	# define IEMOP_HLP_MIN_586() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_PENTIUM, true)
278	#endif
279
280	/** The instruction requires a PentiumPro (686) or later. */
281	#if IEM_CFG_TARGET_CPU >= IEMTARGETCPU_PPRO
282	# define IEMOP_HLP_MIN_686() do { } while (0)
283	#else
284	# define IEMOP_HLP_MIN_686() IEMOP_HLP_MIN_CPU(IEMTARGETCPU_PPRO, true)
285	#endif
286
287
288	/** The instruction raises an \#UD in real and V8086 mode. */
289	#define IEMOP_HLP_NO_REAL_OR_V86_MODE() \
290	do \
291	{ \
292	if (!IEM_IS_REAL_OR_V86_MODE(pVCpu)) { /* likely */ } \
293	else IEMOP_RAISE_INVALID_OPCODE_RET(); \
294	} while (0)
295
296	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
297	/** This instruction raises an \#UD in real and V8086 mode or when not using a
298	* 64-bit code segment when in long mode (applicable to all VMX instructions
299	* except VMCALL).
300	*
301	* @todo r=bird: This is not recompiler friendly. The scenario with
302	* 16-bit/32-bit code running in long mode doesn't fit at all.
303	*/
304	# define IEMOP_HLP_VMX_INSTR(a_szInstr, a_InsDiagPrefix) \
305	do \
306	{ \
307	if ( !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
308	&& ( !IEM_IS_LONG_MODE(pVCpu) \
309	\|\| IEM_IS_64BIT_CODE(pVCpu))) \
310	{ /* likely */ } \
311	else \
312	{ \
313	if (IEM_IS_REAL_OR_V86_MODE(pVCpu)) \
314	{ \
315	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_RealOrV86Mode; \
316	Log5((a_szInstr ": Real or v8086 mode -> #UD\n")); \
317	IEMOP_RAISE_INVALID_OPCODE_RET(); \
318	} \
319	if (IEM_IS_LONG_MODE(pVCpu) && !IEM_IS_64BIT_CODE(pVCpu)) \
320	{ \
321	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_LongModeCS; \
322	Log5((a_szInstr ": Long mode without 64-bit code segment -> #UD\n")); \
323	IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET(); /** @todo This doesn't work. */ \
324	} \
325	} \
326	} while (0)
327
328	/** The instruction can only be executed in VMX operation (VMX root mode and
329	* non-root mode).
330	*
331	* @note Update IEM_VMX_IN_VMX_OPERATION if changes are made here.
332	*
333	* @todo r=bird: This is absolutely INCORRECT since IEM_VMX_IS_ROOT_MODE
334	* is a complicated runtime state (calls CPUMIsGuestInVmxRootMode), and
335	* not something we can decide while decoding. Convert to an IEM_MC!
336	*/
337	# define IEMOP_HLP_IN_VMX_OPERATION(a_szInstr, a_InsDiagPrefix) \
338	do \
339	{ \
340	if (IEM_VMX_IS_ROOT_MODE(pVCpu)) { /* likely */ } \
341	else \
342	{ \
343	pVCpu->cpum.GstCtx.hwvirt.vmx.enmDiag = a_InsDiagPrefix##_VmxRoot; \
344	Log5((a_szInstr ": Not in VMX operation (root mode) -> #UD\n")); \
345	IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET(); /** @todo This doesn't work. */ \
346	} \
347	} while (0)
348	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
349
350	/** The instruction is not available in 64-bit mode, throw \#UD if we're in
351	* 64-bit mode. */
352	#define IEMOP_HLP_NO_64BIT() \
353	do \
354	{ \
355	if (!IEM_IS_64BIT_CODE(pVCpu)) \
356	{ /* likely */ } \
357	else \
358	IEMOP_RAISE_INVALID_OPCODE_RET(); \
359	} while (0)
360
361	/** The instruction is only available in 64-bit mode, throw \#UD if we're not in
362	* 64-bit mode. */
363	#define IEMOP_HLP_ONLY_64BIT() \
364	do \
365	{ \
366	if (IEM_IS_64BIT_CODE(pVCpu)) \
367	{ /* likely */ } \
368	else \
369	IEMOP_RAISE_INVALID_OPCODE_RET(); \
370	} while (0)
371
372	/** The instruction defaults to 64-bit operand size if 64-bit mode. */
373	#define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() \
374	do \
375	{ \
376	if (IEM_IS_64BIT_CODE(pVCpu)) \
377	iemRecalEffOpSize64Default(pVCpu); \
378	} while (0)
379
380	/** The instruction defaults to 64-bit operand size if 64-bit mode and intel
381	* CPUs ignore the operand size prefix complete (e.g. relative jumps). */
382	#define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE_AND_INTEL_IGNORES_OP_SIZE_PREFIX() \
383	do \
384	{ \
385	if (IEM_IS_64BIT_CODE(pVCpu)) \
386	iemRecalEffOpSize64DefaultAndIntelIgnoresOpSizePrefix(pVCpu); \
387	} while (0)
388
389	/** The instruction has 64-bit operand size if 64-bit mode. */
390	#define IEMOP_HLP_64BIT_OP_SIZE() \
391	do \
392	{ \
393	if (IEM_IS_64BIT_CODE(pVCpu)) \
394	pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT; \
395	} while (0)
396
397	/** Only a REX prefix immediately preceeding the first opcode byte takes
398	* effect. This macro helps ensuring this as well as logging bad guest code. */
399	#define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) \
400	do \
401	{ \
402	if (RT_UNLIKELY(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX)) \
403	{ \
404	Log5((a_szPrf ": Overriding REX prefix at %RX16! fPrefixes=%#x\n", pVCpu->cpum.GstCtx.rip, pVCpu->iem.s.fPrefixes)); \
405	pVCpu->iem.s.fPrefixes &= ~IEM_OP_PRF_REX_MASK; \
406	pVCpu->iem.s.uRexB = 0; \
407	pVCpu->iem.s.uRexIndex = 0; \
408	pVCpu->iem.s.uRexReg = 0; \
409	iemRecalEffOpSize(pVCpu); \
410	} \
411	} while (0)
412
413	/**
414	* Done decoding.
415	*/
416	#define IEMOP_HLP_DONE_DECODING() \
417	do \
418	{ \
419	/nothing for now, maybe later... / \
420	} while (0)
421
422	#define IEMOP_HLP_DONE_DECODING_EX(a_fFeature) \
423	do \
424	{ \
425	if (RT_LIKELY(IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
426	{ /* likely */ } \
427	else \
428	IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
429	} while (0)
430
431	/**
432	* Done decoding, raise \#UD exception if lock prefix present.
433	*/
434	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() \
435	do \
436	{ \
437	if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))) \
438	{ /* likely */ } \
439	else \
440	IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
441	} while (0)
442
443	/**
444	* Done decoding, raise \#UD exception if lock prefix present, or if the
445	* a_fFeature is present in the guest CPU.
446	*/
447	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(a_fFeature) \
448	do \
449	{ \
450	if (RT_LIKELY( !(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK) \
451	&& IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
452	{ /* likely */ } \
453	else \
454	IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
455	} while (0)
456
457	/**
458	* Done decoding, raise \#UD exception if lock prefix present, or if the
459	* a_fFeature is present in the guest CPU.
460	*/
461	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX_2_OR(a_fFeature1, a_fFeature2) \
462	do \
463	{ \
464	if (RT_LIKELY( !(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK) \
465	&& ( IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature1 \
466	\|\| IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature2) )) \
467	{ /* likely */ } \
468	else \
469	IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
470	} while (0)
471
472
473	/**
474	* Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
475	* repnz or size prefixes are present, if in real or v8086 mode, or if the
476	* a_fFeature is not present in the guest CPU.
477	*/
478	#define IEMOP_HLP_DONE_VEX_DECODING_EX(a_fFeature) \
479	do \
480	{ \
481	if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
482	& (IEM_OP_PRF_LOCK \| IEM_OP_PRF_REPZ \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REX)) \
483	&& !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
484	&& IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
485	{ /* likely */ } \
486	else \
487	IEMOP_RAISE_INVALID_OPCODE_RET(); \
488	} while (0)
489
490	/**
491	* Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
492	* repnz or size prefixes are present, or if in real or v8086 mode, or if the
493	* a_fFeature is not present in the guest CPU.
494	*/
495	#define IEMOP_HLP_DONE_VEX_DECODING_L0_EX(a_fFeature) \
496	do \
497	{ \
498	if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
499	& (IEM_OP_PRF_LOCK \| IEM_OP_PRF_REPZ \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REX)) \
500	&& !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
501	&& pVCpu->iem.s.uVexLength == 0 \
502	&& IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
503	{ /* likely */ } \
504	else \
505	IEMOP_RAISE_INVALID_OPCODE_RET(); \
506	} while (0)
507
508	/**
509	* Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
510	* repnz or size prefixes are present, or if in real or v8086 mode, or if the
511	* a_fFeature is not present in the guest CPU.
512	*/
513	#define IEMOP_HLP_DONE_VEX_DECODING_L1_EX(a_fFeature) \
514	do \
515	{ \
516	if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
517	& (IEM_OP_PRF_LOCK \| IEM_OP_PRF_REPZ \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REX)) \
518	&& !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
519	&& pVCpu->iem.s.uVexLength == 1 \
520	&& IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
521	{ /* likely */ } \
522	else \
523	IEMOP_RAISE_INVALID_OPCODE_RET(); \
524	} while (0)
525
526	/**
527	* Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
528	* repnz or size prefixes are present, or if VEX.W is one, or if in real or
529	* v8086 mode, or if the a_fFeature is not present in the guest CPU.
530	*/
531	#define IEMOP_HLP_DONE_VEX_DECODING_W0_EX(a_fFeature) \
532	do \
533	{ \
534	if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
535	& (IEM_OP_PRF_LOCK \| IEM_OP_PRF_REPZ \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REX \
536	\| IEM_OP_PRF_SIZE_REX_W /VEX.W/)) \
537	&& !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
538	&& IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature)) \
539	{ /* likely */ } \
540	else \
541	IEMOP_RAISE_INVALID_OPCODE_RET(); \
542	} while (0)
543
544	/**
545	* Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
546	* repnz or size prefixes are present, or if the VEX.VVVV field doesn't indicate
547	* register 0, if in real or v8086 mode, or if the a_fFeature is not present in
548	* the guest CPU.
549	*/
550	#define IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV_EX(a_fFeature) \
551	do \
552	{ \
553	if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
554	& (IEM_OP_PRF_LOCK \| IEM_OP_PRF_REPZ \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REX)) \
555	&& !pVCpu->iem.s.uVex3rdReg \
556	&& !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
557	&& IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature )) \
558	{ /* likely */ } \
559	else \
560	IEMOP_RAISE_INVALID_OPCODE_RET(); \
561	} while (0)
562
563	/**
564	* Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz,
565	* repnz or size prefixes are present, or if VEX.W is one, or if the VEX.VVVV field doesn't indicate
566	* register 0, if in real or v8086 mode, or if the a_fFeature is not present in
567	* the guest CPU.
568	*/
569	#define IEMOP_HLP_DONE_VEX_DECODING_W0_AND_NO_VVVV_EX(a_fFeature) \
570	do \
571	{ \
572	if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
573	& (IEM_OP_PRF_LOCK \| IEM_OP_PRF_REPZ \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REX \
574	\| IEM_OP_PRF_SIZE_REX_W /VEX.W/)) \
575	&& !pVCpu->iem.s.uVex3rdReg \
576	&& !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
577	&& IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature )) \
578	{ /* likely */ } \
579	else \
580	IEMOP_RAISE_INVALID_OPCODE_RET(); \
581	} while (0)
582
583	/**
584	* Done decoding VEX, no V, L=0.
585	* Raises \#UD exception if rex, rep, opsize or lock prefixes are present, if
586	* we're in real or v8086 mode, if VEX.V!=0xf, if VEX.L!=0, or if the a_fFeature
587	* is not present in the guest CPU.
588	*/
589	#define IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(a_fFeature) \
590	do \
591	{ \
592	if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
593	& (IEM_OP_PRF_LOCK \| IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REPZ \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_REX)) \
594	&& pVCpu->iem.s.uVexLength == 0 \
595	&& pVCpu->iem.s.uVex3rdReg == 0 \
596	&& !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
597	&& IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature )) \
598	{ /* likely */ } \
599	else \
600	IEMOP_RAISE_INVALID_OPCODE_RET(); \
601	} while (0)
602
603	/**
604	* Done decoding VEX, no V, L=1.
605	* Raises \#UD exception if rex, rep, opsize or lock prefixes are present, if
606	* we're in real or v8086 mode, if VEX.V!=0xf, if VEX.L!=1, or if the a_fFeature
607	* is not present in the guest CPU.
608	*/
609	#define IEMOP_HLP_DONE_VEX_DECODING_L1_AND_NO_VVVV_EX(a_fFeature) \
610	do \
611	{ \
612	if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
613	& (IEM_OP_PRF_LOCK \| IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REPZ \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_REX)) \
614	&& pVCpu->iem.s.uVexLength == 1 \
615	&& pVCpu->iem.s.uVex3rdReg == 0 \
616	&& !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
617	&& IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature )) \
618	{ /* likely */ } \
619	else \
620	IEMOP_RAISE_INVALID_OPCODE_RET(); \
621	} while (0)
622
623	/**
624	* Done decoding VEX, L=0 and W=0.
625	* Raises \#UD exception if rex, rep, opsize or lock prefixes are present,
626	* if we're in real or v8086 mode, if VEX.L!=0, if VEX.W!=0, or if the
627	* a_fFeature is not present in the guest CPU.
628	*/
629	#define IEMOP_HLP_DONE_VEX_DECODING_L0_AND_W0_EX(a_fFeature) \
630	do \
631	{ \
632	if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \
633	& (IEM_OP_PRF_LOCK \| IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REPZ \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_REX \
634	\| IEM_OP_PRF_SIZE_REX_W /VEX.W/)) \
635	&& pVCpu->iem.s.uVexLength == 0 \
636	&& !IEM_IS_REAL_OR_V86_MODE(pVCpu) \
637	&& IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature )) \
638	{ /* likely */ } \
639	else \
640	IEMOP_RAISE_INVALID_OPCODE_RET(); \
641	} while (0)
642
643
644	#define IEMOP_HLP_DECODED_NL_1(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_fDisOpType) \
645	do \
646	{ \
647	if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))) \
648	{ /* likely */ } \
649	else \
650	{ \
651	NOREF(a_uDisOpNo); NOREF(a_fIemOpFlags); NOREF(a_uDisParam0); NOREF(a_fDisOpType); \
652	IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
653	} \
654	} while (0)
655	#define IEMOP_HLP_DECODED_NL_2(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_uDisParam1, a_fDisOpType) \
656	do \
657	{ \
658	if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK))) \
659	{ /* likely */ } \
660	else \
661	{ \
662	NOREF(a_uDisOpNo); NOREF(a_fIemOpFlags); NOREF(a_uDisParam0); NOREF(a_uDisParam1); NOREF(a_fDisOpType); \
663	IEMOP_RAISE_INVALID_LOCK_PREFIX_RET(); \
664	} \
665	} while (0)
666
667	/**
668	* Done decoding, raise \#UD exception if any lock, repz or repnz prefixes
669	* are present.
670	*/
671	#define IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES() \
672	do \
673	{ \
674	if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_LOCK \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_REPZ)))) \
675	{ /* likely */ } \
676	else \
677	IEMOP_RAISE_INVALID_OPCODE_RET(); \
678	} while (0)
679
680	/**
681	* Done decoding, raise \#UD exception if any operand-size override, repz or repnz
682	* prefixes are present.
683	*/
684	#define IEMOP_HLP_DONE_DECODING_NO_SIZE_OP_REPZ_OR_REPNZ_PREFIXES() \
685	do \
686	{ \
687	if (RT_LIKELY(!(pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_OP \| IEM_OP_PRF_REPNZ \| IEM_OP_PRF_REPZ)))) \
688	{ /* likely */ } \
689	else \
690	IEMOP_RAISE_INVALID_OPCODE_RET(); \
691	} while (0)
692
693	/**
694	* Check for a CPUMFEATURES member to be true, raise \#UD if clear.
695	*/
696	#define IEMOP_HLP_RAISE_UD_IF_MISSING_GUEST_FEATURE(pVCpu, a_fFeature) \
697	do \
698	{ \
699	if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->a_fFeature) \
700	{ /* likely */ } \
701	else \
702	IEMOP_RAISE_INVALID_OPCODE_RET(); \
703	} while (0)
704
705	VBOXSTRICTRC iemOpHlpCalcRmEffAddr(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, PRTGCPTR pGCPtrEff) RT_NOEXCEPT;
706	VBOXSTRICTRC iemOpHlpCalcRmEffAddrEx(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, PRTGCPTR pGCPtrEff, uint64_t *puInfo) RT_NOEXCEPT;
707	#ifdef IEM_WITH_SETJMP
708	RTGCPTR iemOpHlpCalcRmEffAddrJmp(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset) IEM_NOEXCEPT_MAY_LONGJMP;
709	RTGCPTR iemOpHlpCalcRmEffAddrJmpEx(PVMCPUCC pVCpu, uint8_t bRm, uint32_t cbImmAndRspOffset, uint64_t *puInfo) IEM_NOEXCEPT_MAY_LONGJMP;
710	#endif
711
712	/** @} */
713
714	#endif /* !VMM_INCLUDED_SRC_include_IEMOpHlp_h */

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source: vbox/trunk/src/VBox/VMM/include/IEMOpHlp.h@ 104626

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