IEMN8veRecompilerTlbLookup.h@ 104821

Last change on this file since 104821 was 104148, checked in by vboxsync, 7 months ago
VMM/IEM: Enabled the LDP & STP optimization for the TLB code on ARM64. bugref:10374
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File size: 44.9 KB

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1	/* $Id: IEMN8veRecompilerTlbLookup.h 104148 2024-04-04 01:24:06Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager - Native Recompiler TLB Lookup Code Emitter.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMN8veRecompilerTlbLookup_h
29	#define VMM_INCLUDED_SRC_include_IEMN8veRecompilerTlbLookup_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include "IEMN8veRecompiler.h"
35	#include "IEMN8veRecompilerEmit.h"
36
37
38	/** @defgroup grp_iem_n8ve_re_tlblookup Native Recompiler TLB Lookup Code Emitter
39	* @ingroup grp_iem_n8ve_re
40	* @{
41	*/
42
43	/*
44	* TLB Lookup config.
45	*/
46	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_ARM64)
47	# define IEMNATIVE_WITH_TLB_LOOKUP
48	#endif
49	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
50	# define IEMNATIVE_WITH_TLB_LOOKUP_FETCH
51	#endif
52	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
53	# define IEMNATIVE_WITH_TLB_LOOKUP_STORE
54	#endif
55	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
56	# define IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
57	#endif
58	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
59	# define IEMNATIVE_WITH_TLB_LOOKUP_PUSH
60	#endif
61	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
62	# define IEMNATIVE_WITH_TLB_LOOKUP_POP
63	#endif
64
65
66	/**
67	* This must be instantiate before branching off to the lookup code,
68	* so that register spilling and whatnot happens for everyone.
69	*/
70	typedef struct IEMNATIVEEMITTLBSTATE
71	{
72	bool const fSkip;
73	uint8_t const idxRegPtrHlp; /*< We don't support immediate variables with register assignment, so this a tmp reg alloc. /
74	uint8_t const idxRegPtr;
75	uint8_t const idxRegSegBase;
76	uint8_t const idxRegSegLimit;
77	uint8_t const idxRegSegAttrib;
78	uint8_t const idxReg1;
79	uint8_t const idxReg2;
80	#if defined(RT_ARCH_ARM64)
81	uint8_t const idxReg3;
82	/** @def IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
83	* Use LDP and STDP to reduce number of instructions accessing memory at the
84	* cost of using more registers. This will typically reduce the number of
85	* instructions emitted as well.
86	* @todo Profile this and ensure that it performs the same or better.
87	*/
88	# define IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
89	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
90	uint8_t const idxReg4;
91	uint8_t const idxReg5;
92	# endif
93	#endif
94	uint64_t const uAbsPtr;
95
96	IEMNATIVEEMITTLBSTATE(PIEMRECOMPILERSTATE a_pReNative, uint32_t *a_poff, uint8_t a_idxVarGCPtrMem,
97	uint8_t a_iSegReg, uint8_t a_cbMem, uint8_t a_offDisp = 0)
98	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
99	/* 32-bit and 64-bit wraparound will require special handling, so skip these for absolute addresses. */
100	: fSkip( a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].enmKind
101	== kIemNativeVarKind_Immediate
102	&& ( (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) != IEMMODE_64BIT
103	? (uint64_t)(UINT32_MAX - a_cbMem - a_offDisp)
104	: (uint64_t)(UINT64_MAX - a_cbMem - a_offDisp))
105	< a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].u.uValue)
106	#else
107	: fSkip(true)
108	#endif
109	#if defined(RT_ARCH_AMD64) /* got good immediate encoding, otherwise we just load the address in a reg immediately. */
110	, idxRegPtrHlp(UINT8_MAX)
111	#else
112	, idxRegPtrHlp( a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].enmKind
113	!= kIemNativeVarKind_Immediate
114	\|\| fSkip
115	? UINT8_MAX
116	: iemNativeRegAllocTmpImm(a_pReNative, a_poff,
117	a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].u.uValue))
118	#endif
119	, idxRegPtr( a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].enmKind
120	!= kIemNativeVarKind_Immediate
121	&& !fSkip
122	? iemNativeVarRegisterAcquire(a_pReNative, a_idxVarGCPtrMem, a_poff,
123	true /fInitialized/, IEMNATIVE_CALL_ARG2_GREG)
124	: idxRegPtrHlp)
125	, idxRegSegBase(a_iSegReg == UINT8_MAX \|\| fSkip
126	? UINT8_MAX
127	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_BASE(a_iSegReg)))
128	, idxRegSegLimit((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
129	? UINT8_MAX
130	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg)))
131	, idxRegSegAttrib((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
132	? UINT8_MAX
133	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg)))
134	, idxReg1(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
135	, idxReg2(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
136	#if defined(RT_ARCH_ARM64)
137	, idxReg3(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
138	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
139	, idxReg4(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
140	, idxReg5(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
141	# endif
142	#endif
143	, uAbsPtr( a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].enmKind
144	!= kIemNativeVarKind_Immediate
145	\|\| fSkip
146	? UINT64_MAX
147	: a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].u.uValue)
148
149	{
150	RT_NOREF(a_cbMem, a_offDisp);
151	}
152
153	/* Alternative constructor for PUSH and POP where we don't have a GCPtrMem
154	variable, only a register derived from the guest RSP. */
155	IEMNATIVEEMITTLBSTATE(PIEMRECOMPILERSTATE a_pReNative, uint8_t a_idxRegPtr, uint32_t *a_poff,
156	uint8_t a_iSegReg, uint8_t a_cbMem)
157	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
158	: fSkip(false)
159	#else
160	: fSkip(true)
161	#endif
162	, idxRegPtrHlp(UINT8_MAX)
163	, idxRegPtr(a_idxRegPtr)
164	, idxRegSegBase(a_iSegReg == UINT8_MAX \|\| fSkip
165	? UINT8_MAX
166	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_BASE(a_iSegReg)))
167	, idxRegSegLimit((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
168	? UINT8_MAX
169	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg)))
170	, idxRegSegAttrib((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
171	? UINT8_MAX
172	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg)))
173	, idxReg1(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
174	, idxReg2(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
175	#if defined(RT_ARCH_ARM64)
176	, idxReg3(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
177	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
178	, idxReg4(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
179	, idxReg5(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
180	# endif
181	#endif
182	, uAbsPtr(UINT64_MAX)
183
184	{
185	RT_NOREF_PV(a_cbMem);
186	}
187
188	/* Alternative constructor for the code TLB lookups where we implictly use RIP
189	variable, only a register derived from the guest RSP. */
190	IEMNATIVEEMITTLBSTATE(PIEMRECOMPILERSTATE a_pReNative, bool a_fFlat, uint32_t *a_poff)
191	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
192	: fSkip(false)
193	#else
194	: fSkip(true)
195	#endif
196	, idxRegPtrHlp(UINT8_MAX)
197	, idxRegPtr(iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, kIemNativeGstReg_Pc))
198	, idxRegSegBase(a_fFlat \|\| fSkip
199	? UINT8_MAX
200	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_BASE(X86_SREG_CS)))
201	, idxRegSegLimit(/*a_fFlat \|\| fSkip
202	? UINT8_MAX
203	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_LIMIT(X86_SREG_CS))*/
204	UINT8_MAX)
205	, idxRegSegAttrib(UINT8_MAX)
206	, idxReg1(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
207	, idxReg2(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
208	#if defined(RT_ARCH_ARM64)
209	, idxReg3(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
210	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
211	, idxReg4(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
212	, idxReg5(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
213	# endif
214	#endif
215	, uAbsPtr(UINT64_MAX)
216
217	{
218	}
219
220	void freeRegsAndReleaseVars(PIEMRECOMPILERSTATE a_pReNative, uint8_t idxVarGCPtrMem = UINT8_MAX, bool fIsCode = false) const
221	{
222	if (!fIsCode)
223	{
224	if (idxRegPtr != UINT8_MAX)
225	{
226	if (idxRegPtrHlp == UINT8_MAX)
227	{
228	if (idxVarGCPtrMem != UINT8_MAX)
229	iemNativeVarRegisterRelease(a_pReNative, idxVarGCPtrMem);
230	}
231	else
232	{
233	Assert(idxRegPtrHlp == idxRegPtr);
234	iemNativeRegFreeTmpImm(a_pReNative, idxRegPtrHlp);
235	}
236	}
237	else
238	Assert(idxRegPtrHlp == UINT8_MAX);
239	}
240	else
241	{
242	Assert(idxVarGCPtrMem == UINT8_MAX);
243	Assert(idxRegPtrHlp == UINT8_MAX);
244	iemNativeRegFreeTmp(a_pReNative, idxRegPtr); /* RIP */
245	}
246	if (idxRegSegBase != UINT8_MAX)
247	iemNativeRegFreeTmp(a_pReNative, idxRegSegBase);
248	if (idxRegSegLimit != UINT8_MAX)
249	iemNativeRegFreeTmp(a_pReNative, idxRegSegLimit);
250	if (idxRegSegAttrib != UINT8_MAX)
251	iemNativeRegFreeTmp(a_pReNative, idxRegSegAttrib);
252	#if defined(RT_ARCH_ARM64)
253	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
254	iemNativeRegFreeTmp(a_pReNative, idxReg5);
255	iemNativeRegFreeTmp(a_pReNative, idxReg4);
256	# endif
257	iemNativeRegFreeTmp(a_pReNative, idxReg3);
258	#endif
259	iemNativeRegFreeTmp(a_pReNative, idxReg2);
260	iemNativeRegFreeTmp(a_pReNative, idxReg1);
261
262	}
263
264	uint32_t getRegsNotToSave() const
265	{
266	if (!fSkip)
267	return RT_BIT_32(idxReg1)
268	\| RT_BIT_32(idxReg2)
269	#if defined(RT_ARCH_ARM64)
270	\| RT_BIT_32(idxReg3)
271	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
272	\| RT_BIT_32(idxReg4)
273	\| RT_BIT_32(idxReg5)
274	# endif
275	#endif
276	;
277	return 0;
278	}
279
280	/** This is only for avoid assertions. */
281	uint32_t getActiveRegsWithShadows(bool fCode = false) const
282	{
283	#ifdef VBOX_STRICT
284	if (!fSkip)
285	return (idxRegSegBase != UINT8_MAX ? RT_BIT_32(idxRegSegBase) : 0)
286	\| (idxRegSegLimit != UINT8_MAX ? RT_BIT_32(idxRegSegLimit) : 0)
287	\| (idxRegSegAttrib != UINT8_MAX ? RT_BIT_32(idxRegSegAttrib) : 0)
288	\| (fCode ? RT_BIT_32(idxRegPtr) : 0);
289	#else
290	RT_NOREF_PV(fCode);
291	#endif
292	return 0;
293	}
294	} IEMNATIVEEMITTLBSTATE;
295
296	DECLASM(void) iemNativeHlpAsmSafeWrapCheckTlbLookup(void);
297
298
299	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
300	template<bool const a_fDataTlb, bool const a_fNoReturn = false>
301	DECL_INLINE_THROW(uint32_t)
302	iemNativeEmitTlbLookup(PIEMRECOMPILERSTATE pReNative, uint32_t off, IEMNATIVEEMITTLBSTATE const * const pTlbState,
303	uint8_t iSegReg, uint8_t cbMem, uint8_t fAlignMask, uint32_t fAccess,
304	uint32_t idxLabelTlbLookup, uint32_t idxLabelTlbMiss, uint8_t idxRegMemResult,
305	uint8_t offDisp = 0)
306	{
307	Assert(!pTlbState->fSkip);
308	uint32_t const offVCpuTlb = a_fDataTlb ? RT_UOFFSETOF(VMCPUCC, iem.s.DataTlb) : RT_UOFFSETOF(VMCPUCC, iem.s.CodeTlb);
309	# if defined(RT_ARCH_AMD64)
310	uint8_t * const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 512);
311	# elif defined(RT_ARCH_ARM64)
312	uint32_t * const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 64);
313	# endif
314
315	/*
316	* The expand down check isn't use all that much, so we emit here to keep
317	* the lookup straighter.
318	*/
319	/* check_expand_down: ; complicted! */
320	uint32_t const offCheckExpandDown = off;
321	uint32_t offFixupLimitDone = 0;
322	if (a_fDataTlb && iSegReg != UINT8_MAX && (pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) != IEMMODE_64BIT)
323	{
324	off = iemNativeEmitBrkEx(pCodeBuf, off, 1); /** @todo this needs testing */
325	/* cmp seglim, regptr */
326	if (pTlbState->idxRegPtr != UINT8_MAX && offDisp == 0)
327	off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit, pTlbState->idxRegPtr);
328	else if (pTlbState->idxRegPtr == UINT8_MAX)
329	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxRegSegLimit,
330	(uint32_t)(pTlbState->uAbsPtr + offDisp));
331	else if (cbMem == 1)
332	off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit, pTlbState->idxReg2);
333	else
334	{ /* use idxRegMemResult to calc the displaced address. */
335	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxRegPtr, offDisp);
336	off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit, idxRegMemResult);
337	}
338	/* ja tlbmiss */
339	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
340
341	/* reg1 = segattr & X86DESCATTR_D (0x4000) */
342	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxRegSegAttrib, X86DESCATTR_D);
343	/* xor reg1, X86DESCATTR_D */
344	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1, X86DESCATTR_D);
345	/* shl reg1, 2 (16 - 14) */
346	AssertCompile((X86DESCATTR_D << 2) == UINT32_C(0x10000));
347	off = iemNativeEmitShiftGpr32LeftEx(pCodeBuf, off, pTlbState->idxReg1, 2);
348	/* dec reg1 (=> 0xffff if D=0; 0xffffffff if D=1) */
349	off = iemNativeEmitSubGpr32ImmEx(pCodeBuf, off, pTlbState->idxReg1, 1);
350	/* cmp reg1, reg2 (64-bit) / imm (32-bit) */
351	if (pTlbState->idxRegPtr != UINT8_MAX)
352	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1,
353	cbMem > 1 \|\| offDisp != 0 ? pTlbState->idxReg2 : pTlbState->idxRegPtr);
354	else
355	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1,
356	(uint32_t)(pTlbState->uAbsPtr + offDisp + cbMem - 1)); /* fSkip=true on overflow. */
357	/* jbe tlbmiss */
358	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_be);
359	/* jmp limitdone */
360	offFixupLimitDone = off;
361	off = iemNativeEmitJmpToFixedEx(pCodeBuf, off, off /* ASSUME short jump suffices */);
362	}
363
364	/*
365	* tlblookup:
366	*/
367	iemNativeLabelDefine(pReNative, idxLabelTlbLookup, off);
368	# if defined(RT_ARCH_ARM64) && 0
369	off = iemNativeEmitBrkEx(pCodeBuf, off, 0);
370	# endif
371
372	/*
373	* 1. Segmentation.
374	*
375	* 1a. Check segment limit and attributes if non-flat 32-bit code. This is complicated.
376	*
377	* This can be skipped for code TLB lookups because limit is checked by jmp, call,
378	* ret, and iret prior to making it. It is also checked by the helpers prior to
379	* doing TLB loading.
380	*/
381	if (a_fDataTlb && iSegReg != UINT8_MAX && (pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) != IEMMODE_64BIT)
382	{
383	/* Check that we've got a segment loaded and that it allows the access.
384	For write access this means a writable data segment.
385	For read-only accesses this means a readable code segment or any data segment. */
386	if (fAccess & IEM_ACCESS_TYPE_WRITE)
387	{
388	uint32_t const fMustBe1 = X86DESCATTR_P \| X86DESCATTR_DT \| X86_SEL_TYPE_WRITE;
389	uint32_t const fMustBe0 = X86DESCATTR_UNUSABLE \| X86_SEL_TYPE_CODE;
390	/* reg1 = segattrs & (must1\|must0) */
391	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1,
392	pTlbState->idxRegSegAttrib, fMustBe1 \| fMustBe0);
393	/* cmp reg1, must1 */
394	AssertCompile(fMustBe1 <= UINT16_MAX);
395	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, fMustBe1);
396	/* jne tlbmiss */
397	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
398	}
399	else
400	{
401	/* U \| !P \|!DT \|!CD \| RW \|
402	16 \| 8 \| 4 \| 3 \| 1 \|
403	-------------------------------
404	0 \| 0 \| 0 \| 0 \| 0 \| execute-only code segment. - must be excluded
405	0 \| 0 \| 0 \| 0 \| 1 \| execute-read code segment.
406	0 \| 0 \| 0 \| 1 \| 0 \| read-only data segment.
407	0 \| 0 \| 0 \| 1 \| 1 \| read-write data segment. - last valid combination
408	*/
409	/* reg1 = segattrs & (relevant attributes) */
410	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxRegSegAttrib,
411	X86DESCATTR_UNUSABLE \| X86DESCATTR_P \| X86DESCATTR_DT
412	\| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_WRITE);
413	/* xor reg1, X86DESCATTR_P \| X86DESCATTR_DT \| X86_SEL_TYPE_CODE ; place C=1 RW=0 at the bottom & limit the range.
414	; EO-code=0, ER-code=2, RO-data=8, RW-data=10 */
415	#ifdef RT_ARCH_ARM64
416	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1, X86DESCATTR_DT \| X86_SEL_TYPE_CODE);
417	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1, X86DESCATTR_P);
418	#else
419	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1,
420	X86DESCATTR_P \| X86DESCATTR_DT \| X86_SEL_TYPE_CODE);
421	#endif
422	/* sub reg1, X86_SEL_TYPE_WRITE ; EO-code=-2, ER-code=0, RO-data=6, RW-data=8 */
423	off = iemNativeEmitSubGpr32ImmEx(pCodeBuf, off, pTlbState->idxReg1, X86_SEL_TYPE_WRITE /* ER-code */);
424	/* cmp reg1, X86_SEL_TYPE_CODE \| X86_SEL_TYPE_WRITE */
425	AssertCompile(X86_SEL_TYPE_CODE == 8);
426	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, X86_SEL_TYPE_CODE);
427	/* ja tlbmiss */
428	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
429	}
430
431	/* If we're accessing more than one byte or if we're working with a non-zero offDisp,
432	put the last address we'll be accessing in idxReg2 (64-bit). */
433	if ((cbMem > 1 \|\| offDisp != 0) && pTlbState->idxRegPtr != UINT8_MAX)
434	{
435	if (!offDisp)
436	/* reg2 = regptr + cbMem - 1; 64-bit result so we can fend of wraparounds/overflows. */
437	off = iemNativeEmitGprEqGprPlusImmEx(pCodeBuf, off, pTlbState->idxReg2,/=/ pTlbState->idxRegPtr,/+/ cbMem - 1);
438	else
439	{
440	/* reg2 = (uint32_t)(regptr + offDisp) + cbMem - 1;. */
441	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off,
442	pTlbState->idxReg2,/=/ pTlbState->idxRegPtr,/+/ + offDisp);
443	off = iemNativeEmitAddGprImmEx(pCodeBuf, off, pTlbState->idxReg2, cbMem - 1);
444	}
445	}
446
447	/*
448	* Check the limit. If this is a write access, we know that it's a
449	* data segment and includes the expand_down bit. For read-only accesses
450	* we need to check that code/data=0 and expanddown=1 before continuing.
451	*/
452	if (fAccess & IEM_ACCESS_TYPE_WRITE)
453	{
454	/* test segattrs, X86_SEL_TYPE_DOWN */
455	AssertCompile(X86_SEL_TYPE_DOWN < 128);
456	off = iemNativeEmitTestAnyBitsInGpr8Ex(pCodeBuf, off, pTlbState->idxRegSegAttrib, X86_SEL_TYPE_DOWN);
457	/* jnz check_expand_down */
458	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, offCheckExpandDown, kIemNativeInstrCond_ne);
459	}
460	else
461	{
462	/* reg1 = segattr & (code \| down) */
463	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1,
464	pTlbState->idxRegSegAttrib, X86_SEL_TYPE_CODE \| X86_SEL_TYPE_DOWN);
465	/* cmp reg1, down */
466	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, X86_SEL_TYPE_DOWN);
467	/* je check_expand_down */
468	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, offCheckExpandDown, kIemNativeInstrCond_e);
469	}
470
471	/* expand_up:
472	cmp seglim, regptr/reg2/imm */
473	if (pTlbState->idxRegPtr != UINT8_MAX)
474	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit,
475	cbMem > 1 \|\| offDisp != 0 ? pTlbState->idxReg2 : pTlbState->idxRegPtr);
476	else
477	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxRegSegLimit,
478	(uint32_t)pTlbState->uAbsPtr + offDisp + cbMem - 1U); /* fSkip=true on overflow. */
479	/* jbe tlbmiss */
480	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_be);
481
482	/* limitdone: */
483	iemNativeFixupFixedJump(pReNative, offFixupLimitDone, off);
484	}
485
486	/* 1b. Add the segment base. We use idxRegMemResult for the ptr register if
487	this step is required or if the address is a constant (simplicity) or
488	if offDisp is non-zero. */
489	uint8_t const idxRegFlatPtr = iSegReg != UINT8_MAX \|\| pTlbState->idxRegPtr == UINT8_MAX \|\| offDisp != 0
490	? idxRegMemResult : pTlbState->idxRegPtr;
491	if (iSegReg != UINT8_MAX)
492	{
493	Assert(idxRegFlatPtr != pTlbState->idxRegPtr);
494	/* regflat = segbase + regptr/imm */
495	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
496	{
497	Assert(iSegReg >= X86_SREG_FS);
498	if (pTlbState->idxRegPtr != UINT8_MAX)
499	{
500	off = iemNativeEmitGprEqGprPlusGprEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegSegBase, pTlbState->idxRegPtr);
501	if (offDisp != 0)
502	off = iemNativeEmitAddGprImmEx(pCodeBuf, off, idxRegFlatPtr, offDisp);
503	}
504	else
505	off = iemNativeEmitGprEqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegSegBase,
506	pTlbState->uAbsPtr + offDisp);
507	}
508	else if (pTlbState->idxRegPtr != UINT8_MAX)
509	{
510	off = iemNativeEmitGpr32EqGprPlusGprEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegSegBase, pTlbState->idxRegPtr);
511	if (offDisp != 0)
512	off = iemNativeEmitAddGpr32ImmEx(pCodeBuf, off, idxRegFlatPtr, offDisp);
513	}
514	else
515	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr,
516	pTlbState->idxRegSegBase, (uint32_t)pTlbState->uAbsPtr + offDisp);
517	}
518	else if (pTlbState->idxRegPtr == UINT8_MAX)
519	{
520	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
521	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->uAbsPtr + offDisp);
522	else
523	off = iemNativeEmitLoadGpr32ImmEx(pCodeBuf, off, idxRegFlatPtr, (uint32_t)pTlbState->uAbsPtr + offDisp);
524	}
525	else if (offDisp != 0)
526	{
527	Assert(idxRegFlatPtr != pTlbState->idxRegPtr);
528	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
529	off = iemNativeEmitGprEqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegPtr, offDisp);
530	else
531	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegPtr, offDisp);
532	}
533	else
534	Assert(idxRegFlatPtr == pTlbState->idxRegPtr);
535
536	/*
537	* 2. Check that the address doesn't cross a page boundrary and doesn't have alignment issues.
538	*
539	* 2a. Alignment check using fAlignMask.
540	*/
541	if (fAlignMask)
542	{
543	Assert(RT_IS_POWER_OF_TWO(fAlignMask + 1));
544	Assert(fAlignMask < 128);
545	/* test regflat, fAlignMask */
546	off = iemNativeEmitTestAnyBitsInGpr8Ex(pCodeBuf, off, idxRegFlatPtr, fAlignMask);
547	/* jnz tlbmiss */
548	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
549	}
550
551	/*
552	* 2b. Check that it's not crossing page a boundrary. This is implicit in
553	* the previous test if the alignment is same or larger than the type.
554	*/
555	if (cbMem > fAlignMask + 1)
556	{
557	/* reg1 = regflat & 0xfff */
558	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1,/=/ idxRegFlatPtr,/&/ GUEST_PAGE_OFFSET_MASK);
559	/* cmp reg1, GUEST_PAGE_SIZE - cbMem */
560	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, GUEST_PAGE_SIZE);
561	/* ja tlbmiss */
562	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
563	}
564
565	/*
566	* 3. TLB lookup.
567	*
568	* 3a. Calculate the TLB tag value (IEMTLB_CALC_TAG).
569	* In 64-bit mode we will also check for non-canonical addresses here.
570	*/
571	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
572	{
573	# if defined(RT_ARCH_AMD64)
574	/* mov reg1, regflat */
575	off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, pTlbState->idxReg1, idxRegFlatPtr);
576	/* rol reg1, 16 */
577	off = iemNativeEmitRotateGprLeftEx(pCodeBuf, off, pTlbState->idxReg1, 16);
578	/** @todo Would 'movsx reg2, word reg1' and working on reg2 in dwords be faster? */
579	/* inc word reg1 */
580	pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
581	if (pTlbState->idxReg1 >= 8)
582	pCodeBuf[off++] = X86_OP_REX_B;
583	pCodeBuf[off++] = 0xff;
584	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, pTlbState->idxReg1 & 7);
585	/* cmp word reg1, 1 */
586	pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
587	if (pTlbState->idxReg1 >= 8)
588	pCodeBuf[off++] = X86_OP_REX_B;
589	pCodeBuf[off++] = 0x83;
590	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, pTlbState->idxReg1 & 7);
591	pCodeBuf[off++] = 1;
592	/* ja tlbmiss */
593	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
594	/* shr reg1, 16 + GUEST_PAGE_SHIFT */
595	off = iemNativeEmitShiftGprRightEx(pCodeBuf, off, pTlbState->idxReg1, 16 + GUEST_PAGE_SHIFT);
596
597	# elif defined(RT_ARCH_ARM64)
598	/* lsr reg1, regflat, #48 */
599	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(pTlbState->idxReg1, idxRegFlatPtr, 48);
600	/* add reg1, reg1, #1 */
601	pCodeBuf[off++] = Armv8A64MkInstrAddUImm12(pTlbState->idxReg1, pTlbState->idxReg1, 1, false /f64Bit/);
602	/* tst reg1, #0xfffe */
603	Assert(Armv8A64ConvertImmRImmS2Mask32(14, 31) == 0xfffe);
604	pCodeBuf[off++] = Armv8A64MkInstrTstImm(pTlbState->idxReg1, 14, 31, false /f64Bit/);
605	/* b.nq tlbmiss */
606	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
607
608	/* ubfx reg1, regflat, #12, #36 */
609	pCodeBuf[off++] = Armv8A64MkInstrUbfx(pTlbState->idxReg1, idxRegFlatPtr, GUEST_PAGE_SHIFT, 48 - GUEST_PAGE_SHIFT);
610	# else
611	# error "Port me"
612	# endif
613	}
614	else
615	{
616	/* reg1 = (uint32_t)(regflat >> 12) */
617	off = iemNativeEmitGpr32EqGprShiftRightImmEx(pCodeBuf, off, pTlbState->idxReg1, idxRegFlatPtr, GUEST_PAGE_SHIFT);
618	}
619	/* or reg1, [qword pVCpu->iem.s.DataTlb.uTlbRevision] */
620	# if defined(RT_ARCH_AMD64)
621	pCodeBuf[off++] = pTlbState->idxReg1 < 8 ? X86_OP_REX_W : X86_OP_REX_W \| X86_OP_REX_R;
622	pCodeBuf[off++] = 0x0b; /* OR r64,r/m64 */
623	off = iemNativeEmitGprByVCpuDisp(pCodeBuf, off, pTlbState->idxReg1, offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbRevision));
624	# else
625	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
626	/* Load uTlbRevision into reg3 and uTlbPhysRev into reg5.
627	We load the offVCpuTlb + aEntries into reg4 and use it for addressing here
628	and later when calculating pTble (save an instruction). */
629	AssertCompileMemberAlignment(IEMTLB, uTlbRevision, 16); /* It is said that misaligned pair loads doesn't perform well. */
630	AssertCompileAdjacentMembers(IEMTLB, uTlbRevision, uTlbPhysRev);
631	AssertCompile(RTASSERT_OFFSET_OF(IEMTLB, uTlbPhysRev) < RTASSERT_OFFSET_OF(IEMTLB, aEntries));
632	AssertCompile(RTASSERT_OFFSET_OF(VMCPUCC, iem.s.DataTlb.aEntries) < _64K);
633	AssertCompile(RTASSERT_OFFSET_OF(VMCPUCC, iem.s.CodeTlb.aEntries) < _64K); /* if larger do: ADD x3, x27, x3, LSL #y */
634	pCodeBuf[off++] = Armv8A64MkInstrMovZ(pTlbState->idxReg4, offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries));
635	pCodeBuf[off++] = Armv8A64MkInstrAddReg(pTlbState->idxReg4, IEMNATIVE_REG_FIXED_PVMCPU, pTlbState->idxReg4);
636	pCodeBuf[off++] = Armv8A64MkInstrLdPairGpr(pTlbState->idxReg3, pTlbState->idxReg5, pTlbState->idxReg4,
637	(RT_OFFSETOF(IEMTLB, uTlbRevision) - RT_OFFSETOF(IEMTLB, aEntries)) / 8);
638	# else
639	off = iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg3, offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbRevision));
640	# endif
641	off = iemNativeEmitOrGprByGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg3);
642	# endif
643
644	/*
645	* 3b. Calc pTlbe.
646	*/
647	# if !defined(RT_ARCH_ARM64) \|\| !defined(IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR)
648	uint32_t const offTlbEntries = offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries);
649	# endif
650	# if defined(RT_ARCH_AMD64)
651	/* movzx reg2, byte reg1 */
652	off = iemNativeEmitLoadGprFromGpr8Ex(pCodeBuf, off, pTlbState->idxReg2, pTlbState->idxReg1);
653	/* shl reg2, 5 ; reg2 = sizeof(IEMTLBENTRY) /
654	AssertCompileSize(IEMTLBENTRY, 32);
655	off = iemNativeEmitShiftGprLeftEx(pCodeBuf, off, pTlbState->idxReg2, 5);
656	/* lea reg2, [pVCpu->iem.s.DataTlb.aEntries + reg2] */
657	AssertCompile(IEMNATIVE_REG_FIXED_PVMCPU < 8);
658	pCodeBuf[off++] = pTlbState->idxReg2 < 8 ? X86_OP_REX_W : X86_OP_REX_W \| X86_OP_REX_X \| X86_OP_REX_R;
659	pCodeBuf[off++] = 0x8d;
660	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM4, pTlbState->idxReg2 & 7, 4 /SIB/);
661	pCodeBuf[off++] = X86_SIB_MAKE(IEMNATIVE_REG_FIXED_PVMCPU & 7, pTlbState->idxReg2 & 7, 0);
662	pCodeBuf[off++] = RT_BYTE1(offTlbEntries);
663	pCodeBuf[off++] = RT_BYTE2(offTlbEntries);
664	pCodeBuf[off++] = RT_BYTE3(offTlbEntries);
665	pCodeBuf[off++] = RT_BYTE4(offTlbEntries);
666
667	# elif defined(RT_ARCH_ARM64)
668	/* reg2 = (reg1 & 0xff) << 5 */
669	pCodeBuf[off++] = Armv8A64MkInstrUbfiz(pTlbState->idxReg2, pTlbState->idxReg1, 5, 8);
670	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
671	/* reg2 += &pVCpu->iem.s.DataTlb.aEntries / CodeTlb.aEntries */
672	pCodeBuf[off++] = Armv8A64MkInstrAddReg(pTlbState->idxReg2, pTlbState->idxReg2, pTlbState->idxReg4);
673	# else
674	/* reg2 += offsetof(VMCPUCC, iem.s.DataTlb.aEntries) */
675	off = iemNativeEmitAddGprImmEx(pCodeBuf, off, pTlbState->idxReg2, offTlbEntries, pTlbState->idxReg3 /iGprTmp/);
676	/* reg2 += pVCpu */
677	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, pTlbState->idxReg2, IEMNATIVE_REG_FIXED_PVMCPU);
678	# endif
679	# else
680	# error "Port me"
681	# endif
682
683	/*
684	* 3c. Compare the TLBE.uTag with the one from 2a (reg1).
685	*/
686	# if defined(RT_ARCH_AMD64)
687	/* cmp reg1, [reg2] */
688	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_R) \| (pTlbState->idxReg2 < 8 ? 0 : X86_OP_REX_B);
689	pCodeBuf[off++] = 0x3b;
690	off = iemNativeEmitGprByGprDisp(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, uTag));
691	# elif defined(RT_ARCH_ARM64)
692	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
693	AssertCompileMemberAlignment(IEMTLBENTRY, uTag, 16); /* It is said that misaligned pair loads doesn't perform well. */
694	AssertCompile(RT_UOFFSETOF(IEMTLBENTRY, uTag) + sizeof(uint64_t) == RT_UOFFSETOF(IEMTLBENTRY, fFlagsAndPhysRev));
695	pCodeBuf[off++] = Armv8A64MkInstrLdPairGpr(pTlbState->idxReg3, pTlbState->idxReg4,
696	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, uTag) / 8);
697	# else
698	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg3, pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, uTag));
699	# endif
700	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg3);
701	# else
702	# error "Port me"
703	# endif
704	/* jne tlbmiss */
705	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
706
707	/*
708	* 4. Check TLB page table level access flags and physical page revision #.
709	*/
710	/* mov reg1, mask */
711	AssertCompile(IEMTLBE_F_PT_NO_USER == 4);
712	uint64_t const fNoUser = (((pReNative->fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK) + 1) & IEMTLBE_F_PT_NO_USER;
713	uint64_t fTlbe = IEMTLBE_F_PHYS_REV \| IEMTLBE_F_NO_MAPPINGR3 \| IEMTLBE_F_PG_UNASSIGNED \| IEMTLBE_F_PT_NO_ACCESSED
714	\| fNoUser;
715	if (fAccess & IEM_ACCESS_TYPE_EXEC)
716	fTlbe \|= IEMTLBE_F_PT_NO_EXEC /\| IEMTLBE_F_PG_NO_READ?/;
717	if (fAccess & IEM_ACCESS_TYPE_READ)
718	fTlbe \|= IEMTLBE_F_PG_NO_READ;
719	if (fAccess & IEM_ACCESS_TYPE_WRITE)
720	fTlbe \|= IEMTLBE_F_PT_NO_WRITE \| IEMTLBE_F_PG_NO_WRITE \| IEMTLBE_F_PT_NO_DIRTY;
721	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, pTlbState->idxReg1, fTlbe);
722	# if defined(RT_ARCH_AMD64)
723	/* and reg1, [reg2->fFlagsAndPhysRev] */
724	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_R) \| (pTlbState->idxReg2 < 8 ? 0 : X86_OP_REX_B);
725	pCodeBuf[off++] = 0x23;
726	off = iemNativeEmitGprByGprDisp(pCodeBuf, off, pTlbState->idxReg1,
727	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, fFlagsAndPhysRev));
728
729	/* cmp reg1, [pVCpu->iem.s.DataTlb.uTlbPhysRev] */
730	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_R);
731	pCodeBuf[off++] = 0x3b;
732	off = iemNativeEmitGprByGprDisp(pCodeBuf, off, pTlbState->idxReg1, IEMNATIVE_REG_FIXED_PVMCPU,
733	offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbPhysRev));
734	# elif defined(RT_ARCH_ARM64)
735	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
736	pCodeBuf[off++] = Armv8A64MkInstrAnd(pTlbState->idxReg1, pTlbState->idxReg1, pTlbState->idxReg4);
737	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg5);
738	# else
739	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg3,
740	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, fFlagsAndPhysRev));
741	pCodeBuf[off++] = Armv8A64MkInstrAnd(pTlbState->idxReg1, pTlbState->idxReg1, pTlbState->idxReg3);
742	off = iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg3, offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbPhysRev));
743	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg3);
744	# endif
745	# else
746	# error "Port me"
747	# endif
748	/* jne tlbmiss */
749	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
750
751	/*
752	* 5. Check that pbMappingR3 isn't NULL (paranoia) and calculate the
753	* resulting pointer.
754	*
755	* For code TLB lookups we have some more work to do here to set various
756	* IEMCPU members and we return a GCPhys address rather than a host pointer.
757	*/
758	# if defined(RT_ARCH_ARM64) && defined(IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR)
759	if (!a_fDataTlb)
760	{
761	/* ldp reg4, reg1, [reg2->GCPhys+pbMappingR3] */
762	AssertCompileMemberAlignment(IEMTLBENTRY, GCPhys, 16);
763	AssertCompileAdjacentMembers(IEMTLBENTRY, GCPhys, pbMappingR3);
764	pCodeBuf[off++] = Armv8A64MkInstrLdPairGpr(pTlbState->idxReg4, pTlbState->idxReg1,
765	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, GCPhys) / 8);
766	}
767	else
768	# endif
769	{
770	/* mov reg1, [reg2->pbMappingR3] */
771	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2,
772	RT_UOFFSETOF(IEMTLBENTRY, pbMappingR3));
773	}
774	/* if (!reg1) goto tlbmiss; */
775	/** @todo eliminate the need for this test? */
776	off = iemNativeEmitTestIfGprIsZeroAndJmpToLabelEx(pReNative, pCodeBuf, off, pTlbState->idxReg1,
777	true /f64Bit/, idxLabelTlbMiss);
778
779	if (a_fDataTlb)
780	{
781	if (idxRegFlatPtr == idxRegMemResult) /* See step 1b. */
782	{
783	/* and result, 0xfff */
784	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegMemResult, GUEST_PAGE_OFFSET_MASK);
785	}
786	else
787	{
788	Assert(idxRegFlatPtr == pTlbState->idxRegPtr);
789	/* result = regflat & 0xfff */
790	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, idxRegMemResult, idxRegFlatPtr, GUEST_PAGE_OFFSET_MASK);
791	}
792
793	/* add result, reg1 */
794	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxReg1);
795	}
796	else
797	{
798	/*
799	* Code TLB use a la iemOpcodeFetchBytesJmp - keep reg2 pointing to the TLBE.
800	*
801	* Note. We do not need to set offCurInstrStart or offInstrNextByte.
802	*/
803	# if !defined(RT_ARCH_ARM64) \|\| !defined(IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR)
804	# ifdef RT_ARCH_AMD64
805	uint8_t const idxReg3 = UINT8_MAX;
806	# else
807	uint8_t const idxReg3 = pTlbState->idxReg3;
808	# endif
809	/* Set pbInstrBuf first since we've got it loaded already. */
810	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg1,
811	RT_UOFFSETOF(VMCPUCC, iem.s.pbInstrBuf), idxReg3);
812	/* Set uInstrBufPc to (FlatPC & ~GUEST_PAGE_OFFSET_MASK). */
813	off = iemNativeEmitGprEqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1, idxRegFlatPtr, ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK);
814	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg1,
815	RT_UOFFSETOF(VMCPUCC, iem.s.uInstrBufPc), idxReg3);
816	/* Set cbInstrBufTotal to GUEST_PAGE_SIZE. / /* @todo this is a simplifications. Calc right size using CS.LIM and EIP? */
817	off = iemNativeEmitStoreImmToVCpuU16Ex(pCodeBuf, off, GUEST_PAGE_SIZE, RT_UOFFSETOF(VMCPUCC, iem.s.cbInstrBufTotal),
818	pTlbState->idxReg1, idxReg3);
819	/* Now set GCPhysInstrBuf last as we'll be returning it in idxRegMemResult. */
820	# if defined(RT_ARCH_ARM64) && defined(IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR)
821	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg4,
822	RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf), idxReg3);
823	# else
824	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg1,
825	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, GCPhys));
826	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg1,
827	RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf), idxReg3);
828	# endif
829	# else
830	/* ARM64: Same as above but using STP. This ASSUMES that we can trash
831	the 6 bytes following iem.s.cbInstrBufTotal! */
832	AssertCompileMemberAlignment(VMCPUCC, iem.s.pbInstrBuf, 16);
833	AssertCompileAdjacentMembers(VMCPUCC, iem.s.pbInstrBuf, iem.s.uInstrBufPc);
834	AssertCompile(RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf) < 512);
835	/* idxReg1 = reg2->pbMappingR3 (see previous LDP) */
836	/* idxReg3 = FlatPC & ~GUEST_PAGE_OFFSET_MASK. */
837	off = iemNativeEmitGprEqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg3, idxRegFlatPtr, ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK);
838	pCodeBuf[off++] = Armv8A64MkInstrStPairGpr(pTlbState->idxReg1, pTlbState->idxReg3,
839	IEMNATIVE_REG_FIXED_PVMCPU, RT_UOFFSETOF(VMCPUCC, iem.s.pbInstrBuf) / 8);
840
841	AssertCompileMemberAlignment(VMCPUCC, iem.s.GCPhysInstrBuf, 16);
842	AssertCompileAdjacentMembers(VMCPUCC, iem.s.GCPhysInstrBuf, iem.s.cbInstrBufTotal);
843	AssertCompile(RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf) < 512);
844	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
845	AssertCompileAdjacentMembers(VMCPUCC, iem.s.cbInstrBufTotal, iem.s.offCurInstrStart);
846	AssertCompileAdjacentMembers(VMCPUCC, iem.s.offCurInstrStart, iem.s.fPrefixes); /* these two will be set to ~0. */
847	# endif
848	/* idxReg4 = reg2->GCPhys (see previous LDP) */
849	/* idxReg3 = GUEST_PAGE_SIZE \| UINT64_C(0xffffffffffff0000) */
850	pCodeBuf[off++] = Armv8A64MkInstrMovN(pTlbState->idxReg3, ~GUEST_PAGE_SIZE & 0xffff);
851	pCodeBuf[off++] = Armv8A64MkInstrStPairGpr(pTlbState->idxReg4, pTlbState->idxReg3,
852	IEMNATIVE_REG_FIXED_PVMCPU, RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf) / 8);
853	# endif
854	if (!a_fNoReturn) /* (We skip this for iemNativeEmitBltLoadTlbAfterBranch.) */
855	{
856	/* Set idxRegMemResult. */
857	if (idxRegFlatPtr == idxRegMemResult) /* See step 1b. */
858	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegMemResult, GUEST_PAGE_OFFSET_MASK);
859	else
860	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, idxRegMemResult, idxRegFlatPtr, GUEST_PAGE_OFFSET_MASK);
861	# if defined(RT_ARCH_ARM64) && defined(IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR)
862	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxReg4);
863	# else
864	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxReg1);
865	# endif
866	}
867	}
868
869	# if 0
870	/*
871	* To verify the result we call a helper function.
872	*
873	* It's like the state logging, so parameters are passed on the stack.
874	* iemNativeHlpAsmSafeWrapCheckTlbLookup(pVCpu, result, addr, seg \| (cbMem << 8) \| (fAccess << 16))
875	*/
876	# ifdef RT_ARCH_AMD64
877	if (a_fDataTlb)
878	{
879	/* push seg \| (cbMem << 8) \| (fAccess << 16) */
880	pCodeBuf[off++] = 0x68;
881	pCodeBuf[off++] = iSegReg;
882	pCodeBuf[off++] = cbMem;
883	pCodeBuf[off++] = RT_BYTE1(fAccess);
884	pCodeBuf[off++] = RT_BYTE2(fAccess);
885	/* push pTlbState->idxRegPtr / immediate address. */
886	if (pTlbState->idxRegPtr != UINT8_MAX)
887	{
888	if (pTlbState->idxRegPtr >= 8)
889	pCodeBuf[off++] = X86_OP_REX_B;
890	pCodeBuf[off++] = 0x50 + (pTlbState->idxRegPtr & 7);
891	}
892	else
893	{
894	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->uAbsPtr);
895	if (pTlbState->idxReg1 >= 8)
896	pCodeBuf[off++] = X86_OP_REX_B;
897	pCodeBuf[off++] = 0x50 + (pTlbState->idxReg1 & 7);
898	}
899	/* push idxRegMemResult */
900	if (idxRegMemResult >= 8)
901	pCodeBuf[off++] = X86_OP_REX_B;
902	pCodeBuf[off++] = 0x50 + (idxRegMemResult & 7);
903	/* push pVCpu */
904	pCodeBuf[off++] = 0x50 + IEMNATIVE_REG_FIXED_PVMCPU;
905	/* mov reg1, helper */
906	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, pTlbState->idxReg1, (uintptr_t)iemNativeHlpAsmSafeWrapCheckTlbLookup);
907	/* call [reg1] */
908	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_B);
909	pCodeBuf[off++] = 0xff;
910	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 2, pTlbState->idxReg1 & 7);
911	/* The stack is cleaned up by helper function. */
912	}
913
914	# else
915	# error "Port me"
916	# endif
917	# endif
918
919	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
920
921	return off;
922	}
923	#endif /* IEMNATIVE_WITH_TLB_LOOKUP */
924
925
926	/** @} */
927
928	#endif /* !VMM_INCLUDED_SRC_include_IEMN8veRecompilerTlbLookup_h */
929

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source: vbox/trunk/src/VBox/VMM/include/IEMN8veRecompilerTlbLookup.h@ 104821

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