VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 99132

Last change on this file since 99132 was 98703, checked in by vboxsync, 22 months ago

VMM/{CPUM,IEM}: Implement SHA instruction set extension emulation in IEM and expose it to the guest if available on the host, bugref:9898
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1/* $Id: IEMMc.h 98703 2023-02-23 15:10:16Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
79 return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
84 return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
89 return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
95 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
96 return iemRaiseUndefinedOpcode(pVCpu); \
97 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
98 return iemRaiseDeviceNotAvailable(pVCpu); \
99 } while (0)
100#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
101 do { \
102 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
103 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
104 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
105 return iemRaiseUndefinedOpcode(pVCpu); \
106 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
107 return iemRaiseDeviceNotAvailable(pVCpu); \
108 } while (0)
109#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
110 do { \
111 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
112 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
113 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAesNi) \
114 return iemRaiseUndefinedOpcode(pVCpu); \
115 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
116 return iemRaiseDeviceNotAvailable(pVCpu); \
117 } while (0)
118#define IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT() \
119 do { \
120 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
121 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
122 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSha) \
123 return iemRaiseUndefinedOpcode(pVCpu); \
124 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
125 return iemRaiseDeviceNotAvailable(pVCpu); \
126 } while (0)
127#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
128 do { \
129 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
130 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
131 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
132 return iemRaiseUndefinedOpcode(pVCpu); \
133 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
134 return iemRaiseDeviceNotAvailable(pVCpu); \
135 } while (0)
136#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
137 do { \
138 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
139 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
140 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
141 return iemRaiseUndefinedOpcode(pVCpu); \
142 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
143 return iemRaiseDeviceNotAvailable(pVCpu); \
144 } while (0)
145#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
146 do { \
147 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
148 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
149 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
150 return iemRaiseUndefinedOpcode(pVCpu); \
151 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
152 return iemRaiseDeviceNotAvailable(pVCpu); \
153 } while (0)
154#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
155 do { \
156 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
157 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
158 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
159 return iemRaiseUndefinedOpcode(pVCpu); \
160 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
161 return iemRaiseDeviceNotAvailable(pVCpu); \
162 } while (0)
163#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
164 do { \
165 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
166 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
167 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
168 return iemRaiseUndefinedOpcode(pVCpu); \
169 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
170 return iemRaiseDeviceNotAvailable(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
173 do { \
174 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
175 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
176 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
177 return iemRaiseUndefinedOpcode(pVCpu); \
178 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
179 return iemRaiseDeviceNotAvailable(pVCpu); \
180 } while (0)
181#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
182 do { \
183 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
184 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
185 return iemRaiseUndefinedOpcode(pVCpu); \
186 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
187 return iemRaiseDeviceNotAvailable(pVCpu); \
188 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
189 return iemRaiseMathFault(pVCpu); \
190 } while (0)
191#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
192 do { \
193 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
194 || !(a_fSupported)) \
195 return iemRaiseUndefinedOpcode(pVCpu); \
196 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
197 return iemRaiseDeviceNotAvailable(pVCpu); \
198 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
199 return iemRaiseMathFault(pVCpu); \
200 } while (0)
201#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
202 do { \
203 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
204 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
205 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
206 return iemRaiseUndefinedOpcode(pVCpu); \
207 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
208 return iemRaiseDeviceNotAvailable(pVCpu); \
209 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
210 return iemRaiseMathFault(pVCpu); \
211 } while (0)
212#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
213 do { \
214 if (pVCpu->iem.s.uCpl != 0) \
215 return iemRaiseGeneralProtectionFault0(pVCpu); \
216 } while (0)
217#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
218 do { \
219 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
220 else return iemRaiseGeneralProtectionFault0(pVCpu); \
221 } while (0)
222#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
223 do { \
224 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
225 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
226 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
227 return iemRaiseUndefinedOpcode(pVCpu); \
228 } while (0)
229#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
230 do { \
231 if (!IEM_IS_CANONICAL(a_u64Addr)) \
232 return iemRaiseGeneralProtectionFault0(pVCpu); \
233 } while (0)
234#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
235 do { \
236 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
237 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
238 { \
239 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
240 return iemRaiseSimdFpException(pVCpu); \
241 else \
242 return iemRaiseUndefinedOpcode(pVCpu); \
243 } \
244 } while (0)
245#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
246 do { \
247 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
248 return iemRaiseSimdFpException(pVCpu); \
249 else \
250 return iemRaiseUndefinedOpcode(pVCpu); \
251 } while (0)
252#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
253 do { \
254 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
255 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
256 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
257 return iemRaiseUndefinedOpcode(pVCpu); \
258 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
259 return iemRaiseDeviceNotAvailable(pVCpu); \
260 } while (0)
261
262
263#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
264#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
265#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
266#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
267#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
268#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
269#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
270 uint32_t a_Name; \
271 uint32_t *a_pName = &a_Name
272#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
273 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
274
275#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
276#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
277
278#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
279#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
280#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
281#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
282#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
283#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
284#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
285#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
286#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
287#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
288#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
289#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
290#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
291#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
292#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
293#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
294#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
295#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
296 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
297 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
298 } while (0)
299#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
300 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
301 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
302 } while (0)
303#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
304 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
305 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
306 } while (0)
307/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
308#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
309 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
310 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
311 } while (0)
312#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
313 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
314 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
315 } while (0)
316/** @note Not for IOPL or IF testing or modification. */
317#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
318#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
319#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
320#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
321
322#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
323#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
324#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
325#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
326#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
327#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
328#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
329#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
330#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
331#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
332#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
333/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
334#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
335 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
336 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
337 } while (0)
338#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
339 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
340 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
341 } while (0)
342#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
343 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
344
345
346#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
347#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
348/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
349 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
350#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
351#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
352#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
353#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
354#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
355#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
356/** @note Not for IOPL or IF testing or modification.
357 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
358#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
359#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
360
361#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
362#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
363#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
364 do { \
365 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
366 *pu32Reg += (a_u32Value); \
367 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
368 } while (0)
369#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
370
371#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
372#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
373#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
374 do { \
375 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
376 *pu32Reg -= (a_u32Value); \
377 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
378 } while (0)
379#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
380#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
381
382#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
383#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
384#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
385#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
386#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
387#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
388#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
389
390#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
391#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
392#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
393#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
394
395#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
396#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
397#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
398
399#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
400#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
401#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
402
403#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
404#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
405#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
406
407#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
408
409#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
410#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
411#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
412
413#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
414
415#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
416
417#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
418#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
419#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
420 do { \
421 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
422 *pu32Reg &= (a_u32Value); \
423 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
424 } while (0)
425#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
426
427#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
428#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
429#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
430 do { \
431 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
432 *pu32Reg |= (a_u32Value); \
433 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
434 } while (0)
435#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
436
437#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
438#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
439#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
440
441/** @note Not for IOPL or IF modification. */
442#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
443/** @note Not for IOPL or IF modification. */
444#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
445/** @note Not for IOPL or IF modification. */
446#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
447
448#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
449
450/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
451#define IEM_MC_FPU_TO_MMX_MODE() do { \
452 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
453 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
454 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
455 } while (0)
456
457/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
458#define IEM_MC_FPU_FROM_MMX_MODE() do { \
459 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
460 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
461 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
462 } while (0)
463
464#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
465 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
466#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
467 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
468#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
469 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
470 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
471 } while (0)
472#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
473 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
474 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
475 } while (0)
476#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
477 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
478#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
479 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
480#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
481 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
482#define IEM_MC_MODIFIED_MREG(a_iMReg) \
483 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
484#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
485 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
486
487#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
488 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
489 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
490 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
491 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
492 } while (0)
493#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
494 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
495 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
496 } while (0)
497#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
498 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
499 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
500 } while (0)
501#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
502 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
503#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
504 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
505#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
506 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
507#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
508 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
509#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
510 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
511 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
512 } while (0)
513#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
514 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
515 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
516 } while (0)
517#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
518 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
519#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
520 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
521#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
522 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
523#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
524 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
525#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
526 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
527#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
528 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
529
530#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
531 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
532 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
533 } while (0)
534
535#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
536 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
537#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
538 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
539#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
540 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
541#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
542 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
543 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
544 } while (0)
545#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
546 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
547#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
548 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
549#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
550 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
551#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
552 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
553#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
554 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
555#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
556 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
557#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
558 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
559#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
560 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
561#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
562 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
563 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
564 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
565 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
566 } while (0)
567
568#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
569 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
570 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
571 } while (0)
572#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
573 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
574 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
575 } while (0)
576#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
577 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
578 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
579 } while (0)
580#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
581 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
582 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
583 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
584 } while (0)
585#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
586 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
587 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
588 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
589 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
590 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
591 } while (0)
592
593#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
594#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
595 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
596 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
597 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
598 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
599 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
600 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
601 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
602 } while (0)
603#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
604 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
605 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
606 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
607 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
608 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
609 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
610 } while (0)
611#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
612 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
613 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
614 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
615 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
616 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
617 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
618 } while (0)
619#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
620 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
621 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
622 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
623 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
624 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
625 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
626 } while (0)
627
628#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
629 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
630#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
631 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
632#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
633 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
634#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
635 do { uintptr_t const iYRegTmp = (a_iYReg); \
636 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
637 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
638 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
639 } while (0)
640
641#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
642 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
643 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
644 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
645 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
646 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
647 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
648 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
649 } while (0)
650#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
651 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
652 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
653 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
654 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
655 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
656 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
657 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
658 } while (0)
659#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
660 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
661 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
662 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
663 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
664 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
665 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
666 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
667 } while (0)
668
669#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
670 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
671 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
672 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
673 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
674 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
675 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
676 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
677 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
678 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
679 } while (0)
680#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
681 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
682 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
683 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
684 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
685 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
686 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
687 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
688 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
689 } while (0)
690#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
691 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
692 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
693 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
694 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
695 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
696 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
697 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
698 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
699 } while (0)
700#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
701 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
702 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
703 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
704 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
705 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
706 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
707 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
708 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
709 } while (0)
710#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
711 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
712 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
713 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
714 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
715 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
716 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
717 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
718 } while (0)
719#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
720 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
721 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
722 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
723 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
724 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
725 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
726 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
727 } while (0)
728
729#ifndef IEM_WITH_SETJMP
730# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
731 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
732# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
733 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
734# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
735 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
736#else
737# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
738 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
739# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
740 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
741# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
742 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
743#endif
744
745#ifndef IEM_WITH_SETJMP
746# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
747 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
748# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
749 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
750# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
751 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
752#else
753# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
754 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
755# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
756 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
757# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
758 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
759#endif
760
761#ifndef IEM_WITH_SETJMP
762# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
763 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
764# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
765 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
766# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
767 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
768#else
769# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
770 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
771# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
772 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
773# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
774 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
775#endif
776
777#ifdef SOME_UNUSED_FUNCTION
778# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
779 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
780#endif
781
782#ifndef IEM_WITH_SETJMP
783# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
784 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
785# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
786 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
787# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
788 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
789# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
790 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
791#else
792# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
793 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
794# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
795 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
796# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
797 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
798# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
799 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
800#endif
801
802#ifndef IEM_WITH_SETJMP
803# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
804 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
805# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
806 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
807# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
808 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
809# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
810 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
811#else
812# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
813 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
814# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
815 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
816# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
817 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
818# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
819 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
820#endif
821
822#ifndef IEM_WITH_SETJMP
823# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
824 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
825# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
826 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
827# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
828 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
829
830# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
831 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
832# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
833 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
834# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
835 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
836# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
837 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
838# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
839 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
840#else
841# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
842 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
843# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
844 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
845# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
846 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
847
848# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
849 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
850# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
851 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
852# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
853 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
854# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
855 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
856# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
857 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
858#endif
859
860#ifndef IEM_WITH_SETJMP
861# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
862 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
863# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
864 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
865# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
866 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
867
868# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
869 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
870# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
871 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
872# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
873 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
874#else
875# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
876 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
877# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
878 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
879# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
880 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
881
882# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
883 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
884# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
885 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
886# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
887 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
888#endif
889
890
891
892#ifndef IEM_WITH_SETJMP
893# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
894 do { \
895 uint8_t u8Tmp; \
896 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
897 (a_u16Dst) = u8Tmp; \
898 } while (0)
899# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
900 do { \
901 uint8_t u8Tmp; \
902 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
903 (a_u32Dst) = u8Tmp; \
904 } while (0)
905# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
906 do { \
907 uint8_t u8Tmp; \
908 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
909 (a_u64Dst) = u8Tmp; \
910 } while (0)
911# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
912 do { \
913 uint16_t u16Tmp; \
914 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
915 (a_u32Dst) = u16Tmp; \
916 } while (0)
917# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
918 do { \
919 uint16_t u16Tmp; \
920 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
921 (a_u64Dst) = u16Tmp; \
922 } while (0)
923# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
924 do { \
925 uint32_t u32Tmp; \
926 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
927 (a_u64Dst) = u32Tmp; \
928 } while (0)
929#else /* IEM_WITH_SETJMP */
930# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
931 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
932# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
933 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
934# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
935 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
936# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
937 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
938# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
939 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
940# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
941 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
942#endif /* IEM_WITH_SETJMP */
943
944#ifndef IEM_WITH_SETJMP
945# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
946 do { \
947 uint8_t u8Tmp; \
948 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
949 (a_u16Dst) = (int8_t)u8Tmp; \
950 } while (0)
951# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
952 do { \
953 uint8_t u8Tmp; \
954 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
955 (a_u32Dst) = (int8_t)u8Tmp; \
956 } while (0)
957# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
958 do { \
959 uint8_t u8Tmp; \
960 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
961 (a_u64Dst) = (int8_t)u8Tmp; \
962 } while (0)
963# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
964 do { \
965 uint16_t u16Tmp; \
966 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
967 (a_u32Dst) = (int16_t)u16Tmp; \
968 } while (0)
969# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
970 do { \
971 uint16_t u16Tmp; \
972 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
973 (a_u64Dst) = (int16_t)u16Tmp; \
974 } while (0)
975# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
976 do { \
977 uint32_t u32Tmp; \
978 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
979 (a_u64Dst) = (int32_t)u32Tmp; \
980 } while (0)
981#else /* IEM_WITH_SETJMP */
982# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
983 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
984# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
985 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
986# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
987 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
988# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
989 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
990# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
991 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
992# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
993 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
994#endif /* IEM_WITH_SETJMP */
995
996#ifndef IEM_WITH_SETJMP
997# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
998 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
999# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
1000 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
1001# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
1002 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
1003# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
1004 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
1005#else
1006# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
1007 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
1008# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
1009 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
1010# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
1011 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
1012# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
1013 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
1014#endif
1015
1016#ifndef IEM_WITH_SETJMP
1017# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1018 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
1019# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1020 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
1021# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1022 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
1023# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1024 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
1025#else
1026# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1027 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
1028# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1029 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
1030# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1031 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1032# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1033 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1034#endif
1035
1036#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1037#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1038#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1039#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1040#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1041#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1042#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1043 do { \
1044 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1045 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1046 } while (0)
1047#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1048 do { \
1049 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1050 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1051 } while (0)
1052
1053#ifndef IEM_WITH_SETJMP
1054# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1055 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1056# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1057 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1058#else
1059# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1060 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1061# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1062 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1063#endif
1064
1065#ifndef IEM_WITH_SETJMP
1066# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1067 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1068# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1069 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1070#else
1071# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1072 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1073# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1074 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1075#endif
1076
1077
1078#define IEM_MC_PUSH_U16(a_u16Value) \
1079 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1080#define IEM_MC_PUSH_U32(a_u32Value) \
1081 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1082#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1083 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1084#define IEM_MC_PUSH_U64(a_u64Value) \
1085 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1086
1087#define IEM_MC_POP_U16(a_pu16Value) \
1088 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1089#define IEM_MC_POP_U32(a_pu32Value) \
1090 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1091#define IEM_MC_POP_U64(a_pu64Value) \
1092 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1093
1094/** Maps guest memory for direct or bounce buffered access.
1095 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1096 * @remarks May return.
1097 */
1098#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1099 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1100 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1101
1102/** Maps guest memory for direct or bounce buffered access.
1103 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1104 * @remarks May return.
1105 */
1106#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1107 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1108 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1109
1110/** Commits the memory and unmaps the guest memory.
1111 * @remarks May return.
1112 */
1113#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1114 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1115
1116/** Commits the memory and unmaps the guest memory unless the FPU status word
1117 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1118 * that would cause FLD not to store.
1119 *
1120 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1121 * store, while \#P will not.
1122 *
1123 * @remarks May in theory return - for now.
1124 */
1125#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1126 do { \
1127 if ( !(a_u16FSW & X86_FSW_ES) \
1128 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1129 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1130 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1131 } while (0)
1132
1133/** Calculate efficient address from R/M. */
1134#ifndef IEM_WITH_SETJMP
1135# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1136 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1137#else
1138# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1139 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1140#endif
1141
1142#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1143#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1144#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1145#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1146#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1147#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1148#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1149
1150/**
1151 * Defers the rest of the instruction emulation to a C implementation routine
1152 * and returns, only taking the standard parameters.
1153 *
1154 * @param a_pfnCImpl The pointer to the C routine.
1155 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1156 */
1157#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1158
1159/**
1160 * Defers the rest of instruction emulation to a C implementation routine and
1161 * returns, taking one argument in addition to the standard ones.
1162 *
1163 * @param a_pfnCImpl The pointer to the C routine.
1164 * @param a0 The argument.
1165 */
1166#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1167
1168/**
1169 * Defers the rest of the instruction emulation to a C implementation routine
1170 * and returns, taking two arguments in addition to the standard ones.
1171 *
1172 * @param a_pfnCImpl The pointer to the C routine.
1173 * @param a0 The first extra argument.
1174 * @param a1 The second extra argument.
1175 */
1176#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1177
1178/**
1179 * Defers the rest of the instruction emulation to a C implementation routine
1180 * and returns, taking three arguments in addition to the standard ones.
1181 *
1182 * @param a_pfnCImpl The pointer to the C routine.
1183 * @param a0 The first extra argument.
1184 * @param a1 The second extra argument.
1185 * @param a2 The third extra argument.
1186 */
1187#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1188
1189/**
1190 * Defers the rest of the instruction emulation to a C implementation routine
1191 * and returns, taking four arguments in addition to the standard ones.
1192 *
1193 * @param a_pfnCImpl The pointer to the C routine.
1194 * @param a0 The first extra argument.
1195 * @param a1 The second extra argument.
1196 * @param a2 The third extra argument.
1197 * @param a3 The fourth extra argument.
1198 */
1199#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1200
1201/**
1202 * Defers the rest of the instruction emulation to a C implementation routine
1203 * and returns, taking two arguments in addition to the standard ones.
1204 *
1205 * @param a_pfnCImpl The pointer to the C routine.
1206 * @param a0 The first extra argument.
1207 * @param a1 The second extra argument.
1208 * @param a2 The third extra argument.
1209 * @param a3 The fourth extra argument.
1210 * @param a4 The fifth extra argument.
1211 */
1212#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1213
1214/**
1215 * Defers the entire instruction emulation to a C implementation routine and
1216 * returns, only taking the standard parameters.
1217 *
1218 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1219 *
1220 * @param a_pfnCImpl The pointer to the C routine.
1221 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1222 */
1223#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1224
1225/**
1226 * Defers the entire instruction emulation to a C implementation routine and
1227 * returns, taking one argument in addition to the standard ones.
1228 *
1229 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1230 *
1231 * @param a_pfnCImpl The pointer to the C routine.
1232 * @param a0 The argument.
1233 */
1234#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1235
1236/**
1237 * Defers the entire instruction emulation to a C implementation routine and
1238 * returns, taking two arguments in addition to the standard ones.
1239 *
1240 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1241 *
1242 * @param a_pfnCImpl The pointer to the C routine.
1243 * @param a0 The first extra argument.
1244 * @param a1 The second extra argument.
1245 */
1246#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1247
1248/**
1249 * Defers the entire instruction emulation to a C implementation routine and
1250 * returns, taking three arguments in addition to the standard ones.
1251 *
1252 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1253 *
1254 * @param a_pfnCImpl The pointer to the C routine.
1255 * @param a0 The first extra argument.
1256 * @param a1 The second extra argument.
1257 * @param a2 The third extra argument.
1258 */
1259#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1260
1261/**
1262 * Calls a FPU assembly implementation taking one visible argument.
1263 *
1264 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1265 * @param a0 The first extra argument.
1266 */
1267#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1268 do { \
1269 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1270 } while (0)
1271
1272/**
1273 * Calls a FPU assembly implementation taking two visible arguments.
1274 *
1275 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1276 * @param a0 The first extra argument.
1277 * @param a1 The second extra argument.
1278 */
1279#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1280 do { \
1281 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1282 } while (0)
1283
1284/**
1285 * Calls a FPU assembly implementation taking three visible arguments.
1286 *
1287 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1288 * @param a0 The first extra argument.
1289 * @param a1 The second extra argument.
1290 * @param a2 The third extra argument.
1291 */
1292#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1293 do { \
1294 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1295 } while (0)
1296
1297#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1298 do { \
1299 (a_FpuData).FSW = (a_FSW); \
1300 (a_FpuData).r80Result = *(a_pr80Value); \
1301 } while (0)
1302
1303/** Pushes FPU result onto the stack. */
1304#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1305 iemFpuPushResult(pVCpu, &a_FpuData)
1306/** Pushes FPU result onto the stack and sets the FPUDP. */
1307#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1308 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1309
1310/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1311#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1312 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1313
1314/** Stores FPU result in a stack register. */
1315#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1316 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1317/** Stores FPU result in a stack register and pops the stack. */
1318#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1319 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1320/** Stores FPU result in a stack register and sets the FPUDP. */
1321#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1322 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1323/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1324 * stack. */
1325#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1326 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1327
1328/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1329#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1330 iemFpuUpdateOpcodeAndIp(pVCpu)
1331/** Free a stack register (for FFREE and FFREEP). */
1332#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1333 iemFpuStackFree(pVCpu, a_iStReg)
1334/** Increment the FPU stack pointer. */
1335#define IEM_MC_FPU_STACK_INC_TOP() \
1336 iemFpuStackIncTop(pVCpu)
1337/** Decrement the FPU stack pointer. */
1338#define IEM_MC_FPU_STACK_DEC_TOP() \
1339 iemFpuStackDecTop(pVCpu)
1340
1341/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1342#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1343 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1344/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1345#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1346 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1347/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1348#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1349 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1350/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1351#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1352 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1353/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1354 * stack. */
1355#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1356 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1357/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1358#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1359 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1360
1361/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1362#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1363 iemFpuStackUnderflow(pVCpu, a_iStDst)
1364/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1365 * stack. */
1366#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1367 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1368/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1369 * FPUDS. */
1370#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1371 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1372/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1373 * FPUDS. Pops stack. */
1374#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1375 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1376/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1377 * stack twice. */
1378#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1379 iemFpuStackUnderflowThenPopPop(pVCpu)
1380/** Raises a FPU stack underflow exception for an instruction pushing a result
1381 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1382#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1383 iemFpuStackPushUnderflow(pVCpu)
1384/** Raises a FPU stack underflow exception for an instruction pushing a result
1385 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1386#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1387 iemFpuStackPushUnderflowTwo(pVCpu)
1388
1389/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1390 * FPUIP, FPUCS and FOP. */
1391#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1392 iemFpuStackPushOverflow(pVCpu)
1393/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1394 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1395#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1396 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1397/** Prepares for using the FPU state.
1398 * Ensures that we can use the host FPU in the current context (RC+R0.
1399 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1400#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1401/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1402#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1403/** Actualizes the guest FPU state so it can be accessed and modified. */
1404#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1405
1406/** Stores SSE SIMD result updating MXCSR. */
1407#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1408 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1409/** Updates MXCSR. */
1410#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1411 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1412
1413/** Prepares for using the SSE state.
1414 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1415 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1416#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1417/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1418#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1419/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1420#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1421
1422/** Prepares for using the AVX state.
1423 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1424 * Ensures the guest AVX state in the CPUMCTX is up to date.
1425 * @note This will include the AVX512 state too when support for it is added
1426 * due to the zero extending feature of VEX instruction. */
1427#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1428/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1429#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1430/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1431#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1432
1433/**
1434 * Calls a MMX assembly implementation taking two visible arguments.
1435 *
1436 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1437 * @param a0 The first extra argument.
1438 * @param a1 The second extra argument.
1439 */
1440#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1441 do { \
1442 IEM_MC_PREPARE_FPU_USAGE(); \
1443 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1444 } while (0)
1445
1446/**
1447 * Calls a MMX assembly implementation taking three visible arguments.
1448 *
1449 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1450 * @param a0 The first extra argument.
1451 * @param a1 The second extra argument.
1452 * @param a2 The third extra argument.
1453 */
1454#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1455 do { \
1456 IEM_MC_PREPARE_FPU_USAGE(); \
1457 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1458 } while (0)
1459
1460
1461/**
1462 * Calls a SSE assembly implementation taking two visible arguments.
1463 *
1464 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1465 * @param a0 The first extra argument.
1466 * @param a1 The second extra argument.
1467 */
1468#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1469 do { \
1470 IEM_MC_PREPARE_SSE_USAGE(); \
1471 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1472 } while (0)
1473
1474/**
1475 * Calls a SSE assembly implementation taking three visible arguments.
1476 *
1477 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1478 * @param a0 The first extra argument.
1479 * @param a1 The second extra argument.
1480 * @param a2 The third extra argument.
1481 */
1482#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1483 do { \
1484 IEM_MC_PREPARE_SSE_USAGE(); \
1485 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1486 } while (0)
1487
1488
1489/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1490 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1491#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1492 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1493
1494/**
1495 * Calls a AVX assembly implementation taking two visible arguments.
1496 *
1497 * There is one implicit zero'th argument, a pointer to the extended state.
1498 *
1499 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1500 * @param a1 The first extra argument.
1501 * @param a2 The second extra argument.
1502 */
1503#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1504 do { \
1505 IEM_MC_PREPARE_AVX_USAGE(); \
1506 a_pfnAImpl(pXState, (a1), (a2)); \
1507 } while (0)
1508
1509/**
1510 * Calls a AVX assembly implementation taking three visible arguments.
1511 *
1512 * There is one implicit zero'th argument, a pointer to the extended state.
1513 *
1514 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1515 * @param a1 The first extra argument.
1516 * @param a2 The second extra argument.
1517 * @param a3 The third extra argument.
1518 */
1519#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1520 do { \
1521 IEM_MC_PREPARE_AVX_USAGE(); \
1522 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1523 } while (0)
1524
1525/** @note Not for IOPL or IF testing. */
1526#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1527/** @note Not for IOPL or IF testing. */
1528#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1529/** @note Not for IOPL or IF testing. */
1530#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1531/** @note Not for IOPL or IF testing. */
1532#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1533/** @note Not for IOPL or IF testing. */
1534#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1535 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1536 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1537/** @note Not for IOPL or IF testing. */
1538#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1539 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1540 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1541/** @note Not for IOPL or IF testing. */
1542#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1543 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1544 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1545 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1546/** @note Not for IOPL or IF testing. */
1547#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1548 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1549 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1550 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1551#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1552#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1553#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1554/** @note Not for IOPL or IF testing. */
1555#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1556 if ( pVCpu->cpum.GstCtx.cx != 0 \
1557 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1558/** @note Not for IOPL or IF testing. */
1559#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1560 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1561 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1562/** @note Not for IOPL or IF testing. */
1563#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1564 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1565 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1566/** @note Not for IOPL or IF testing. */
1567#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1568 if ( pVCpu->cpum.GstCtx.cx != 0 \
1569 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1570/** @note Not for IOPL or IF testing. */
1571#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1572 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1573 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1574/** @note Not for IOPL or IF testing. */
1575#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1576 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1577 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1578#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1579#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1580
1581#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1582 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1583#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1584 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1585#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1586 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1587#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1588 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1589#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1590 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1591#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1592 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1593#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1594 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1595#define IEM_MC_IF_FCW_IM() \
1596 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1597#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1598 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1599 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1600
1601#define IEM_MC_ELSE() } else {
1602#define IEM_MC_ENDIF() } do {} while (0)
1603
1604/** @} */
1605
1606#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1607
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