VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 97441

Last change on this file since 97441 was 97441, checked in by vboxsync, 2 years ago

VMM/IEM: Single stepping for short and near jumps (relative) and corrected o16 prefix behaviour on intel CPUs in 64-bit mode (ignored). Also, #DB seems to implicitly clear, or at least not set, the resume flag (RF). bugref:9898
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File size: 84.3 KB
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1/* $Id: IEMMc.h 97441 2022-11-08 00:07:49Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJump((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJump((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJump((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
79 return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
84 return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
89 return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
95 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
96 return iemRaiseUndefinedOpcode(pVCpu); \
97 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
98 return iemRaiseDeviceNotAvailable(pVCpu); \
99 } while (0)
100#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
101 do { \
102 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
103 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
104 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
105 return iemRaiseUndefinedOpcode(pVCpu); \
106 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
107 return iemRaiseDeviceNotAvailable(pVCpu); \
108 } while (0)
109#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
110 do { \
111 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
112 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
113 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAesNi) \
114 return iemRaiseUndefinedOpcode(pVCpu); \
115 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
116 return iemRaiseDeviceNotAvailable(pVCpu); \
117 } while (0)
118#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
119 do { \
120 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
121 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
122 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
123 return iemRaiseUndefinedOpcode(pVCpu); \
124 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
125 return iemRaiseDeviceNotAvailable(pVCpu); \
126 } while (0)
127#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
128 do { \
129 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
130 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
131 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
132 return iemRaiseUndefinedOpcode(pVCpu); \
133 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
134 return iemRaiseDeviceNotAvailable(pVCpu); \
135 } while (0)
136#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
137 do { \
138 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
139 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
140 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
141 return iemRaiseUndefinedOpcode(pVCpu); \
142 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
143 return iemRaiseDeviceNotAvailable(pVCpu); \
144 } while (0)
145#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
146 do { \
147 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
148 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
149 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
150 return iemRaiseUndefinedOpcode(pVCpu); \
151 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
152 return iemRaiseDeviceNotAvailable(pVCpu); \
153 } while (0)
154#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
155 do { \
156 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
157 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
158 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
159 return iemRaiseUndefinedOpcode(pVCpu); \
160 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
161 return iemRaiseDeviceNotAvailable(pVCpu); \
162 } while (0)
163#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
164 do { \
165 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
166 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
167 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
168 return iemRaiseUndefinedOpcode(pVCpu); \
169 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
170 return iemRaiseDeviceNotAvailable(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
173 do { \
174 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
175 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
176 return iemRaiseUndefinedOpcode(pVCpu); \
177 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
178 return iemRaiseDeviceNotAvailable(pVCpu); \
179 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
180 return iemRaiseMathFault(pVCpu); \
181 } while (0)
182#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
183 do { \
184 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
185 || !(a_fSupported)) \
186 return iemRaiseUndefinedOpcode(pVCpu); \
187 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
188 return iemRaiseDeviceNotAvailable(pVCpu); \
189 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
190 return iemRaiseMathFault(pVCpu); \
191 } while (0)
192#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
193 do { \
194 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
195 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
196 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
197 return iemRaiseUndefinedOpcode(pVCpu); \
198 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
199 return iemRaiseDeviceNotAvailable(pVCpu); \
200 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
201 return iemRaiseMathFault(pVCpu); \
202 } while (0)
203#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
204 do { \
205 if (pVCpu->iem.s.uCpl != 0) \
206 return iemRaiseGeneralProtectionFault0(pVCpu); \
207 } while (0)
208#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
209 do { \
210 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
211 else return iemRaiseGeneralProtectionFault0(pVCpu); \
212 } while (0)
213#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
214 do { \
215 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
216 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
217 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
218 return iemRaiseUndefinedOpcode(pVCpu); \
219 } while (0)
220#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
221 do { \
222 if (!IEM_IS_CANONICAL(a_u64Addr)) \
223 return iemRaiseGeneralProtectionFault0(pVCpu); \
224 } while (0)
225#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
226 do { \
227 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
228 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
229 { \
230 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
231 return iemRaiseSimdFpException(pVCpu); \
232 else \
233 return iemRaiseUndefinedOpcode(pVCpu); \
234 } \
235 } while (0)
236#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
237 do { \
238 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
239 return iemRaiseSimdFpException(pVCpu); \
240 else \
241 return iemRaiseUndefinedOpcode(pVCpu); \
242 } while (0)
243#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
244 do { \
245 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
246 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
247 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
248 return iemRaiseUndefinedOpcode(pVCpu); \
249 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
250 return iemRaiseDeviceNotAvailable(pVCpu); \
251 } while (0)
252
253
254#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
255#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
256#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
257#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
258#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
259#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
260#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
261 uint32_t a_Name; \
262 uint32_t *a_pName = &a_Name
263#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
264 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
265
266#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
267#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
268
269#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
270#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
271#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
272#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
273#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
274#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
275#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
276#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
277#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
278#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
279#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
280#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
281#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
282#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
283#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
284#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
285#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
286#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
287 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
288 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
289 } while (0)
290#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
291 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
292 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
293 } while (0)
294#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
295 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
296 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
297 } while (0)
298/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
299#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
300 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
301 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
302 } while (0)
303#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
304 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
305 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
306 } while (0)
307/** @note Not for IOPL or IF testing or modification. */
308#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
309#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
310#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
311#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
312
313#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
314#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
315#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
316#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
317#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
318#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
319#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
320#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
321#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
322#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
323#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
324/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
325#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
326 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
327 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
328 } while (0)
329#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
330 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
331 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
332 } while (0)
333#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
334 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
335
336
337#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
338#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
339/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
340 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
341#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
342#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
343#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
344#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
345#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
346#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
347/** @note Not for IOPL or IF testing or modification.
348 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
349#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
350#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
351
352#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
353#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
354#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
355 do { \
356 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
357 *pu32Reg += (a_u32Value); \
358 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
359 } while (0)
360#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
361
362#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
363#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
364#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
365 do { \
366 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
367 *pu32Reg -= (a_u32Value); \
368 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
369 } while (0)
370#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
371#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
372
373#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
374#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
375#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
376#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
377#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
378#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
379#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
380
381#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
382#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
383#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
384#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
385
386#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
387#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
388#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
389
390#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
391#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
392#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
393
394#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
395#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
396#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
397
398#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
399#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
400#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
401
402#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
403
404#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
405
406#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
407#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
408#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
409 do { \
410 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
411 *pu32Reg &= (a_u32Value); \
412 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
413 } while (0)
414#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
415
416#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
417#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
418#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
419 do { \
420 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
421 *pu32Reg |= (a_u32Value); \
422 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
423 } while (0)
424#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
425
426
427/** @note Not for IOPL or IF modification. */
428#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
429/** @note Not for IOPL or IF modification. */
430#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
431/** @note Not for IOPL or IF modification. */
432#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
433
434#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
435
436/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
437#define IEM_MC_FPU_TO_MMX_MODE() do { \
438 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
439 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
440 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
441 } while (0)
442
443/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
444#define IEM_MC_FPU_FROM_MMX_MODE() do { \
445 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
446 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
447 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
448 } while (0)
449
450#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
451 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
452#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
453 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
454#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
455 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
456 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
457 } while (0)
458#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
459 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
460 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
461 } while (0)
462#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
463 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
464#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
465 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
466#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
467 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
468#define IEM_MC_MODIFIED_MREG(a_iMReg) \
469 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
470#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
471 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
472
473#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
474 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
475 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
476 } while (0)
477#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
478 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
479 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
480 } while (0)
481#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
482 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
483#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
484 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
485#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
486 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
487#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
488 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
489 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
490 } while (0)
491#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
492 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
493 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
494 } while (0)
495#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
496 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
497#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
498 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
499#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
500 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
501#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
502 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
503 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
504 } while (0)
505#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
506 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
507#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
508 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
509#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
510 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
511#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
512 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
513 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
514 } while (0)
515#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
516 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
517#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
518 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
519#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
520 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
521#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
522 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
523#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
524 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
525#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
526 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
527#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
528 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
529#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
530 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
531#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
532 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
533 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
534 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
535 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
536 } while (0)
537
538#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
539 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
540 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
541 } while (0)
542#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
543 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
544 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
545 } while (0)
546#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
547 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
548 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
549 } while (0)
550#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
551 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
552 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
553 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
554 } while (0)
555#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
556 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
557 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
558 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
559 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
560 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
561 } while (0)
562
563#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
564#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
565 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
566 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
567 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
568 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
569 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
570 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
571 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
572 } while (0)
573#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
574 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
575 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
576 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
577 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
578 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
579 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
580 } while (0)
581#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
582 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
583 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
584 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
585 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
586 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
587 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
588 } while (0)
589#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
590 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
591 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
592 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
593 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
594 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
595 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
596 } while (0)
597
598#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
599 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
600#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
601 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
602#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
603 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
604#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
605 do { uintptr_t const iYRegTmp = (a_iYReg); \
606 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
607 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
608 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
609 } while (0)
610
611#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
612 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
613 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
614 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
615 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
616 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
617 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
618 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
619 } while (0)
620#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
621 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
622 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
623 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
624 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
625 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
626 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
627 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
628 } while (0)
629#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
630 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
631 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
632 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
633 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
634 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
635 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
636 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
637 } while (0)
638
639#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
640 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
641 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
642 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
643 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
644 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
645 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
646 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
647 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
648 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
649 } while (0)
650#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
651 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
652 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
653 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
654 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
655 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
656 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
657 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
658 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
659 } while (0)
660#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
661 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
662 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
663 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
664 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
665 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
666 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
667 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
668 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
669 } while (0)
670#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
671 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
672 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
673 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
674 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
675 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
676 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
677 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
678 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
679 } while (0)
680#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
681 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
682 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
683 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
684 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
685 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
686 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
687 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
688 } while (0)
689#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
690 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
691 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
692 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
693 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
694 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
695 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
696 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
697 } while (0)
698
699#ifndef IEM_WITH_SETJMP
700# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
701 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
702# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
703 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
704# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
705 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
706#else
707# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
708 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
709# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
710 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
711# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
712 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
713#endif
714
715#ifndef IEM_WITH_SETJMP
716# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
717 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
718# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
719 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
720# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
721 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
722#else
723# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
724 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
725# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
726 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
727# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
728 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
729#endif
730
731#ifndef IEM_WITH_SETJMP
732# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
733 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
734# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
735 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
736# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
737 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
738#else
739# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
740 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
741# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
742 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
743# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
744 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
745#endif
746
747#ifdef SOME_UNUSED_FUNCTION
748# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
749 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
750#endif
751
752#ifndef IEM_WITH_SETJMP
753# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
754 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
755# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
756 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
757# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
758 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
759# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
760 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
761#else
762# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
763 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
764# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
765 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
766# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
767 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
768# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
769 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
770#endif
771
772#ifndef IEM_WITH_SETJMP
773# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
774 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
775# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
776 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
777# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
778 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
779# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
780 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
781#else
782# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
783 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
784# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
785 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
786# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
787 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
788# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
789 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
790#endif
791
792#ifndef IEM_WITH_SETJMP
793# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
794 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
795# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
796 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
797# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
798 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
799
800# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
801 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
802# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
803 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
804# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
805 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
806# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
807 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
808# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
809 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
810#else
811# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
812 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
813# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
814 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
815# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
816 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
817
818# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
819 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
820# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
821 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
822# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
823 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
824# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
825 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
826# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
827 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
828#endif
829
830#ifndef IEM_WITH_SETJMP
831# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
832 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
833# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
834 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
835# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
836 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
837
838# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
839 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
840# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
841 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
842# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
843 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
844#else
845# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
846 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
847# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
848 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
849# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
850 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
851
852# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
853 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
854# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
855 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
856# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
857 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
858#endif
859
860
861
862#ifndef IEM_WITH_SETJMP
863# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
864 do { \
865 uint8_t u8Tmp; \
866 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
867 (a_u16Dst) = u8Tmp; \
868 } while (0)
869# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
870 do { \
871 uint8_t u8Tmp; \
872 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
873 (a_u32Dst) = u8Tmp; \
874 } while (0)
875# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
876 do { \
877 uint8_t u8Tmp; \
878 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
879 (a_u64Dst) = u8Tmp; \
880 } while (0)
881# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
882 do { \
883 uint16_t u16Tmp; \
884 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
885 (a_u32Dst) = u16Tmp; \
886 } while (0)
887# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
888 do { \
889 uint16_t u16Tmp; \
890 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
891 (a_u64Dst) = u16Tmp; \
892 } while (0)
893# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
894 do { \
895 uint32_t u32Tmp; \
896 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
897 (a_u64Dst) = u32Tmp; \
898 } while (0)
899#else /* IEM_WITH_SETJMP */
900# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
901 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
902# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
903 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
904# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
905 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
906# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
907 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
908# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
909 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
910# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
911 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
912#endif /* IEM_WITH_SETJMP */
913
914#ifndef IEM_WITH_SETJMP
915# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
916 do { \
917 uint8_t u8Tmp; \
918 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
919 (a_u16Dst) = (int8_t)u8Tmp; \
920 } while (0)
921# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
922 do { \
923 uint8_t u8Tmp; \
924 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
925 (a_u32Dst) = (int8_t)u8Tmp; \
926 } while (0)
927# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
928 do { \
929 uint8_t u8Tmp; \
930 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
931 (a_u64Dst) = (int8_t)u8Tmp; \
932 } while (0)
933# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
934 do { \
935 uint16_t u16Tmp; \
936 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
937 (a_u32Dst) = (int16_t)u16Tmp; \
938 } while (0)
939# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
940 do { \
941 uint16_t u16Tmp; \
942 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
943 (a_u64Dst) = (int16_t)u16Tmp; \
944 } while (0)
945# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
946 do { \
947 uint32_t u32Tmp; \
948 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
949 (a_u64Dst) = (int32_t)u32Tmp; \
950 } while (0)
951#else /* IEM_WITH_SETJMP */
952# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
953 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
954# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
955 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
956# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
957 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
958# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
959 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
960# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
961 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
962# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
963 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
964#endif /* IEM_WITH_SETJMP */
965
966#ifndef IEM_WITH_SETJMP
967# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
968 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
969# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
970 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
971# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
972 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
973# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
974 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
975#else
976# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
977 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
978# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
979 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
980# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
981 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
982# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
983 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
984#endif
985
986#ifndef IEM_WITH_SETJMP
987# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
988 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
989# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
990 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
991# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
992 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
993# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
994 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
995#else
996# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
997 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
998# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
999 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
1000# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1001 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1002# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1003 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1004#endif
1005
1006#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1007#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1008#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1009#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1010#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1011#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1012#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1013 do { \
1014 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1015 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1016 } while (0)
1017#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1018 do { \
1019 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1020 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1021 } while (0)
1022
1023#ifndef IEM_WITH_SETJMP
1024# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1025 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1026# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1027 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1028#else
1029# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1030 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1031# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1032 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1033#endif
1034
1035#ifndef IEM_WITH_SETJMP
1036# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1037 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1038# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1039 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1040#else
1041# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1042 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1043# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1044 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1045#endif
1046
1047
1048#define IEM_MC_PUSH_U16(a_u16Value) \
1049 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1050#define IEM_MC_PUSH_U32(a_u32Value) \
1051 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1052#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1053 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1054#define IEM_MC_PUSH_U64(a_u64Value) \
1055 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1056
1057#define IEM_MC_POP_U16(a_pu16Value) \
1058 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1059#define IEM_MC_POP_U32(a_pu32Value) \
1060 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1061#define IEM_MC_POP_U64(a_pu64Value) \
1062 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1063
1064/** Maps guest memory for direct or bounce buffered access.
1065 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1066 * @remarks May return.
1067 */
1068#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1069 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1070 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1071
1072/** Maps guest memory for direct or bounce buffered access.
1073 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1074 * @remarks May return.
1075 */
1076#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1077 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1078 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1079
1080/** Commits the memory and unmaps the guest memory.
1081 * @remarks May return.
1082 */
1083#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1084 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1085
1086/** Commits the memory and unmaps the guest memory unless the FPU status word
1087 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1088 * that would cause FLD not to store.
1089 *
1090 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1091 * store, while \#P will not.
1092 *
1093 * @remarks May in theory return - for now.
1094 */
1095#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1096 do { \
1097 if ( !(a_u16FSW & X86_FSW_ES) \
1098 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1099 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1100 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1101 } while (0)
1102
1103/** Calculate efficient address from R/M. */
1104#ifndef IEM_WITH_SETJMP
1105# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1106 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1107#else
1108# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1109 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1110#endif
1111
1112#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1113#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1114#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1115#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1116#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1117#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1118#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1119
1120/**
1121 * Defers the rest of the instruction emulation to a C implementation routine
1122 * and returns, only taking the standard parameters.
1123 *
1124 * @param a_pfnCImpl The pointer to the C routine.
1125 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1126 */
1127#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1128
1129/**
1130 * Defers the rest of instruction emulation to a C implementation routine and
1131 * returns, taking one argument in addition to the standard ones.
1132 *
1133 * @param a_pfnCImpl The pointer to the C routine.
1134 * @param a0 The argument.
1135 */
1136#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1137
1138/**
1139 * Defers the rest of the instruction emulation to a C implementation routine
1140 * and returns, taking two arguments in addition to the standard ones.
1141 *
1142 * @param a_pfnCImpl The pointer to the C routine.
1143 * @param a0 The first extra argument.
1144 * @param a1 The second extra argument.
1145 */
1146#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1147
1148/**
1149 * Defers the rest of the instruction emulation to a C implementation routine
1150 * and returns, taking three arguments in addition to the standard ones.
1151 *
1152 * @param a_pfnCImpl The pointer to the C routine.
1153 * @param a0 The first extra argument.
1154 * @param a1 The second extra argument.
1155 * @param a2 The third extra argument.
1156 */
1157#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1158
1159/**
1160 * Defers the rest of the instruction emulation to a C implementation routine
1161 * and returns, taking four arguments in addition to the standard ones.
1162 *
1163 * @param a_pfnCImpl The pointer to the C routine.
1164 * @param a0 The first extra argument.
1165 * @param a1 The second extra argument.
1166 * @param a2 The third extra argument.
1167 * @param a3 The fourth extra argument.
1168 */
1169#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1170
1171/**
1172 * Defers the rest of the instruction emulation to a C implementation routine
1173 * and returns, taking two arguments in addition to the standard ones.
1174 *
1175 * @param a_pfnCImpl The pointer to the C routine.
1176 * @param a0 The first extra argument.
1177 * @param a1 The second extra argument.
1178 * @param a2 The third extra argument.
1179 * @param a3 The fourth extra argument.
1180 * @param a4 The fifth extra argument.
1181 */
1182#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1183
1184/**
1185 * Defers the entire instruction emulation to a C implementation routine and
1186 * returns, only taking the standard parameters.
1187 *
1188 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1189 *
1190 * @param a_pfnCImpl The pointer to the C routine.
1191 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1192 */
1193#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1194
1195/**
1196 * Defers the entire instruction emulation to a C implementation routine and
1197 * returns, taking one argument in addition to the standard ones.
1198 *
1199 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1200 *
1201 * @param a_pfnCImpl The pointer to the C routine.
1202 * @param a0 The argument.
1203 */
1204#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1205
1206/**
1207 * Defers the entire instruction emulation to a C implementation routine and
1208 * returns, taking two arguments in addition to the standard ones.
1209 *
1210 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1211 *
1212 * @param a_pfnCImpl The pointer to the C routine.
1213 * @param a0 The first extra argument.
1214 * @param a1 The second extra argument.
1215 */
1216#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1217
1218/**
1219 * Defers the entire instruction emulation to a C implementation routine and
1220 * returns, taking three arguments in addition to the standard ones.
1221 *
1222 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1223 *
1224 * @param a_pfnCImpl The pointer to the C routine.
1225 * @param a0 The first extra argument.
1226 * @param a1 The second extra argument.
1227 * @param a2 The third extra argument.
1228 */
1229#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1230
1231/**
1232 * Calls a FPU assembly implementation taking one visible argument.
1233 *
1234 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1235 * @param a0 The first extra argument.
1236 */
1237#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1238 do { \
1239 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1240 } while (0)
1241
1242/**
1243 * Calls a FPU assembly implementation taking two visible arguments.
1244 *
1245 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1246 * @param a0 The first extra argument.
1247 * @param a1 The second extra argument.
1248 */
1249#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1250 do { \
1251 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1252 } while (0)
1253
1254/**
1255 * Calls a FPU assembly implementation taking three visible arguments.
1256 *
1257 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1258 * @param a0 The first extra argument.
1259 * @param a1 The second extra argument.
1260 * @param a2 The third extra argument.
1261 */
1262#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1263 do { \
1264 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1265 } while (0)
1266
1267#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1268 do { \
1269 (a_FpuData).FSW = (a_FSW); \
1270 (a_FpuData).r80Result = *(a_pr80Value); \
1271 } while (0)
1272
1273/** Pushes FPU result onto the stack. */
1274#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1275 iemFpuPushResult(pVCpu, &a_FpuData)
1276/** Pushes FPU result onto the stack and sets the FPUDP. */
1277#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1278 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1279
1280/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1281#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1282 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1283
1284/** Stores FPU result in a stack register. */
1285#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1286 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1287/** Stores FPU result in a stack register and pops the stack. */
1288#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1289 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1290/** Stores FPU result in a stack register and sets the FPUDP. */
1291#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1292 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1293/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1294 * stack. */
1295#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1296 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1297
1298/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1299#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1300 iemFpuUpdateOpcodeAndIp(pVCpu)
1301/** Free a stack register (for FFREE and FFREEP). */
1302#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1303 iemFpuStackFree(pVCpu, a_iStReg)
1304/** Increment the FPU stack pointer. */
1305#define IEM_MC_FPU_STACK_INC_TOP() \
1306 iemFpuStackIncTop(pVCpu)
1307/** Decrement the FPU stack pointer. */
1308#define IEM_MC_FPU_STACK_DEC_TOP() \
1309 iemFpuStackDecTop(pVCpu)
1310
1311/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1312#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1313 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1314/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1315#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1316 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1317/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1318#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1319 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1320/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1321#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1322 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1323/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1324 * stack. */
1325#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1326 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1327/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1328#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1329 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1330
1331/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1332#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1333 iemFpuStackUnderflow(pVCpu, a_iStDst)
1334/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1335 * stack. */
1336#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1337 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1338/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1339 * FPUDS. */
1340#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1341 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1342/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1343 * FPUDS. Pops stack. */
1344#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1345 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1346/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1347 * stack twice. */
1348#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1349 iemFpuStackUnderflowThenPopPop(pVCpu)
1350/** Raises a FPU stack underflow exception for an instruction pushing a result
1351 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1352#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1353 iemFpuStackPushUnderflow(pVCpu)
1354/** Raises a FPU stack underflow exception for an instruction pushing a result
1355 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1356#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1357 iemFpuStackPushUnderflowTwo(pVCpu)
1358
1359/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1360 * FPUIP, FPUCS and FOP. */
1361#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1362 iemFpuStackPushOverflow(pVCpu)
1363/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1364 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1365#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1366 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1367/** Prepares for using the FPU state.
1368 * Ensures that we can use the host FPU in the current context (RC+R0.
1369 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1370#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1371/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1372#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1373/** Actualizes the guest FPU state so it can be accessed and modified. */
1374#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1375
1376/** Stores SSE SIMD result updating MXCSR. */
1377#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1378 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1379/** Updates MXCSR. */
1380#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1381 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1382
1383/** Prepares for using the SSE state.
1384 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1385 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1386#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1387/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1388#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1389/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1390#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1391
1392/** Prepares for using the AVX state.
1393 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1394 * Ensures the guest AVX state in the CPUMCTX is up to date.
1395 * @note This will include the AVX512 state too when support for it is added
1396 * due to the zero extending feature of VEX instruction. */
1397#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1398/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1399#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1400/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1401#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1402
1403/**
1404 * Calls a MMX assembly implementation taking two visible arguments.
1405 *
1406 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1407 * @param a0 The first extra argument.
1408 * @param a1 The second extra argument.
1409 */
1410#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1411 do { \
1412 IEM_MC_PREPARE_FPU_USAGE(); \
1413 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1414 } while (0)
1415
1416/**
1417 * Calls a MMX assembly implementation taking three visible arguments.
1418 *
1419 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1420 * @param a0 The first extra argument.
1421 * @param a1 The second extra argument.
1422 * @param a2 The third extra argument.
1423 */
1424#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1425 do { \
1426 IEM_MC_PREPARE_FPU_USAGE(); \
1427 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1428 } while (0)
1429
1430
1431/**
1432 * Calls a SSE assembly implementation taking two visible arguments.
1433 *
1434 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1435 * @param a0 The first extra argument.
1436 * @param a1 The second extra argument.
1437 */
1438#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1439 do { \
1440 IEM_MC_PREPARE_SSE_USAGE(); \
1441 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1442 } while (0)
1443
1444/**
1445 * Calls a SSE assembly implementation taking three visible arguments.
1446 *
1447 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1448 * @param a0 The first extra argument.
1449 * @param a1 The second extra argument.
1450 * @param a2 The third extra argument.
1451 */
1452#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1453 do { \
1454 IEM_MC_PREPARE_SSE_USAGE(); \
1455 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1456 } while (0)
1457
1458
1459/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1460 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1461#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1462 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1463
1464/**
1465 * Calls a AVX assembly implementation taking two visible arguments.
1466 *
1467 * There is one implicit zero'th argument, a pointer to the extended state.
1468 *
1469 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1470 * @param a1 The first extra argument.
1471 * @param a2 The second extra argument.
1472 */
1473#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1474 do { \
1475 IEM_MC_PREPARE_AVX_USAGE(); \
1476 a_pfnAImpl(pXState, (a1), (a2)); \
1477 } while (0)
1478
1479/**
1480 * Calls a AVX assembly implementation taking three visible arguments.
1481 *
1482 * There is one implicit zero'th argument, a pointer to the extended state.
1483 *
1484 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1485 * @param a1 The first extra argument.
1486 * @param a2 The second extra argument.
1487 * @param a3 The third extra argument.
1488 */
1489#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1490 do { \
1491 IEM_MC_PREPARE_AVX_USAGE(); \
1492 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1493 } while (0)
1494
1495/** @note Not for IOPL or IF testing. */
1496#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1497/** @note Not for IOPL or IF testing. */
1498#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1499/** @note Not for IOPL or IF testing. */
1500#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1501/** @note Not for IOPL or IF testing. */
1502#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1503/** @note Not for IOPL or IF testing. */
1504#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1505 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1506 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1507/** @note Not for IOPL or IF testing. */
1508#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1509 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1510 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1511/** @note Not for IOPL or IF testing. */
1512#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1513 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1514 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1515 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1516/** @note Not for IOPL or IF testing. */
1517#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1518 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1519 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1520 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1521#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1522#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1523#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1524/** @note Not for IOPL or IF testing. */
1525#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1526 if ( pVCpu->cpum.GstCtx.cx != 0 \
1527 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1528/** @note Not for IOPL or IF testing. */
1529#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1530 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1531 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1532/** @note Not for IOPL or IF testing. */
1533#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1534 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1535 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1536/** @note Not for IOPL or IF testing. */
1537#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1538 if ( pVCpu->cpum.GstCtx.cx != 0 \
1539 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1540/** @note Not for IOPL or IF testing. */
1541#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1542 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1543 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1544/** @note Not for IOPL or IF testing. */
1545#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1546 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1547 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1548#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1549#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1550
1551#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1552 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1553#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1554 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1555#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1556 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1557#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1558 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1559#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1560 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1561#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1562 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1563#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1564 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1565#define IEM_MC_IF_FCW_IM() \
1566 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1567#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1568 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1569 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1570
1571#define IEM_MC_ELSE() } else {
1572#define IEM_MC_ENDIF() } do {} while (0)
1573
1574/** @} */
1575
1576#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1577
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