VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 96652

Last change on this file since 96652 was 96652, checked in by vboxsync, 2 years ago

VMM/IEM: Implement [v]pclmulqdq instruction, ​bugref:9898
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1/* $Id: IEMMc.h 96652 2022-09-08 08:49:40Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44#define IEM_MC_PAUSE() do {} while (0)
45#define IEM_MC_CONTINUE() do {} while (0)
46
47/** Internal macro. */
48#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
49 do \
50 { \
51 VBOXSTRICTRC rcStrict2 = a_Expr; \
52 if (rcStrict2 != VINF_SUCCESS) \
53 return rcStrict2; \
54 } while (0)
55
56
57#define IEM_MC_ADVANCE_RIP() iemRegUpdateRipAndClearRF(pVCpu)
58#define IEM_MC_REL_JMP_S8(a_i8) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
59#define IEM_MC_REL_JMP_S16(a_i16) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
60#define IEM_MC_REL_JMP_S32(a_i32) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
61#define IEM_MC_SET_RIP_U16(a_u16NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
62#define IEM_MC_SET_RIP_U32(a_u32NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
63#define IEM_MC_SET_RIP_U64(a_u64NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
64#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
65#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
66 do { \
67 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
68 return iemRaiseDeviceNotAvailable(pVCpu); \
69 } while (0)
70#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
71 do { \
72 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
73 return iemRaiseDeviceNotAvailable(pVCpu); \
74 } while (0)
75#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
76 do { \
77 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
78 return iemRaiseMathFault(pVCpu); \
79 } while (0)
80#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
81 do { \
82 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
83 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
84 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
85 return iemRaiseUndefinedOpcode(pVCpu); \
86 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
87 return iemRaiseDeviceNotAvailable(pVCpu); \
88 } while (0)
89#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
90 do { \
91 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
92 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
93 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
94 return iemRaiseUndefinedOpcode(pVCpu); \
95 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
96 return iemRaiseDeviceNotAvailable(pVCpu); \
97 } while (0)
98#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
99 do { \
100 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
101 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
102 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
103 return iemRaiseUndefinedOpcode(pVCpu); \
104 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
105 return iemRaiseDeviceNotAvailable(pVCpu); \
106 } while (0)
107#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
108 do { \
109 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
110 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
111 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
112 return iemRaiseUndefinedOpcode(pVCpu); \
113 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
114 return iemRaiseDeviceNotAvailable(pVCpu); \
115 } while (0)
116#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
117 do { \
118 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
119 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
120 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
121 return iemRaiseUndefinedOpcode(pVCpu); \
122 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
123 return iemRaiseDeviceNotAvailable(pVCpu); \
124 } while (0)
125#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
126 do { \
127 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
128 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
129 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
130 return iemRaiseUndefinedOpcode(pVCpu); \
131 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
132 return iemRaiseDeviceNotAvailable(pVCpu); \
133 } while (0)
134#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
135 do { \
136 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
137 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
138 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
139 return iemRaiseUndefinedOpcode(pVCpu); \
140 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
141 return iemRaiseDeviceNotAvailable(pVCpu); \
142 } while (0)
143#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
144 do { \
145 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
146 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
147 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
148 return iemRaiseUndefinedOpcode(pVCpu); \
149 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
150 return iemRaiseDeviceNotAvailable(pVCpu); \
151 } while (0)
152#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
153 do { \
154 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
155 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
156 return iemRaiseUndefinedOpcode(pVCpu); \
157 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
158 return iemRaiseDeviceNotAvailable(pVCpu); \
159 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
160 return iemRaiseMathFault(pVCpu); \
161 } while (0)
162#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
163 do { \
164 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
165 || !(a_fSupported)) \
166 return iemRaiseUndefinedOpcode(pVCpu); \
167 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
168 return iemRaiseDeviceNotAvailable(pVCpu); \
169 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
170 return iemRaiseMathFault(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
173 do { \
174 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
175 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
176 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
177 return iemRaiseUndefinedOpcode(pVCpu); \
178 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
179 return iemRaiseDeviceNotAvailable(pVCpu); \
180 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
181 return iemRaiseMathFault(pVCpu); \
182 } while (0)
183#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
184 do { \
185 if (pVCpu->iem.s.uCpl != 0) \
186 return iemRaiseGeneralProtectionFault0(pVCpu); \
187 } while (0)
188#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
189 do { \
190 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
191 else return iemRaiseGeneralProtectionFault0(pVCpu); \
192 } while (0)
193#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
194 do { \
195 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
196 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
197 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
198 return iemRaiseUndefinedOpcode(pVCpu); \
199 } while (0)
200#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
201 do { \
202 if (!IEM_IS_CANONICAL(a_u64Addr)) \
203 return iemRaiseGeneralProtectionFault0(pVCpu); \
204 } while (0)
205#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
206 do { \
207 if (( ((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
208 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
209 { \
210 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
211 return iemRaiseSimdFpException(pVCpu); \
212 else \
213 return iemRaiseUndefinedOpcode(pVCpu); \
214 } \
215 } while (0)
216#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
217 do { \
218 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
219 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
220 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
221 return iemRaiseUndefinedOpcode(pVCpu); \
222 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
223 return iemRaiseDeviceNotAvailable(pVCpu); \
224 } while (0)
225
226
227#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
228#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
229#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
230#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
231#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
232#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
233#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
234 uint32_t a_Name; \
235 uint32_t *a_pName = &a_Name
236#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
237 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
238
239#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
240#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
241
242#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
243#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
244#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
245#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
246#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
247#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
248#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
249#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
250#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
251#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
252#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
253#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
254#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
255#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
256#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
257#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
258#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
259#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
260 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
261 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
262 } while (0)
263#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
264 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
265 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
266 } while (0)
267#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
268 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
269 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
270 } while (0)
271/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
272#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
273 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
274 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
275 } while (0)
276#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
277 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
278 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
279 } while (0)
280/** @note Not for IOPL or IF testing or modification. */
281#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
282#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
283#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
284#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
285
286#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
287#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
288#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
289#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
290#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
291#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
292#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
293#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
294#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
295#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
296/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
297#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
298 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
299 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
300 } while (0)
301#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
302 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
303 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
304 } while (0)
305#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
306 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
307
308
309#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
310#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
311/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
312 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
313#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
314#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
315/** @note Not for IOPL or IF testing or modification. */
316#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.u
317
318#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
319#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
320#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
321 do { \
322 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
323 *pu32Reg += (a_u32Value); \
324 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
325 } while (0)
326#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
327
328#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
329#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
330#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
331 do { \
332 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
333 *pu32Reg -= (a_u32Value); \
334 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
335 } while (0)
336#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
337#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
338
339#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
340#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
341#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
342#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
343#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
344#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
345#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
346
347#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
348#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
349#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
350#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
351
352#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
353#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
354#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
355
356#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
357#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
358#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
359
360#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
361#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
362#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
363
364#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
365#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
366#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
367
368#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
369
370#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
371
372#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
373#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
374#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
375 do { \
376 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
377 *pu32Reg &= (a_u32Value); \
378 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
379 } while (0)
380#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
381
382#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
383#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
384#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
385 do { \
386 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
387 *pu32Reg |= (a_u32Value); \
388 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
389 } while (0)
390#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
391
392
393/** @note Not for IOPL or IF modification. */
394#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
395/** @note Not for IOPL or IF modification. */
396#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
397/** @note Not for IOPL or IF modification. */
398#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
399
400#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
401
402/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
403#define IEM_MC_FPU_TO_MMX_MODE() do { \
404 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
405 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
406 } while (0)
407
408/** Switches the FPU state from MMX mode (FTW=0xffff). */
409#define IEM_MC_FPU_FROM_MMX_MODE() do { \
410 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
411 } while (0)
412
413#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
414 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
415#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
416 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
417#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
418 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
419 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
420 } while (0)
421#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
422 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
423 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
424 } while (0)
425#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
426 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
427#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
428 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
429#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
430 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
431#define IEM_MC_MODIFIED_MREG(a_iMReg) \
432 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
433#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
434 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
435
436#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
437 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
438 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
439 } while (0)
440#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
441 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
442#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
443 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
444#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
445 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
446#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
447 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
448 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
449 } while (0)
450#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
451 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
452#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
453 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
454 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
455 } while (0)
456#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
457 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
458#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
459 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
460 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
461 } while (0)
462#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
463 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
464#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
465 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
466#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
467 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
468#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
469 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
470#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
471 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
472#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
473 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
474#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
475 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
476#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
477 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
478 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
479 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
480 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
481 } while (0)
482
483#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
484 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
485 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
486 } while (0)
487#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
488 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
489 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
490 } while (0)
491#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
492 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
493 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
494 } while (0)
495#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
496 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
497 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
498 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
499 } while (0)
500#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
501 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
502 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
503 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
504 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
505 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
506 } while (0)
507
508#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
509#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
510 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
511 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
512 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
513 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
514 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
515 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
516 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
517 } while (0)
518#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
519 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
520 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
521 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
522 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
523 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
524 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
525 } while (0)
526#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
527 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
528 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
529 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
530 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
531 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
532 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
533 } while (0)
534#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
535 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
536 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
537 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
538 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
539 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
540 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
541 } while (0)
542
543#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
544 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
545#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
546 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
547#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
548 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
549#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
550 do { uintptr_t const iYRegTmp = (a_iYReg); \
551 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
552 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
553 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
554 } while (0)
555
556#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
557 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
558 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
559 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
560 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
561 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
562 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
563 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
564 } while (0)
565#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
566 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
567 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
568 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
569 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
570 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
571 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
572 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
573 } while (0)
574#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
575 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
576 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
577 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
578 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
579 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
580 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
581 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
582 } while (0)
583
584#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
585 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
586 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
587 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
588 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
589 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
590 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
591 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
592 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
593 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
594 } while (0)
595#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
596 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
597 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
598 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
599 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
600 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
601 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
602 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
603 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
604 } while (0)
605#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
606 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
607 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
608 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
609 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
610 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
611 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
612 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
613 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
614 } while (0)
615#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
616 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
617 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
618 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
619 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
620 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
621 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
622 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
623 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
624 } while (0)
625#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
626 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
627 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
628 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
629 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
630 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
631 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
632 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
633 } while (0)
634#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
635 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
636 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
637 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
638 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
639 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
640 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
641 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
642 } while (0)
643
644#ifndef IEM_WITH_SETJMP
645# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
646 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
647# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
648 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
649# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
650 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
651#else
652# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
653 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
654# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
655 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
656# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
657 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
658#endif
659
660#ifndef IEM_WITH_SETJMP
661# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
662 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
663# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
664 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
665# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
666 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
667#else
668# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
669 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
670# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
671 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
672# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
673 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
674#endif
675
676#ifndef IEM_WITH_SETJMP
677# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
678 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
679# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
680 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
681# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
682 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
683#else
684# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
685 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
686# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
687 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
688# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
689 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
690#endif
691
692#ifdef SOME_UNUSED_FUNCTION
693# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
694 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
695#endif
696
697#ifndef IEM_WITH_SETJMP
698# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
699 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
700# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
701 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
702# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
703 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
704# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
705 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
706#else
707# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
708 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
709# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
710 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
711# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
712 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
713# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
714 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
715#endif
716
717#ifndef IEM_WITH_SETJMP
718# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
719 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
720# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
721 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
722# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
723 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
724# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
725 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
726#else
727# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
728 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
729# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
730 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
731# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
732 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
733# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
734 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
735#endif
736
737#ifndef IEM_WITH_SETJMP
738# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
739 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
740# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
741 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
742# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
743 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
744
745# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
746 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
747# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
748 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
749# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
750 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
751#else
752# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
753 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
754# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
755 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
756# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
757 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
758
759# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
760 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
761# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
762 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
763# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
764 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
765#endif
766
767#ifndef IEM_WITH_SETJMP
768# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
769 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
770# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
771 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
772# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
773 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
774
775# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
776 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
777# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
778 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
779# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
780 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
781#else
782# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
783 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
784# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
785 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
786# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
787 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
788
789# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
790 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
791# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
792 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
793# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
794 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
795#endif
796
797
798
799#ifndef IEM_WITH_SETJMP
800# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
801 do { \
802 uint8_t u8Tmp; \
803 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
804 (a_u16Dst) = u8Tmp; \
805 } while (0)
806# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
807 do { \
808 uint8_t u8Tmp; \
809 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
810 (a_u32Dst) = u8Tmp; \
811 } while (0)
812# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
813 do { \
814 uint8_t u8Tmp; \
815 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
816 (a_u64Dst) = u8Tmp; \
817 } while (0)
818# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
819 do { \
820 uint16_t u16Tmp; \
821 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
822 (a_u32Dst) = u16Tmp; \
823 } while (0)
824# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
825 do { \
826 uint16_t u16Tmp; \
827 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
828 (a_u64Dst) = u16Tmp; \
829 } while (0)
830# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
831 do { \
832 uint32_t u32Tmp; \
833 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
834 (a_u64Dst) = u32Tmp; \
835 } while (0)
836#else /* IEM_WITH_SETJMP */
837# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
838 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
839# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
840 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
841# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
842 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
843# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
844 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
845# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
846 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
847# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
848 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
849#endif /* IEM_WITH_SETJMP */
850
851#ifndef IEM_WITH_SETJMP
852# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
853 do { \
854 uint8_t u8Tmp; \
855 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
856 (a_u16Dst) = (int8_t)u8Tmp; \
857 } while (0)
858# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
859 do { \
860 uint8_t u8Tmp; \
861 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
862 (a_u32Dst) = (int8_t)u8Tmp; \
863 } while (0)
864# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
865 do { \
866 uint8_t u8Tmp; \
867 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
868 (a_u64Dst) = (int8_t)u8Tmp; \
869 } while (0)
870# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
871 do { \
872 uint16_t u16Tmp; \
873 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
874 (a_u32Dst) = (int16_t)u16Tmp; \
875 } while (0)
876# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
877 do { \
878 uint16_t u16Tmp; \
879 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
880 (a_u64Dst) = (int16_t)u16Tmp; \
881 } while (0)
882# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
883 do { \
884 uint32_t u32Tmp; \
885 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
886 (a_u64Dst) = (int32_t)u32Tmp; \
887 } while (0)
888#else /* IEM_WITH_SETJMP */
889# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
890 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
891# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
892 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
893# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
894 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
895# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
896 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
897# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
898 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
899# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
900 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
901#endif /* IEM_WITH_SETJMP */
902
903#ifndef IEM_WITH_SETJMP
904# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
905 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
906# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
907 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
908# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
909 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
910# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
911 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
912#else
913# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
914 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
915# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
916 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
917# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
918 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
919# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
920 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
921#endif
922
923#ifndef IEM_WITH_SETJMP
924# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
925 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
926# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
927 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
928# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
929 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
930# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
931 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
932#else
933# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
934 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
935# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
936 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
937# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
938 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
939# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
940 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
941#endif
942
943#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
944#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
945#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
946#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
947#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
948#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
949#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
950 do { \
951 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
952 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
953 } while (0)
954#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
955 do { \
956 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
957 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
958 } while (0)
959
960#ifndef IEM_WITH_SETJMP
961# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
962 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
963# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
964 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
965#else
966# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
967 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
968# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
969 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
970#endif
971
972#ifndef IEM_WITH_SETJMP
973# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
974 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
975# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
976 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
977#else
978# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
979 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
980# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
981 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
982#endif
983
984
985#define IEM_MC_PUSH_U16(a_u16Value) \
986 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
987#define IEM_MC_PUSH_U32(a_u32Value) \
988 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
989#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
990 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
991#define IEM_MC_PUSH_U64(a_u64Value) \
992 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
993
994#define IEM_MC_POP_U16(a_pu16Value) \
995 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
996#define IEM_MC_POP_U32(a_pu32Value) \
997 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
998#define IEM_MC_POP_U64(a_pu64Value) \
999 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1000
1001/** Maps guest memory for direct or bounce buffered access.
1002 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1003 * @remarks May return.
1004 */
1005#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1006 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1007 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1008
1009/** Maps guest memory for direct or bounce buffered access.
1010 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1011 * @remarks May return.
1012 */
1013#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1014 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1015 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1016
1017/** Commits the memory and unmaps the guest memory.
1018 * @remarks May return.
1019 */
1020#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1021 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1022
1023/** Commits the memory and unmaps the guest memory unless the FPU status word
1024 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1025 * that would cause FLD not to store.
1026 *
1027 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1028 * store, while \#P will not.
1029 *
1030 * @remarks May in theory return - for now.
1031 */
1032#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1033 do { \
1034 if ( !(a_u16FSW & X86_FSW_ES) \
1035 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1036 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1037 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1038 } while (0)
1039
1040/** Calculate efficient address from R/M. */
1041#ifndef IEM_WITH_SETJMP
1042# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1043 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1044#else
1045# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1046 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1047#endif
1048
1049#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1050#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1051#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1052#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1053#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1054#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1055#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1056
1057/**
1058 * Defers the rest of the instruction emulation to a C implementation routine
1059 * and returns, only taking the standard parameters.
1060 *
1061 * @param a_pfnCImpl The pointer to the C routine.
1062 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1063 */
1064#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1065
1066/**
1067 * Defers the rest of instruction emulation to a C implementation routine and
1068 * returns, taking one argument in addition to the standard ones.
1069 *
1070 * @param a_pfnCImpl The pointer to the C routine.
1071 * @param a0 The argument.
1072 */
1073#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1074
1075/**
1076 * Defers the rest of the instruction emulation to a C implementation routine
1077 * and returns, taking two arguments in addition to the standard ones.
1078 *
1079 * @param a_pfnCImpl The pointer to the C routine.
1080 * @param a0 The first extra argument.
1081 * @param a1 The second extra argument.
1082 */
1083#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1084
1085/**
1086 * Defers the rest of the instruction emulation to a C implementation routine
1087 * and returns, taking three arguments in addition to the standard ones.
1088 *
1089 * @param a_pfnCImpl The pointer to the C routine.
1090 * @param a0 The first extra argument.
1091 * @param a1 The second extra argument.
1092 * @param a2 The third extra argument.
1093 */
1094#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1095
1096/**
1097 * Defers the rest of the instruction emulation to a C implementation routine
1098 * and returns, taking four arguments in addition to the standard ones.
1099 *
1100 * @param a_pfnCImpl The pointer to the C routine.
1101 * @param a0 The first extra argument.
1102 * @param a1 The second extra argument.
1103 * @param a2 The third extra argument.
1104 * @param a3 The fourth extra argument.
1105 */
1106#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1107
1108/**
1109 * Defers the rest of the instruction emulation to a C implementation routine
1110 * and returns, taking two arguments in addition to the standard ones.
1111 *
1112 * @param a_pfnCImpl The pointer to the C routine.
1113 * @param a0 The first extra argument.
1114 * @param a1 The second extra argument.
1115 * @param a2 The third extra argument.
1116 * @param a3 The fourth extra argument.
1117 * @param a4 The fifth extra argument.
1118 */
1119#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1120
1121/**
1122 * Defers the entire instruction emulation to a C implementation routine and
1123 * returns, only taking the standard parameters.
1124 *
1125 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1126 *
1127 * @param a_pfnCImpl The pointer to the C routine.
1128 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1129 */
1130#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1131
1132/**
1133 * Defers the entire instruction emulation to a C implementation routine and
1134 * returns, taking one argument in addition to the standard ones.
1135 *
1136 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1137 *
1138 * @param a_pfnCImpl The pointer to the C routine.
1139 * @param a0 The argument.
1140 */
1141#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1142
1143/**
1144 * Defers the entire instruction emulation to a C implementation routine and
1145 * returns, taking two arguments in addition to the standard ones.
1146 *
1147 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1148 *
1149 * @param a_pfnCImpl The pointer to the C routine.
1150 * @param a0 The first extra argument.
1151 * @param a1 The second extra argument.
1152 */
1153#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1154
1155/**
1156 * Defers the entire instruction emulation to a C implementation routine and
1157 * returns, taking three arguments in addition to the standard ones.
1158 *
1159 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1160 *
1161 * @param a_pfnCImpl The pointer to the C routine.
1162 * @param a0 The first extra argument.
1163 * @param a1 The second extra argument.
1164 * @param a2 The third extra argument.
1165 */
1166#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1167
1168/**
1169 * Calls a FPU assembly implementation taking one visible argument.
1170 *
1171 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1172 * @param a0 The first extra argument.
1173 */
1174#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1175 do { \
1176 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1177 } while (0)
1178
1179/**
1180 * Calls a FPU assembly implementation taking two visible arguments.
1181 *
1182 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1183 * @param a0 The first extra argument.
1184 * @param a1 The second extra argument.
1185 */
1186#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1187 do { \
1188 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1189 } while (0)
1190
1191/**
1192 * Calls a FPU assembly implementation taking three visible arguments.
1193 *
1194 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1195 * @param a0 The first extra argument.
1196 * @param a1 The second extra argument.
1197 * @param a2 The third extra argument.
1198 */
1199#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1200 do { \
1201 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1202 } while (0)
1203
1204#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1205 do { \
1206 (a_FpuData).FSW = (a_FSW); \
1207 (a_FpuData).r80Result = *(a_pr80Value); \
1208 } while (0)
1209
1210/** Pushes FPU result onto the stack. */
1211#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1212 iemFpuPushResult(pVCpu, &a_FpuData)
1213/** Pushes FPU result onto the stack and sets the FPUDP. */
1214#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1215 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1216
1217/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1218#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1219 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1220
1221/** Stores FPU result in a stack register. */
1222#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1223 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1224/** Stores FPU result in a stack register and pops the stack. */
1225#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1226 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1227/** Stores FPU result in a stack register and sets the FPUDP. */
1228#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1229 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1230/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1231 * stack. */
1232#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1233 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1234
1235/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1236#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1237 iemFpuUpdateOpcodeAndIp(pVCpu)
1238/** Free a stack register (for FFREE and FFREEP). */
1239#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1240 iemFpuStackFree(pVCpu, a_iStReg)
1241/** Increment the FPU stack pointer. */
1242#define IEM_MC_FPU_STACK_INC_TOP() \
1243 iemFpuStackIncTop(pVCpu)
1244/** Decrement the FPU stack pointer. */
1245#define IEM_MC_FPU_STACK_DEC_TOP() \
1246 iemFpuStackDecTop(pVCpu)
1247
1248/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1249#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1250 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1251/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1252#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1253 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1254/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1255#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1256 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1257/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1258#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1259 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1260/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1261 * stack. */
1262#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1263 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1264/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1265#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1266 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1267
1268/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1269#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1270 iemFpuStackUnderflow(pVCpu, a_iStDst)
1271/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1272 * stack. */
1273#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1274 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1275/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1276 * FPUDS. */
1277#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1278 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1279/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1280 * FPUDS. Pops stack. */
1281#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1282 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1283/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1284 * stack twice. */
1285#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1286 iemFpuStackUnderflowThenPopPop(pVCpu)
1287/** Raises a FPU stack underflow exception for an instruction pushing a result
1288 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1289#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1290 iemFpuStackPushUnderflow(pVCpu)
1291/** Raises a FPU stack underflow exception for an instruction pushing a result
1292 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1293#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1294 iemFpuStackPushUnderflowTwo(pVCpu)
1295
1296/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1297 * FPUIP, FPUCS and FOP. */
1298#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1299 iemFpuStackPushOverflow(pVCpu)
1300/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1301 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1302#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1303 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1304/** Prepares for using the FPU state.
1305 * Ensures that we can use the host FPU in the current context (RC+R0.
1306 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1307#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1308/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1309#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1310/** Actualizes the guest FPU state so it can be accessed and modified. */
1311#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1312
1313/** Stores SSE SIMD result in a stack register. */
1314#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1315 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1316/** Prepares for using the SSE state.
1317 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1318 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1319#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1320/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1321#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1322/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1323#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1324
1325/** Prepares for using the AVX state.
1326 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1327 * Ensures the guest AVX state in the CPUMCTX is up to date.
1328 * @note This will include the AVX512 state too when support for it is added
1329 * due to the zero extending feature of VEX instruction. */
1330#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1331/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1332#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1333/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1334#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1335
1336/**
1337 * Calls a MMX assembly implementation taking two visible arguments.
1338 *
1339 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1340 * @param a0 The first extra argument.
1341 * @param a1 The second extra argument.
1342 */
1343#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1344 do { \
1345 IEM_MC_PREPARE_FPU_USAGE(); \
1346 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1347 } while (0)
1348
1349/**
1350 * Calls a MMX assembly implementation taking three visible arguments.
1351 *
1352 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1353 * @param a0 The first extra argument.
1354 * @param a1 The second extra argument.
1355 * @param a2 The third extra argument.
1356 */
1357#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1358 do { \
1359 IEM_MC_PREPARE_FPU_USAGE(); \
1360 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1361 } while (0)
1362
1363
1364/**
1365 * Calls a SSE assembly implementation taking two visible arguments.
1366 *
1367 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1368 * @param a0 The first extra argument.
1369 * @param a1 The second extra argument.
1370 */
1371#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1372 do { \
1373 IEM_MC_PREPARE_SSE_USAGE(); \
1374 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1375 } while (0)
1376
1377/**
1378 * Calls a SSE assembly implementation taking three visible arguments.
1379 *
1380 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1381 * @param a0 The first extra argument.
1382 * @param a1 The second extra argument.
1383 * @param a2 The third extra argument.
1384 */
1385#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1386 do { \
1387 IEM_MC_PREPARE_SSE_USAGE(); \
1388 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1389 } while (0)
1390
1391
1392/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1393 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1394#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1395 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1396
1397/**
1398 * Calls a AVX assembly implementation taking two visible arguments.
1399 *
1400 * There is one implicit zero'th argument, a pointer to the extended state.
1401 *
1402 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1403 * @param a1 The first extra argument.
1404 * @param a2 The second extra argument.
1405 */
1406#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1407 do { \
1408 IEM_MC_PREPARE_AVX_USAGE(); \
1409 a_pfnAImpl(pXState, (a1), (a2)); \
1410 } while (0)
1411
1412/**
1413 * Calls a AVX assembly implementation taking three visible arguments.
1414 *
1415 * There is one implicit zero'th argument, a pointer to the extended state.
1416 *
1417 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1418 * @param a1 The first extra argument.
1419 * @param a2 The second extra argument.
1420 * @param a3 The third extra argument.
1421 */
1422#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1423 do { \
1424 IEM_MC_PREPARE_AVX_USAGE(); \
1425 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1426 } while (0)
1427
1428/** @note Not for IOPL or IF testing. */
1429#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1430/** @note Not for IOPL or IF testing. */
1431#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1432/** @note Not for IOPL or IF testing. */
1433#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1434/** @note Not for IOPL or IF testing. */
1435#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1436/** @note Not for IOPL or IF testing. */
1437#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1438 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1439 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1440/** @note Not for IOPL or IF testing. */
1441#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1442 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1443 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1444/** @note Not for IOPL or IF testing. */
1445#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1446 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1447 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1448 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1449/** @note Not for IOPL or IF testing. */
1450#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1451 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1452 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1453 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1454#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1455#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1456#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1457/** @note Not for IOPL or IF testing. */
1458#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1459 if ( pVCpu->cpum.GstCtx.cx != 0 \
1460 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1461/** @note Not for IOPL or IF testing. */
1462#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1463 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1464 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1465/** @note Not for IOPL or IF testing. */
1466#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1467 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1468 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1469/** @note Not for IOPL or IF testing. */
1470#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1471 if ( pVCpu->cpum.GstCtx.cx != 0 \
1472 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1473/** @note Not for IOPL or IF testing. */
1474#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1475 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1476 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1477/** @note Not for IOPL or IF testing. */
1478#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1479 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1480 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1481#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1482#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1483
1484#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1485 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1486#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1487 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1488#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1489 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1490#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1491 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1492#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1493 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1494#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1495 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1496#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1497 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1498#define IEM_MC_IF_FCW_IM() \
1499 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1500
1501#define IEM_MC_ELSE() } else {
1502#define IEM_MC_ENDIF() } do {} while (0)
1503
1504/** @} */
1505
1506#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1507
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