VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 97405

Last change on this file since 97405 was 97370, checked in by vboxsync, 2 years ago

VMM/IEM: iemRegAddToRipAndClearRF -> iemRegUpdateRipAndFinishClearingRF and made callers use the return code. bugref:9898
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1/* $Id: IEMMc.h 97370 2022-11-02 00:53:30Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegUpdateRipAndFinishClearingRF(pVCpu)
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) return iemRegRipRelativeJumpS8(pVCpu, (a_i8))
60/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
61#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) return iemRegRipRelativeJumpS16(pVCpu, (a_i16))
62/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
63#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) return iemRegRipRelativeJumpS32(pVCpu, (a_i32))
64/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
65#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJump((pVCpu), (a_u16NewIP))
66/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
67#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJump((pVCpu), (a_u32NewIP))
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJump((pVCpu), (a_u64NewIP))
70
71#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
72#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
73 do { \
74 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
75 return iemRaiseDeviceNotAvailable(pVCpu); \
76 } while (0)
77#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
78 do { \
79 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
80 return iemRaiseDeviceNotAvailable(pVCpu); \
81 } while (0)
82#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
83 do { \
84 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
85 return iemRaiseMathFault(pVCpu); \
86 } while (0)
87#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
88 do { \
89 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
90 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
91 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
92 return iemRaiseUndefinedOpcode(pVCpu); \
93 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
94 return iemRaiseDeviceNotAvailable(pVCpu); \
95 } while (0)
96#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
97 do { \
98 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
99 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
100 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
101 return iemRaiseUndefinedOpcode(pVCpu); \
102 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
103 return iemRaiseDeviceNotAvailable(pVCpu); \
104 } while (0)
105#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
106 do { \
107 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
108 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
109 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAesNi) \
110 return iemRaiseUndefinedOpcode(pVCpu); \
111 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
112 return iemRaiseDeviceNotAvailable(pVCpu); \
113 } while (0)
114#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
115 do { \
116 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
117 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
118 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
119 return iemRaiseUndefinedOpcode(pVCpu); \
120 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
121 return iemRaiseDeviceNotAvailable(pVCpu); \
122 } while (0)
123#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
124 do { \
125 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
126 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
127 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
128 return iemRaiseUndefinedOpcode(pVCpu); \
129 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
130 return iemRaiseDeviceNotAvailable(pVCpu); \
131 } while (0)
132#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
133 do { \
134 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
135 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
136 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
137 return iemRaiseUndefinedOpcode(pVCpu); \
138 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
139 return iemRaiseDeviceNotAvailable(pVCpu); \
140 } while (0)
141#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
142 do { \
143 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
144 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
145 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
146 return iemRaiseUndefinedOpcode(pVCpu); \
147 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
148 return iemRaiseDeviceNotAvailable(pVCpu); \
149 } while (0)
150#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
151 do { \
152 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
153 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
154 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
155 return iemRaiseUndefinedOpcode(pVCpu); \
156 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
157 return iemRaiseDeviceNotAvailable(pVCpu); \
158 } while (0)
159#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
160 do { \
161 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
162 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
163 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
164 return iemRaiseUndefinedOpcode(pVCpu); \
165 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
166 return iemRaiseDeviceNotAvailable(pVCpu); \
167 } while (0)
168#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
169 do { \
170 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
171 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
172 return iemRaiseUndefinedOpcode(pVCpu); \
173 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
174 return iemRaiseDeviceNotAvailable(pVCpu); \
175 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
176 return iemRaiseMathFault(pVCpu); \
177 } while (0)
178#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
179 do { \
180 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
181 || !(a_fSupported)) \
182 return iemRaiseUndefinedOpcode(pVCpu); \
183 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
184 return iemRaiseDeviceNotAvailable(pVCpu); \
185 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
186 return iemRaiseMathFault(pVCpu); \
187 } while (0)
188#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
189 do { \
190 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
191 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
192 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
193 return iemRaiseUndefinedOpcode(pVCpu); \
194 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
195 return iemRaiseDeviceNotAvailable(pVCpu); \
196 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
197 return iemRaiseMathFault(pVCpu); \
198 } while (0)
199#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
200 do { \
201 if (pVCpu->iem.s.uCpl != 0) \
202 return iemRaiseGeneralProtectionFault0(pVCpu); \
203 } while (0)
204#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
205 do { \
206 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
207 else return iemRaiseGeneralProtectionFault0(pVCpu); \
208 } while (0)
209#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
210 do { \
211 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
212 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
213 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
214 return iemRaiseUndefinedOpcode(pVCpu); \
215 } while (0)
216#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
217 do { \
218 if (!IEM_IS_CANONICAL(a_u64Addr)) \
219 return iemRaiseGeneralProtectionFault0(pVCpu); \
220 } while (0)
221#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
222 do { \
223 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
224 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
225 { \
226 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
227 return iemRaiseSimdFpException(pVCpu); \
228 else \
229 return iemRaiseUndefinedOpcode(pVCpu); \
230 } \
231 } while (0)
232#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
233 do { \
234 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
235 return iemRaiseSimdFpException(pVCpu); \
236 else \
237 return iemRaiseUndefinedOpcode(pVCpu); \
238 } while (0)
239#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
240 do { \
241 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
242 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
243 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
244 return iemRaiseUndefinedOpcode(pVCpu); \
245 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
246 return iemRaiseDeviceNotAvailable(pVCpu); \
247 } while (0)
248
249
250#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
251#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
252#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
253#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
254#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
255#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
256#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
257 uint32_t a_Name; \
258 uint32_t *a_pName = &a_Name
259#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
260 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
261
262#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
263#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
264
265#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
266#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
267#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
268#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
269#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
270#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
271#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
272#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
273#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
274#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
275#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
276#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
277#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
278#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
279#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
280#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
281#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
282#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
283 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
284 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
285 } while (0)
286#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
287 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
288 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
289 } while (0)
290#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
291 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
292 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
293 } while (0)
294/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
295#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
296 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
297 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
298 } while (0)
299#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
300 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
301 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
302 } while (0)
303/** @note Not for IOPL or IF testing or modification. */
304#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
305#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
306#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
307#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
308
309#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
310#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
311#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
312#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
313#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
314#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
315#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
316#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
317#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
318#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
319#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
320/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
321#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
322 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
323 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
324 } while (0)
325#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
326 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
327 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
328 } while (0)
329#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
330 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
331
332
333#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
334#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
335/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
336 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
337#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
338#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
339#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
340#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
341#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
342#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
343/** @note Not for IOPL or IF testing or modification.
344 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
345#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
346#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
347
348#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
349#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
350#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
351 do { \
352 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
353 *pu32Reg += (a_u32Value); \
354 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
355 } while (0)
356#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
357
358#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
359#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
360#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
361 do { \
362 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
363 *pu32Reg -= (a_u32Value); \
364 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
365 } while (0)
366#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
367#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
368
369#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
370#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
371#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
372#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
373#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
374#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
375#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
376
377#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
378#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
379#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
380#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
381
382#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
383#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
384#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
385
386#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
387#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
388#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
389
390#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
391#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
392#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
393
394#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
395#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
396#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
397
398#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
399
400#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
401
402#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
403#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
404#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
405 do { \
406 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
407 *pu32Reg &= (a_u32Value); \
408 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
409 } while (0)
410#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
411
412#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
413#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
414#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
415 do { \
416 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
417 *pu32Reg |= (a_u32Value); \
418 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
419 } while (0)
420#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
421
422
423/** @note Not for IOPL or IF modification. */
424#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
425/** @note Not for IOPL or IF modification. */
426#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
427/** @note Not for IOPL or IF modification. */
428#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
429
430#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
431
432/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
433#define IEM_MC_FPU_TO_MMX_MODE() do { \
434 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
435 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
436 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
437 } while (0)
438
439/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
440#define IEM_MC_FPU_FROM_MMX_MODE() do { \
441 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
442 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
443 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
444 } while (0)
445
446#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
447 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
448#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
449 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
450#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
451 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
452 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
453 } while (0)
454#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
455 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
456 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
457 } while (0)
458#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
459 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
460#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
461 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
462#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
463 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
464#define IEM_MC_MODIFIED_MREG(a_iMReg) \
465 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
466#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
467 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
468
469#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
470 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
471 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
472 } while (0)
473#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
474 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
475 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
476 } while (0)
477#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
478 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
479#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
480 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
481#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
482 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
483#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
484 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
485 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
486 } while (0)
487#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
488 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
489 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
490 } while (0)
491#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
492 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
493#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
494 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
495#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
496 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
497#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
498 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
499 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
500 } while (0)
501#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
502 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
503#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
504 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
505#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
506 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
507#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
508 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
509 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
510 } while (0)
511#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
512 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
513#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
514 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
515#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
516 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
517#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
518 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
519#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
520 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
521#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
522 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
523#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
524 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
525#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
526 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
527#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
528 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
529 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
530 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
531 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
532 } while (0)
533
534#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
535 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
536 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
537 } while (0)
538#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
539 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
540 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
541 } while (0)
542#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
543 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
544 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
545 } while (0)
546#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
547 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
548 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
549 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
550 } while (0)
551#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
552 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
553 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
554 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
555 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
556 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
557 } while (0)
558
559#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
560#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
561 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
562 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
563 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
564 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
565 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
566 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
567 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
568 } while (0)
569#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
570 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
571 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
572 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
573 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
574 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
575 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
576 } while (0)
577#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
578 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
579 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
580 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
581 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
582 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
583 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
584 } while (0)
585#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
586 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
587 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
588 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
589 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
590 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
591 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
592 } while (0)
593
594#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
595 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
596#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
597 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
598#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
599 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
600#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
601 do { uintptr_t const iYRegTmp = (a_iYReg); \
602 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
603 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
604 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
605 } while (0)
606
607#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
608 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
609 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
610 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
611 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
612 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
613 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
614 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
615 } while (0)
616#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
617 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
618 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
619 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
620 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
621 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
622 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
623 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
624 } while (0)
625#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
626 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
627 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
628 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
629 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
630 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
631 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
632 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
633 } while (0)
634
635#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
636 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
637 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
638 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
639 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
640 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
641 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
642 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
643 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
644 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
645 } while (0)
646#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
647 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
648 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
649 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
650 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
651 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
652 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
653 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
654 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
655 } while (0)
656#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
657 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
658 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
659 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
660 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
661 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
662 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
663 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
664 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
665 } while (0)
666#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
667 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
668 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
669 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
670 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
671 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
672 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
673 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
674 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
675 } while (0)
676#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
677 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
678 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
679 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
680 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
681 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
682 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
683 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
684 } while (0)
685#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
686 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
687 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
688 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
689 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
690 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
691 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
692 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
693 } while (0)
694
695#ifndef IEM_WITH_SETJMP
696# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
697 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
698# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
699 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
700# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
701 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
702#else
703# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
704 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
705# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
706 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
707# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
708 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
709#endif
710
711#ifndef IEM_WITH_SETJMP
712# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
713 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
714# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
715 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
716# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
717 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
718#else
719# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
720 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
721# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
722 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
723# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
724 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
725#endif
726
727#ifndef IEM_WITH_SETJMP
728# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
729 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
730# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
731 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
732# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
733 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
734#else
735# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
736 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
737# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
738 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
739# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
740 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
741#endif
742
743#ifdef SOME_UNUSED_FUNCTION
744# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
745 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
746#endif
747
748#ifndef IEM_WITH_SETJMP
749# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
750 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
751# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
752 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
753# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
754 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
755# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
756 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
757#else
758# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
759 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
760# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
761 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
762# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
763 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
764# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
765 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
766#endif
767
768#ifndef IEM_WITH_SETJMP
769# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
770 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
771# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
772 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
773# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
774 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
775# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
776 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
777#else
778# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
779 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
780# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
781 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
782# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
783 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
784# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
785 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
786#endif
787
788#ifndef IEM_WITH_SETJMP
789# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
790 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
791# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
792 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
793# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
794 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
795
796# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
797 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
798# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
799 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
800# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
801 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
802# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
803 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
804# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
805 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
806#else
807# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
808 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
809# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
810 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
811# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
812 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
813
814# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
815 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
816# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
817 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
818# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
819 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
820# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
821 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
822# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
823 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
824#endif
825
826#ifndef IEM_WITH_SETJMP
827# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
828 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
829# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
830 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
831# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
832 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
833
834# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
835 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
836# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
837 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
838# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
839 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
840#else
841# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
842 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
843# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
844 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
845# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
846 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
847
848# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
849 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
850# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
851 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
852# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
853 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
854#endif
855
856
857
858#ifndef IEM_WITH_SETJMP
859# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
860 do { \
861 uint8_t u8Tmp; \
862 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
863 (a_u16Dst) = u8Tmp; \
864 } while (0)
865# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
866 do { \
867 uint8_t u8Tmp; \
868 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
869 (a_u32Dst) = u8Tmp; \
870 } while (0)
871# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
872 do { \
873 uint8_t u8Tmp; \
874 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
875 (a_u64Dst) = u8Tmp; \
876 } while (0)
877# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
878 do { \
879 uint16_t u16Tmp; \
880 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
881 (a_u32Dst) = u16Tmp; \
882 } while (0)
883# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
884 do { \
885 uint16_t u16Tmp; \
886 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
887 (a_u64Dst) = u16Tmp; \
888 } while (0)
889# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
890 do { \
891 uint32_t u32Tmp; \
892 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
893 (a_u64Dst) = u32Tmp; \
894 } while (0)
895#else /* IEM_WITH_SETJMP */
896# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
897 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
898# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
899 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
900# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
901 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
902# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
903 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
904# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
905 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
906# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
907 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
908#endif /* IEM_WITH_SETJMP */
909
910#ifndef IEM_WITH_SETJMP
911# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
912 do { \
913 uint8_t u8Tmp; \
914 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
915 (a_u16Dst) = (int8_t)u8Tmp; \
916 } while (0)
917# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
918 do { \
919 uint8_t u8Tmp; \
920 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
921 (a_u32Dst) = (int8_t)u8Tmp; \
922 } while (0)
923# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
924 do { \
925 uint8_t u8Tmp; \
926 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
927 (a_u64Dst) = (int8_t)u8Tmp; \
928 } while (0)
929# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
930 do { \
931 uint16_t u16Tmp; \
932 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
933 (a_u32Dst) = (int16_t)u16Tmp; \
934 } while (0)
935# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
936 do { \
937 uint16_t u16Tmp; \
938 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
939 (a_u64Dst) = (int16_t)u16Tmp; \
940 } while (0)
941# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
942 do { \
943 uint32_t u32Tmp; \
944 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
945 (a_u64Dst) = (int32_t)u32Tmp; \
946 } while (0)
947#else /* IEM_WITH_SETJMP */
948# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
949 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
950# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
951 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
952# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
953 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
954# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
955 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
956# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
957 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
958# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
959 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
960#endif /* IEM_WITH_SETJMP */
961
962#ifndef IEM_WITH_SETJMP
963# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
964 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
965# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
966 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
967# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
968 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
969# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
970 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
971#else
972# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
973 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
974# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
975 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
976# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
977 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
978# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
979 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
980#endif
981
982#ifndef IEM_WITH_SETJMP
983# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
984 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
985# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
986 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
987# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
988 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
989# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
990 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
991#else
992# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
993 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
994# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
995 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
996# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
997 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
998# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
999 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1000#endif
1001
1002#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1003#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1004#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1005#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1006#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1007#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1008#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1009 do { \
1010 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1011 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1012 } while (0)
1013#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1014 do { \
1015 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1016 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1017 } while (0)
1018
1019#ifndef IEM_WITH_SETJMP
1020# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1021 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1022# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1023 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1024#else
1025# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1026 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1027# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1028 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1029#endif
1030
1031#ifndef IEM_WITH_SETJMP
1032# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1033 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1034# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1035 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1036#else
1037# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1038 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1039# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1040 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1041#endif
1042
1043
1044#define IEM_MC_PUSH_U16(a_u16Value) \
1045 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1046#define IEM_MC_PUSH_U32(a_u32Value) \
1047 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1048#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1049 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1050#define IEM_MC_PUSH_U64(a_u64Value) \
1051 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1052
1053#define IEM_MC_POP_U16(a_pu16Value) \
1054 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1055#define IEM_MC_POP_U32(a_pu32Value) \
1056 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1057#define IEM_MC_POP_U64(a_pu64Value) \
1058 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1059
1060/** Maps guest memory for direct or bounce buffered access.
1061 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1062 * @remarks May return.
1063 */
1064#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1065 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1066 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1067
1068/** Maps guest memory for direct or bounce buffered access.
1069 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1070 * @remarks May return.
1071 */
1072#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1073 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1074 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1075
1076/** Commits the memory and unmaps the guest memory.
1077 * @remarks May return.
1078 */
1079#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1080 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1081
1082/** Commits the memory and unmaps the guest memory unless the FPU status word
1083 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1084 * that would cause FLD not to store.
1085 *
1086 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1087 * store, while \#P will not.
1088 *
1089 * @remarks May in theory return - for now.
1090 */
1091#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1092 do { \
1093 if ( !(a_u16FSW & X86_FSW_ES) \
1094 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1095 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1096 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1097 } while (0)
1098
1099/** Calculate efficient address from R/M. */
1100#ifndef IEM_WITH_SETJMP
1101# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1102 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1103#else
1104# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1105 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1106#endif
1107
1108#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1109#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1110#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1111#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1112#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1113#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1114#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1115
1116/**
1117 * Defers the rest of the instruction emulation to a C implementation routine
1118 * and returns, only taking the standard parameters.
1119 *
1120 * @param a_pfnCImpl The pointer to the C routine.
1121 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1122 */
1123#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1124
1125/**
1126 * Defers the rest of instruction emulation to a C implementation routine and
1127 * returns, taking one argument in addition to the standard ones.
1128 *
1129 * @param a_pfnCImpl The pointer to the C routine.
1130 * @param a0 The argument.
1131 */
1132#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1133
1134/**
1135 * Defers the rest of the instruction emulation to a C implementation routine
1136 * and returns, taking two arguments in addition to the standard ones.
1137 *
1138 * @param a_pfnCImpl The pointer to the C routine.
1139 * @param a0 The first extra argument.
1140 * @param a1 The second extra argument.
1141 */
1142#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1143
1144/**
1145 * Defers the rest of the instruction emulation to a C implementation routine
1146 * and returns, taking three arguments in addition to the standard ones.
1147 *
1148 * @param a_pfnCImpl The pointer to the C routine.
1149 * @param a0 The first extra argument.
1150 * @param a1 The second extra argument.
1151 * @param a2 The third extra argument.
1152 */
1153#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1154
1155/**
1156 * Defers the rest of the instruction emulation to a C implementation routine
1157 * and returns, taking four arguments in addition to the standard ones.
1158 *
1159 * @param a_pfnCImpl The pointer to the C routine.
1160 * @param a0 The first extra argument.
1161 * @param a1 The second extra argument.
1162 * @param a2 The third extra argument.
1163 * @param a3 The fourth extra argument.
1164 */
1165#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1166
1167/**
1168 * Defers the rest of the instruction emulation to a C implementation routine
1169 * and returns, taking two arguments in addition to the standard ones.
1170 *
1171 * @param a_pfnCImpl The pointer to the C routine.
1172 * @param a0 The first extra argument.
1173 * @param a1 The second extra argument.
1174 * @param a2 The third extra argument.
1175 * @param a3 The fourth extra argument.
1176 * @param a4 The fifth extra argument.
1177 */
1178#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1179
1180/**
1181 * Defers the entire instruction emulation to a C implementation routine and
1182 * returns, only taking the standard parameters.
1183 *
1184 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1185 *
1186 * @param a_pfnCImpl The pointer to the C routine.
1187 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1188 */
1189#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1190
1191/**
1192 * Defers the entire instruction emulation to a C implementation routine and
1193 * returns, taking one argument in addition to the standard ones.
1194 *
1195 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1196 *
1197 * @param a_pfnCImpl The pointer to the C routine.
1198 * @param a0 The argument.
1199 */
1200#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1201
1202/**
1203 * Defers the entire instruction emulation to a C implementation routine and
1204 * returns, taking two arguments in addition to the standard ones.
1205 *
1206 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1207 *
1208 * @param a_pfnCImpl The pointer to the C routine.
1209 * @param a0 The first extra argument.
1210 * @param a1 The second extra argument.
1211 */
1212#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1213
1214/**
1215 * Defers the entire instruction emulation to a C implementation routine and
1216 * returns, taking three arguments in addition to the standard ones.
1217 *
1218 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1219 *
1220 * @param a_pfnCImpl The pointer to the C routine.
1221 * @param a0 The first extra argument.
1222 * @param a1 The second extra argument.
1223 * @param a2 The third extra argument.
1224 */
1225#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1226
1227/**
1228 * Calls a FPU assembly implementation taking one visible argument.
1229 *
1230 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1231 * @param a0 The first extra argument.
1232 */
1233#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1234 do { \
1235 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1236 } while (0)
1237
1238/**
1239 * Calls a FPU assembly implementation taking two visible arguments.
1240 *
1241 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1242 * @param a0 The first extra argument.
1243 * @param a1 The second extra argument.
1244 */
1245#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1246 do { \
1247 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1248 } while (0)
1249
1250/**
1251 * Calls a FPU assembly implementation taking three visible arguments.
1252 *
1253 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1254 * @param a0 The first extra argument.
1255 * @param a1 The second extra argument.
1256 * @param a2 The third extra argument.
1257 */
1258#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1259 do { \
1260 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1261 } while (0)
1262
1263#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1264 do { \
1265 (a_FpuData).FSW = (a_FSW); \
1266 (a_FpuData).r80Result = *(a_pr80Value); \
1267 } while (0)
1268
1269/** Pushes FPU result onto the stack. */
1270#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1271 iemFpuPushResult(pVCpu, &a_FpuData)
1272/** Pushes FPU result onto the stack and sets the FPUDP. */
1273#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1274 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1275
1276/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1277#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1278 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1279
1280/** Stores FPU result in a stack register. */
1281#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1282 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1283/** Stores FPU result in a stack register and pops the stack. */
1284#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1285 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1286/** Stores FPU result in a stack register and sets the FPUDP. */
1287#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1288 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1289/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1290 * stack. */
1291#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1292 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1293
1294/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1295#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1296 iemFpuUpdateOpcodeAndIp(pVCpu)
1297/** Free a stack register (for FFREE and FFREEP). */
1298#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1299 iemFpuStackFree(pVCpu, a_iStReg)
1300/** Increment the FPU stack pointer. */
1301#define IEM_MC_FPU_STACK_INC_TOP() \
1302 iemFpuStackIncTop(pVCpu)
1303/** Decrement the FPU stack pointer. */
1304#define IEM_MC_FPU_STACK_DEC_TOP() \
1305 iemFpuStackDecTop(pVCpu)
1306
1307/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1308#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1309 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1310/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1311#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1312 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1313/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1314#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1315 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1316/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1317#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1318 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1319/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1320 * stack. */
1321#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1322 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1323/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1324#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1325 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1326
1327/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1328#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1329 iemFpuStackUnderflow(pVCpu, a_iStDst)
1330/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1331 * stack. */
1332#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1333 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1334/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1335 * FPUDS. */
1336#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1337 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1338/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1339 * FPUDS. Pops stack. */
1340#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1341 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1342/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1343 * stack twice. */
1344#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1345 iemFpuStackUnderflowThenPopPop(pVCpu)
1346/** Raises a FPU stack underflow exception for an instruction pushing a result
1347 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1348#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1349 iemFpuStackPushUnderflow(pVCpu)
1350/** Raises a FPU stack underflow exception for an instruction pushing a result
1351 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1352#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1353 iemFpuStackPushUnderflowTwo(pVCpu)
1354
1355/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1356 * FPUIP, FPUCS and FOP. */
1357#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1358 iemFpuStackPushOverflow(pVCpu)
1359/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1360 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1361#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1362 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1363/** Prepares for using the FPU state.
1364 * Ensures that we can use the host FPU in the current context (RC+R0.
1365 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1366#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1367/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1368#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1369/** Actualizes the guest FPU state so it can be accessed and modified. */
1370#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1371
1372/** Stores SSE SIMD result updating MXCSR. */
1373#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1374 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1375/** Updates MXCSR. */
1376#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1377 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1378
1379/** Prepares for using the SSE state.
1380 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1381 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1382#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1383/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1384#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1385/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1386#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1387
1388/** Prepares for using the AVX state.
1389 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1390 * Ensures the guest AVX state in the CPUMCTX is up to date.
1391 * @note This will include the AVX512 state too when support for it is added
1392 * due to the zero extending feature of VEX instruction. */
1393#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1394/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1395#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1396/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1397#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1398
1399/**
1400 * Calls a MMX assembly implementation taking two visible arguments.
1401 *
1402 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1403 * @param a0 The first extra argument.
1404 * @param a1 The second extra argument.
1405 */
1406#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1407 do { \
1408 IEM_MC_PREPARE_FPU_USAGE(); \
1409 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1410 } while (0)
1411
1412/**
1413 * Calls a MMX assembly implementation taking three visible arguments.
1414 *
1415 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1416 * @param a0 The first extra argument.
1417 * @param a1 The second extra argument.
1418 * @param a2 The third extra argument.
1419 */
1420#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1421 do { \
1422 IEM_MC_PREPARE_FPU_USAGE(); \
1423 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1424 } while (0)
1425
1426
1427/**
1428 * Calls a SSE assembly implementation taking two visible arguments.
1429 *
1430 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1431 * @param a0 The first extra argument.
1432 * @param a1 The second extra argument.
1433 */
1434#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1435 do { \
1436 IEM_MC_PREPARE_SSE_USAGE(); \
1437 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1438 } while (0)
1439
1440/**
1441 * Calls a SSE assembly implementation taking three visible arguments.
1442 *
1443 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1444 * @param a0 The first extra argument.
1445 * @param a1 The second extra argument.
1446 * @param a2 The third extra argument.
1447 */
1448#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1449 do { \
1450 IEM_MC_PREPARE_SSE_USAGE(); \
1451 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1452 } while (0)
1453
1454
1455/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1456 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1457#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1458 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1459
1460/**
1461 * Calls a AVX assembly implementation taking two visible arguments.
1462 *
1463 * There is one implicit zero'th argument, a pointer to the extended state.
1464 *
1465 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1466 * @param a1 The first extra argument.
1467 * @param a2 The second extra argument.
1468 */
1469#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1470 do { \
1471 IEM_MC_PREPARE_AVX_USAGE(); \
1472 a_pfnAImpl(pXState, (a1), (a2)); \
1473 } while (0)
1474
1475/**
1476 * Calls a AVX assembly implementation taking three visible arguments.
1477 *
1478 * There is one implicit zero'th argument, a pointer to the extended state.
1479 *
1480 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1481 * @param a1 The first extra argument.
1482 * @param a2 The second extra argument.
1483 * @param a3 The third extra argument.
1484 */
1485#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1486 do { \
1487 IEM_MC_PREPARE_AVX_USAGE(); \
1488 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1489 } while (0)
1490
1491/** @note Not for IOPL or IF testing. */
1492#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1493/** @note Not for IOPL or IF testing. */
1494#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1495/** @note Not for IOPL or IF testing. */
1496#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1497/** @note Not for IOPL or IF testing. */
1498#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1499/** @note Not for IOPL or IF testing. */
1500#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1501 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1502 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1503/** @note Not for IOPL or IF testing. */
1504#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1505 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1506 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1507/** @note Not for IOPL or IF testing. */
1508#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1509 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1510 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1511 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1512/** @note Not for IOPL or IF testing. */
1513#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1514 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1515 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1516 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1517#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1518#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1519#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1520/** @note Not for IOPL or IF testing. */
1521#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1522 if ( pVCpu->cpum.GstCtx.cx != 0 \
1523 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1524/** @note Not for IOPL or IF testing. */
1525#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1526 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1527 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1528/** @note Not for IOPL or IF testing. */
1529#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1530 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1531 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1532/** @note Not for IOPL or IF testing. */
1533#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1534 if ( pVCpu->cpum.GstCtx.cx != 0 \
1535 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1536/** @note Not for IOPL or IF testing. */
1537#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1538 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1539 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1540/** @note Not for IOPL or IF testing. */
1541#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1542 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1543 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1544#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1545#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1546
1547#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1548 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1549#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1550 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1551#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1552 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1553#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1554 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1555#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1556 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1557#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1558 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1559#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1560 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1561#define IEM_MC_IF_FCW_IM() \
1562 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1563#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1564 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1565 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1566
1567#define IEM_MC_ELSE() } else {
1568#define IEM_MC_ENDIF() } do {} while (0)
1569
1570/** @} */
1571
1572#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1573
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