VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 95512

Last change on this file since 95512 was 95512, checked in by vboxsync, 2 years ago

VMM/IEM: Use the IEM_GET_MODRM_* and IEM_IS_MODRM_* macros to make the code more readable. bugref:9898
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1/* $Id: IEMInternal.h 95512 2022-07-05 08:17:51Z vboxsync $ */
2/** @file
3 * IEM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
19#define VMM_INCLUDED_SRC_include_IEMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/vmm/cpum.h>
25#include <VBox/vmm/iem.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/stam.h>
28#include <VBox/param.h>
29
30#include <iprt/setjmp-without-sigmask.h>
31
32
33RT_C_DECLS_BEGIN
34
35
36/** @defgroup grp_iem_int Internals
37 * @ingroup grp_iem
38 * @internal
39 * @{
40 */
41
42/** For expanding symbol in slickedit and other products tagging and
43 * crossreferencing IEM symbols. */
44#ifndef IEM_STATIC
45# define IEM_STATIC static
46#endif
47
48/** @def IEM_WITH_SETJMP
49 * Enables alternative status code handling using setjmps.
50 *
51 * This adds a bit of expense via the setjmp() call since it saves all the
52 * non-volatile registers. However, it eliminates return code checks and allows
53 * for more optimal return value passing (return regs instead of stack buffer).
54 */
55#if defined(DOXYGEN_RUNNING) || defined(RT_OS_WINDOWS) || 1
56# define IEM_WITH_SETJMP
57#endif
58
59#define IEM_IMPLEMENTS_TASKSWITCH
60
61/** @def IEM_WITH_3DNOW
62 * Includes the 3DNow decoding. */
63#define IEM_WITH_3DNOW
64
65/** @def IEM_WITH_THREE_0F_38
66 * Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
67#define IEM_WITH_THREE_0F_38
68
69/** @def IEM_WITH_THREE_0F_3A
70 * Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
71#define IEM_WITH_THREE_0F_3A
72
73/** @def IEM_WITH_VEX
74 * Includes the VEX decoding. */
75#define IEM_WITH_VEX
76
77/** @def IEM_CFG_TARGET_CPU
78 * The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
79 *
80 * By default we allow this to be configured by the user via the
81 * CPUM/GuestCpuName config string, but this comes at a slight cost during
82 * decoding. So, for applications of this code where there is no need to
83 * be dynamic wrt target CPU, just modify this define.
84 */
85#if !defined(IEM_CFG_TARGET_CPU) || defined(DOXYGEN_RUNNING)
86# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
87#endif
88
89//#define IEM_WITH_CODE_TLB // - work in progress
90//#define IEM_WITH_DATA_TLB // - work in progress
91
92
93/** @def IEM_USE_UNALIGNED_DATA_ACCESS
94 * Use unaligned accesses instead of elaborate byte assembly. */
95#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) || defined(DOXYGEN_RUNNING)
96# define IEM_USE_UNALIGNED_DATA_ACCESS
97#endif
98
99//#define IEM_LOG_MEMORY_WRITES
100
101#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
102/** Instruction statistics. */
103typedef struct IEMINSTRSTATS
104{
105# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
106# include "IEMInstructionStatisticsTmpl.h"
107# undef IEM_DO_INSTR_STAT
108} IEMINSTRSTATS;
109#else
110struct IEMINSTRSTATS;
111typedef struct IEMINSTRSTATS IEMINSTRSTATS;
112#endif
113/** Pointer to IEM instruction statistics. */
114typedef IEMINSTRSTATS *PIEMINSTRSTATS;
115
116
117/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
118 * @{ */
119#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /**< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. */
120#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /**< Intel EFLAGS result. */
121#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /**< AMD EFLAGS result */
122#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /**< Reserved/dummy entry slot that's the same as 0. */
123#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /**< For masking the index before use. */
124/** Selects the right variant from a_aArray.
125 * pVCpu is implicit in the caller context. */
126#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
127 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
128/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
129 * be used because the host CPU does not support the operation. */
130#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
131 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
132/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
133 * array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
134 * into the two.
135 * @sa IEM_SELECT_NATIVE_OR_FALLBACK */
136#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
137# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
138 (a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
139#else
140# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
141 (a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
142#endif
143/** @} */
144
145/**
146 * Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
147 * indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
148 *
149 * On non-x86 hosts, this will shortcut to the fallback w/o checking the
150 * indicator.
151 *
152 * @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
153 */
154#if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
155# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
156 (g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
157#else
158# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
159#endif
160
161
162/**
163 * Extended operand mode that includes a representation of 8-bit.
164 *
165 * This is used for packing down modes when invoking some C instruction
166 * implementations.
167 */
168typedef enum IEMMODEX
169{
170 IEMMODEX_16BIT = IEMMODE_16BIT,
171 IEMMODEX_32BIT = IEMMODE_32BIT,
172 IEMMODEX_64BIT = IEMMODE_64BIT,
173 IEMMODEX_8BIT
174} IEMMODEX;
175AssertCompileSize(IEMMODEX, 4);
176
177
178/**
179 * Branch types.
180 */
181typedef enum IEMBRANCH
182{
183 IEMBRANCH_JUMP = 1,
184 IEMBRANCH_CALL,
185 IEMBRANCH_TRAP,
186 IEMBRANCH_SOFTWARE_INT,
187 IEMBRANCH_HARDWARE_INT
188} IEMBRANCH;
189AssertCompileSize(IEMBRANCH, 4);
190
191
192/**
193 * INT instruction types.
194 */
195typedef enum IEMINT
196{
197 /** INT n instruction (opcode 0xcd imm). */
198 IEMINT_INTN = 0,
199 /** Single byte INT3 instruction (opcode 0xcc). */
200 IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
201 /** Single byte INTO instruction (opcode 0xce). */
202 IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
203 /** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
204 IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
205} IEMINT;
206AssertCompileSize(IEMINT, 4);
207
208
209/**
210 * A FPU result.
211 */
212typedef struct IEMFPURESULT
213{
214 /** The output value. */
215 RTFLOAT80U r80Result;
216 /** The output status. */
217 uint16_t FSW;
218} IEMFPURESULT;
219AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
220/** Pointer to a FPU result. */
221typedef IEMFPURESULT *PIEMFPURESULT;
222/** Pointer to a const FPU result. */
223typedef IEMFPURESULT const *PCIEMFPURESULT;
224
225
226/**
227 * A FPU result consisting of two output values and FSW.
228 */
229typedef struct IEMFPURESULTTWO
230{
231 /** The first output value. */
232 RTFLOAT80U r80Result1;
233 /** The output status. */
234 uint16_t FSW;
235 /** The second output value. */
236 RTFLOAT80U r80Result2;
237} IEMFPURESULTTWO;
238AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
239AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
240/** Pointer to a FPU result consisting of two output values and FSW. */
241typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
242/** Pointer to a const FPU result consisting of two output values and FSW. */
243typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
244
245
246/**
247 * IEM TLB entry.
248 *
249 * Lookup assembly:
250 * @code{.asm}
251 ; Calculate tag.
252 mov rax, [VA]
253 shl rax, 16
254 shr rax, 16 + X86_PAGE_SHIFT
255 or rax, [uTlbRevision]
256
257 ; Do indexing.
258 movzx ecx, al
259 lea rcx, [pTlbEntries + rcx]
260
261 ; Check tag.
262 cmp [rcx + IEMTLBENTRY.uTag], rax
263 jne .TlbMiss
264
265 ; Check access.
266 mov rax, ACCESS_FLAGS | MAPPING_R3_NOT_VALID | 0xffffff00
267 and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
268 cmp rax, [uTlbPhysRev]
269 jne .TlbMiss
270
271 ; Calc address and we're done.
272 mov eax, X86_PAGE_OFFSET_MASK
273 and eax, [VA]
274 or rax, [rcx + IEMTLBENTRY.pMappingR3]
275 %ifdef VBOX_WITH_STATISTICS
276 inc qword [cTlbHits]
277 %endif
278 jmp .Done
279
280 .TlbMiss:
281 mov r8d, ACCESS_FLAGS
282 mov rdx, [VA]
283 mov rcx, [pVCpu]
284 call iemTlbTypeMiss
285 .Done:
286
287 @endcode
288 *
289 */
290typedef struct IEMTLBENTRY
291{
292 /** The TLB entry tag.
293 * Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
294 * is ASSUMING a virtual address width of 48 bits.
295 *
296 * Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
297 *
298 * The TLB lookup code uses the current TLB revision, which won't ever be zero,
299 * enabling an extremely cheap TLB invalidation most of the time. When the TLB
300 * revision wraps around though, the tags needs to be zeroed.
301 *
302 * @note Try use SHRD instruction? After seeing
303 * https://gmplib.org/~tege/x86-timing.pdf, maybe not.
304 *
305 * @todo This will need to be reorganized for 57-bit wide virtual address and
306 * PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
307 * have to move the TLB entry versioning entirely to the
308 * fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
309 * 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
310 * consumed by PCID and ASID (12 + 6 = 18).
311 */
312 uint64_t uTag;
313 /** Access flags and physical TLB revision.
314 *
315 * - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
316 * - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
317 * - Bit 2 - page tables - not user (complemented X86_PTE_US).
318 * - Bit 3 - pgm phys/virt - not directly writable.
319 * - Bit 4 - pgm phys page - not directly readable.
320 * - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
321 * - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
322 * - Bit 7 - tlb entry - pMappingR3 member not valid.
323 * - Bits 63 thru 8 are used for the physical TLB revision number.
324 *
325 * We're using complemented bit meanings here because it makes it easy to check
326 * whether special action is required. For instance a user mode write access
327 * would do a "TEST fFlags, (X86_PTE_RW | X86_PTE_US | X86_PTE_D)" and a
328 * non-zero result would mean special handling needed because either it wasn't
329 * writable, or it wasn't user, or the page wasn't dirty. A user mode read
330 * access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
331 * need to check any PTE flag.
332 */
333 uint64_t fFlagsAndPhysRev;
334 /** The guest physical page address. */
335 uint64_t GCPhys;
336 /** Pointer to the ring-3 mapping. */
337 R3PTRTYPE(uint8_t *) pbMappingR3;
338#if HC_ARCH_BITS == 32
339 uint32_t u32Padding1;
340#endif
341} IEMTLBENTRY;
342AssertCompileSize(IEMTLBENTRY, 32);
343/** Pointer to an IEM TLB entry. */
344typedef IEMTLBENTRY *PIEMTLBENTRY;
345
346/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
347 * @{ */
348#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /**< Page tables: Not executable. */
349#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /**< Page tables: Not writable. */
350#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /**< Page tables: Not user accessible (supervisor only). */
351#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /**< Phys page: Not writable (access handler, ROM, whatever). */
352#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /**< Phys page: Not readable (MMIO / access handler, ROM) */
353#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /**< Phys tables: Not accessed (need to be marked accessed). */
354#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /**< Page tables: Not dirty (needs to be made dirty on write). */
355#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /**< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. */
356#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /**< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
357#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
358/** @} */
359
360
361/**
362 * An IEM TLB.
363 *
364 * We've got two of these, one for data and one for instructions.
365 */
366typedef struct IEMTLB
367{
368 /** The TLB entries.
369 * We've choosen 256 because that way we can obtain the result directly from a
370 * 8-bit register without an additional AND instruction. */
371 IEMTLBENTRY aEntries[256];
372 /** The TLB revision.
373 * This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
374 * by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
375 * the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
376 * (The revision zero indicates an invalid TLB entry.)
377 *
378 * The initial value is choosen to cause an early wraparound. */
379 uint64_t uTlbRevision;
380 /** The TLB physical address revision - shadow of PGM variable.
381 *
382 * This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
383 * incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
384 * a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
385 * as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
386 *
387 * The initial value is choosen to cause an early wraparound. */
388 uint64_t volatile uTlbPhysRev;
389
390 /* Statistics: */
391
392 /** TLB hits (VBOX_WITH_STATISTICS only). */
393 uint64_t cTlbHits;
394 /** TLB misses. */
395 uint32_t cTlbMisses;
396 /** Slow read path. */
397 uint32_t cTlbSlowReadPath;
398#if 0
399 /** TLB misses because of tag mismatch. */
400 uint32_t cTlbMissesTag;
401 /** TLB misses because of virtual access violation. */
402 uint32_t cTlbMissesVirtAccess;
403 /** TLB misses because of dirty bit. */
404 uint32_t cTlbMissesDirty;
405 /** TLB misses because of MMIO */
406 uint32_t cTlbMissesMmio;
407 /** TLB misses because of write access handlers. */
408 uint32_t cTlbMissesWriteHandler;
409 /** TLB misses because no r3(/r0) mapping. */
410 uint32_t cTlbMissesMapping;
411#endif
412 /** Alignment padding. */
413 uint32_t au32Padding[3+5];
414} IEMTLB;
415AssertCompileSizeAlignment(IEMTLB, 64);
416/** IEMTLB::uTlbRevision increment. */
417#define IEMTLB_REVISION_INCR RT_BIT_64(36)
418/** IEMTLB::uTlbRevision mask. */
419#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
420/** IEMTLB::uTlbPhysRev increment.
421 * @sa IEMTLBE_F_PHYS_REV */
422#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
423/**
424 * Calculates the TLB tag for a virtual address.
425 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
426 * @param a_pTlb The TLB.
427 * @param a_GCPtr The virtual address.
428 */
429#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) | (a_pTlb)->uTlbRevision )
430/**
431 * Calculates the TLB tag for a virtual address but without TLB revision.
432 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
433 * @param a_GCPtr The virtual address.
434 */
435#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
436/**
437 * Converts a TLB tag value into a TLB index.
438 * @returns Index into IEMTLB::aEntries.
439 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
440 */
441#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
442/**
443 * Converts a TLB tag value into a TLB index.
444 * @returns Index into IEMTLB::aEntries.
445 * @param a_pTlb The TLB.
446 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
447 */
448#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
449
450
451/**
452 * The per-CPU IEM state.
453 */
454typedef struct IEMCPU
455{
456 /** Info status code that needs to be propagated to the IEM caller.
457 * This cannot be passed internally, as it would complicate all success
458 * checks within the interpreter making the code larger and almost impossible
459 * to get right. Instead, we'll store status codes to pass on here. Each
460 * source of these codes will perform appropriate sanity checks. */
461 int32_t rcPassUp; /* 0x00 */
462
463 /** The current CPU execution mode (CS). */
464 IEMMODE enmCpuMode; /* 0x04 */
465 /** The CPL. */
466 uint8_t uCpl; /* 0x05 */
467
468 /** Whether to bypass access handlers or not. */
469 bool fBypassHandlers; /* 0x06 */
470 /** Whether to disregard the lock prefix (implied or not). */
471 bool fDisregardLock; /* 0x07 */
472
473 /** @name Decoder state.
474 * @{ */
475#ifdef IEM_WITH_CODE_TLB
476 /** The offset of the next instruction byte. */
477 uint32_t offInstrNextByte; /* 0x08 */
478 /** The number of bytes available at pbInstrBuf for the current instruction.
479 * This takes the max opcode length into account so that doesn't need to be
480 * checked separately. */
481 uint32_t cbInstrBuf; /* 0x0c */
482 /** Pointer to the page containing RIP, user specified buffer or abOpcode.
483 * This can be NULL if the page isn't mappable for some reason, in which
484 * case we'll do fallback stuff.
485 *
486 * If we're executing an instruction from a user specified buffer,
487 * IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
488 * aligned pointer but pointer to the user data.
489 *
490 * For instructions crossing pages, this will start on the first page and be
491 * advanced to the next page by the time we've decoded the instruction. This
492 * therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
493 */
494 uint8_t const *pbInstrBuf; /* 0x10 */
495# if ARCH_BITS == 32
496 uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
497# endif
498 /** The program counter corresponding to pbInstrBuf.
499 * This is set to a non-canonical address when we need to invalidate it. */
500 uint64_t uInstrBufPc; /* 0x18 */
501 /** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
502 * This takes the CS segment limit into account. */
503 uint16_t cbInstrBufTotal; /* 0x20 */
504 /** Offset into pbInstrBuf of the first byte of the current instruction.
505 * Can be negative to efficiently handle cross page instructions. */
506 int16_t offCurInstrStart; /* 0x22 */
507
508 /** The prefix mask (IEM_OP_PRF_XXX). */
509 uint32_t fPrefixes; /* 0x24 */
510 /** The extra REX ModR/M register field bit (REX.R << 3). */
511 uint8_t uRexReg; /* 0x28 */
512 /** The extra REX ModR/M r/m field, SIB base and opcode reg bit
513 * (REX.B << 3). */
514 uint8_t uRexB; /* 0x29 */
515 /** The extra REX SIB index field bit (REX.X << 3). */
516 uint8_t uRexIndex; /* 0x2a */
517
518 /** The effective segment register (X86_SREG_XXX). */
519 uint8_t iEffSeg; /* 0x2b */
520
521 /** The offset of the ModR/M byte relative to the start of the instruction. */
522 uint8_t offModRm; /* 0x2c */
523#else
524 /** The size of what has currently been fetched into abOpcode. */
525 uint8_t cbOpcode; /* 0x08 */
526 /** The current offset into abOpcode. */
527 uint8_t offOpcode; /* 0x09 */
528 /** The offset of the ModR/M byte relative to the start of the instruction. */
529 uint8_t offModRm; /* 0x0a */
530
531 /** The effective segment register (X86_SREG_XXX). */
532 uint8_t iEffSeg; /* 0x0b */
533
534 /** The prefix mask (IEM_OP_PRF_XXX). */
535 uint32_t fPrefixes; /* 0x0c */
536 /** The extra REX ModR/M register field bit (REX.R << 3). */
537 uint8_t uRexReg; /* 0x10 */
538 /** The extra REX ModR/M r/m field, SIB base and opcode reg bit
539 * (REX.B << 3). */
540 uint8_t uRexB; /* 0x11 */
541 /** The extra REX SIB index field bit (REX.X << 3). */
542 uint8_t uRexIndex; /* 0x12 */
543
544#endif
545
546 /** The effective operand mode. */
547 IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
548 /** The default addressing mode. */
549 IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
550 /** The effective addressing mode. */
551 IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
552 /** The default operand mode. */
553 IEMMODE enmDefOpSize; /* 0x30, 0x16 */
554
555 /** Prefix index (VEX.pp) for two byte and three byte tables. */
556 uint8_t idxPrefix; /* 0x31, 0x17 */
557 /** 3rd VEX/EVEX/XOP register.
558 * Please use IEM_GET_EFFECTIVE_VVVV to access. */
559 uint8_t uVex3rdReg; /* 0x32, 0x18 */
560 /** The VEX/EVEX/XOP length field. */
561 uint8_t uVexLength; /* 0x33, 0x19 */
562 /** Additional EVEX stuff. */
563 uint8_t fEvexStuff; /* 0x34, 0x1a */
564
565 /** Explicit alignment padding. */
566 uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
567 /** The FPU opcode (FOP). */
568 uint16_t uFpuOpcode; /* 0x36, 0x1c */
569#ifndef IEM_WITH_CODE_TLB
570 /** Explicit alignment padding. */
571 uint8_t abAlignment2b[2]; /* 0x1e */
572#endif
573
574 /** The opcode bytes. */
575 uint8_t abOpcode[15]; /* 0x48, 0x20 */
576 /** Explicit alignment padding. */
577#ifdef IEM_WITH_CODE_TLB
578 uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
579#else
580 uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
581#endif
582 /** @} */
583
584
585 /** The flags of the current exception / interrupt. */
586 uint32_t fCurXcpt; /* 0x48, 0x48 */
587 /** The current exception / interrupt. */
588 uint8_t uCurXcpt;
589 /** Exception / interrupt recursion depth. */
590 int8_t cXcptRecursions;
591
592 /** The number of active guest memory mappings. */
593 uint8_t cActiveMappings;
594 /** The next unused mapping index. */
595 uint8_t iNextMapping;
596 /** Records for tracking guest memory mappings. */
597 struct
598 {
599 /** The address of the mapped bytes. */
600 void *pv;
601 /** The access flags (IEM_ACCESS_XXX).
602 * IEM_ACCESS_INVALID if the entry is unused. */
603 uint32_t fAccess;
604#if HC_ARCH_BITS == 64
605 uint32_t u32Alignment4; /**< Alignment padding. */
606#endif
607 } aMemMappings[3];
608
609 /** Locking records for the mapped memory. */
610 union
611 {
612 PGMPAGEMAPLOCK Lock;
613 uint64_t au64Padding[2];
614 } aMemMappingLocks[3];
615
616 /** Bounce buffer info.
617 * This runs in parallel to aMemMappings. */
618 struct
619 {
620 /** The physical address of the first byte. */
621 RTGCPHYS GCPhysFirst;
622 /** The physical address of the second page. */
623 RTGCPHYS GCPhysSecond;
624 /** The number of bytes in the first page. */
625 uint16_t cbFirst;
626 /** The number of bytes in the second page. */
627 uint16_t cbSecond;
628 /** Whether it's unassigned memory. */
629 bool fUnassigned;
630 /** Explicit alignment padding. */
631 bool afAlignment5[3];
632 } aMemBbMappings[3];
633
634 /** Bounce buffer storage.
635 * This runs in parallel to aMemMappings and aMemBbMappings. */
636 struct
637 {
638 uint8_t ab[512];
639 } aBounceBuffers[3];
640
641
642 /** Pointer set jump buffer - ring-3 context. */
643 R3PTRTYPE(jmp_buf *) pJmpBufR3;
644 /** Pointer set jump buffer - ring-0 context. */
645 R0PTRTYPE(jmp_buf *) pJmpBufR0;
646
647 /** @todo Should move this near @a fCurXcpt later. */
648 /** The CR2 for the current exception / interrupt. */
649 uint64_t uCurXcptCr2;
650 /** The error code for the current exception / interrupt. */
651 uint32_t uCurXcptErr;
652
653 /** @name Statistics
654 * @{ */
655 /** The number of instructions we've executed. */
656 uint32_t cInstructions;
657 /** The number of potential exits. */
658 uint32_t cPotentialExits;
659 /** The number of bytes data or stack written (mostly for IEMExecOneEx).
660 * This may contain uncommitted writes. */
661 uint32_t cbWritten;
662 /** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
663 uint32_t cRetInstrNotImplemented;
664 /** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
665 uint32_t cRetAspectNotImplemented;
666 /** Counts informational statuses returned (other than VINF_SUCCESS). */
667 uint32_t cRetInfStatuses;
668 /** Counts other error statuses returned. */
669 uint32_t cRetErrStatuses;
670 /** Number of times rcPassUp has been used. */
671 uint32_t cRetPassUpStatus;
672 /** Number of times RZ left with instruction commit pending for ring-3. */
673 uint32_t cPendingCommit;
674 /** Number of long jumps. */
675 uint32_t cLongJumps;
676 /** @} */
677
678 /** @name Target CPU information.
679 * @{ */
680#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
681 /** The target CPU. */
682 uint8_t uTargetCpu;
683#else
684 uint8_t bTargetCpuPadding;
685#endif
686 /** For selecting assembly works matching the target CPU EFLAGS behaviour, see
687 * IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
688 * native host support and the 2nd for when there is.
689 *
690 * The two values are typically indexed by a g_CpumHostFeatures bit.
691 *
692 * This is for instance used for the BSF & BSR instructions where AMD and
693 * Intel CPUs produce different EFLAGS. */
694 uint8_t aidxTargetCpuEflFlavour[2];
695
696 /** The CPU vendor. */
697 CPUMCPUVENDOR enmCpuVendor;
698 /** @} */
699
700 /** @name Host CPU information.
701 * @{ */
702 /** The CPU vendor. */
703 CPUMCPUVENDOR enmHostCpuVendor;
704 /** @} */
705
706 /** Counts RDMSR \#GP(0) LogRel(). */
707 uint8_t cLogRelRdMsr;
708 /** Counts WRMSR \#GP(0) LogRel(). */
709 uint8_t cLogRelWrMsr;
710 /** Alignment padding. */
711 uint8_t abAlignment8[50];
712
713 /** Data TLB.
714 * @remarks Must be 64-byte aligned. */
715 IEMTLB DataTlb;
716 /** Instruction TLB.
717 * @remarks Must be 64-byte aligned. */
718 IEMTLB CodeTlb;
719
720#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
721 /** Instruction statistics for ring-0/raw-mode. */
722 IEMINSTRSTATS StatsRZ;
723 /** Instruction statistics for ring-3. */
724 IEMINSTRSTATS StatsR3;
725#endif
726} IEMCPU;
727AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
728AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
729AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
730/** Pointer to the per-CPU IEM state. */
731typedef IEMCPU *PIEMCPU;
732/** Pointer to the const per-CPU IEM state. */
733typedef IEMCPU const *PCIEMCPU;
734
735
736/** @def IEM_GET_CTX
737 * Gets the guest CPU context for the calling EMT.
738 * @returns PCPUMCTX
739 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
740 */
741#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
742
743/** @def IEM_CTX_ASSERT
744 * Asserts that the @a a_fExtrnMbz is present in the CPU context.
745 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
746 * @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
747 */
748#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
749 ("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
750 (a_fExtrnMbz)))
751
752/** @def IEM_CTX_IMPORT_RET
753 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
754 *
755 * Will call the keep to import the bits as needed.
756 *
757 * Returns on import failure.
758 *
759 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
760 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
761 */
762#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
763 do { \
764 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
765 { /* likely */ } \
766 else \
767 { \
768 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
769 AssertRCReturn(rcCtxImport, rcCtxImport); \
770 } \
771 } while (0)
772
773/** @def IEM_CTX_IMPORT_NORET
774 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
775 *
776 * Will call the keep to import the bits as needed.
777 *
778 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
779 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
780 */
781#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
782 do { \
783 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
784 { /* likely */ } \
785 else \
786 { \
787 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
788 AssertLogRelRC(rcCtxImport); \
789 } \
790 } while (0)
791
792/** @def IEM_CTX_IMPORT_JMP
793 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
794 *
795 * Will call the keep to import the bits as needed.
796 *
797 * Jumps on import failure.
798 *
799 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
800 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
801 */
802#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
803 do { \
804 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
805 { /* likely */ } \
806 else \
807 { \
808 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
809 AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
810 } \
811 } while (0)
812
813
814
815/** @def IEM_GET_TARGET_CPU
816 * Gets the current IEMTARGETCPU value.
817 * @returns IEMTARGETCPU value.
818 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
819 */
820#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
821# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
822#else
823# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
824#endif
825
826/** @def IEM_GET_INSTR_LEN
827 * Gets the instruction length. */
828#ifdef IEM_WITH_CODE_TLB
829# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
830#else
831# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
832#endif
833
834
835/**
836 * Shared per-VM IEM data.
837 */
838typedef struct IEM
839{
840 /** The VMX APIC-access page handler type. */
841 PGMPHYSHANDLERTYPE hVmxApicAccessPage;
842} IEM;
843
844
845
846/** @name IEM_ACCESS_XXX - Access details.
847 * @{ */
848#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
849#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
850#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
851#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
852#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
853#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
854#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
855#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
856#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
857#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
858/** The writes are partial, so if initialize the bounce buffer with the
859 * orignal RAM content. */
860#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
861/** Used in aMemMappings to indicate that the entry is bounce buffered. */
862#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
863/** Bounce buffer with ring-3 write pending, first page. */
864#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
865/** Bounce buffer with ring-3 write pending, second page. */
866#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
867/** Not locked, accessed via the TLB. */
868#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
869/** Valid bit mask. */
870#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
871/** Shift count for the TLB flags (upper word). */
872#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
873
874/** Read+write data alias. */
875#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
876/** Write data alias. */
877#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
878/** Read data alias. */
879#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA)
880/** Instruction fetch alias. */
881#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC | IEM_ACCESS_WHAT_CODE)
882/** Stack write alias. */
883#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
884/** Stack read alias. */
885#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_STACK)
886/** Stack read+write alias. */
887#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
888/** Read system table alias. */
889#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_SYS)
890/** Read+write system table alias. */
891#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_SYS)
892/** @} */
893
894/** @name Prefix constants (IEMCPU::fPrefixes)
895 * @{ */
896#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /**< CS segment prefix (0x2e). */
897#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /**< SS segment prefix (0x36). */
898#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /**< DS segment prefix (0x3e). */
899#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /**< ES segment prefix (0x26). */
900#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /**< FS segment prefix (0x64). */
901#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /**< GS segment prefix (0x65). */
902#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
903
904#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /**< Operand size prefix (0x66). */
905#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /**< REX.W prefix (0x48-0x4f). */
906#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /**< Address size prefix (0x67). */
907
908#define IEM_OP_PRF_LOCK RT_BIT_32(16) /**< Lock prefix (0xf0). */
909#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /**< Repeat-not-zero prefix (0xf2). */
910#define IEM_OP_PRF_REPZ RT_BIT_32(18) /**< Repeat-if-zero prefix (0xf3). */
911
912#define IEM_OP_PRF_REX RT_BIT_32(24) /**< Any REX prefix (0x40-0x4f). */
913#define IEM_OP_PRF_REX_R RT_BIT_32(25) /**< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). */
914#define IEM_OP_PRF_REX_B RT_BIT_32(26) /**< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). */
915#define IEM_OP_PRF_REX_X RT_BIT_32(27) /**< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). */
916/** Mask with all the REX prefix flags.
917 * This is generally for use when needing to undo the REX prefixes when they
918 * are followed legacy prefixes and therefore does not immediately preceed
919 * the first opcode byte.
920 * For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
921#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X | IEM_OP_PRF_SIZE_REX_W )
922
923#define IEM_OP_PRF_VEX RT_BIT_32(28) /**< Indiciates VEX prefix. */
924#define IEM_OP_PRF_EVEX RT_BIT_32(29) /**< Indiciates EVEX prefix. */
925#define IEM_OP_PRF_XOP RT_BIT_32(30) /**< Indiciates XOP prefix. */
926/** @} */
927
928/** @name IEMOPFORM_XXX - Opcode forms
929 * @note These are ORed together with IEMOPHINT_XXX.
930 * @{ */
931/** ModR/M: reg, r/m */
932#define IEMOPFORM_RM 0
933/** ModR/M: reg, r/m (register) */
934#define IEMOPFORM_RM_REG (IEMOPFORM_RM | IEMOPFORM_MOD3)
935/** ModR/M: reg, r/m (memory) */
936#define IEMOPFORM_RM_MEM (IEMOPFORM_RM | IEMOPFORM_NOT_MOD3)
937/** ModR/M: reg, r/m */
938#define IEMOPFORM_RMI 1
939/** ModR/M: reg, r/m (register) */
940#define IEMOPFORM_RMI_REG (IEMOPFORM_RM | IEMOPFORM_MOD3)
941/** ModR/M: reg, r/m (memory) */
942#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM | IEMOPFORM_NOT_MOD3)
943/** ModR/M: r/m, reg */
944#define IEMOPFORM_MR 2
945/** ModR/M: r/m (register), reg */
946#define IEMOPFORM_MR_REG (IEMOPFORM_MR | IEMOPFORM_MOD3)
947/** ModR/M: r/m (memory), reg */
948#define IEMOPFORM_MR_MEM (IEMOPFORM_MR | IEMOPFORM_NOT_MOD3)
949/** ModR/M: r/m only */
950#define IEMOPFORM_M 3
951/** ModR/M: r/m only (register). */
952#define IEMOPFORM_M_REG (IEMOPFORM_M | IEMOPFORM_MOD3)
953/** ModR/M: r/m only (memory). */
954#define IEMOPFORM_M_MEM (IEMOPFORM_M | IEMOPFORM_NOT_MOD3)
955/** ModR/M: reg only */
956#define IEMOPFORM_R 4
957
958/** VEX+ModR/M: reg, r/m */
959#define IEMOPFORM_VEX_RM 8
960/** VEX+ModR/M: reg, r/m (register) */
961#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM | IEMOPFORM_MOD3)
962/** VEX+ModR/M: reg, r/m (memory) */
963#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM | IEMOPFORM_NOT_MOD3)
964/** VEX+ModR/M: r/m, reg */
965#define IEMOPFORM_VEX_MR 9
966/** VEX+ModR/M: r/m (register), reg */
967#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR | IEMOPFORM_MOD3)
968/** VEX+ModR/M: r/m (memory), reg */
969#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR | IEMOPFORM_NOT_MOD3)
970/** VEX+ModR/M: r/m only */
971#define IEMOPFORM_VEX_M 10
972/** VEX+ModR/M: r/m only (register). */
973#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M | IEMOPFORM_MOD3)
974/** VEX+ModR/M: r/m only (memory). */
975#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M | IEMOPFORM_NOT_MOD3)
976/** VEX+ModR/M: reg only */
977#define IEMOPFORM_VEX_R 11
978/** VEX+ModR/M: reg, vvvv, r/m */
979#define IEMOPFORM_VEX_RVM 12
980/** VEX+ModR/M: reg, vvvv, r/m (register). */
981#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM | IEMOPFORM_MOD3)
982/** VEX+ModR/M: reg, vvvv, r/m (memory). */
983#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM | IEMOPFORM_NOT_MOD3)
984/** VEX+ModR/M: reg, r/m, vvvv */
985#define IEMOPFORM_VEX_RMV 13
986/** VEX+ModR/M: reg, r/m, vvvv (register). */
987#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV | IEMOPFORM_MOD3)
988/** VEX+ModR/M: reg, r/m, vvvv (memory). */
989#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV | IEMOPFORM_NOT_MOD3)
990/** VEX+ModR/M: reg, r/m, imm8 */
991#define IEMOPFORM_VEX_RMI 14
992/** VEX+ModR/M: reg, r/m, imm8 (register). */
993#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI | IEMOPFORM_MOD3)
994/** VEX+ModR/M: reg, r/m, imm8 (memory). */
995#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI | IEMOPFORM_NOT_MOD3)
996/** VEX+ModR/M: r/m, vvvv, reg */
997#define IEMOPFORM_VEX_MVR 15
998/** VEX+ModR/M: r/m, vvvv, reg (register) */
999#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR | IEMOPFORM_MOD3)
1000/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1001#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR | IEMOPFORM_NOT_MOD3)
1002/** VEX+ModR/M+/n: vvvv, r/m */
1003#define IEMOPFORM_VEX_VM 16
1004/** VEX+ModR/M+/n: vvvv, r/m (register) */
1005#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM | IEMOPFORM_MOD3)
1006/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1007#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM | IEMOPFORM_NOT_MOD3)
1008
1009/** Fixed register instruction, no R/M. */
1010#define IEMOPFORM_FIXED 32
1011
1012/** The r/m is a register. */
1013#define IEMOPFORM_MOD3 RT_BIT_32(8)
1014/** The r/m is a memory access. */
1015#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1016/** @} */
1017
1018/** @name IEMOPHINT_XXX - Additional Opcode Hints
1019 * @note These are ORed together with IEMOPFORM_XXX.
1020 * @{ */
1021/** Ignores the operand size prefix (66h). */
1022#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1023/** Ignores REX.W (aka WIG). */
1024#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1025/** Both the operand size prefixes (66h + REX.W) are ignored. */
1026#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_IGNORES_REXW)
1027/** Allowed with the lock prefix. */
1028#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1029/** The VEX.L value is ignored (aka LIG). */
1030#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1031/** The VEX.L value must be zero (i.e. 128-bit width only). */
1032#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1033/** The VEX.V value must be zero. */
1034#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1035
1036/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1037#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1038/** @} */
1039
1040/**
1041 * Possible hardware task switch sources.
1042 */
1043typedef enum IEMTASKSWITCH
1044{
1045 /** Task switch caused by an interrupt/exception. */
1046 IEMTASKSWITCH_INT_XCPT = 1,
1047 /** Task switch caused by a far CALL. */
1048 IEMTASKSWITCH_CALL,
1049 /** Task switch caused by a far JMP. */
1050 IEMTASKSWITCH_JUMP,
1051 /** Task switch caused by an IRET. */
1052 IEMTASKSWITCH_IRET
1053} IEMTASKSWITCH;
1054AssertCompileSize(IEMTASKSWITCH, 4);
1055
1056/**
1057 * Possible CrX load (write) sources.
1058 */
1059typedef enum IEMACCESSCRX
1060{
1061 /** CrX access caused by 'mov crX' instruction. */
1062 IEMACCESSCRX_MOV_CRX,
1063 /** CrX (CR0) write caused by 'lmsw' instruction. */
1064 IEMACCESSCRX_LMSW,
1065 /** CrX (CR0) write caused by 'clts' instruction. */
1066 IEMACCESSCRX_CLTS,
1067 /** CrX (CR0) read caused by 'smsw' instruction. */
1068 IEMACCESSCRX_SMSW
1069} IEMACCESSCRX;
1070
1071#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1072/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1073 *
1074 * These flags provide further context to SLAT page-walk failures that could not be
1075 * determined by PGM (e.g, PGM is not privy to memory access permissions).
1076 *
1077 * @{
1078 */
1079/** Translating a nested-guest linear address failed accessing a nested-guest
1080 * physical address. */
1081# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1082/** Translating a nested-guest linear address failed accessing a
1083 * paging-structure entry or updating accessed/dirty bits. */
1084# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1085/** @} */
1086
1087DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1088# ifndef IN_RING3
1089DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1090# endif
1091#endif
1092
1093/**
1094 * Indicates to the verifier that the given flag set is undefined.
1095 *
1096 * Can be invoked again to add more flags.
1097 *
1098 * This is a NOOP if the verifier isn't compiled in.
1099 *
1100 * @note We're temporarily keeping this until code is converted to new
1101 * disassembler style opcode handling.
1102 */
1103#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1104
1105
1106/** @def IEM_DECL_IMPL_TYPE
1107 * For typedef'ing an instruction implementation function.
1108 *
1109 * @param a_RetType The return type.
1110 * @param a_Name The name of the type.
1111 * @param a_ArgList The argument list enclosed in parentheses.
1112 */
1113
1114/** @def IEM_DECL_IMPL_DEF
1115 * For defining an instruction implementation function.
1116 *
1117 * @param a_RetType The return type.
1118 * @param a_Name The name of the type.
1119 * @param a_ArgList The argument list enclosed in parentheses.
1120 */
1121
1122#if defined(__GNUC__) && defined(RT_ARCH_X86)
1123# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1124 __attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1125# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1126 __attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1127# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1128 __attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1129
1130#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1131# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1132 a_RetType (__fastcall a_Name) a_ArgList
1133# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1134 a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1135# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1136 a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1137
1138#elif __cplusplus >= 201700 /* P0012R1 support */
1139# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1140 a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1141# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1142 a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1143# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1144 a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1145
1146#else
1147# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1148 a_RetType (VBOXCALL a_Name) a_ArgList
1149# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1150 a_RetType VBOXCALL a_Name a_ArgList
1151# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1152 a_RetType VBOXCALL a_Name a_ArgList
1153
1154#endif
1155
1156/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1157RT_C_DECLS_BEGIN
1158extern uint8_t const g_afParity[256];
1159RT_C_DECLS_END
1160
1161
1162/** @name Arithmetic assignment operations on bytes (binary).
1163 * @{ */
1164typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t *pu8Dst, uint8_t u8Src, uint32_t *pEFlags));
1165typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1166FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1167FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1168FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1169FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1170FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1171FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1172FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1173/** @} */
1174
1175/** @name Arithmetic assignment operations on words (binary).
1176 * @{ */
1177typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t *pu16Dst, uint16_t u16Src, uint32_t *pEFlags));
1178typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1179FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1180FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1181FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1182FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1183FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1184FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1185FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1186/** @} */
1187
1188/** @name Arithmetic assignment operations on double words (binary).
1189 * @{ */
1190typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t *pu32Dst, uint32_t u32Src, uint32_t *pEFlags));
1191typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1192FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1193FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1194FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1195FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1196FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1197FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1198FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1199FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1200FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1201FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1202/** @} */
1203
1204/** @name Arithmetic assignment operations on quad words (binary).
1205 * @{ */
1206typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t *pu64Dst, uint64_t u64Src, uint32_t *pEFlags));
1207typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1208FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1209FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1210FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1211FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1212FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1213FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1214FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1215FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1216FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1217FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1218/** @} */
1219
1220/** @name Compare operations (thrown in with the binary ops).
1221 * @{ */
1222FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1223FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1224FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1225FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1226/** @} */
1227
1228/** @name Test operations (thrown in with the binary ops).
1229 * @{ */
1230FNIEMAIMPLBINU8 iemAImpl_test_u8;
1231FNIEMAIMPLBINU16 iemAImpl_test_u16;
1232FNIEMAIMPLBINU32 iemAImpl_test_u32;
1233FNIEMAIMPLBINU64 iemAImpl_test_u64;
1234/** @} */
1235
1236/** @name Bit operations operations (thrown in with the binary ops).
1237 * @{ */
1238FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1239FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1240FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1241FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1242FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1243FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1244FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1245FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1246FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1247FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1248FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1249FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1250/** @} */
1251
1252/** @name Arithmetic three operand operations on double words (binary).
1253 * @{ */
1254typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t *pEFlags));
1255typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1256FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1257FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1258FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1259/** @} */
1260
1261/** @name Arithmetic three operand operations on quad words (binary).
1262 * @{ */
1263typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t *pEFlags));
1264typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1265FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1266FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1267FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1268/** @} */
1269
1270/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1271 * @{ */
1272typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1273typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1274FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1275FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1276FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1277FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1278FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1279FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1280/** @} */
1281
1282/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1283 * @{ */
1284typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1285typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1286FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1287FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1288FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1289FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1290FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1291FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1292/** @} */
1293
1294/** @name MULX 32-bit and 64-bit.
1295 * @{ */
1296typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t *puDst1, uint32_t *puDst2, uint32_t uSrc1, uint32_t uSrc2));
1297typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1298FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1299
1300typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t *puDst1, uint64_t *puDst2, uint64_t uSrc1, uint64_t uSrc2));
1301typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1302FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1303/** @} */
1304
1305
1306/** @name Exchange memory with register operations.
1307 * @{ */
1308IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t *pu8Mem, uint8_t *pu8Reg));
1309IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t *pu16Mem, uint16_t *pu16Reg));
1310IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t *pu32Mem, uint32_t *pu32Reg));
1311IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t *pu64Mem, uint64_t *pu64Reg));
1312IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t *pu8Mem, uint8_t *pu8Reg));
1313IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t *pu16Mem, uint16_t *pu16Reg));
1314IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t *pu32Mem, uint32_t *pu32Reg));
1315IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t *pu64Mem, uint64_t *pu64Reg));
1316/** @} */
1317
1318/** @name Exchange and add operations.
1319 * @{ */
1320IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t *pu8Dst, uint8_t *pu8Reg, uint32_t *pEFlags));
1321IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t *pu16Dst, uint16_t *pu16Reg, uint32_t *pEFlags));
1322IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t *pu32Dst, uint32_t *pu32Reg, uint32_t *pEFlags));
1323IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t *pu64Dst, uint64_t *pu64Reg, uint32_t *pEFlags));
1324IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t *pu8Dst, uint8_t *pu8Reg, uint32_t *pEFlags));
1325IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t *pu16Dst, uint16_t *pu16Reg, uint32_t *pEFlags));
1326IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t *pu32Dst, uint32_t *pu32Reg, uint32_t *pEFlags));
1327IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t *pu64Dst, uint64_t *pu64Reg, uint32_t *pEFlags));
1328/** @} */
1329
1330/** @name Compare and exchange.
1331 * @{ */
1332IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1333IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1334IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1335IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1336IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1337IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1338#if ARCH_BITS == 32
1339IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags));
1340IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags));
1341#else
1342IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1343IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1344#endif
1345IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1346 uint32_t *pEFlags));
1347IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1348 uint32_t *pEFlags));
1349IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1350 uint32_t *pEFlags));
1351IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1352 uint32_t *pEFlags));
1353#ifndef RT_ARCH_ARM64
1354IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1355 PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1356#endif
1357/** @} */
1358
1359/** @name Memory ordering
1360 * @{ */
1361typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1362typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1363IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1364IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1365IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1366#ifndef RT_ARCH_ARM64
1367IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1368#endif
1369/** @} */
1370
1371/** @name Double precision shifts
1372 * @{ */
1373typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t *pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t *pEFlags));
1374typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1375typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t *pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t *pEFlags));
1376typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1377typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t *pEFlags));
1378typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1379FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1380FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1381FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1382FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1383FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1384FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1385/** @} */
1386
1387
1388/** @name Bit search operations (thrown in with the binary ops).
1389 * @{ */
1390FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1391FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1392FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1393FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1394FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1395FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1396FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1397FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1398FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1399FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1400FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1401FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1402FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1403FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1404FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1405/** @} */
1406
1407/** @name Signed multiplication operations (thrown in with the binary ops).
1408 * @{ */
1409FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1410FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1411FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1412/** @} */
1413
1414/** @name Arithmetic assignment operations on bytes (unary).
1415 * @{ */
1416typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t *pu8Dst, uint32_t *pEFlags));
1417typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1418FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1419FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1420FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1421FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1422/** @} */
1423
1424/** @name Arithmetic assignment operations on words (unary).
1425 * @{ */
1426typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t *pu16Dst, uint32_t *pEFlags));
1427typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1428FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1429FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1430FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1431FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1432/** @} */
1433
1434/** @name Arithmetic assignment operations on double words (unary).
1435 * @{ */
1436typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t *pu32Dst, uint32_t *pEFlags));
1437typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1438FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1439FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1440FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1441FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1442/** @} */
1443
1444/** @name Arithmetic assignment operations on quad words (unary).
1445 * @{ */
1446typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t *pu64Dst, uint32_t *pEFlags));
1447typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1448FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1449FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1450FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1451FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1452/** @} */
1453
1454
1455/** @name Shift operations on bytes (Group 2).
1456 * @{ */
1457typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t *pu8Dst, uint8_t cShift, uint32_t *pEFlags));
1458typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1459FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1460FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1461FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1462FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1463FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1464FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1465FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1466/** @} */
1467
1468/** @name Shift operations on words (Group 2).
1469 * @{ */
1470typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t *pu16Dst, uint8_t cShift, uint32_t *pEFlags));
1471typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1472FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1473FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1474FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1475FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1476FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1477FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1478FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1479/** @} */
1480
1481/** @name Shift operations on double words (Group 2).
1482 * @{ */
1483typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t *pu32Dst, uint8_t cShift, uint32_t *pEFlags));
1484typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1485FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1486FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1487FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1488FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1489FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1490FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1491FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1492/** @} */
1493
1494/** @name Shift operations on words (Group 2).
1495 * @{ */
1496typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t *pu64Dst, uint8_t cShift, uint32_t *pEFlags));
1497typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1498FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1499FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1500FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1501FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1502FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1503FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1504FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1505/** @} */
1506
1507/** @name Multiplication and division operations.
1508 * @{ */
1509typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t *pu16AX, uint8_t u8FactorDivisor, uint32_t *pEFlags));
1510typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1511FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1512FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1513FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1514FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1515
1516typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t *pu16AX, uint16_t *pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1517typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1518FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1519FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1520FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1521FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1522
1523typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t *pu32EAX, uint32_t *pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1524typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1525FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1526FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1527FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1528FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1529
1530typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1531typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1532FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1533FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1534FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1535FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1536/** @} */
1537
1538/** @name Byte Swap.
1539 * @{ */
1540IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t *pu32Dst)); /* Yes, 32-bit register access. */
1541IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1542IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1543/** @} */
1544
1545/** @name Misc.
1546 * @{ */
1547FNIEMAIMPLBINU16 iemAImpl_arpl;
1548/** @} */
1549
1550
1551/** @name FPU operations taking a 32-bit float argument
1552 * @{ */
1553typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1554 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1555typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1556
1557typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1558 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1559typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1560
1561FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1562FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1563FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1564FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1565FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1566FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1567FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1568
1569IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1570IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1571 PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1572/** @} */
1573
1574/** @name FPU operations taking a 64-bit float argument
1575 * @{ */
1576typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1577 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1578typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1579
1580typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1581 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1582typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1583
1584FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1585FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1586FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1587FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1588FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1589FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1590FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1591
1592IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1593IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1594 PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1595/** @} */
1596
1597/** @name FPU operations taking a 80-bit float argument
1598 * @{ */
1599typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1600 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1601typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1602FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1603FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1604FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1605FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1606FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1607FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1608FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1609FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1610FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1611
1612FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1613FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1614FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1615
1616typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1617 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1618typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1619FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1620FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1621
1622typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1623 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1624typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1625FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1626FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1627
1628typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1629typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1630FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1631FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1632FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1633FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1634FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1635FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1636FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1637
1638typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1639typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1640FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1641FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1642
1643typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1644typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1645FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1646FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1647FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1648FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1649FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1650FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1651FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1652
1653typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1654 PCRTFLOAT80U pr80Val));
1655typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1656FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1657FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1658FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1659
1660IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1661IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1662 PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1663
1664IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1665IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1666 PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1667
1668/** @} */
1669
1670/** @name FPU operations taking a 16-bit signed integer argument
1671 * @{ */
1672typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1673 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1674typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1675typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1676 int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1677typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1678
1679FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1680FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1681FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1682FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1683FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1684FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1685
1686typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1687 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1688typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1689FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1690
1691IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1692FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1693FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1694/** @} */
1695
1696/** @name FPU operations taking a 32-bit signed integer argument
1697 * @{ */
1698typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1699 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1700typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1701typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1702 int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1703typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1704
1705FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1706FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1707FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1708FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1709FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1710FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1711
1712typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1713 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1714typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1715FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1716
1717IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1718FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1719FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1720/** @} */
1721
1722/** @name FPU operations taking a 64-bit signed integer argument
1723 * @{ */
1724typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1725 int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1726typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1727
1728IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1729FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1730FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1731/** @} */
1732
1733
1734/** Temporary type representing a 256-bit vector register. */
1735typedef struct { uint64_t au64[4]; } IEMVMM256;
1736/** Temporary type pointing to a 256-bit vector register. */
1737typedef IEMVMM256 *PIEMVMM256;
1738/** Temporary type pointing to a const 256-bit vector register. */
1739typedef IEMVMM256 *PCIEMVMM256;
1740
1741
1742/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1743 * @{ */
1744typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t *puDst, uint64_t const *puSrc));
1745typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1746typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1747typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1748typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1749typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1750typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1751typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1752typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t *puDst, uint64_t const *puSrc));
1753typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1754typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1755typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1756typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1757typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1758typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1759typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1760FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1761FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1762FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1763FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1764FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64;
1765FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64;
1766FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1767FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1768FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64;
1769FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64;
1770FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1771FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1772
1773FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1774FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1775FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1776FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1777FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1778FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1779FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128;
1780FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128;
1781FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1782FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1783FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128;
1784FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128;
1785FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1786FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1787
1788FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
1789FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
1790FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
1791FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
1792FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
1793FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
1794FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
1795FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
1796FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
1797FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
1798FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
1799FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
1800FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
1801FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
1802FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
1803FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
1804FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
1805FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
1806FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
1807FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
1808FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
1809
1810FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
1811FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
1812FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
1813FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
1814FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
1815FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
1816FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
1817FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
1818FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
1819FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
1820FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
1821FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
1822FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
1823FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
1824FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
1825FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
1826FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
1827FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
1828FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
1829FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
1830FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
1831/** @} */
1832
1833/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1834 * @{ */
1835FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1836FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1837FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
1838 iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
1839 iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
1840 iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback;
1841FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
1842 iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
1843 iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
1844 iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback;
1845/** @} */
1846
1847/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1848 * @{ */
1849FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1850FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1851FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
1852 iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
1853 iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
1854 iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
1855FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
1856 iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
1857 iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
1858 iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
1859/** @} */
1860
1861/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1862 * @{ */
1863typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
1864typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
1865typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
1866typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
1867IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t *puDst, uint64_t const *puSrc, uint8_t bEvil));
1868FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
1869#ifndef IEM_WITHOUT_ASSEMBLY
1870FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
1871#endif
1872FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
1873/** @} */
1874
1875/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1876 * @{ */
1877IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t *pu64Dst, uint64_t const *puSrc));
1878IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
1879#ifndef IEM_WITHOUT_ASSEMBLY
1880IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
1881#endif
1882IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
1883/** @} */
1884
1885/** @name Media (SSE/MMX/AVX) operation: Sort this later
1886 * @{ */
1887IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1888IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1889IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1890
1891IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1892IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1893IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1894IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1895
1896/** @} */
1897
1898/** @name Media Odds and Ends
1899 * @{ */
1900typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
1901typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
1902typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
1903typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
1904FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
1905FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
1906FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
1907FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
1908/** @} */
1909
1910
1911/** @name Function tables.
1912 * @{
1913 */
1914
1915/**
1916 * Function table for a binary operator providing implementation based on
1917 * operand size.
1918 */
1919typedef struct IEMOPBINSIZES
1920{
1921 PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1922 PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1923 PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1924 PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1925} IEMOPBINSIZES;
1926/** Pointer to a binary operator function table. */
1927typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1928
1929
1930/**
1931 * Function table for a unary operator providing implementation based on
1932 * operand size.
1933 */
1934typedef struct IEMOPUNARYSIZES
1935{
1936 PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1937 PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1938 PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1939 PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1940} IEMOPUNARYSIZES;
1941/** Pointer to a unary operator function table. */
1942typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1943
1944
1945/**
1946 * Function table for a shift operator providing implementation based on
1947 * operand size.
1948 */
1949typedef struct IEMOPSHIFTSIZES
1950{
1951 PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1952 PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1953 PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1954 PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1955} IEMOPSHIFTSIZES;
1956/** Pointer to a shift operator function table. */
1957typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1958
1959
1960/**
1961 * Function table for a multiplication or division operation.
1962 */
1963typedef struct IEMOPMULDIVSIZES
1964{
1965 PFNIEMAIMPLMULDIVU8 pfnU8;
1966 PFNIEMAIMPLMULDIVU16 pfnU16;
1967 PFNIEMAIMPLMULDIVU32 pfnU32;
1968 PFNIEMAIMPLMULDIVU64 pfnU64;
1969} IEMOPMULDIVSIZES;
1970/** Pointer to a multiplication or division operation function table. */
1971typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1972
1973
1974/**
1975 * Function table for a double precision shift operator providing implementation
1976 * based on operand size.
1977 */
1978typedef struct IEMOPSHIFTDBLSIZES
1979{
1980 PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1981 PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1982 PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1983} IEMOPSHIFTDBLSIZES;
1984/** Pointer to a double precision shift function table. */
1985typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1986
1987
1988/**
1989 * Function table for media instruction taking two full sized media registers,
1990 * optionally the 2nd being a memory reference (only modifying the first op.)
1991 *
1992 * @deprecated This won't be needed as MMX and SSE decoding needs to be handled
1993 * separate from one another.
1994 */
1995typedef struct IEMOPMEDIAF2
1996{
1997 PFNIEMAIMPLMEDIAF2U64 pfnU64;
1998 PFNIEMAIMPLMEDIAF2U128 pfnU128;
1999} IEMOPMEDIAF2;
2000/** Pointer to a media operation function table for full sized ops. */
2001typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
2002
2003/**
2004 * Function table for media instruction taking two full sized media source
2005 * registers and one full sized destination register (AVX).
2006 */
2007typedef struct IEMOPMEDIAF3
2008{
2009 PFNIEMAIMPLMEDIAF3U128 pfnU128;
2010 PFNIEMAIMPLMEDIAF3U256 pfnU256;
2011} IEMOPMEDIAF3;
2012/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2013typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2014
2015/**
2016 * Function table for media instruction taking two full sized media source
2017 * registers and one full sized destination register, but no additional state
2018 * (AVX).
2019 */
2020typedef struct IEMOPMEDIAOPTF3
2021{
2022 PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2023 PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2024} IEMOPMEDIAOPTF3;
2025/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2026typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2027
2028/** @def IEMOPMEDIAOPTF3_INIT_VARS
2029 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2030 * given functions as initializers. For use in AVX functions where a pair of
2031 * functions are only used once and the function table need not be public. */
2032#ifndef TST_IEM_CHECK_MC
2033# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2034# define IEMOPMEDIAOPTF3_INIT_VARS(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2035 static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2036 static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2037# else
2038# define IEMOPMEDIAOPTF3_INIT_VARS(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2039 static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2040# endif
2041#else
2042# define IEMOPMEDIAOPTF3_INIT_VARS(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2043#endif
2044
2045
2046/** @} */
2047
2048
2049/** @name C instruction implementations for anything slightly complicated.
2050 * @{ */
2051
2052/**
2053 * For typedef'ing or declaring a C instruction implementation function taking
2054 * no extra arguments.
2055 *
2056 * @param a_Name The name of the type.
2057 */
2058# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
2059 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2060/**
2061 * For defining a C instruction implementation function taking no extra
2062 * arguments.
2063 *
2064 * @param a_Name The name of the function
2065 */
2066# define IEM_CIMPL_DEF_0(a_Name) \
2067 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2068/**
2069 * Prototype version of IEM_CIMPL_DEF_0.
2070 */
2071# define IEM_CIMPL_PROTO_0(a_Name) \
2072 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2073/**
2074 * For calling a C instruction implementation function taking no extra
2075 * arguments.
2076 *
2077 * This special call macro adds default arguments to the call and allow us to
2078 * change these later.
2079 *
2080 * @param a_fn The name of the function.
2081 */
2082# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
2083
2084/**
2085 * For typedef'ing or declaring a C instruction implementation function taking
2086 * one extra argument.
2087 *
2088 * @param a_Name The name of the type.
2089 * @param a_Type0 The argument type.
2090 * @param a_Arg0 The argument name.
2091 */
2092# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
2093 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2094/**
2095 * For defining a C instruction implementation function taking one extra
2096 * argument.
2097 *
2098 * @param a_Name The name of the function
2099 * @param a_Type0 The argument type.
2100 * @param a_Arg0 The argument name.
2101 */
2102# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
2103 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2104/**
2105 * Prototype version of IEM_CIMPL_DEF_1.
2106 */
2107# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
2108 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2109/**
2110 * For calling a C instruction implementation function taking one extra
2111 * argument.
2112 *
2113 * This special call macro adds default arguments to the call and allow us to
2114 * change these later.
2115 *
2116 * @param a_fn The name of the function.
2117 * @param a0 The name of the 1st argument.
2118 */
2119# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
2120
2121/**
2122 * For typedef'ing or declaring a C instruction implementation function taking
2123 * two extra arguments.
2124 *
2125 * @param a_Name The name of the type.
2126 * @param a_Type0 The type of the 1st argument
2127 * @param a_Arg0 The name of the 1st argument.
2128 * @param a_Type1 The type of the 2nd argument.
2129 * @param a_Arg1 The name of the 2nd argument.
2130 */
2131# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2132 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2133/**
2134 * For defining a C instruction implementation function taking two extra
2135 * arguments.
2136 *
2137 * @param a_Name The name of the function.
2138 * @param a_Type0 The type of the 1st argument
2139 * @param a_Arg0 The name of the 1st argument.
2140 * @param a_Type1 The type of the 2nd argument.
2141 * @param a_Arg1 The name of the 2nd argument.
2142 */
2143# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2144 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2145/**
2146 * Prototype version of IEM_CIMPL_DEF_2.
2147 */
2148# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2149 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2150/**
2151 * For calling a C instruction implementation function taking two extra
2152 * arguments.
2153 *
2154 * This special call macro adds default arguments to the call and allow us to
2155 * change these later.
2156 *
2157 * @param a_fn The name of the function.
2158 * @param a0 The name of the 1st argument.
2159 * @param a1 The name of the 2nd argument.
2160 */
2161# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
2162
2163/**
2164 * For typedef'ing or declaring a C instruction implementation function taking
2165 * three extra arguments.
2166 *
2167 * @param a_Name The name of the type.
2168 * @param a_Type0 The type of the 1st argument
2169 * @param a_Arg0 The name of the 1st argument.
2170 * @param a_Type1 The type of the 2nd argument.
2171 * @param a_Arg1 The name of the 2nd argument.
2172 * @param a_Type2 The type of the 3rd argument.
2173 * @param a_Arg2 The name of the 3rd argument.
2174 */
2175# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2176 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2177/**
2178 * For defining a C instruction implementation function taking three extra
2179 * arguments.
2180 *
2181 * @param a_Name The name of the function.
2182 * @param a_Type0 The type of the 1st argument
2183 * @param a_Arg0 The name of the 1st argument.
2184 * @param a_Type1 The type of the 2nd argument.
2185 * @param a_Arg1 The name of the 2nd argument.
2186 * @param a_Type2 The type of the 3rd argument.
2187 * @param a_Arg2 The name of the 3rd argument.
2188 */
2189# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2190 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2191/**
2192 * Prototype version of IEM_CIMPL_DEF_3.
2193 */
2194# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2195 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2196/**
2197 * For calling a C instruction implementation function taking three extra
2198 * arguments.
2199 *
2200 * This special call macro adds default arguments to the call and allow us to
2201 * change these later.
2202 *
2203 * @param a_fn The name of the function.
2204 * @param a0 The name of the 1st argument.
2205 * @param a1 The name of the 2nd argument.
2206 * @param a2 The name of the 3rd argument.
2207 */
2208# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
2209
2210
2211/**
2212 * For typedef'ing or declaring a C instruction implementation function taking
2213 * four extra arguments.
2214 *
2215 * @param a_Name The name of the type.
2216 * @param a_Type0 The type of the 1st argument
2217 * @param a_Arg0 The name of the 1st argument.
2218 * @param a_Type1 The type of the 2nd argument.
2219 * @param a_Arg1 The name of the 2nd argument.
2220 * @param a_Type2 The type of the 3rd argument.
2221 * @param a_Arg2 The name of the 3rd argument.
2222 * @param a_Type3 The type of the 4th argument.
2223 * @param a_Arg3 The name of the 4th argument.
2224 */
2225# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2226 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
2227/**
2228 * For defining a C instruction implementation function taking four extra
2229 * arguments.
2230 *
2231 * @param a_Name The name of the function.
2232 * @param a_Type0 The type of the 1st argument
2233 * @param a_Arg0 The name of the 1st argument.
2234 * @param a_Type1 The type of the 2nd argument.
2235 * @param a_Arg1 The name of the 2nd argument.
2236 * @param a_Type2 The type of the 3rd argument.
2237 * @param a_Arg2 The name of the 3rd argument.
2238 * @param a_Type3 The type of the 4th argument.
2239 * @param a_Arg3 The name of the 4th argument.
2240 */
2241# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2242 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2243 a_Type2 a_Arg2, a_Type3 a_Arg3))
2244/**
2245 * Prototype version of IEM_CIMPL_DEF_4.
2246 */
2247# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2248 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2249 a_Type2 a_Arg2, a_Type3 a_Arg3))
2250/**
2251 * For calling a C instruction implementation function taking four extra
2252 * arguments.
2253 *
2254 * This special call macro adds default arguments to the call and allow us to
2255 * change these later.
2256 *
2257 * @param a_fn The name of the function.
2258 * @param a0 The name of the 1st argument.
2259 * @param a1 The name of the 2nd argument.
2260 * @param a2 The name of the 3rd argument.
2261 * @param a3 The name of the 4th argument.
2262 */
2263# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
2264
2265
2266/**
2267 * For typedef'ing or declaring a C instruction implementation function taking
2268 * five extra arguments.
2269 *
2270 * @param a_Name The name of the type.
2271 * @param a_Type0 The type of the 1st argument
2272 * @param a_Arg0 The name of the 1st argument.
2273 * @param a_Type1 The type of the 2nd argument.
2274 * @param a_Arg1 The name of the 2nd argument.
2275 * @param a_Type2 The type of the 3rd argument.
2276 * @param a_Arg2 The name of the 3rd argument.
2277 * @param a_Type3 The type of the 4th argument.
2278 * @param a_Arg3 The name of the 4th argument.
2279 * @param a_Type4 The type of the 5th argument.
2280 * @param a_Arg4 The name of the 5th argument.
2281 */
2282# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2283 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
2284 a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
2285 a_Type3 a_Arg3, a_Type4 a_Arg4))
2286/**
2287 * For defining a C instruction implementation function taking five extra
2288 * arguments.
2289 *
2290 * @param a_Name The name of the function.
2291 * @param a_Type0 The type of the 1st argument
2292 * @param a_Arg0 The name of the 1st argument.
2293 * @param a_Type1 The type of the 2nd argument.
2294 * @param a_Arg1 The name of the 2nd argument.
2295 * @param a_Type2 The type of the 3rd argument.
2296 * @param a_Arg2 The name of the 3rd argument.
2297 * @param a_Type3 The type of the 4th argument.
2298 * @param a_Arg3 The name of the 4th argument.
2299 * @param a_Type4 The type of the 5th argument.
2300 * @param a_Arg4 The name of the 5th argument.
2301 */
2302# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2303 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2304 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2305/**
2306 * Prototype version of IEM_CIMPL_DEF_5.
2307 */
2308# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2309 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2310 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2311/**
2312 * For calling a C instruction implementation function taking five extra
2313 * arguments.
2314 *
2315 * This special call macro adds default arguments to the call and allow us to
2316 * change these later.
2317 *
2318 * @param a_fn The name of the function.
2319 * @param a0 The name of the 1st argument.
2320 * @param a1 The name of the 2nd argument.
2321 * @param a2 The name of the 3rd argument.
2322 * @param a3 The name of the 4th argument.
2323 * @param a4 The name of the 5th argument.
2324 */
2325# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
2326
2327/** @} */
2328
2329
2330/** @name Opcode Decoder Function Types.
2331 * @{ */
2332
2333/** @typedef PFNIEMOP
2334 * Pointer to an opcode decoder function.
2335 */
2336
2337/** @def FNIEMOP_DEF
2338 * Define an opcode decoder function.
2339 *
2340 * We're using macors for this so that adding and removing parameters as well as
2341 * tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
2342 *
2343 * @param a_Name The function name.
2344 */
2345
2346/** @typedef PFNIEMOPRM
2347 * Pointer to an opcode decoder function with RM byte.
2348 */
2349
2350/** @def FNIEMOPRM_DEF
2351 * Define an opcode decoder function with RM byte.
2352 *
2353 * We're using macors for this so that adding and removing parameters as well as
2354 * tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
2355 *
2356 * @param a_Name The function name.
2357 */
2358
2359#if defined(__GNUC__) && defined(RT_ARCH_X86)
2360typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
2361typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2362# define FNIEMOP_DEF(a_Name) \
2363 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
2364# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2365 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2366# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2367 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2368
2369#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2370typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
2371typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2372# define FNIEMOP_DEF(a_Name) \
2373 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2374# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2375 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2376# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2377 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2378
2379#elif defined(__GNUC__)
2380typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2381typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2382# define FNIEMOP_DEF(a_Name) \
2383 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
2384# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2385 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2386# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2387 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2388
2389#else
2390typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2391typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2392# define FNIEMOP_DEF(a_Name) \
2393 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2394# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2395 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2396# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2397 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2398
2399#endif
2400#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
2401
2402/**
2403 * Call an opcode decoder function.
2404 *
2405 * We're using macors for this so that adding and removing parameters can be
2406 * done as we please. See FNIEMOP_DEF.
2407 */
2408#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
2409
2410/**
2411 * Call a common opcode decoder function taking one extra argument.
2412 *
2413 * We're using macors for this so that adding and removing parameters can be
2414 * done as we please. See FNIEMOP_DEF_1.
2415 */
2416#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
2417
2418/**
2419 * Call a common opcode decoder function taking one extra argument.
2420 *
2421 * We're using macors for this so that adding and removing parameters can be
2422 * done as we please. See FNIEMOP_DEF_1.
2423 */
2424#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
2425/** @} */
2426
2427
2428/** @name Misc Helpers
2429 * @{ */
2430
2431/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
2432 * due to GCC lacking knowledge about the value range of a switch. */
2433#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
2434
2435/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
2436#define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
2437
2438/**
2439 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2440 * occation.
2441 */
2442#ifdef LOG_ENABLED
2443# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2444 do { \
2445 /*Log*/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
2446 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2447 } while (0)
2448#else
2449# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2450 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2451#endif
2452
2453/**
2454 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2455 * occation using the supplied logger statement.
2456 *
2457 * @param a_LoggerArgs What to log on failure.
2458 */
2459#ifdef LOG_ENABLED
2460# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2461 do { \
2462 LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
2463 /*LogFunc(a_LoggerArgs);*/ \
2464 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2465 } while (0)
2466#else
2467# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2468 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2469#endif
2470
2471/**
2472 * Check if we're currently executing in real or virtual 8086 mode.
2473 *
2474 * @returns @c true if it is, @c false if not.
2475 * @param a_pVCpu The IEM state of the current CPU.
2476 */
2477#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2478
2479/**
2480 * Check if we're currently executing in virtual 8086 mode.
2481 *
2482 * @returns @c true if it is, @c false if not.
2483 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2484 */
2485#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2486
2487/**
2488 * Check if we're currently executing in long mode.
2489 *
2490 * @returns @c true if it is, @c false if not.
2491 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2492 */
2493#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
2494
2495/**
2496 * Check if we're currently executing in a 64-bit code segment.
2497 *
2498 * @returns @c true if it is, @c false if not.
2499 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2500 */
2501#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
2502
2503/**
2504 * Check if we're currently executing in real mode.
2505 *
2506 * @returns @c true if it is, @c false if not.
2507 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2508 */
2509#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
2510
2511/**
2512 * Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
2513 * @returns PCCPUMFEATURES
2514 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2515 */
2516#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
2517
2518/**
2519 * Returns a (const) pointer to the CPUMFEATURES for the host CPU.
2520 * @returns PCCPUMFEATURES
2521 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2522 */
2523#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
2524
2525/**
2526 * Evaluates to true if we're presenting an Intel CPU to the guest.
2527 */
2528#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
2529
2530/**
2531 * Evaluates to true if we're presenting an AMD CPU to the guest.
2532 */
2533#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD || (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
2534
2535/**
2536 * Check if the address is canonical.
2537 */
2538#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
2539
2540/** Checks if the ModR/M byte is in register mode or not. */
2541#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
2542/** Checks if the ModR/M byte is in memory mode or not. */
2543#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
2544
2545/**
2546 * Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
2547 *
2548 * For use during decoding.
2549 */
2550#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | (a_pVCpu)->iem.s.uRexReg )
2551/**
2552 * Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
2553 *
2554 * For use during decoding.
2555 */
2556#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) | (a_pVCpu)->iem.s.uRexB )
2557
2558/**
2559 * Gets the register (reg) part of a ModR/M encoding, without REX.R.
2560 *
2561 * For use during decoding.
2562 */
2563#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
2564/**
2565 * Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
2566 *
2567 * For use during decoding.
2568 */
2569#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
2570
2571/**
2572 * Gets the effective VEX.VVVV value.
2573 *
2574 * The 4th bit is ignored if not 64-bit code.
2575 * @returns effective V-register value.
2576 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2577 */
2578#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
2579 ((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
2580
2581
2582#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2583
2584/**
2585 * Check if the guest has entered VMX root operation.
2586 */
2587# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
2588
2589/**
2590 * Check if the guest has entered VMX non-root operation.
2591 */
2592# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
2593
2594/**
2595 * Check if the nested-guest has the given Pin-based VM-execution control set.
2596 */
2597# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
2598 (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
2599
2600/**
2601 * Check if the nested-guest has the given Processor-based VM-execution control set.
2602 */
2603# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
2604 (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
2605
2606/**
2607 * Check if the nested-guest has the given Secondary Processor-based VM-execution
2608 * control set.
2609 */
2610# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
2611 (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
2612
2613/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
2614# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
2615
2616/** Whether a shadow VMCS is present for the given VCPU. */
2617# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
2618
2619/** Gets the VMXON region pointer. */
2620# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
2621
2622/** Gets the guest-physical address of the current VMCS for the given VCPU. */
2623# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
2624
2625/** Whether a current VMCS is present for the given VCPU. */
2626# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
2627
2628/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
2629# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
2630 do \
2631 { \
2632 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
2633 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
2634 } while (0)
2635
2636/** Clears any current VMCS for the given VCPU. */
2637# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
2638 do \
2639 { \
2640 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
2641 } while (0)
2642
2643/**
2644 * Invokes the VMX VM-exit handler for an instruction intercept.
2645 */
2646# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
2647 do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
2648
2649/**
2650 * Invokes the VMX VM-exit handler for an instruction intercept where the
2651 * instruction provides additional VM-exit information.
2652 */
2653# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
2654 do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
2655
2656/**
2657 * Invokes the VMX VM-exit handler for a task switch.
2658 */
2659# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
2660 do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
2661
2662/**
2663 * Invokes the VMX VM-exit handler for MWAIT.
2664 */
2665# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
2666 do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
2667
2668/**
2669 * Invokes the VMX VM-exit handler for EPT faults.
2670 */
2671# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
2672 do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
2673
2674/**
2675 * Invokes the VMX VM-exit handler.
2676 */
2677# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
2678 do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
2679
2680#else
2681# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
2682# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
2683# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
2684# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
2685# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
2686# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2687# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2688# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2689# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2690# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2691# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
2692
2693#endif
2694
2695#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2696/**
2697 * Check if an SVM control/instruction intercept is set.
2698 */
2699# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
2700 (CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
2701
2702/**
2703 * Check if an SVM read CRx intercept is set.
2704 */
2705# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
2706 (CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
2707
2708/**
2709 * Check if an SVM write CRx intercept is set.
2710 */
2711# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
2712 (CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
2713
2714/**
2715 * Check if an SVM read DRx intercept is set.
2716 */
2717# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
2718 (CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
2719
2720/**
2721 * Check if an SVM write DRx intercept is set.
2722 */
2723# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
2724 (CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
2725
2726/**
2727 * Check if an SVM exception intercept is set.
2728 */
2729# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
2730 (CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
2731
2732/**
2733 * Invokes the SVM \#VMEXIT handler for the nested-guest.
2734 */
2735# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
2736 do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
2737
2738/**
2739 * Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
2740 * corresponding decode assist information.
2741 */
2742# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
2743 do \
2744 { \
2745 uint64_t uExitInfo1; \
2746 if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
2747 && (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
2748 uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK | ((a_iGReg) & 7); \
2749 else \
2750 uExitInfo1 = 0; \
2751 IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
2752 } while (0)
2753
2754/** Check and handles SVM nested-guest instruction intercept and updates
2755 * NRIP if needed.
2756 */
2757# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
2758 do \
2759 { \
2760 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
2761 { \
2762 IEM_SVM_UPDATE_NRIP(a_pVCpu); \
2763 IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
2764 } \
2765 } while (0)
2766
2767/** Checks and handles SVM nested-guest CR0 read intercept. */
2768# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
2769 do \
2770 { \
2771 if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
2772 { /* probably likely */ } \
2773 else \
2774 { \
2775 IEM_SVM_UPDATE_NRIP(a_pVCpu); \
2776 IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
2777 } \
2778 } while (0)
2779
2780/**
2781 * Updates the NextRIP (NRI) field in the nested-guest VMCB.
2782 */
2783# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
2784 do { \
2785 if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
2786 CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
2787 } while (0)
2788
2789#else
2790# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
2791# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
2792# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
2793# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
2794# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
2795# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
2796# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
2797# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
2798# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
2799# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
2800# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
2801
2802#endif
2803
2804/** @} */
2805
2806
2807
2808/**
2809 * Selector descriptor table entry as fetched by iemMemFetchSelDesc.
2810 */
2811typedef union IEMSELDESC
2812{
2813 /** The legacy view. */
2814 X86DESC Legacy;
2815 /** The long mode view. */
2816 X86DESC64 Long;
2817} IEMSELDESC;
2818/** Pointer to a selector descriptor table entry. */
2819typedef IEMSELDESC *PIEMSELDESC;
2820
2821/** @name Raising Exceptions.
2822 * @{ */
2823VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
2824 uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
2825
2826VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
2827 uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
2828#ifdef IEM_WITH_SETJMP
2829DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
2830 uint32_t fFlags, uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
2831#endif
2832VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
2833VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
2834VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
2835VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
2836VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
2837VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2838VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
2839VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
2840VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2841/*VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;*/
2842VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2843VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2844VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2845VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2846VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2847VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
2848#ifdef IEM_WITH_SETJMP
2849DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2850#endif
2851VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2852VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
2853VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2854#ifdef IEM_WITH_SETJMP
2855DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2856#endif
2857VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2858#ifdef IEM_WITH_SETJMP
2859DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2860#endif
2861VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2862#ifdef IEM_WITH_SETJMP
2863DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2864#endif
2865VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
2866#ifdef IEM_WITH_SETJMP
2867DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
2868#endif
2869VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu);
2870VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu);
2871#ifdef IEM_WITH_SETJMP
2872DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2873#endif
2874
2875IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
2876IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
2877IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
2878
2879/**
2880 * Macro for calling iemCImplRaiseDivideError().
2881 *
2882 * This enables us to add/remove arguments and force different levels of
2883 * inlining as we wish.
2884 *
2885 * @return Strict VBox status code.
2886 */
2887#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
2888
2889/**
2890 * Macro for calling iemCImplRaiseInvalidLockPrefix().
2891 *
2892 * This enables us to add/remove arguments and force different levels of
2893 * inlining as we wish.
2894 *
2895 * @return Strict VBox status code.
2896 */
2897#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
2898
2899/**
2900 * Macro for calling iemCImplRaiseInvalidOpcode().
2901 *
2902 * This enables us to add/remove arguments and force different levels of
2903 * inlining as we wish.
2904 *
2905 * @return Strict VBox status code.
2906 */
2907#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
2908/** @} */
2909
2910/** @name Register Access.
2911 * @{ */
2912VBOXSTRICTRC iemRegRipRelativeJumpS8(PVMCPUCC pVCpu, int8_t offNextInstr) RT_NOEXCEPT;
2913VBOXSTRICTRC iemRegRipRelativeJumpS16(PVMCPUCC pVCpu, int16_t offNextInstr) RT_NOEXCEPT;
2914VBOXSTRICTRC iemRegRipRelativeJumpS32(PVMCPUCC pVCpu, int32_t offNextInstr) RT_NOEXCEPT;
2915VBOXSTRICTRC iemRegRipJump(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
2916/** @} */
2917
2918/** @name FPU access and helpers.
2919 * @{ */
2920void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
2921void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2922void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
2923void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
2924void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
2925void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
2926 uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2927void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
2928 uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2929void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2930void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2931void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2932void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2933void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2934void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2935void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
2936void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2937void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
2938void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2939void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
2940void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
2941void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
2942void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
2943void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2944/** @} */
2945
2946/** @name Memory access.
2947 * @{ */
2948
2949/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
2950#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
2951/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
2952 * when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
2953#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
2954/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
2955 * Users include FXSAVE & FXRSTOR. */
2956#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
2957
2958VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
2959 uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
2960VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
2961#ifndef IN_RING3
2962VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
2963#endif
2964void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
2965VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
2966VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2967VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
2968
2969#ifdef IEM_WITH_CODE_TLB
2970void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) RT_NOEXCEPT;
2971#else
2972VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
2973#endif
2974#ifdef IEM_WITH_SETJMP
2975uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2976uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2977uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2978uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2979#else
2980VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
2981VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
2982VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2983VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2984VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
2985VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2986VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2987VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2988VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2989VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2990VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2991#endif
2992
2993VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2994VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2995VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2996VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2997VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2998VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2999VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3000VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3001VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3002VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3003VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3004VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3005VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3006 RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
3007#ifdef IEM_WITH_SETJMP
3008uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3009uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3010uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3011uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3012uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3013void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3014void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3015void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3016void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3017void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3018void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3019#endif
3020
3021VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3022VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3023VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3024VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3025VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
3026
3027VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3028VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3029VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3030VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3031VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3032VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3033VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3034VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3035VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3036#ifdef IEM_WITH_SETJMP
3037void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3038void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3039void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3040void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3041void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3042void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3043void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3044void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3045#endif
3046
3047VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3048 void **ppvMem, uint64_t *puNewRsp) RT_NOEXCEPT;
3049VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
3050VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
3051VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3052VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
3053VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3054VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3055VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3056VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3057VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3058 void const **ppvMem, uint64_t *puNewRsp) RT_NOEXCEPT;
3059VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t cbMem, void const **ppvMem, uint64_t *puNewRsp) RT_NOEXCEPT;
3060VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
3061VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
3062VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
3063VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
3064VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3065VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3066VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3067/** @} */
3068
3069/** @name IEMAllCImpl.cpp
3070 * @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
3071 * @{ */
3072IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
3073IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
3074IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
3075IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
3076IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
3077IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
3078IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
3079IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
3080IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
3081IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
3082IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
3083IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
3084IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3085IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3086IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3087IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3088IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3089IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3090IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3091IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3092IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
3093IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
3094IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
3095IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
3096IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
3097IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
3098IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
3099IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
3100IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
3101IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
3102IEM_CIMPL_PROTO_0(iemCImpl_syscall);
3103IEM_CIMPL_PROTO_0(iemCImpl_sysret);
3104IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
3105IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
3106IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
3107IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
3108IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
3109IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
3110IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
3111IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
3112IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
3113IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3114IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3115IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3116IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3117IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
3118IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3119IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3120IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
3121IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3122IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3123IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
3124IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3125IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3126IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
3127IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
3128IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
3129IEM_CIMPL_PROTO_0(iemCImpl_clts);
3130IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
3131IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
3132IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
3133IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
3134IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
3135IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
3136IEM_CIMPL_PROTO_0(iemCImpl_invd);
3137IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
3138IEM_CIMPL_PROTO_0(iemCImpl_rsm);
3139IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
3140IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
3141IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
3142IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
3143IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
3144IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
3145IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
3146IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
3147IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
3148IEM_CIMPL_PROTO_0(iemCImpl_cli);
3149IEM_CIMPL_PROTO_0(iemCImpl_sti);
3150IEM_CIMPL_PROTO_0(iemCImpl_hlt);
3151IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
3152IEM_CIMPL_PROTO_0(iemCImpl_mwait);
3153IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
3154IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
3155IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
3156IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
3157IEM_CIMPL_PROTO_0(iemCImpl_daa);
3158IEM_CIMPL_PROTO_0(iemCImpl_das);
3159IEM_CIMPL_PROTO_0(iemCImpl_aaa);
3160IEM_CIMPL_PROTO_0(iemCImpl_aas);
3161IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
3162IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
3163IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
3164IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
3165IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
3166 PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
3167IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3168IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
3169IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3170IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3171IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3172IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3173IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3174IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3175IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3176IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3177IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3178IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
3179IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
3180IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
3181IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
3182IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
3183/** @} */
3184
3185/** @name IEMAllCImplStrInstr.cpp.h
3186 * @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
3187 * -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
3188 * @{ */
3189IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
3190IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
3191IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
3192IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
3193IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
3194IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
3195IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
3196IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
3197IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
3198IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3199IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3200
3201IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
3202IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
3203IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
3204IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
3205IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
3206IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
3207IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
3208IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
3209IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
3210IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3211IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3212
3213IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
3214IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
3215IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
3216IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
3217IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
3218IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
3219IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
3220IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
3221IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
3222IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3223IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3224
3225
3226IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
3227IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
3228IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
3229IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
3230IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
3231IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
3232IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
3233IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
3234IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
3235IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3236IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3237
3238IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
3239IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
3240IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
3241IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
3242IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
3243IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
3244IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
3245IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
3246IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
3247IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3248IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3249
3250IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
3251IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
3252IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
3253IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
3254IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
3255IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
3256IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
3257IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
3258IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
3259IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3260IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3261
3262IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
3263IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
3264IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
3265IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
3266IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
3267IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
3268IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
3269IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
3270IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
3271IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3272IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3273
3274
3275IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
3276IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
3277IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
3278IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
3279IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
3280IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
3281IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
3282IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
3283IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
3284IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3285IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3286
3287IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
3288IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
3289IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
3290IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
3291IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
3292IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
3293IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
3294IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
3295IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
3296IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3297IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3298
3299IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
3300IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
3301IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
3302IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
3303IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
3304IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
3305IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
3306IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
3307IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
3308IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3309IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3310
3311IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
3312IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
3313IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
3314IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
3315IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
3316IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
3317IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
3318IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
3319IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
3320IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3321IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3322/** @} */
3323
3324#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3325VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
3326VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
3327VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
3328VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
3329VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
3330VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3331VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
3332VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
3333VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
3334VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3335 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
3336VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3337 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
3338VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3339VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3340VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3341VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3342VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3343VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3344VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
3345VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
3346 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
3347VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
3348VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
3349VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
3350uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
3351void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
3352VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
3353 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
3354bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
3355IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
3356IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
3357IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
3358IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
3359IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3360IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3361IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3362IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
3363IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
3364IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
3365IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
3366IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
3367IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
3368IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
3369IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
3370IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
3371#endif
3372
3373#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3374VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
3375VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3376VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
3377 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
3378VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
3379IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
3380IEM_CIMPL_PROTO_0(iemCImpl_vmload);
3381IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
3382IEM_CIMPL_PROTO_0(iemCImpl_clgi);
3383IEM_CIMPL_PROTO_0(iemCImpl_stgi);
3384IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
3385IEM_CIMPL_PROTO_0(iemCImpl_skinit);
3386IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
3387#endif
3388
3389IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
3390IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
3391IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
3392
3393
3394extern const PFNIEMOP g_apfnOneByteMap[256];
3395
3396/** @} */
3397
3398RT_C_DECLS_END
3399
3400#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
3401
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