IEMInternal.h@ 89975

Last change on this file since 89975 was 89975, checked in by vboxsync, 3 years ago
IEM: Added IEMExecOneIgnoreLock for use with split-lock cases. bugref:10052
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1	/* $Id: IEMInternal.h 89975 2021-06-30 11:02:26Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
19	#define VMM_INCLUDED_SRC_include_IEMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/param.h>
29
30	#include <setjmp.h>
31
32
33	RT_C_DECLS_BEGIN
34
35
36	/** @defgroup grp_iem_int Internals
37	* @ingroup grp_iem
38	* @internal
39	* @{
40	*/
41
42	/** For expanding symbol in slickedit and other products tagging and
43	* crossreferencing IEM symbols. */
44	#ifndef IEM_STATIC
45	# define IEM_STATIC static
46	#endif
47
48	/** @def IEM_WITH_3DNOW
49	* Includes the 3DNow decoding. */
50	#define IEM_WITH_3DNOW
51
52	/** @def IEM_WITH_THREE_0F_38
53	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
54	#define IEM_WITH_THREE_0F_38
55
56	/** @def IEM_WITH_THREE_0F_3A
57	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
58	#define IEM_WITH_THREE_0F_3A
59
60	/** @def IEM_WITH_VEX
61	* Includes the VEX decoding. */
62	#define IEM_WITH_VEX
63
64	/** @def IEM_CFG_TARGET_CPU
65	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
66	*
67	* By default we allow this to be configured by the user via the
68	* CPUM/GuestCpuName config string, but this comes at a slight cost during
69	* decoding. So, for applications of this code where there is no need to
70	* be dynamic wrt target CPU, just modify this define.
71	*/
72	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
73	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
74	#endif
75
76
77	//#define IEM_WITH_CODE_TLB// - work in progress
78
79
80	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
81	/** Instruction statistics. */
82	typedef struct IEMINSTRSTATS
83	{
84	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
85	# include "IEMInstructionStatisticsTmpl.h"
86	# undef IEM_DO_INSTR_STAT
87	} IEMINSTRSTATS;
88	#else
89	struct IEMINSTRSTATS;
90	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
91	#endif
92	/** Pointer to IEM instruction statistics. */
93	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
94
95	/** Finish and move to types.h */
96	typedef union
97	{
98	uint32_t u32;
99	} RTFLOAT32U;
100	typedef RTFLOAT32U *PRTFLOAT32U;
101	typedef RTFLOAT32U const *PCRTFLOAT32U;
102
103
104	/**
105	* Extended operand mode that includes a representation of 8-bit.
106	*
107	* This is used for packing down modes when invoking some C instruction
108	* implementations.
109	*/
110	typedef enum IEMMODEX
111	{
112	IEMMODEX_16BIT = IEMMODE_16BIT,
113	IEMMODEX_32BIT = IEMMODE_32BIT,
114	IEMMODEX_64BIT = IEMMODE_64BIT,
115	IEMMODEX_8BIT
116	} IEMMODEX;
117	AssertCompileSize(IEMMODEX, 4);
118
119
120	/**
121	* Branch types.
122	*/
123	typedef enum IEMBRANCH
124	{
125	IEMBRANCH_JUMP = 1,
126	IEMBRANCH_CALL,
127	IEMBRANCH_TRAP,
128	IEMBRANCH_SOFTWARE_INT,
129	IEMBRANCH_HARDWARE_INT
130	} IEMBRANCH;
131	AssertCompileSize(IEMBRANCH, 4);
132
133
134	/**
135	* INT instruction types.
136	*/
137	typedef enum IEMINT
138	{
139	/** INT n instruction (opcode 0xcd imm). */
140	IEMINT_INTN = 0,
141	/** Single byte INT3 instruction (opcode 0xcc). */
142	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
143	/** Single byte INTO instruction (opcode 0xce). */
144	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
145	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
146	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
147	} IEMINT;
148	AssertCompileSize(IEMINT, 4);
149
150
151	/**
152	* A FPU result.
153	*/
154	typedef struct IEMFPURESULT
155	{
156	/** The output value. */
157	RTFLOAT80U r80Result;
158	/** The output status. */
159	uint16_t FSW;
160	} IEMFPURESULT;
161	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
162	/** Pointer to a FPU result. */
163	typedef IEMFPURESULT *PIEMFPURESULT;
164	/** Pointer to a const FPU result. */
165	typedef IEMFPURESULT const *PCIEMFPURESULT;
166
167
168	/**
169	* A FPU result consisting of two output values and FSW.
170	*/
171	typedef struct IEMFPURESULTTWO
172	{
173	/** The first output value. */
174	RTFLOAT80U r80Result1;
175	/** The output status. */
176	uint16_t FSW;
177	/** The second output value. */
178	RTFLOAT80U r80Result2;
179	} IEMFPURESULTTWO;
180	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
181	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
182	/** Pointer to a FPU result consisting of two output values and FSW. */
183	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
184	/** Pointer to a const FPU result consisting of two output values and FSW. */
185	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
186
187
188	/**
189	* IEM TLB entry.
190	*
191	* Lookup assembly:
192	* @code{.asm}
193	; Calculate tag.
194	mov rax, [VA]
195	shl rax, 16
196	shr rax, 16 + X86_PAGE_SHIFT
197	or rax, [uTlbRevision]
198
199	; Do indexing.
200	movzx ecx, al
201	lea rcx, [pTlbEntries + rcx]
202
203	; Check tag.
204	cmp [rcx + IEMTLBENTRY.uTag], rax
205	jne .TlbMiss
206
207	; Check access.
208	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
209	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
210	cmp rax, [uTlbPhysRev]
211	jne .TlbMiss
212
213	; Calc address and we're done.
214	mov eax, X86_PAGE_OFFSET_MASK
215	and eax, [VA]
216	or rax, [rcx + IEMTLBENTRY.pMappingR3]
217	%ifdef VBOX_WITH_STATISTICS
218	inc qword [cTlbHits]
219	%endif
220	jmp .Done
221
222	.TlbMiss:
223	mov r8d, ACCESS_FLAGS
224	mov rdx, [VA]
225	mov rcx, [pVCpu]
226	call iemTlbTypeMiss
227	.Done:
228
229	@endcode
230	*
231	*/
232	typedef struct IEMTLBENTRY
233	{
234	/** The TLB entry tag.
235	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
236	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
237	*
238	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
239	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
240	* revision wraps around though, the tags needs to be zeroed.
241	*
242	* @note Try use SHRD instruction? After seeing
243	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
244	*/
245	uint64_t uTag;
246	/** Access flags and physical TLB revision.
247	*
248	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
249	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
250	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
251	* - Bit 3 - pgm phys/virt - not directly writable.
252	* - Bit 4 - pgm phys page - not directly readable.
253	* - Bit 5 - currently unused.
254	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
255	* - Bit 7 - tlb entry - pMappingR3 member not valid.
256	* - Bits 63 thru 8 are used for the physical TLB revision number.
257	*
258	* We're using complemented bit meanings here because it makes it easy to check
259	* whether special action is required. For instance a user mode write access
260	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
261	* non-zero result would mean special handling needed because either it wasn't
262	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
263	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
264	* need to check any PTE flag.
265	*/
266	uint64_t fFlagsAndPhysRev;
267	/** The guest physical page address. */
268	uint64_t GCPhys;
269	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
270	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
271	R3PTRTYPE(uint8_t *) pbMappingR3;
272	#else
273	R3R0PTRTYPE(uint8_t *) pbMappingR3;
274	#endif
275	#if HC_ARCH_BITS == 32
276	uint32_t u32Padding1;
277	#endif
278	} IEMTLBENTRY;
279	AssertCompileSize(IEMTLBENTRY, 32);
280	/** Pointer to an IEM TLB entry. */
281	typedef IEMTLBENTRY *PIEMTLBENTRY;
282
283	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
284	* @{ */
285	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
286	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
287	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
288	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
289	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
290	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(5) /*< Page tables: Not dirty (needs to be made dirty on write). /
291	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(6) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
292	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
293	/** @} */
294
295
296	/**
297	* An IEM TLB.
298	*
299	* We've got two of these, one for data and one for instructions.
300	*/
301	typedef struct IEMTLB
302	{
303	/** The TLB entries.
304	* We've choosen 256 because that way we can obtain the result directly from a
305	* 8-bit register without an additional AND instruction. */
306	IEMTLBENTRY aEntries[256];
307	/** The TLB revision.
308	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
309	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
310	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
311	* (The revision zero indicates an invalid TLB entry.)
312	*
313	* The initial value is choosen to cause an early wraparound. */
314	uint64_t uTlbRevision;
315	/** The TLB physical address revision - shadow of PGM variable.
316	*
317	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
318	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
319	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
320	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
321	*
322	* The initial value is choosen to cause an early wraparound. */
323	uint64_t volatile uTlbPhysRev;
324
325	/* Statistics: */
326
327	/** TLB hits (VBOX_WITH_STATISTICS only). */
328	uint64_t cTlbHits;
329	/** TLB misses. */
330	uint32_t cTlbMisses;
331	/** Slow read path. */
332	uint32_t cTlbSlowReadPath;
333	#if 0
334	/** TLB misses because of tag mismatch. */
335	uint32_t cTlbMissesTag;
336	/** TLB misses because of virtual access violation. */
337	uint32_t cTlbMissesVirtAccess;
338	/** TLB misses because of dirty bit. */
339	uint32_t cTlbMissesDirty;
340	/** TLB misses because of MMIO */
341	uint32_t cTlbMissesMmio;
342	/** TLB misses because of write access handlers. */
343	uint32_t cTlbMissesWriteHandler;
344	/** TLB misses because no r3(/r0) mapping. */
345	uint32_t cTlbMissesMapping;
346	#endif
347	/** Alignment padding. */
348	uint32_t au32Padding[3+5];
349	} IEMTLB;
350	AssertCompileSizeAlignment(IEMTLB, 64);
351	/** IEMTLB::uTlbRevision increment. */
352	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
353	/** IEMTLB::uTlbPhysRev increment. */
354	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
355
356
357	/**
358	* The per-CPU IEM state.
359	*/
360	typedef struct IEMCPU
361	{
362	/** Info status code that needs to be propagated to the IEM caller.
363	* This cannot be passed internally, as it would complicate all success
364	* checks within the interpreter making the code larger and almost impossible
365	* to get right. Instead, we'll store status codes to pass on here. Each
366	* source of these codes will perform appropriate sanity checks. */
367	int32_t rcPassUp; /* 0x00 */
368
369	/** The current CPU execution mode (CS). */
370	IEMMODE enmCpuMode; /* 0x04 */
371	/** The CPL. */
372	uint8_t uCpl; /* 0x05 */
373
374	/** Whether to bypass access handlers or not. */
375	bool fBypassHandlers; /* 0x06 */
376	/** Whether to disregard the lock prefix (implied or not). */
377	bool fDisregardLock; /* 0x07 */
378
379	/** @name Decoder state.
380	* @{ */
381	#ifdef IEM_WITH_CODE_TLB
382	/** The offset of the next instruction byte. */
383	uint32_t offInstrNextByte; /* 0x08 */
384	/** The number of bytes available at pbInstrBuf for the current instruction.
385	* This takes the max opcode length into account so that doesn't need to be
386	* checked separately. */
387	uint32_t cbInstrBuf; /* 0x0c */
388	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
389	* This can be NULL if the page isn't mappable for some reason, in which
390	* case we'll do fallback stuff.
391	*
392	* If we're executing an instruction from a user specified buffer,
393	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
394	* aligned pointer but pointer to the user data.
395	*
396	* For instructions crossing pages, this will start on the first page and be
397	* advanced to the next page by the time we've decoded the instruction. This
398	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
399	*/
400	uint8_t const pbInstrBuf; / 0x10 */
401	# if ARCH_BITS == 32
402	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
403	# endif
404	/** The program counter corresponding to pbInstrBuf.
405	* This is set to a non-canonical address when we need to invalidate it. */
406	uint64_t uInstrBufPc; /* 0x18 */
407	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
408	* This takes the CS segment limit into account. */
409	uint16_t cbInstrBufTotal; /* 0x20 */
410	/** Offset into pbInstrBuf of the first byte of the current instruction.
411	* Can be negative to efficiently handle cross page instructions. */
412	int16_t offCurInstrStart; /* 0x22 */
413
414	/** The prefix mask (IEM_OP_PRF_XXX). */
415	uint32_t fPrefixes; /* 0x24 */
416	/** The extra REX ModR/M register field bit (REX.R << 3). */
417	uint8_t uRexReg; /* 0x28 */
418	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
419	* (REX.B << 3). */
420	uint8_t uRexB; /* 0x29 */
421	/** The extra REX SIB index field bit (REX.X << 3). */
422	uint8_t uRexIndex; /* 0x2a */
423
424	/** The effective segment register (X86_SREG_XXX). */
425	uint8_t iEffSeg; /* 0x2b */
426
427	/** The offset of the ModR/M byte relative to the start of the instruction. */
428	uint8_t offModRm; /* 0x2c */
429	#else
430	/** The size of what has currently been fetched into abOpcode. */
431	uint8_t cbOpcode; /* 0x08 */
432	/** The current offset into abOpcode. */
433	uint8_t offOpcode; /* 0x09 */
434	/** The offset of the ModR/M byte relative to the start of the instruction. */
435	uint8_t offModRm; /* 0x0a */
436
437	/** The effective segment register (X86_SREG_XXX). */
438	uint8_t iEffSeg; /* 0x0b */
439
440	/** The prefix mask (IEM_OP_PRF_XXX). */
441	uint32_t fPrefixes; /* 0x0c */
442	/** The extra REX ModR/M register field bit (REX.R << 3). */
443	uint8_t uRexReg; /* 0x10 */
444	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
445	* (REX.B << 3). */
446	uint8_t uRexB; /* 0x11 */
447	/** The extra REX SIB index field bit (REX.X << 3). */
448	uint8_t uRexIndex; /* 0x12 */
449
450	#endif
451
452	/** The effective operand mode. */
453	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
454	/** The default addressing mode. */
455	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
456	/** The effective addressing mode. */
457	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
458	/** The default operand mode. */
459	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
460
461	/** Prefix index (VEX.pp) for two byte and three byte tables. */
462	uint8_t idxPrefix; /* 0x31, 0x17 */
463	/** 3rd VEX/EVEX/XOP register.
464	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
465	uint8_t uVex3rdReg; /* 0x32, 0x18 */
466	/** The VEX/EVEX/XOP length field. */
467	uint8_t uVexLength; /* 0x33, 0x19 */
468	/** Additional EVEX stuff. */
469	uint8_t fEvexStuff; /* 0x34, 0x1a */
470
471	/** Explicit alignment padding. */
472	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
473	/** The FPU opcode (FOP). */
474	uint16_t uFpuOpcode; /* 0x36, 0x1c */
475	#ifndef IEM_WITH_CODE_TLB
476	/** Explicit alignment padding. */
477	uint8_t abAlignment2b[2]; /* 0x1e */
478	#endif
479
480	/** The opcode bytes. */
481	uint8_t abOpcode[15]; /* 0x48, 0x20 */
482	/** Explicit alignment padding. */
483	#ifdef IEM_WITH_CODE_TLB
484	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
485	#else
486	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
487	#endif
488	/** @} */
489
490
491	/** The flags of the current exception / interrupt. */
492	uint32_t fCurXcpt; /* 0x48, 0x48 */
493	/** The current exception / interrupt. */
494	uint8_t uCurXcpt;
495	/** Exception / interrupt recursion depth. */
496	int8_t cXcptRecursions;
497
498	/** The number of active guest memory mappings. */
499	uint8_t cActiveMappings;
500	/** The next unused mapping index. */
501	uint8_t iNextMapping;
502	/** Records for tracking guest memory mappings. */
503	struct
504	{
505	/** The address of the mapped bytes. */
506	void *pv;
507	/** The access flags (IEM_ACCESS_XXX).
508	* IEM_ACCESS_INVALID if the entry is unused. */
509	uint32_t fAccess;
510	#if HC_ARCH_BITS == 64
511	uint32_t u32Alignment4; /*< Alignment padding. /
512	#endif
513	} aMemMappings[3];
514
515	/** Locking records for the mapped memory. */
516	union
517	{
518	PGMPAGEMAPLOCK Lock;
519	uint64_t au64Padding[2];
520	} aMemMappingLocks[3];
521
522	/** Bounce buffer info.
523	* This runs in parallel to aMemMappings. */
524	struct
525	{
526	/** The physical address of the first byte. */
527	RTGCPHYS GCPhysFirst;
528	/** The physical address of the second page. */
529	RTGCPHYS GCPhysSecond;
530	/** The number of bytes in the first page. */
531	uint16_t cbFirst;
532	/** The number of bytes in the second page. */
533	uint16_t cbSecond;
534	/** Whether it's unassigned memory. */
535	bool fUnassigned;
536	/** Explicit alignment padding. */
537	bool afAlignment5[3];
538	} aMemBbMappings[3];
539
540	/** Bounce buffer storage.
541	* This runs in parallel to aMemMappings and aMemBbMappings. */
542	struct
543	{
544	uint8_t ab[512];
545	} aBounceBuffers[3];
546
547
548	/** Pointer set jump buffer - ring-3 context. */
549	R3PTRTYPE(jmp_buf *) pJmpBufR3;
550	/** Pointer set jump buffer - ring-0 context. */
551	R0PTRTYPE(jmp_buf *) pJmpBufR0;
552
553	/** @todo Should move this near @a fCurXcpt later. */
554	/** The CR2 for the current exception / interrupt. */
555	uint64_t uCurXcptCr2;
556	/** The error code for the current exception / interrupt. */
557	uint32_t uCurXcptErr;
558	/** The VMX APIC-access page handler type. */
559	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
560
561	/** @name Statistics
562	* @{ */
563	/** The number of instructions we've executed. */
564	uint32_t cInstructions;
565	/** The number of potential exits. */
566	uint32_t cPotentialExits;
567	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
568	* This may contain uncommitted writes. */
569	uint32_t cbWritten;
570	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
571	uint32_t cRetInstrNotImplemented;
572	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
573	uint32_t cRetAspectNotImplemented;
574	/** Counts informational statuses returned (other than VINF_SUCCESS). */
575	uint32_t cRetInfStatuses;
576	/** Counts other error statuses returned. */
577	uint32_t cRetErrStatuses;
578	/** Number of times rcPassUp has been used. */
579	uint32_t cRetPassUpStatus;
580	/** Number of times RZ left with instruction commit pending for ring-3. */
581	uint32_t cPendingCommit;
582	/** Number of long jumps. */
583	uint32_t cLongJumps;
584	/** @} */
585
586	/** @name Target CPU information.
587	* @{ */
588	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
589	/** The target CPU. */
590	uint32_t uTargetCpu;
591	#else
592	uint32_t u32TargetCpuPadding;
593	#endif
594	/** The CPU vendor. */
595	CPUMCPUVENDOR enmCpuVendor;
596	/** @} */
597
598	/** @name Host CPU information.
599	* @{ */
600	/** The CPU vendor. */
601	CPUMCPUVENDOR enmHostCpuVendor;
602	/** @} */
603
604	/** Counts RDMSR \#GP(0) LogRel(). */
605	uint8_t cLogRelRdMsr;
606	/** Counts WRMSR \#GP(0) LogRel(). */
607	uint8_t cLogRelWrMsr;
608	/** Alignment padding. */
609	uint8_t abAlignment8[50];
610
611	/** Data TLB.
612	* @remarks Must be 64-byte aligned. */
613	IEMTLB DataTlb;
614	/** Instruction TLB.
615	* @remarks Must be 64-byte aligned. */
616	IEMTLB CodeTlb;
617
618	/** Pointer to instruction statistics for ring-0 context. */
619	R0PTRTYPE(PIEMINSTRSTATS) pStatsR0;
620	/** Ring-3 pointer to instruction statistics for non-ring-3 code. */
621	R3PTRTYPE(PIEMINSTRSTATS) pStatsCCR3;
622	/** Pointer to instruction statistics for ring-3 context. */
623	R3PTRTYPE(PIEMINSTRSTATS) pStatsR3;
624	} IEMCPU;
625	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
626	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
627	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
628	/** Pointer to the per-CPU IEM state. */
629	typedef IEMCPU *PIEMCPU;
630	/** Pointer to the const per-CPU IEM state. */
631	typedef IEMCPU const *PCIEMCPU;
632
633
634	/** @def IEM_GET_CTX
635	* Gets the guest CPU context for the calling EMT.
636	* @returns PCPUMCTX
637	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
638	*/
639	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
640
641	/** @def IEM_CTX_ASSERT
642	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
643	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
644	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
645	*/
646	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
647	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
648	(a_fExtrnMbz)))
649
650	/** @def IEM_CTX_IMPORT_RET
651	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
652	*
653	* Will call the keep to import the bits as needed.
654	*
655	* Returns on import failure.
656	*
657	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
658	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
659	*/
660	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
661	do { \
662	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
663	{ /* likely */ } \
664	else \
665	{ \
666	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
667	AssertRCReturn(rcCtxImport, rcCtxImport); \
668	} \
669	} while (0)
670
671	/** @def IEM_CTX_IMPORT_NORET
672	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
673	*
674	* Will call the keep to import the bits as needed.
675	*
676	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
677	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
678	*/
679	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
680	do { \
681	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
682	{ /* likely */ } \
683	else \
684	{ \
685	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
686	AssertLogRelRC(rcCtxImport); \
687	} \
688	} while (0)
689
690	/** @def IEM_CTX_IMPORT_JMP
691	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
692	*
693	* Will call the keep to import the bits as needed.
694	*
695	* Jumps on import failure.
696	*
697	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
698	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
699	*/
700	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
701	do { \
702	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
703	{ /* likely */ } \
704	else \
705	{ \
706	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
707	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
708	} \
709	} while (0)
710
711
712
713	/** @def IEM_GET_TARGET_CPU
714	* Gets the current IEMTARGETCPU value.
715	* @returns IEMTARGETCPU value.
716	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
717	*/
718	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
719	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
720	#else
721	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
722	#endif
723
724	/** @def IEM_GET_INSTR_LEN
725	* Gets the instruction length. */
726	#ifdef IEM_WITH_CODE_TLB
727	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
728	#else
729	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
730	#endif
731
732
733	/** @name IEM_ACCESS_XXX - Access details.
734	* @{ */
735	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
736	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
737	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
738	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
739	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
740	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
741	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
742	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
743	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
744	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
745	/** The writes are partial, so if initialize the bounce buffer with the
746	* orignal RAM content. */
747	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
748	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
749	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
750	/** Bounce buffer with ring-3 write pending, first page. */
751	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
752	/** Bounce buffer with ring-3 write pending, second page. */
753	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
754	/** Valid bit mask. */
755	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
756	/** Read+write data alias. */
757	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
758	/** Write data alias. */
759	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
760	/** Read data alias. */
761	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
762	/** Instruction fetch alias. */
763	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
764	/** Stack write alias. */
765	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
766	/** Stack read alias. */
767	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
768	/** Stack read+write alias. */
769	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
770	/** Read system table alias. */
771	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
772	/** Read+write system table alias. */
773	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
774	/** @} */
775
776	/** @name Prefix constants (IEMCPU::fPrefixes)
777	* @{ */
778	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
779	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
780	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
781	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
782	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
783	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
784	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
785
786	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
787	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
788	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
789
790	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
791	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
792	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
793
794	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
795	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
796	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
797	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
798	/** Mask with all the REX prefix flags.
799	* This is generally for use when needing to undo the REX prefixes when they
800	* are followed legacy prefixes and therefore does not immediately preceed
801	* the first opcode byte.
802	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
803	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
804
805	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
806	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
807	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
808	/** @} */
809
810	/** @name IEMOPFORM_XXX - Opcode forms
811	* @note These are ORed together with IEMOPHINT_XXX.
812	* @{ */
813	/** ModR/M: reg, r/m */
814	#define IEMOPFORM_RM 0
815	/** ModR/M: reg, r/m (register) */
816	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
817	/** ModR/M: reg, r/m (memory) */
818	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
819	/** ModR/M: r/m, reg */
820	#define IEMOPFORM_MR 1
821	/** ModR/M: r/m (register), reg */
822	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
823	/** ModR/M: r/m (memory), reg */
824	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
825	/** ModR/M: r/m only */
826	#define IEMOPFORM_M 2
827	/** ModR/M: r/m only (register). */
828	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
829	/** ModR/M: r/m only (memory). */
830	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
831	/** ModR/M: reg only */
832	#define IEMOPFORM_R 3
833
834	/** VEX+ModR/M: reg, r/m */
835	#define IEMOPFORM_VEX_RM 4
836	/** VEX+ModR/M: reg, r/m (register) */
837	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
838	/** VEX+ModR/M: reg, r/m (memory) */
839	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
840	/** VEX+ModR/M: r/m, reg */
841	#define IEMOPFORM_VEX_MR 5
842	/** VEX+ModR/M: r/m (register), reg */
843	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
844	/** VEX+ModR/M: r/m (memory), reg */
845	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
846	/** VEX+ModR/M: r/m only */
847	#define IEMOPFORM_VEX_M 6
848	/** VEX+ModR/M: r/m only (register). */
849	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
850	/** VEX+ModR/M: r/m only (memory). */
851	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
852	/** VEX+ModR/M: reg only */
853	#define IEMOPFORM_VEX_R 7
854	/** VEX+ModR/M: reg, vvvv, r/m */
855	#define IEMOPFORM_VEX_RVM 8
856	/** VEX+ModR/M: reg, vvvv, r/m (register). */
857	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
858	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
859	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
860	/** VEX+ModR/M: r/m, vvvv, reg */
861	#define IEMOPFORM_VEX_MVR 9
862	/** VEX+ModR/M: r/m, vvvv, reg (register) */
863	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
864	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
865	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
866
867	/** Fixed register instruction, no R/M. */
868	#define IEMOPFORM_FIXED 16
869
870	/** The r/m is a register. */
871	#define IEMOPFORM_MOD3 RT_BIT_32(8)
872	/** The r/m is a memory access. */
873	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
874	/** @} */
875
876	/** @name IEMOPHINT_XXX - Additional Opcode Hints
877	* @note These are ORed together with IEMOPFORM_XXX.
878	* @{ */
879	/** Ignores the operand size prefix (66h). */
880	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
881	/** Ignores REX.W (aka WIG). */
882	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
883	/** Both the operand size prefixes (66h + REX.W) are ignored. */
884	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
885	/** Allowed with the lock prefix. */
886	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
887	/** The VEX.L value is ignored (aka LIG). */
888	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
889	/** The VEX.L value must be zero (i.e. 128-bit width only). */
890	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
891
892	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
893	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
894	/** @} */
895
896	/**
897	* Possible hardware task switch sources.
898	*/
899	typedef enum IEMTASKSWITCH
900	{
901	/** Task switch caused by an interrupt/exception. */
902	IEMTASKSWITCH_INT_XCPT = 1,
903	/** Task switch caused by a far CALL. */
904	IEMTASKSWITCH_CALL,
905	/** Task switch caused by a far JMP. */
906	IEMTASKSWITCH_JUMP,
907	/** Task switch caused by an IRET. */
908	IEMTASKSWITCH_IRET
909	} IEMTASKSWITCH;
910	AssertCompileSize(IEMTASKSWITCH, 4);
911
912	/**
913	* Possible CrX load (write) sources.
914	*/
915	typedef enum IEMACCESSCRX
916	{
917	/** CrX access caused by 'mov crX' instruction. */
918	IEMACCESSCRX_MOV_CRX,
919	/** CrX (CR0) write caused by 'lmsw' instruction. */
920	IEMACCESSCRX_LMSW,
921	/** CrX (CR0) write caused by 'clts' instruction. */
922	IEMACCESSCRX_CLTS,
923	/** CrX (CR0) read caused by 'smsw' instruction. */
924	IEMACCESSCRX_SMSW
925	} IEMACCESSCRX;
926
927	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX
928	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
929	# endif
930
931	/**
932	* Indicates to the verifier that the given flag set is undefined.
933	*
934	* Can be invoked again to add more flags.
935	*
936	* This is a NOOP if the verifier isn't compiled in.
937	*
938	* @note We're temporarily keeping this until code is converted to new
939	* disassembler style opcode handling.
940	*/
941	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
942
943
944	/** @def IEM_DECL_IMPL_TYPE
945	* For typedef'ing an instruction implementation function.
946	*
947	* @param a_RetType The return type.
948	* @param a_Name The name of the type.
949	* @param a_ArgList The argument list enclosed in parentheses.
950	*/
951
952	/** @def IEM_DECL_IMPL_DEF
953	* For defining an instruction implementation function.
954	*
955	* @param a_RetType The return type.
956	* @param a_Name The name of the type.
957	* @param a_ArgList The argument list enclosed in parentheses.
958	*/
959
960	#if defined(__GNUC__) && defined(RT_ARCH_X86)
961	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
962	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
963	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
964	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
965
966	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
967	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
968	a_RetType (__fastcall a_Name) a_ArgList
969	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
970	a_RetType __fastcall a_Name a_ArgList
971
972	#else
973	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
974	a_RetType (VBOXCALL a_Name) a_ArgList
975	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
976	a_RetType VBOXCALL a_Name a_ArgList
977
978	#endif
979
980	/** @name Arithmetic assignment operations on bytes (binary).
981	* @{ */
982	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
983	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
984	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
985	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
986	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
987	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
988	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
989	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
990	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
991	/** @} */
992
993	/** @name Arithmetic assignment operations on words (binary).
994	* @{ */
995	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
996	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
997	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
998	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
999	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1000	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1001	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1002	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1003	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1004	/** @} */
1005
1006	/** @name Arithmetic assignment operations on double words (binary).
1007	* @{ */
1008	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1009	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1010	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1011	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1012	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1013	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1014	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1015	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1016	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1017	/** @} */
1018
1019	/** @name Arithmetic assignment operations on quad words (binary).
1020	* @{ */
1021	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1022	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1023	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1024	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1025	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1026	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1027	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1028	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1029	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1030	/** @} */
1031
1032	/** @name Compare operations (thrown in with the binary ops).
1033	* @{ */
1034	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1035	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1036	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1037	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1038	/** @} */
1039
1040	/** @name Test operations (thrown in with the binary ops).
1041	* @{ */
1042	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1043	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1044	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1045	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1046	/** @} */
1047
1048	/** @name Bit operations operations (thrown in with the binary ops).
1049	* @{ */
1050	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1051	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1052	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1053	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1054	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1055	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1056	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1057	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1058	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1059	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1060	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1061	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1062	/** @} */
1063
1064	/** @name Exchange memory with register operations.
1065	* @{ */
1066	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1067	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1068	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1069	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1070	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1071	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1072	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1073	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1074	/** @} */
1075
1076	/** @name Exchange and add operations.
1077	* @{ */
1078	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1079	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1080	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1081	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1082	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1083	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1084	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1085	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1086	/** @} */
1087
1088	/** @name Compare and exchange.
1089	* @{ */
1090	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1091	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1092	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1093	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1094	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1095	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1096	#ifdef RT_ARCH_X86
1097	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1098	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1099	#else
1100	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1101	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1102	#endif
1103	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1104	uint32_t *pEFlags));
1105	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1106	uint32_t *pEFlags));
1107	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1108	uint32_t *pEFlags));
1109	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1110	uint32_t *pEFlags));
1111	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1112	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1113	/** @} */
1114
1115	/** @name Memory ordering
1116	* @{ */
1117	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1118	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1119	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1120	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1121	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1122	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1123	/** @} */
1124
1125	/** @name Double precision shifts
1126	* @{ */
1127	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1128	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1129	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1130	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1131	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1132	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1133	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1134	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1135	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1136	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1137	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1138	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1139	/** @} */
1140
1141
1142	/** @name Bit search operations (thrown in with the binary ops).
1143	* @{ */
1144	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1145	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1146	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1147	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1148	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1149	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1150	/** @} */
1151
1152	/** @name Signed multiplication operations (thrown in with the binary ops).
1153	* @{ */
1154	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1155	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1156	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1157	/** @} */
1158
1159	/** @name Arithmetic assignment operations on bytes (unary).
1160	* @{ */
1161	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1162	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1163	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1164	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1165	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1166	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1167	/** @} */
1168
1169	/** @name Arithmetic assignment operations on words (unary).
1170	* @{ */
1171	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1172	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1173	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1174	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1175	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1176	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1177	/** @} */
1178
1179	/** @name Arithmetic assignment operations on double words (unary).
1180	* @{ */
1181	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1182	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1183	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1184	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1185	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1186	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1187	/** @} */
1188
1189	/** @name Arithmetic assignment operations on quad words (unary).
1190	* @{ */
1191	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1192	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1193	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1194	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1195	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1196	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1197	/** @} */
1198
1199
1200	/** @name Shift operations on bytes (Group 2).
1201	* @{ */
1202	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1203	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1204	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1205	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1206	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1207	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1208	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1209	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1210	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1211	/** @} */
1212
1213	/** @name Shift operations on words (Group 2).
1214	* @{ */
1215	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1216	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1217	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1218	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1219	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1220	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1221	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1222	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1223	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1224	/** @} */
1225
1226	/** @name Shift operations on double words (Group 2).
1227	* @{ */
1228	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1229	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1230	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1231	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1232	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1233	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1234	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1235	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1236	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1237	/** @} */
1238
1239	/** @name Shift operations on words (Group 2).
1240	* @{ */
1241	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1242	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1243	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1244	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1245	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1246	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1247	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1248	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1249	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1250	/** @} */
1251
1252	/** @name Multiplication and division operations.
1253	* @{ */
1254	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1255	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1256	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1257	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1258
1259	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1260	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1261	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1262	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1263
1264	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1265	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1266	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1267	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1268
1269	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1270	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1271	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1272	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1273	/** @} */
1274
1275	/** @name Byte Swap.
1276	* @{ */
1277	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1278	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1279	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1280	/** @} */
1281
1282	/** @name Misc.
1283	* @{ */
1284	FNIEMAIMPLBINU16 iemAImpl_arpl;
1285	/** @} */
1286
1287
1288	/** @name FPU operations taking a 32-bit float argument
1289	* @{ */
1290	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1291	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1292	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1293
1294	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1295	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1296	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1297
1298	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1299	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1300	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1301	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1302	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1303	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1304	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1305
1306	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1307	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1308	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1309	/** @} */
1310
1311	/** @name FPU operations taking a 64-bit float argument
1312	* @{ */
1313	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1314	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1315	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1316
1317	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1318	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1319	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1320	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1321	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1322	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1323
1324	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1325	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1326	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1327	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1328	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1329	/** @} */
1330
1331	/** @name FPU operations taking a 80-bit float argument
1332	* @{ */
1333	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1334	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1335	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1336	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1337	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1338	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1339	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1340	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1341	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1342	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1343	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1344	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1345
1346	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1347	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80;
1348	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1349
1350	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1351	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1352	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1353	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1354	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1355
1356	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1357	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1358	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1359	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1360	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1361
1362	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1363	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1364	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1365	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1366	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1367	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1368	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1369	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1370	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1371
1372	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1373	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1374	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1375	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1376
1377	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1378	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1379	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1380	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1381	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1382	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1383	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1384	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1385	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1386
1387	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1388	PCRTFLOAT80U pr80Val));
1389	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1390	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1391	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1392	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1393
1394	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1395	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1396	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1397
1398	/** @} */
1399
1400	/** @name FPU operations taking a 16-bit signed integer argument
1401	* @{ */
1402	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1403	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1404	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1405
1406	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1407	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1408	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1409	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1410	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1411	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1412
1413	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1414	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1415
1416	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1417	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1418	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1419	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1420	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1421	/** @} */
1422
1423	/** @name FPU operations taking a 32-bit signed integer argument
1424	* @{ */
1425	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1426	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1427	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1428
1429	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1430	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1431	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1432	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1433	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1434	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1435
1436	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1437	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1438
1439	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1440	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1441	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1442	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1443	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1444	/** @} */
1445
1446	/** @name FPU operations taking a 64-bit signed integer argument
1447	* @{ */
1448	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1449	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1450	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1451
1452	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1453	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1454	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1455	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1456	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1457	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1458
1459	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1460	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1461
1462	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1463	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1464	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1465	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1466	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1467	/** @} */
1468
1469
1470	/** Temporary type representing a 256-bit vector register. */
1471	typedef struct {uint64_t au64[4]; } IEMVMM256;
1472	/** Temporary type pointing to a 256-bit vector register. */
1473	typedef IEMVMM256 *PIEMVMM256;
1474	/** Temporary type pointing to a const 256-bit vector register. */
1475	typedef IEMVMM256 *PCIEMVMM256;
1476
1477
1478	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1479	* @{ */
1480	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1481	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1482	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1483	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1484	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1485	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1486	/** @} */
1487
1488	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1489	* @{ */
1490	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1491	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1492	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1493	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1494	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1495	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1496	/** @} */
1497
1498	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1499	* @{ */
1500	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1501	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1502	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1503	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1504	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1505	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1506	/** @} */
1507
1508	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1509	* @{ */
1510	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1511	PCRTUINT128U pu128Src, uint8_t bEvil));
1512	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1513	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1514	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1515	/** @} */
1516
1517	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1518	* @{ */
1519	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1520	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1521	/** @} */
1522
1523	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1524	* @{ */
1525	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1526	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1527	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1528
1529	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1530	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1531	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1532	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1533
1534	/** @} */
1535
1536
1537	/** @name Function tables.
1538	* @{
1539	*/
1540
1541	/**
1542	* Function table for a binary operator providing implementation based on
1543	* operand size.
1544	*/
1545	typedef struct IEMOPBINSIZES
1546	{
1547	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1548	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1549	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1550	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1551	} IEMOPBINSIZES;
1552	/** Pointer to a binary operator function table. */
1553	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1554
1555
1556	/**
1557	* Function table for a unary operator providing implementation based on
1558	* operand size.
1559	*/
1560	typedef struct IEMOPUNARYSIZES
1561	{
1562	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1563	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1564	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1565	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1566	} IEMOPUNARYSIZES;
1567	/** Pointer to a unary operator function table. */
1568	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1569
1570
1571	/**
1572	* Function table for a shift operator providing implementation based on
1573	* operand size.
1574	*/
1575	typedef struct IEMOPSHIFTSIZES
1576	{
1577	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1578	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1579	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1580	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1581	} IEMOPSHIFTSIZES;
1582	/** Pointer to a shift operator function table. */
1583	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1584
1585
1586	/**
1587	* Function table for a multiplication or division operation.
1588	*/
1589	typedef struct IEMOPMULDIVSIZES
1590	{
1591	PFNIEMAIMPLMULDIVU8 pfnU8;
1592	PFNIEMAIMPLMULDIVU16 pfnU16;
1593	PFNIEMAIMPLMULDIVU32 pfnU32;
1594	PFNIEMAIMPLMULDIVU64 pfnU64;
1595	} IEMOPMULDIVSIZES;
1596	/** Pointer to a multiplication or division operation function table. */
1597	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1598
1599
1600	/**
1601	* Function table for a double precision shift operator providing implementation
1602	* based on operand size.
1603	*/
1604	typedef struct IEMOPSHIFTDBLSIZES
1605	{
1606	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1607	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1608	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1609	} IEMOPSHIFTDBLSIZES;
1610	/** Pointer to a double precision shift function table. */
1611	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1612
1613
1614	/**
1615	* Function table for media instruction taking two full sized media registers,
1616	* optionally the 2nd being a memory reference (only modifying the first op.)
1617	*/
1618	typedef struct IEMOPMEDIAF2
1619	{
1620	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1621	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1622	} IEMOPMEDIAF2;
1623	/** Pointer to a media operation function table for full sized ops. */
1624	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1625
1626	/**
1627	* Function table for media instruction taking taking one full and one lower
1628	* half media register.
1629	*/
1630	typedef struct IEMOPMEDIAF1L1
1631	{
1632	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1633	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1634	} IEMOPMEDIAF1L1;
1635	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1636	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1637
1638	/**
1639	* Function table for media instruction taking taking one full and one high half
1640	* media register.
1641	*/
1642	typedef struct IEMOPMEDIAF1H1
1643	{
1644	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1645	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1646	} IEMOPMEDIAF1H1;
1647	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1648	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1649
1650
1651	/** @} */
1652
1653
1654	/** @name C instruction implementations for anything slightly complicated.
1655	* @{ */
1656
1657	/**
1658	* For typedef'ing or declaring a C instruction implementation function taking
1659	* no extra arguments.
1660	*
1661	* @param a_Name The name of the type.
1662	*/
1663	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1664	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1665	/**
1666	* For defining a C instruction implementation function taking no extra
1667	* arguments.
1668	*
1669	* @param a_Name The name of the function
1670	*/
1671	# define IEM_CIMPL_DEF_0(a_Name) \
1672	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1673	/**
1674	* For calling a C instruction implementation function taking no extra
1675	* arguments.
1676	*
1677	* This special call macro adds default arguments to the call and allow us to
1678	* change these later.
1679	*
1680	* @param a_fn The name of the function.
1681	*/
1682	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1683
1684	/**
1685	* For typedef'ing or declaring a C instruction implementation function taking
1686	* one extra argument.
1687	*
1688	* @param a_Name The name of the type.
1689	* @param a_Type0 The argument type.
1690	* @param a_Arg0 The argument name.
1691	*/
1692	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1693	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1694	/**
1695	* For defining a C instruction implementation function taking one extra
1696	* argument.
1697	*
1698	* @param a_Name The name of the function
1699	* @param a_Type0 The argument type.
1700	* @param a_Arg0 The argument name.
1701	*/
1702	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1703	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1704	/**
1705	* For calling a C instruction implementation function taking one extra
1706	* argument.
1707	*
1708	* This special call macro adds default arguments to the call and allow us to
1709	* change these later.
1710	*
1711	* @param a_fn The name of the function.
1712	* @param a0 The name of the 1st argument.
1713	*/
1714	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1715
1716	/**
1717	* For typedef'ing or declaring a C instruction implementation function taking
1718	* two extra arguments.
1719	*
1720	* @param a_Name The name of the type.
1721	* @param a_Type0 The type of the 1st argument
1722	* @param a_Arg0 The name of the 1st argument.
1723	* @param a_Type1 The type of the 2nd argument.
1724	* @param a_Arg1 The name of the 2nd argument.
1725	*/
1726	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1727	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1728	/**
1729	* For defining a C instruction implementation function taking two extra
1730	* arguments.
1731	*
1732	* @param a_Name The name of the function.
1733	* @param a_Type0 The type of the 1st argument
1734	* @param a_Arg0 The name of the 1st argument.
1735	* @param a_Type1 The type of the 2nd argument.
1736	* @param a_Arg1 The name of the 2nd argument.
1737	*/
1738	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1739	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1740	/**
1741	* For calling a C instruction implementation function taking two extra
1742	* arguments.
1743	*
1744	* This special call macro adds default arguments to the call and allow us to
1745	* change these later.
1746	*
1747	* @param a_fn The name of the function.
1748	* @param a0 The name of the 1st argument.
1749	* @param a1 The name of the 2nd argument.
1750	*/
1751	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1752
1753	/**
1754	* For typedef'ing or declaring a C instruction implementation function taking
1755	* three extra arguments.
1756	*
1757	* @param a_Name The name of the type.
1758	* @param a_Type0 The type of the 1st argument
1759	* @param a_Arg0 The name of the 1st argument.
1760	* @param a_Type1 The type of the 2nd argument.
1761	* @param a_Arg1 The name of the 2nd argument.
1762	* @param a_Type2 The type of the 3rd argument.
1763	* @param a_Arg2 The name of the 3rd argument.
1764	*/
1765	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1766	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1767	/**
1768	* For defining a C instruction implementation function taking three extra
1769	* arguments.
1770	*
1771	* @param a_Name The name of the function.
1772	* @param a_Type0 The type of the 1st argument
1773	* @param a_Arg0 The name of the 1st argument.
1774	* @param a_Type1 The type of the 2nd argument.
1775	* @param a_Arg1 The name of the 2nd argument.
1776	* @param a_Type2 The type of the 3rd argument.
1777	* @param a_Arg2 The name of the 3rd argument.
1778	*/
1779	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1780	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1781	/**
1782	* For calling a C instruction implementation function taking three extra
1783	* arguments.
1784	*
1785	* This special call macro adds default arguments to the call and allow us to
1786	* change these later.
1787	*
1788	* @param a_fn The name of the function.
1789	* @param a0 The name of the 1st argument.
1790	* @param a1 The name of the 2nd argument.
1791	* @param a2 The name of the 3rd argument.
1792	*/
1793	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1794
1795
1796	/**
1797	* For typedef'ing or declaring a C instruction implementation function taking
1798	* four extra arguments.
1799	*
1800	* @param a_Name The name of the type.
1801	* @param a_Type0 The type of the 1st argument
1802	* @param a_Arg0 The name of the 1st argument.
1803	* @param a_Type1 The type of the 2nd argument.
1804	* @param a_Arg1 The name of the 2nd argument.
1805	* @param a_Type2 The type of the 3rd argument.
1806	* @param a_Arg2 The name of the 3rd argument.
1807	* @param a_Type3 The type of the 4th argument.
1808	* @param a_Arg3 The name of the 4th argument.
1809	*/
1810	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1811	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1812	/**
1813	* For defining a C instruction implementation function taking four extra
1814	* arguments.
1815	*
1816	* @param a_Name The name of the function.
1817	* @param a_Type0 The type of the 1st argument
1818	* @param a_Arg0 The name of the 1st argument.
1819	* @param a_Type1 The type of the 2nd argument.
1820	* @param a_Arg1 The name of the 2nd argument.
1821	* @param a_Type2 The type of the 3rd argument.
1822	* @param a_Arg2 The name of the 3rd argument.
1823	* @param a_Type3 The type of the 4th argument.
1824	* @param a_Arg3 The name of the 4th argument.
1825	*/
1826	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1827	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1828	a_Type2 a_Arg2, a_Type3 a_Arg3))
1829	/**
1830	* For calling a C instruction implementation function taking four extra
1831	* arguments.
1832	*
1833	* This special call macro adds default arguments to the call and allow us to
1834	* change these later.
1835	*
1836	* @param a_fn The name of the function.
1837	* @param a0 The name of the 1st argument.
1838	* @param a1 The name of the 2nd argument.
1839	* @param a2 The name of the 3rd argument.
1840	* @param a3 The name of the 4th argument.
1841	*/
1842	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1843
1844
1845	/**
1846	* For typedef'ing or declaring a C instruction implementation function taking
1847	* five extra arguments.
1848	*
1849	* @param a_Name The name of the type.
1850	* @param a_Type0 The type of the 1st argument
1851	* @param a_Arg0 The name of the 1st argument.
1852	* @param a_Type1 The type of the 2nd argument.
1853	* @param a_Arg1 The name of the 2nd argument.
1854	* @param a_Type2 The type of the 3rd argument.
1855	* @param a_Arg2 The name of the 3rd argument.
1856	* @param a_Type3 The type of the 4th argument.
1857	* @param a_Arg3 The name of the 4th argument.
1858	* @param a_Type4 The type of the 5th argument.
1859	* @param a_Arg4 The name of the 5th argument.
1860	*/
1861	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1862	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
1863	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1864	a_Type3 a_Arg3, a_Type4 a_Arg4))
1865	/**
1866	* For defining a C instruction implementation function taking five extra
1867	* arguments.
1868	*
1869	* @param a_Name The name of the function.
1870	* @param a_Type0 The type of the 1st argument
1871	* @param a_Arg0 The name of the 1st argument.
1872	* @param a_Type1 The type of the 2nd argument.
1873	* @param a_Arg1 The name of the 2nd argument.
1874	* @param a_Type2 The type of the 3rd argument.
1875	* @param a_Arg2 The name of the 3rd argument.
1876	* @param a_Type3 The type of the 4th argument.
1877	* @param a_Arg3 The name of the 4th argument.
1878	* @param a_Type4 The type of the 5th argument.
1879	* @param a_Arg4 The name of the 5th argument.
1880	*/
1881	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1882	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
1883	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1884	a_Type3 a_Arg3, a_Type4 a_Arg4))
1885	/**
1886	* For calling a C instruction implementation function taking five extra
1887	* arguments.
1888	*
1889	* This special call macro adds default arguments to the call and allow us to
1890	* change these later.
1891	*
1892	* @param a_fn The name of the function.
1893	* @param a0 The name of the 1st argument.
1894	* @param a1 The name of the 2nd argument.
1895	* @param a2 The name of the 3rd argument.
1896	* @param a3 The name of the 4th argument.
1897	* @param a4 The name of the 5th argument.
1898	*/
1899	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1900
1901	/** @} */
1902
1903
1904	/** @} */
1905
1906	RT_C_DECLS_END
1907
1908	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
1909

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 89975

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