IEMInternal.h@ 77807

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1	/* $Id: IEMInternal.h 76585 2019-01-01 06:31:29Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
19	#define VMM_INCLUDED_SRC_include_IEMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/param.h>
29
30	#include <setjmp.h>
31
32
33	RT_C_DECLS_BEGIN
34
35
36	/** @defgroup grp_iem_int Internals
37	* @ingroup grp_iem
38	* @internal
39	* @{
40	*/
41
42	/** For expanding symbol in slickedit and other products tagging and
43	* crossreferencing IEM symbols. */
44	#ifndef IEM_STATIC
45	# define IEM_STATIC static
46	#endif
47
48	/** @def IEM_WITH_3DNOW
49	* Includes the 3DNow decoding. */
50	#define IEM_WITH_3DNOW
51
52	/** @def IEM_WITH_THREE_0F_38
53	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
54	#define IEM_WITH_THREE_0F_38
55
56	/** @def IEM_WITH_THREE_0F_3A
57	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
58	#define IEM_WITH_THREE_0F_3A
59
60	/** @def IEM_WITH_VEX
61	* Includes the VEX decoding. */
62	#define IEM_WITH_VEX
63
64	/** @def IEM_CFG_TARGET_CPU
65	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
66	*
67	* By default we allow this to be configured by the user via the
68	* CPUM/GuestCpuName config string, but this comes at a slight cost during
69	* decoding. So, for applications of this code where there is no need to
70	* be dynamic wrt target CPU, just modify this define.
71	*/
72	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
73	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
74	#endif
75
76
77	//#define IEM_WITH_CODE_TLB// - work in progress
78
79
80	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
81	/** Instruction statistics. */
82	typedef struct IEMINSTRSTATS
83	{
84	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
85	# include "IEMInstructionStatisticsTmpl.h"
86	# undef IEM_DO_INSTR_STAT
87	} IEMINSTRSTATS;
88	#else
89	struct IEMINSTRSTATS;
90	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
91	#endif
92	/** Pointer to IEM instruction statistics. */
93	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
94
95	/** Finish and move to types.h */
96	typedef union
97	{
98	uint32_t u32;
99	} RTFLOAT32U;
100	typedef RTFLOAT32U *PRTFLOAT32U;
101	typedef RTFLOAT32U const *PCRTFLOAT32U;
102
103
104	/**
105	* Extended operand mode that includes a representation of 8-bit.
106	*
107	* This is used for packing down modes when invoking some C instruction
108	* implementations.
109	*/
110	typedef enum IEMMODEX
111	{
112	IEMMODEX_16BIT = IEMMODE_16BIT,
113	IEMMODEX_32BIT = IEMMODE_32BIT,
114	IEMMODEX_64BIT = IEMMODE_64BIT,
115	IEMMODEX_8BIT
116	} IEMMODEX;
117	AssertCompileSize(IEMMODEX, 4);
118
119
120	/**
121	* Branch types.
122	*/
123	typedef enum IEMBRANCH
124	{
125	IEMBRANCH_JUMP = 1,
126	IEMBRANCH_CALL,
127	IEMBRANCH_TRAP,
128	IEMBRANCH_SOFTWARE_INT,
129	IEMBRANCH_HARDWARE_INT
130	} IEMBRANCH;
131	AssertCompileSize(IEMBRANCH, 4);
132
133
134	/**
135	* INT instruction types.
136	*/
137	typedef enum IEMINT
138	{
139	/** INT n instruction (opcode 0xcd imm). */
140	IEMINT_INTN = 0,
141	/** Single byte INT3 instruction (opcode 0xcc). */
142	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
143	/** Single byte INTO instruction (opcode 0xce). */
144	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
145	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
146	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
147	} IEMINT;
148	AssertCompileSize(IEMINT, 4);
149
150
151	/**
152	* A FPU result.
153	*/
154	typedef struct IEMFPURESULT
155	{
156	/** The output value. */
157	RTFLOAT80U r80Result;
158	/** The output status. */
159	uint16_t FSW;
160	} IEMFPURESULT;
161	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
162	/** Pointer to a FPU result. */
163	typedef IEMFPURESULT *PIEMFPURESULT;
164	/** Pointer to a const FPU result. */
165	typedef IEMFPURESULT const *PCIEMFPURESULT;
166
167
168	/**
169	* A FPU result consisting of two output values and FSW.
170	*/
171	typedef struct IEMFPURESULTTWO
172	{
173	/** The first output value. */
174	RTFLOAT80U r80Result1;
175	/** The output status. */
176	uint16_t FSW;
177	/** The second output value. */
178	RTFLOAT80U r80Result2;
179	} IEMFPURESULTTWO;
180	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
181	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
182	/** Pointer to a FPU result consisting of two output values and FSW. */
183	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
184	/** Pointer to a const FPU result consisting of two output values and FSW. */
185	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
186
187
188	/**
189	* IEM TLB entry.
190	*
191	* Lookup assembly:
192	* @code{.asm}
193	; Calculate tag.
194	mov rax, [VA]
195	shl rax, 16
196	shr rax, 16 + X86_PAGE_SHIFT
197	or rax, [uTlbRevision]
198
199	; Do indexing.
200	movzx ecx, al
201	lea rcx, [pTlbEntries + rcx]
202
203	; Check tag.
204	cmp [rcx + IEMTLBENTRY.uTag], rax
205	jne .TlbMiss
206
207	; Check access.
208	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
209	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
210	cmp rax, [uTlbPhysRev]
211	jne .TlbMiss
212
213	; Calc address and we're done.
214	mov eax, X86_PAGE_OFFSET_MASK
215	and eax, [VA]
216	or rax, [rcx + IEMTLBENTRY.pMappingR3]
217	%ifdef VBOX_WITH_STATISTICS
218	inc qword [cTlbHits]
219	%endif
220	jmp .Done
221
222	.TlbMiss:
223	mov r8d, ACCESS_FLAGS
224	mov rdx, [VA]
225	mov rcx, [pVCpu]
226	call iemTlbTypeMiss
227	.Done:
228
229	@endcode
230	*
231	*/
232	typedef struct IEMTLBENTRY
233	{
234	/** The TLB entry tag.
235	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
236	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
237	*
238	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
239	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
240	* revision wraps around though, the tags needs to be zeroed.
241	*
242	* @note Try use SHRD instruction? After seeing
243	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
244	*/
245	uint64_t uTag;
246	/** Access flags and physical TLB revision.
247	*
248	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
249	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
250	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
251	* - Bit 3 - pgm phys/virt - not directly writable.
252	* - Bit 4 - pgm phys page - not directly readable.
253	* - Bit 5 - currently unused.
254	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
255	* - Bit 7 - tlb entry - pMappingR3 member not valid.
256	* - Bits 63 thru 8 are used for the physical TLB revision number.
257	*
258	* We're using complemented bit meanings here because it makes it easy to check
259	* whether special action is required. For instance a user mode write access
260	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
261	* non-zero result would mean special handling needed because either it wasn't
262	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
263	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
264	* need to check any PTE flag.
265	*/
266	uint64_t fFlagsAndPhysRev;
267	/** The guest physical page address. */
268	uint64_t GCPhys;
269	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
270	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
271	R3PTRTYPE(uint8_t *) pbMappingR3;
272	#else
273	R3R0PTRTYPE(uint8_t *) pbMappingR3;
274	#endif
275	#if HC_ARCH_BITS == 32
276	uint32_t u32Padding1;
277	#endif
278	} IEMTLBENTRY;
279	AssertCompileSize(IEMTLBENTRY, 32);
280	/** Pointer to an IEM TLB entry. */
281	typedef IEMTLBENTRY *PIEMTLBENTRY;
282
283	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
284	* @{ */
285	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
286	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
287	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
288	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
289	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
290	#define IEMTLBE_F_PATCH_CODE RT_BIT_64(5) /*< Code TLB: Patch code (PATM). /
291	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
292	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
293	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
294	/** @} */
295
296
297	/**
298	* An IEM TLB.
299	*
300	* We've got two of these, one for data and one for instructions.
301	*/
302	typedef struct IEMTLB
303	{
304	/** The TLB entries.
305	* We've choosen 256 because that way we can obtain the result directly from a
306	* 8-bit register without an additional AND instruction. */
307	IEMTLBENTRY aEntries[256];
308	/** The TLB revision.
309	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
310	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
311	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
312	* (The revision zero indicates an invalid TLB entry.)
313	*
314	* The initial value is choosen to cause an early wraparound. */
315	uint64_t uTlbRevision;
316	/** The TLB physical address revision - shadow of PGM variable.
317	*
318	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
319	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
320	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
321	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
322	*
323	* The initial value is choosen to cause an early wraparound. */
324	uint64_t volatile uTlbPhysRev;
325
326	/* Statistics: */
327
328	/** TLB hits (VBOX_WITH_STATISTICS only). */
329	uint64_t cTlbHits;
330	/** TLB misses. */
331	uint32_t cTlbMisses;
332	/** Slow read path. */
333	uint32_t cTlbSlowReadPath;
334	#if 0
335	/** TLB misses because of tag mismatch. */
336	uint32_t cTlbMissesTag;
337	/** TLB misses because of virtual access violation. */
338	uint32_t cTlbMissesVirtAccess;
339	/** TLB misses because of dirty bit. */
340	uint32_t cTlbMissesDirty;
341	/** TLB misses because of MMIO */
342	uint32_t cTlbMissesMmio;
343	/** TLB misses because of write access handlers. */
344	uint32_t cTlbMissesWriteHandler;
345	/** TLB misses because no r3(/r0) mapping. */
346	uint32_t cTlbMissesMapping;
347	#endif
348	/** Alignment padding. */
349	uint32_t au32Padding[3+5];
350	} IEMTLB;
351	AssertCompileSizeAlignment(IEMTLB, 64);
352	/** IEMTLB::uTlbRevision increment. */
353	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
354	/** IEMTLB::uTlbPhysRev increment. */
355	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
356
357
358	/**
359	* The per-CPU IEM state.
360	*/
361	typedef struct IEMCPU
362	{
363	/** Info status code that needs to be propagated to the IEM caller.
364	* This cannot be passed internally, as it would complicate all success
365	* checks within the interpreter making the code larger and almost impossible
366	* to get right. Instead, we'll store status codes to pass on here. Each
367	* source of these codes will perform appropriate sanity checks. */
368	int32_t rcPassUp; /* 0x00 */
369
370	/** The current CPU execution mode (CS). */
371	IEMMODE enmCpuMode; /* 0x04 */
372	/** The CPL. */
373	uint8_t uCpl; /* 0x05 */
374
375	/** Whether to bypass access handlers or not. */
376	bool fBypassHandlers; /* 0x06 */
377	/** Indicates that we're interpreting patch code - RC only! */
378	bool fInPatchCode; /* 0x07 */
379
380	/** @name Decoder state.
381	* @{ */
382	#ifdef IEM_WITH_CODE_TLB
383	/** The offset of the next instruction byte. */
384	uint32_t offInstrNextByte; /* 0x08 */
385	/** The number of bytes available at pbInstrBuf for the current instruction.
386	* This takes the max opcode length into account so that doesn't need to be
387	* checked separately. */
388	uint32_t cbInstrBuf; /* 0x0c */
389	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
390	* This can be NULL if the page isn't mappable for some reason, in which
391	* case we'll do fallback stuff.
392	*
393	* If we're executing an instruction from a user specified buffer,
394	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
395	* aligned pointer but pointer to the user data.
396	*
397	* For instructions crossing pages, this will start on the first page and be
398	* advanced to the next page by the time we've decoded the instruction. This
399	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
400	*/
401	uint8_t const pbInstrBuf; / 0x10 */
402	# if ARCH_BITS == 32
403	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
404	# endif
405	/** The program counter corresponding to pbInstrBuf.
406	* This is set to a non-canonical address when we need to invalidate it. */
407	uint64_t uInstrBufPc; /* 0x18 */
408	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
409	* This takes the CS segment limit into account. */
410	uint16_t cbInstrBufTotal; /* 0x20 */
411	/** Offset into pbInstrBuf of the first byte of the current instruction.
412	* Can be negative to efficiently handle cross page instructions. */
413	int16_t offCurInstrStart; /* 0x22 */
414
415	/** The prefix mask (IEM_OP_PRF_XXX). */
416	uint32_t fPrefixes; /* 0x24 */
417	/** The extra REX ModR/M register field bit (REX.R << 3). */
418	uint8_t uRexReg; /* 0x28 */
419	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
420	* (REX.B << 3). */
421	uint8_t uRexB; /* 0x29 */
422	/** The extra REX SIB index field bit (REX.X << 3). */
423	uint8_t uRexIndex; /* 0x2a */
424
425	/** The effective segment register (X86_SREG_XXX). */
426	uint8_t iEffSeg; /* 0x2b */
427
428	/** The offset of the ModR/M byte relative to the start of the instruction. */
429	uint8_t offModRm; /* 0x2c */
430	#else
431	/** The size of what has currently been fetched into abOpcode. */
432	uint8_t cbOpcode; /* 0x08 */
433	/** The current offset into abOpcode. */
434	uint8_t offOpcode; /* 0x09 */
435	/** The offset of the ModR/M byte relative to the start of the instruction. */
436	uint8_t offModRm; /* 0x0a */
437
438	/** The effective segment register (X86_SREG_XXX). */
439	uint8_t iEffSeg; /* 0x0b */
440
441	/** The prefix mask (IEM_OP_PRF_XXX). */
442	uint32_t fPrefixes; /* 0x0c */
443	/** The extra REX ModR/M register field bit (REX.R << 3). */
444	uint8_t uRexReg; /* 0x10 */
445	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
446	* (REX.B << 3). */
447	uint8_t uRexB; /* 0x11 */
448	/** The extra REX SIB index field bit (REX.X << 3). */
449	uint8_t uRexIndex; /* 0x12 */
450
451	#endif
452
453	/** The effective operand mode. */
454	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
455	/** The default addressing mode. */
456	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
457	/** The effective addressing mode. */
458	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
459	/** The default operand mode. */
460	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
461
462	/** Prefix index (VEX.pp) for two byte and three byte tables. */
463	uint8_t idxPrefix; /* 0x31, 0x17 */
464	/** 3rd VEX/EVEX/XOP register.
465	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
466	uint8_t uVex3rdReg; /* 0x32, 0x18 */
467	/** The VEX/EVEX/XOP length field. */
468	uint8_t uVexLength; /* 0x33, 0x19 */
469	/** Additional EVEX stuff. */
470	uint8_t fEvexStuff; /* 0x34, 0x1a */
471
472	/** Explicit alignment padding. */
473	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
474	/** The FPU opcode (FOP). */
475	uint16_t uFpuOpcode; /* 0x36, 0x1c */
476	#ifndef IEM_WITH_CODE_TLB
477	/** Explicit alignment padding. */
478	uint8_t abAlignment2b[2]; /* 0x1e */
479	#endif
480
481	/** The opcode bytes. */
482	uint8_t abOpcode[15]; /* 0x48, 0x20 */
483	/** Explicit alignment padding. */
484	#ifdef IEM_WITH_CODE_TLB
485	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
486	#else
487	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
488	#endif
489	/** @} */
490
491
492	/** The flags of the current exception / interrupt. */
493	uint32_t fCurXcpt; /* 0x48, 0x48 */
494	/** The current exception / interrupt. */
495	uint8_t uCurXcpt;
496	/** Exception / interrupt recursion depth. */
497	int8_t cXcptRecursions;
498
499	/** The number of active guest memory mappings. */
500	uint8_t cActiveMappings;
501	/** The next unused mapping index. */
502	uint8_t iNextMapping;
503	/** Records for tracking guest memory mappings. */
504	struct
505	{
506	/** The address of the mapped bytes. */
507	void *pv;
508	#if defined(IN_RC) && HC_ARCH_BITS == 64
509	uint32_t u32Alignment3; /*< Alignment padding. /
510	#endif
511	/** The access flags (IEM_ACCESS_XXX).
512	* IEM_ACCESS_INVALID if the entry is unused. */
513	uint32_t fAccess;
514	#if HC_ARCH_BITS == 64
515	uint32_t u32Alignment4; /*< Alignment padding. /
516	#endif
517	} aMemMappings[3];
518
519	/** Locking records for the mapped memory. */
520	union
521	{
522	PGMPAGEMAPLOCK Lock;
523	uint64_t au64Padding[2];
524	} aMemMappingLocks[3];
525
526	/** Bounce buffer info.
527	* This runs in parallel to aMemMappings. */
528	struct
529	{
530	/** The physical address of the first byte. */
531	RTGCPHYS GCPhysFirst;
532	/** The physical address of the second page. */
533	RTGCPHYS GCPhysSecond;
534	/** The number of bytes in the first page. */
535	uint16_t cbFirst;
536	/** The number of bytes in the second page. */
537	uint16_t cbSecond;
538	/** Whether it's unassigned memory. */
539	bool fUnassigned;
540	/** Explicit alignment padding. */
541	bool afAlignment5[3];
542	} aMemBbMappings[3];
543
544	/** Bounce buffer storage.
545	* This runs in parallel to aMemMappings and aMemBbMappings. */
546	struct
547	{
548	uint8_t ab[512];
549	} aBounceBuffers[3];
550
551
552	/** Pointer set jump buffer - ring-3 context. */
553	R3PTRTYPE(jmp_buf *) pJmpBufR3;
554	/** Pointer set jump buffer - ring-0 context. */
555	R0PTRTYPE(jmp_buf *) pJmpBufR0;
556	/** Pointer set jump buffer - raw-mode context. */
557	RCPTRTYPE(jmp_buf *) pJmpBufRC;
558
559	/** @todo Should move this near @a fCurXcpt later. */
560	/** The error code for the current exception / interrupt. */
561	uint32_t uCurXcptErr;
562	/** The CR2 for the current exception / interrupt. */
563	uint64_t uCurXcptCr2;
564	/** The VMX APIC-access page handler type. */
565	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
566
567	/** @name Statistics
568	* @{ */
569	/** The number of instructions we've executed. */
570	uint32_t cInstructions;
571	/** The number of potential exits. */
572	uint32_t cPotentialExits;
573	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
574	* This may contain uncommitted writes. */
575	uint32_t cbWritten;
576	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
577	uint32_t cRetInstrNotImplemented;
578	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
579	uint32_t cRetAspectNotImplemented;
580	/** Counts informational statuses returned (other than VINF_SUCCESS). */
581	uint32_t cRetInfStatuses;
582	/** Counts other error statuses returned. */
583	uint32_t cRetErrStatuses;
584	/** Number of times rcPassUp has been used. */
585	uint32_t cRetPassUpStatus;
586	/** Number of times RZ left with instruction commit pending for ring-3. */
587	uint32_t cPendingCommit;
588	/** Number of long jumps. */
589	uint32_t cLongJumps;
590	/** @} */
591
592	/** @name Target CPU information.
593	* @{ */
594	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
595	/** The target CPU. */
596	uint32_t uTargetCpu;
597	#else
598	uint32_t u32TargetCpuPadding;
599	#endif
600	/** The CPU vendor. */
601	CPUMCPUVENDOR enmCpuVendor;
602	/** @} */
603
604	/** @name Host CPU information.
605	* @{ */
606	/** The CPU vendor. */
607	CPUMCPUVENDOR enmHostCpuVendor;
608	/** @} */
609
610	/** Counts RDMSR \#GP(0) LogRel(). */
611	uint8_t cLogRelRdMsr;
612	/** Counts WRMSR \#GP(0) LogRel(). */
613	uint8_t cLogRelWrMsr;
614	/** Alignment padding. */
615	uint8_t abAlignment8[HC_ARCH_BITS == 64 ? 46 : 14];
616
617	/** Data TLB.
618	* @remarks Must be 64-byte aligned. */
619	IEMTLB DataTlb;
620	/** Instruction TLB.
621	* @remarks Must be 64-byte aligned. */
622	IEMTLB CodeTlb;
623
624	/** Pointer to instruction statistics for raw-mode context (same as R0). */
625	RCPTRTYPE(PIEMINSTRSTATS) pStatsRC;
626	/** Alignment padding. */
627	RTRCPTR RCPtrPadding;
628	/** Pointer to instruction statistics for ring-0 context (same as RC). */
629	R0PTRTYPE(PIEMINSTRSTATS) pStatsR0;
630	/** Pointer to instruction statistics for non-ring-3 code. */
631	R3PTRTYPE(PIEMINSTRSTATS) pStatsCCR3;
632	/** Pointer to instruction statistics for ring-3 context. */
633	R3PTRTYPE(PIEMINSTRSTATS) pStatsR3;
634	} IEMCPU;
635	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
636	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
637	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
638	/** Pointer to the per-CPU IEM state. */
639	typedef IEMCPU *PIEMCPU;
640	/** Pointer to the const per-CPU IEM state. */
641	typedef IEMCPU const *PCIEMCPU;
642
643
644	/** @def IEM_GET_CTX
645	* Gets the guest CPU context for the calling EMT.
646	* @returns PCPUMCTX
647	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
648	*/
649	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
650
651	/** @def IEM_CTX_ASSERT
652	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
653	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
654	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
655	*/
656	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
657	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
658	(a_fExtrnMbz)))
659
660	/** @def IEM_CTX_IMPORT_RET
661	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
662	*
663	* Will call the keep to import the bits as needed.
664	*
665	* Returns on import failure.
666	*
667	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
668	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
669	*/
670	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
671	do { \
672	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
673	{ /* likely */ } \
674	else \
675	{ \
676	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
677	AssertRCReturn(rcCtxImport, rcCtxImport); \
678	} \
679	} while (0)
680
681	/** @def IEM_CTX_IMPORT_NORET
682	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
683	*
684	* Will call the keep to import the bits as needed.
685	*
686	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
687	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
688	*/
689	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
690	do { \
691	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
692	{ /* likely */ } \
693	else \
694	{ \
695	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
696	AssertLogRelRC(rcCtxImport); \
697	} \
698	} while (0)
699
700	/** @def IEM_CTX_IMPORT_JMP
701	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
702	*
703	* Will call the keep to import the bits as needed.
704	*
705	* Jumps on import failure.
706	*
707	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
708	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
709	*/
710	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
711	do { \
712	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
713	{ /* likely */ } \
714	else \
715	{ \
716	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
717	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
718	} \
719	} while (0)
720
721
722
723	/** Gets the current IEMTARGETCPU value.
724	* @returns IEMTARGETCPU value.
725	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
726	*/
727	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
728	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
729	#else
730	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
731	#endif
732
733	/** @def Gets the instruction length. */
734	#ifdef IEM_WITH_CODE_TLB
735	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
736	#else
737	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
738	#endif
739
740
741	/** @name IEM_ACCESS_XXX - Access details.
742	* @{ */
743	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
744	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
745	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
746	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
747	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
748	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
749	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
750	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
751	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
752	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
753	/** The writes are partial, so if initialize the bounce buffer with the
754	* orignal RAM content. */
755	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
756	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
757	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
758	/** Bounce buffer with ring-3 write pending, first page. */
759	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
760	/** Bounce buffer with ring-3 write pending, second page. */
761	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
762	/** Valid bit mask. */
763	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
764	/** Read+write data alias. */
765	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
766	/** Write data alias. */
767	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
768	/** Read data alias. */
769	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
770	/** Instruction fetch alias. */
771	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
772	/** Stack write alias. */
773	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
774	/** Stack read alias. */
775	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
776	/** Stack read+write alias. */
777	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
778	/** Read system table alias. */
779	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
780	/** Read+write system table alias. */
781	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
782	/** @} */
783
784	/** @name Prefix constants (IEMCPU::fPrefixes)
785	* @{ */
786	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
787	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
788	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
789	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
790	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
791	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
792	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
793
794	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
795	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
796	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
797
798	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
799	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
800	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
801
802	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
803	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
804	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
805	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
806	/** Mask with all the REX prefix flags.
807	* This is generally for use when needing to undo the REX prefixes when they
808	* are followed legacy prefixes and therefore does not immediately preceed
809	* the first opcode byte.
810	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
811	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
812
813	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
814	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
815	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
816	/** @} */
817
818	/** @name IEMOPFORM_XXX - Opcode forms
819	* @note These are ORed together with IEMOPHINT_XXX.
820	* @{ */
821	/** ModR/M: reg, r/m */
822	#define IEMOPFORM_RM 0
823	/** ModR/M: reg, r/m (register) */
824	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
825	/** ModR/M: reg, r/m (memory) */
826	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
827	/** ModR/M: r/m, reg */
828	#define IEMOPFORM_MR 1
829	/** ModR/M: r/m (register), reg */
830	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
831	/** ModR/M: r/m (memory), reg */
832	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
833	/** ModR/M: r/m only */
834	#define IEMOPFORM_M 2
835	/** ModR/M: r/m only (register). */
836	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
837	/** ModR/M: r/m only (memory). */
838	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
839	/** ModR/M: reg only */
840	#define IEMOPFORM_R 3
841
842	/** VEX+ModR/M: reg, r/m */
843	#define IEMOPFORM_VEX_RM 4
844	/** VEX+ModR/M: reg, r/m (register) */
845	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
846	/** VEX+ModR/M: reg, r/m (memory) */
847	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
848	/** VEX+ModR/M: r/m, reg */
849	#define IEMOPFORM_VEX_MR 5
850	/** VEX+ModR/M: r/m (register), reg */
851	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
852	/** VEX+ModR/M: r/m (memory), reg */
853	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
854	/** VEX+ModR/M: r/m only */
855	#define IEMOPFORM_VEX_M 6
856	/** VEX+ModR/M: r/m only (register). */
857	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
858	/** VEX+ModR/M: r/m only (memory). */
859	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
860	/** VEX+ModR/M: reg only */
861	#define IEMOPFORM_VEX_R 7
862	/** VEX+ModR/M: reg, vvvv, r/m */
863	#define IEMOPFORM_VEX_RVM 8
864	/** VEX+ModR/M: reg, vvvv, r/m (register). */
865	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
866	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
867	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
868	/** VEX+ModR/M: r/m, vvvv, reg */
869	#define IEMOPFORM_VEX_MVR 9
870	/** VEX+ModR/M: r/m, vvvv, reg (register) */
871	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
872	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
873	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
874
875	/** Fixed register instruction, no R/M. */
876	#define IEMOPFORM_FIXED 16
877
878	/** The r/m is a register. */
879	#define IEMOPFORM_MOD3 RT_BIT_32(8)
880	/** The r/m is a memory access. */
881	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
882	/** @} */
883
884	/** @name IEMOPHINT_XXX - Additional Opcode Hints
885	* @note These are ORed together with IEMOPFORM_XXX.
886	* @{ */
887	/** Ignores the operand size prefix (66h). */
888	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
889	/** Ignores REX.W (aka WIG). */
890	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
891	/** Both the operand size prefixes (66h + REX.W) are ignored. */
892	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
893	/** Allowed with the lock prefix. */
894	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
895	/** The VEX.L value is ignored (aka LIG). */
896	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
897	/** The VEX.L value must be zero (i.e. 128-bit width only). */
898	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
899
900	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
901	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
902	/** @} */
903
904	/**
905	* Possible hardware task switch sources.
906	*/
907	typedef enum IEMTASKSWITCH
908	{
909	/** Task switch caused by an interrupt/exception. */
910	IEMTASKSWITCH_INT_XCPT = 1,
911	/** Task switch caused by a far CALL. */
912	IEMTASKSWITCH_CALL,
913	/** Task switch caused by a far JMP. */
914	IEMTASKSWITCH_JUMP,
915	/** Task switch caused by an IRET. */
916	IEMTASKSWITCH_IRET
917	} IEMTASKSWITCH;
918	AssertCompileSize(IEMTASKSWITCH, 4);
919
920	/**
921	* Possible CrX load (write) sources.
922	*/
923	typedef enum IEMACCESSCRX
924	{
925	/** CrX access caused by 'mov crX' instruction. */
926	IEMACCESSCRX_MOV_CRX,
927	/** CrX (CR0) write caused by 'lmsw' instruction. */
928	IEMACCESSCRX_LMSW,
929	/** CrX (CR0) write caused by 'clts' instruction. */
930	IEMACCESSCRX_CLTS,
931	/** CrX (CR0) read caused by 'smsw' instruction. */
932	IEMACCESSCRX_SMSW
933	} IEMACCESSCRX;
934
935	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX
936	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
937	# endif
938
939	/**
940	* Indicates to the verifier that the given flag set is undefined.
941	*
942	* Can be invoked again to add more flags.
943	*
944	* This is a NOOP if the verifier isn't compiled in.
945	*
946	* @note We're temporarily keeping this until code is converted to new
947	* disassembler style opcode handling.
948	*/
949	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
950
951
952	/** @def IEM_DECL_IMPL_TYPE
953	* For typedef'ing an instruction implementation function.
954	*
955	* @param a_RetType The return type.
956	* @param a_Name The name of the type.
957	* @param a_ArgList The argument list enclosed in parentheses.
958	*/
959
960	/** @def IEM_DECL_IMPL_DEF
961	* For defining an instruction implementation function.
962	*
963	* @param a_RetType The return type.
964	* @param a_Name The name of the type.
965	* @param a_ArgList The argument list enclosed in parentheses.
966	*/
967
968	#if defined(__GNUC__) && defined(RT_ARCH_X86)
969	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
970	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
971	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
972	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
973
974	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
975	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
976	a_RetType (__fastcall a_Name) a_ArgList
977	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
978	a_RetType __fastcall a_Name a_ArgList
979
980	#else
981	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
982	a_RetType (VBOXCALL a_Name) a_ArgList
983	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
984	a_RetType VBOXCALL a_Name a_ArgList
985
986	#endif
987
988	/** @name Arithmetic assignment operations on bytes (binary).
989	* @{ */
990	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
991	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
992	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
993	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
994	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
995	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
996	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
997	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
998	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
999	/** @} */
1000
1001	/** @name Arithmetic assignment operations on words (binary).
1002	* @{ */
1003	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1004	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1005	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1006	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1007	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1008	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1009	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1010	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1011	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1012	/** @} */
1013
1014	/** @name Arithmetic assignment operations on double words (binary).
1015	* @{ */
1016	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1017	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1018	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1019	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1020	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1021	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1022	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1023	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1024	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1025	/** @} */
1026
1027	/** @name Arithmetic assignment operations on quad words (binary).
1028	* @{ */
1029	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1030	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1031	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1032	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1033	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1034	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1035	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1036	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1037	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1038	/** @} */
1039
1040	/** @name Compare operations (thrown in with the binary ops).
1041	* @{ */
1042	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1043	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1044	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1045	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1046	/** @} */
1047
1048	/** @name Test operations (thrown in with the binary ops).
1049	* @{ */
1050	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1051	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1052	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1053	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1054	/** @} */
1055
1056	/** @name Bit operations operations (thrown in with the binary ops).
1057	* @{ */
1058	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1059	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1060	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1061	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1062	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1063	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1064	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1065	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1066	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1067	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1068	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1069	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1070	/** @} */
1071
1072	/** @name Exchange memory with register operations.
1073	* @{ */
1074	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
1075	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
1076	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
1077	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
1078	/** @} */
1079
1080	/** @name Exchange and add operations.
1081	* @{ */
1082	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1083	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1084	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1085	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1086	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1087	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1088	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1089	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1090	/** @} */
1091
1092	/** @name Compare and exchange.
1093	* @{ */
1094	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1095	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1096	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1097	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1098	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1099	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1100	#ifdef RT_ARCH_X86
1101	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1102	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1103	#else
1104	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1105	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1106	#endif
1107	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1108	uint32_t *pEFlags));
1109	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1110	uint32_t *pEFlags));
1111	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1112	uint32_t *pEFlags));
1113	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1114	uint32_t *pEFlags));
1115	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1116	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1117	/** @} */
1118
1119	/** @name Memory ordering
1120	* @{ */
1121	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1122	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1123	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1124	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1125	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1126	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1127	/** @} */
1128
1129	/** @name Double precision shifts
1130	* @{ */
1131	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1132	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1133	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1134	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1135	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1136	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1137	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1138	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1139	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1140	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1141	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1142	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1143	/** @} */
1144
1145
1146	/** @name Bit search operations (thrown in with the binary ops).
1147	* @{ */
1148	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1149	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1150	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1151	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1152	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1153	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1154	/** @} */
1155
1156	/** @name Signed multiplication operations (thrown in with the binary ops).
1157	* @{ */
1158	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1159	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1160	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1161	/** @} */
1162
1163	/** @name Arithmetic assignment operations on bytes (unary).
1164	* @{ */
1165	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1166	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1167	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1168	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1169	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1170	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1171	/** @} */
1172
1173	/** @name Arithmetic assignment operations on words (unary).
1174	* @{ */
1175	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1176	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1177	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1178	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1179	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1180	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1181	/** @} */
1182
1183	/** @name Arithmetic assignment operations on double words (unary).
1184	* @{ */
1185	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1186	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1187	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1188	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1189	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1190	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1191	/** @} */
1192
1193	/** @name Arithmetic assignment operations on quad words (unary).
1194	* @{ */
1195	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1196	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1197	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1198	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1199	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1200	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1201	/** @} */
1202
1203
1204	/** @name Shift operations on bytes (Group 2).
1205	* @{ */
1206	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1207	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1208	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1209	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1210	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1211	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1212	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1213	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1214	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1215	/** @} */
1216
1217	/** @name Shift operations on words (Group 2).
1218	* @{ */
1219	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1220	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1221	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1222	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1223	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1224	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1225	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1226	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1227	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1228	/** @} */
1229
1230	/** @name Shift operations on double words (Group 2).
1231	* @{ */
1232	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1233	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1234	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1235	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1236	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1237	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1238	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1239	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1240	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1241	/** @} */
1242
1243	/** @name Shift operations on words (Group 2).
1244	* @{ */
1245	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1246	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1247	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1248	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1249	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1250	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1251	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1252	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1253	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1254	/** @} */
1255
1256	/** @name Multiplication and division operations.
1257	* @{ */
1258	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1259	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1260	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1261	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1262
1263	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1264	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1265	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1266	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1267
1268	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1269	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1270	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1271	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1272
1273	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1274	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1275	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1276	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1277	/** @} */
1278
1279	/** @name Byte Swap.
1280	* @{ */
1281	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1282	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1283	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1284	/** @} */
1285
1286	/** @name Misc.
1287	* @{ */
1288	FNIEMAIMPLBINU16 iemAImpl_arpl;
1289	/** @} */
1290
1291
1292	/** @name FPU operations taking a 32-bit float argument
1293	* @{ */
1294	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1295	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1296	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1297
1298	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1299	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1300	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1301
1302	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1303	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1304	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1305	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1306	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1307	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1308	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1309
1310	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1311	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1312	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1313	/** @} */
1314
1315	/** @name FPU operations taking a 64-bit float argument
1316	* @{ */
1317	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1318	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1319	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1320
1321	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1322	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1323	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1324	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1325	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1326	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1327
1328	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1329	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1330	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1331	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1332	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1333	/** @} */
1334
1335	/** @name FPU operations taking a 80-bit float argument
1336	* @{ */
1337	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1338	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1339	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1340	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1341	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1342	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1343	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1344	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1345	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1346	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1347	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1348	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1349
1350	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1351	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80;
1352	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1353
1354	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1355	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1356	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1357	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1358	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1359
1360	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1361	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1362	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1363	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1364	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1365
1366	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1367	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1368	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1369	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1370	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1371	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1372	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1373	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1374	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1375
1376	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1377	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1378	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1379	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1380
1381	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1382	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1383	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1384	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1385	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1386	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1387	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1388	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1389	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1390
1391	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1392	PCRTFLOAT80U pr80Val));
1393	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1394	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1395	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1396	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1397
1398	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1399	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1400	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1401
1402	/** @} */
1403
1404	/** @name FPU operations taking a 16-bit signed integer argument
1405	* @{ */
1406	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1407	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1408	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1409
1410	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1411	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1412	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1413	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1414	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1415	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1416
1417	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1418	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1419
1420	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1421	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1422	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1423	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1424	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1425	/** @} */
1426
1427	/** @name FPU operations taking a 32-bit signed integer argument
1428	* @{ */
1429	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1430	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1431	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1432
1433	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1434	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1435	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1436	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1437	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1438	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1439
1440	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1441	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1442
1443	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1444	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1445	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1446	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1447	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1448	/** @} */
1449
1450	/** @name FPU operations taking a 64-bit signed integer argument
1451	* @{ */
1452	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1453	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1454	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1455
1456	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1457	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1458	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1459	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1460	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1461	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1462
1463	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1464	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1465
1466	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1467	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1468	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1469	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1470	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1471	/** @} */
1472
1473
1474	/** Temporary type representing a 256-bit vector register. */
1475	typedef struct {uint64_t au64[4]; } IEMVMM256;
1476	/** Temporary type pointing to a 256-bit vector register. */
1477	typedef IEMVMM256 *PIEMVMM256;
1478	/** Temporary type pointing to a const 256-bit vector register. */
1479	typedef IEMVMM256 *PCIEMVMM256;
1480
1481
1482	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1483	* @{ */
1484	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1485	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1486	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1487	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1488	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1489	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1490	/** @} */
1491
1492	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1493	* @{ */
1494	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1495	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1496	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1497	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1498	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1499	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1500	/** @} */
1501
1502	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1503	* @{ */
1504	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1505	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1506	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1507	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1508	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1509	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1510	/** @} */
1511
1512	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1513	* @{ */
1514	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1515	PCRTUINT128U pu128Src, uint8_t bEvil));
1516	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1517	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1518	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1519	/** @} */
1520
1521	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1522	* @{ */
1523	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1524	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1525	/** @} */
1526
1527	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1528	* @{ */
1529	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1530	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1531	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1532
1533	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1534	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1535	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1536	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1537
1538	/** @} */
1539
1540
1541	/** @name Function tables.
1542	* @{
1543	*/
1544
1545	/**
1546	* Function table for a binary operator providing implementation based on
1547	* operand size.
1548	*/
1549	typedef struct IEMOPBINSIZES
1550	{
1551	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1552	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1553	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1554	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1555	} IEMOPBINSIZES;
1556	/** Pointer to a binary operator function table. */
1557	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1558
1559
1560	/**
1561	* Function table for a unary operator providing implementation based on
1562	* operand size.
1563	*/
1564	typedef struct IEMOPUNARYSIZES
1565	{
1566	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1567	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1568	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1569	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1570	} IEMOPUNARYSIZES;
1571	/** Pointer to a unary operator function table. */
1572	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1573
1574
1575	/**
1576	* Function table for a shift operator providing implementation based on
1577	* operand size.
1578	*/
1579	typedef struct IEMOPSHIFTSIZES
1580	{
1581	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1582	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1583	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1584	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1585	} IEMOPSHIFTSIZES;
1586	/** Pointer to a shift operator function table. */
1587	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1588
1589
1590	/**
1591	* Function table for a multiplication or division operation.
1592	*/
1593	typedef struct IEMOPMULDIVSIZES
1594	{
1595	PFNIEMAIMPLMULDIVU8 pfnU8;
1596	PFNIEMAIMPLMULDIVU16 pfnU16;
1597	PFNIEMAIMPLMULDIVU32 pfnU32;
1598	PFNIEMAIMPLMULDIVU64 pfnU64;
1599	} IEMOPMULDIVSIZES;
1600	/** Pointer to a multiplication or division operation function table. */
1601	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1602
1603
1604	/**
1605	* Function table for a double precision shift operator providing implementation
1606	* based on operand size.
1607	*/
1608	typedef struct IEMOPSHIFTDBLSIZES
1609	{
1610	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1611	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1612	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1613	} IEMOPSHIFTDBLSIZES;
1614	/** Pointer to a double precision shift function table. */
1615	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1616
1617
1618	/**
1619	* Function table for media instruction taking two full sized media registers,
1620	* optionally the 2nd being a memory reference (only modifying the first op.)
1621	*/
1622	typedef struct IEMOPMEDIAF2
1623	{
1624	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1625	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1626	} IEMOPMEDIAF2;
1627	/** Pointer to a media operation function table for full sized ops. */
1628	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1629
1630	/**
1631	* Function table for media instruction taking taking one full and one lower
1632	* half media register.
1633	*/
1634	typedef struct IEMOPMEDIAF1L1
1635	{
1636	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1637	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1638	} IEMOPMEDIAF1L1;
1639	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1640	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1641
1642	/**
1643	* Function table for media instruction taking taking one full and one high half
1644	* media register.
1645	*/
1646	typedef struct IEMOPMEDIAF1H1
1647	{
1648	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1649	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1650	} IEMOPMEDIAF1H1;
1651	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1652	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1653
1654
1655	/** @} */
1656
1657
1658	/** @name C instruction implementations for anything slightly complicated.
1659	* @{ */
1660
1661	/**
1662	* For typedef'ing or declaring a C instruction implementation function taking
1663	* no extra arguments.
1664	*
1665	* @param a_Name The name of the type.
1666	*/
1667	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1668	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1669	/**
1670	* For defining a C instruction implementation function taking no extra
1671	* arguments.
1672	*
1673	* @param a_Name The name of the function
1674	*/
1675	# define IEM_CIMPL_DEF_0(a_Name) \
1676	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1677	/**
1678	* For calling a C instruction implementation function taking no extra
1679	* arguments.
1680	*
1681	* This special call macro adds default arguments to the call and allow us to
1682	* change these later.
1683	*
1684	* @param a_fn The name of the function.
1685	*/
1686	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1687
1688	/**
1689	* For typedef'ing or declaring a C instruction implementation function taking
1690	* one extra argument.
1691	*
1692	* @param a_Name The name of the type.
1693	* @param a_Type0 The argument type.
1694	* @param a_Arg0 The argument name.
1695	*/
1696	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1697	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1698	/**
1699	* For defining a C instruction implementation function taking one extra
1700	* argument.
1701	*
1702	* @param a_Name The name of the function
1703	* @param a_Type0 The argument type.
1704	* @param a_Arg0 The argument name.
1705	*/
1706	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1707	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1708	/**
1709	* For calling a C instruction implementation function taking one extra
1710	* argument.
1711	*
1712	* This special call macro adds default arguments to the call and allow us to
1713	* change these later.
1714	*
1715	* @param a_fn The name of the function.
1716	* @param a0 The name of the 1st argument.
1717	*/
1718	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1719
1720	/**
1721	* For typedef'ing or declaring a C instruction implementation function taking
1722	* two extra arguments.
1723	*
1724	* @param a_Name The name of the type.
1725	* @param a_Type0 The type of the 1st argument
1726	* @param a_Arg0 The name of the 1st argument.
1727	* @param a_Type1 The type of the 2nd argument.
1728	* @param a_Arg1 The name of the 2nd argument.
1729	*/
1730	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1731	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1732	/**
1733	* For defining a C instruction implementation function taking two extra
1734	* arguments.
1735	*
1736	* @param a_Name The name of the function.
1737	* @param a_Type0 The type of the 1st argument
1738	* @param a_Arg0 The name of the 1st argument.
1739	* @param a_Type1 The type of the 2nd argument.
1740	* @param a_Arg1 The name of the 2nd argument.
1741	*/
1742	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1743	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1744	/**
1745	* For calling a C instruction implementation function taking two extra
1746	* arguments.
1747	*
1748	* This special call macro adds default arguments to the call and allow us to
1749	* change these later.
1750	*
1751	* @param a_fn The name of the function.
1752	* @param a0 The name of the 1st argument.
1753	* @param a1 The name of the 2nd argument.
1754	*/
1755	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1756
1757	/**
1758	* For typedef'ing or declaring a C instruction implementation function taking
1759	* three extra arguments.
1760	*
1761	* @param a_Name The name of the type.
1762	* @param a_Type0 The type of the 1st argument
1763	* @param a_Arg0 The name of the 1st argument.
1764	* @param a_Type1 The type of the 2nd argument.
1765	* @param a_Arg1 The name of the 2nd argument.
1766	* @param a_Type2 The type of the 3rd argument.
1767	* @param a_Arg2 The name of the 3rd argument.
1768	*/
1769	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1770	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1771	/**
1772	* For defining a C instruction implementation function taking three extra
1773	* arguments.
1774	*
1775	* @param a_Name The name of the function.
1776	* @param a_Type0 The type of the 1st argument
1777	* @param a_Arg0 The name of the 1st argument.
1778	* @param a_Type1 The type of the 2nd argument.
1779	* @param a_Arg1 The name of the 2nd argument.
1780	* @param a_Type2 The type of the 3rd argument.
1781	* @param a_Arg2 The name of the 3rd argument.
1782	*/
1783	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1784	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1785	/**
1786	* For calling a C instruction implementation function taking three extra
1787	* arguments.
1788	*
1789	* This special call macro adds default arguments to the call and allow us to
1790	* change these later.
1791	*
1792	* @param a_fn The name of the function.
1793	* @param a0 The name of the 1st argument.
1794	* @param a1 The name of the 2nd argument.
1795	* @param a2 The name of the 3rd argument.
1796	*/
1797	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1798
1799
1800	/**
1801	* For typedef'ing or declaring a C instruction implementation function taking
1802	* four extra arguments.
1803	*
1804	* @param a_Name The name of the type.
1805	* @param a_Type0 The type of the 1st argument
1806	* @param a_Arg0 The name of the 1st argument.
1807	* @param a_Type1 The type of the 2nd argument.
1808	* @param a_Arg1 The name of the 2nd argument.
1809	* @param a_Type2 The type of the 3rd argument.
1810	* @param a_Arg2 The name of the 3rd argument.
1811	* @param a_Type3 The type of the 4th argument.
1812	* @param a_Arg3 The name of the 4th argument.
1813	*/
1814	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1815	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1816	/**
1817	* For defining a C instruction implementation function taking four extra
1818	* arguments.
1819	*
1820	* @param a_Name The name of the function.
1821	* @param a_Type0 The type of the 1st argument
1822	* @param a_Arg0 The name of the 1st argument.
1823	* @param a_Type1 The type of the 2nd argument.
1824	* @param a_Arg1 The name of the 2nd argument.
1825	* @param a_Type2 The type of the 3rd argument.
1826	* @param a_Arg2 The name of the 3rd argument.
1827	* @param a_Type3 The type of the 4th argument.
1828	* @param a_Arg3 The name of the 4th argument.
1829	*/
1830	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1831	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1832	a_Type2 a_Arg2, a_Type3 a_Arg3))
1833	/**
1834	* For calling a C instruction implementation function taking four extra
1835	* arguments.
1836	*
1837	* This special call macro adds default arguments to the call and allow us to
1838	* change these later.
1839	*
1840	* @param a_fn The name of the function.
1841	* @param a0 The name of the 1st argument.
1842	* @param a1 The name of the 2nd argument.
1843	* @param a2 The name of the 3rd argument.
1844	* @param a3 The name of the 4th argument.
1845	*/
1846	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1847
1848
1849	/**
1850	* For typedef'ing or declaring a C instruction implementation function taking
1851	* five extra arguments.
1852	*
1853	* @param a_Name The name of the type.
1854	* @param a_Type0 The type of the 1st argument
1855	* @param a_Arg0 The name of the 1st argument.
1856	* @param a_Type1 The type of the 2nd argument.
1857	* @param a_Arg1 The name of the 2nd argument.
1858	* @param a_Type2 The type of the 3rd argument.
1859	* @param a_Arg2 The name of the 3rd argument.
1860	* @param a_Type3 The type of the 4th argument.
1861	* @param a_Arg3 The name of the 4th argument.
1862	* @param a_Type4 The type of the 5th argument.
1863	* @param a_Arg4 The name of the 5th argument.
1864	*/
1865	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1866	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1867	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1868	a_Type3 a_Arg3, a_Type4 a_Arg4))
1869	/**
1870	* For defining a C instruction implementation function taking five extra
1871	* arguments.
1872	*
1873	* @param a_Name The name of the function.
1874	* @param a_Type0 The type of the 1st argument
1875	* @param a_Arg0 The name of the 1st argument.
1876	* @param a_Type1 The type of the 2nd argument.
1877	* @param a_Arg1 The name of the 2nd argument.
1878	* @param a_Type2 The type of the 3rd argument.
1879	* @param a_Arg2 The name of the 3rd argument.
1880	* @param a_Type3 The type of the 4th argument.
1881	* @param a_Arg3 The name of the 4th argument.
1882	* @param a_Type4 The type of the 5th argument.
1883	* @param a_Arg4 The name of the 5th argument.
1884	*/
1885	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1886	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1887	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1888	a_Type3 a_Arg3, a_Type4 a_Arg4))
1889	/**
1890	* For calling a C instruction implementation function taking five extra
1891	* arguments.
1892	*
1893	* This special call macro adds default arguments to the call and allow us to
1894	* change these later.
1895	*
1896	* @param a_fn The name of the function.
1897	* @param a0 The name of the 1st argument.
1898	* @param a1 The name of the 2nd argument.
1899	* @param a2 The name of the 3rd argument.
1900	* @param a3 The name of the 4th argument.
1901	* @param a4 The name of the 5th argument.
1902	*/
1903	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1904
1905	/** @} */
1906
1907
1908	/** @} */
1909
1910	RT_C_DECLS_END
1911
1912	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
1913

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 77807

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