IEMInternal.h@ 66471

Last change on this file since 66471 was 66471, checked in by vboxsync, 8 years ago
IEM: Split the 3DNow! instruction out into a separate file.
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1	/* $Id: IEMInternal.h 66471 2017-04-07 09:48:47Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___IEMInternal_h
19	#define ___IEMInternal_h
20
21	#include <VBox/vmm/cpum.h>
22	#include <VBox/vmm/iem.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/param.h>
25
26	#include <setjmp.h>
27
28
29	RT_C_DECLS_BEGIN
30
31
32	/** @defgroup grp_iem_int Internals
33	* @ingroup grp_iem
34	* @internal
35	* @{
36	*/
37
38	/** For expanding symbol in slickedit and other products tagging and
39	* crossreferencing IEM symbols. */
40	#ifndef IEM_STATIC
41	# define IEM_STATIC static
42	#endif
43
44	/** @def IEM_WITH_VEX
45	* Enables the VEX decoding. */
46	#define IEM_WITH_VEX
47
48	/** @def IEM_WITH_3DNOW
49	* Enables the 3DNow decoding. */
50	#define IEM_WITH_3DNOW
51
52
53	/** @def IEM_VERIFICATION_MODE_FULL
54	* Shorthand for:
55	* defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL)
56	*/
57	#if (defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL) && !defined(IEM_VERIFICATION_MODE_FULL)) \
58	\|\| defined(DOXYGEN_RUNNING)
59	# define IEM_VERIFICATION_MODE_FULL
60	#endif
61
62
63	/** @def IEM_CFG_TARGET_CPU
64	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
65	*
66	* By default we allow this to be configured by the user via the
67	* CPUM/GuestCpuName config string, but this comes at a slight cost during
68	* decoding. So, for applications of this code where there is no need to
69	* be dynamic wrt target CPU, just modify this define.
70	*/
71	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
72	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
73	#endif
74
75
76	//#define IEM_WITH_CODE_TLB// - work in progress
77
78
79	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
80	/** Instruction statistics. */
81	typedef struct IEMINSTRSTATS
82	{
83	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
84	# include "IEMInstructionStatisticsTmpl.h"
85	# undef IEM_DO_INSTR_STAT
86	} IEMINSTRSTATS;
87	#else
88	struct IEMINSTRSTATS;
89	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
90	#endif
91	/** Pointer to IEM instruction statistics. */
92	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
93
94	/** Finish and move to types.h */
95	typedef union
96	{
97	uint32_t u32;
98	} RTFLOAT32U;
99	typedef RTFLOAT32U *PRTFLOAT32U;
100	typedef RTFLOAT32U const *PCRTFLOAT32U;
101
102
103	/**
104	* Extended operand mode that includes a representation of 8-bit.
105	*
106	* This is used for packing down modes when invoking some C instruction
107	* implementations.
108	*/
109	typedef enum IEMMODEX
110	{
111	IEMMODEX_16BIT = IEMMODE_16BIT,
112	IEMMODEX_32BIT = IEMMODE_32BIT,
113	IEMMODEX_64BIT = IEMMODE_64BIT,
114	IEMMODEX_8BIT
115	} IEMMODEX;
116	AssertCompileSize(IEMMODEX, 4);
117
118
119	/**
120	* Branch types.
121	*/
122	typedef enum IEMBRANCH
123	{
124	IEMBRANCH_JUMP = 1,
125	IEMBRANCH_CALL,
126	IEMBRANCH_TRAP,
127	IEMBRANCH_SOFTWARE_INT,
128	IEMBRANCH_HARDWARE_INT
129	} IEMBRANCH;
130	AssertCompileSize(IEMBRANCH, 4);
131
132
133	/**
134	* A FPU result.
135	*/
136	typedef struct IEMFPURESULT
137	{
138	/** The output value. */
139	RTFLOAT80U r80Result;
140	/** The output status. */
141	uint16_t FSW;
142	} IEMFPURESULT;
143	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
144	/** Pointer to a FPU result. */
145	typedef IEMFPURESULT *PIEMFPURESULT;
146	/** Pointer to a const FPU result. */
147	typedef IEMFPURESULT const *PCIEMFPURESULT;
148
149
150	/**
151	* A FPU result consisting of two output values and FSW.
152	*/
153	typedef struct IEMFPURESULTTWO
154	{
155	/** The first output value. */
156	RTFLOAT80U r80Result1;
157	/** The output status. */
158	uint16_t FSW;
159	/** The second output value. */
160	RTFLOAT80U r80Result2;
161	} IEMFPURESULTTWO;
162	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
163	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
164	/** Pointer to a FPU result consisting of two output values and FSW. */
165	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
166	/** Pointer to a const FPU result consisting of two output values and FSW. */
167	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
168
169
170
171	#ifdef IEM_VERIFICATION_MODE_FULL
172
173	/**
174	* Verification event type.
175	*/
176	typedef enum IEMVERIFYEVENT
177	{
178	IEMVERIFYEVENT_INVALID = 0,
179	IEMVERIFYEVENT_IOPORT_READ,
180	IEMVERIFYEVENT_IOPORT_WRITE,
181	IEMVERIFYEVENT_IOPORT_STR_READ,
182	IEMVERIFYEVENT_IOPORT_STR_WRITE,
183	IEMVERIFYEVENT_RAM_WRITE,
184	IEMVERIFYEVENT_RAM_READ
185	} IEMVERIFYEVENT;
186
187	/** Checks if the event type is a RAM read or write. */
188	# define IEMVERIFYEVENT_IS_RAM(a_enmType) ((a_enmType) == IEMVERIFYEVENT_RAM_WRITE \|\| (a_enmType) == IEMVERIFYEVENT_RAM_READ)
189
190	/**
191	* Verification event record.
192	*/
193	typedef struct IEMVERIFYEVTREC
194	{
195	/** Pointer to the next record in the list. */
196	struct IEMVERIFYEVTREC *pNext;
197	/** The event type. */
198	IEMVERIFYEVENT enmEvent;
199	/** The event data. */
200	union
201	{
202	/** IEMVERIFYEVENT_IOPORT_READ */
203	struct
204	{
205	RTIOPORT Port;
206	uint8_t cbValue;
207	} IOPortRead;
208
209	/** IEMVERIFYEVENT_IOPORT_WRITE */
210	struct
211	{
212	RTIOPORT Port;
213	uint8_t cbValue;
214	uint32_t u32Value;
215	} IOPortWrite;
216
217	/** IEMVERIFYEVENT_IOPORT_STR_READ */
218	struct
219	{
220	RTIOPORT Port;
221	uint8_t cbValue;
222	RTGCUINTREG cTransfers;
223	} IOPortStrRead;
224
225	/** IEMVERIFYEVENT_IOPORT_STR_WRITE */
226	struct
227	{
228	RTIOPORT Port;
229	uint8_t cbValue;
230	RTGCUINTREG cTransfers;
231	} IOPortStrWrite;
232
233	/** IEMVERIFYEVENT_RAM_READ */
234	struct
235	{
236	RTGCPHYS GCPhys;
237	uint32_t cb;
238	} RamRead;
239
240	/** IEMVERIFYEVENT_RAM_WRITE */
241	struct
242	{
243	RTGCPHYS GCPhys;
244	uint32_t cb;
245	uint8_t ab[512];
246	} RamWrite;
247	} u;
248	} IEMVERIFYEVTREC;
249	/** Pointer to an IEM event verification records. */
250	typedef IEMVERIFYEVTREC *PIEMVERIFYEVTREC;
251
252	#endif /* IEM_VERIFICATION_MODE_FULL */
253
254
255	/**
256	* IEM TLB entry.
257	*
258	* Lookup assembly:
259	* @code{.asm}
260	; Calculate tag.
261	mov rax, [VA]
262	shl rax, 16
263	shr rax, 16 + X86_PAGE_SHIFT
264	or rax, [uTlbRevision]
265
266	; Do indexing.
267	movzx ecx, al
268	lea rcx, [pTlbEntries + rcx]
269
270	; Check tag.
271	cmp [rcx + IEMTLBENTRY.uTag], rax
272	jne .TlbMiss
273
274	; Check access.
275	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
276	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
277	cmp rax, [uTlbPhysRev]
278	jne .TlbMiss
279
280	; Calc address and we're done.
281	mov eax, X86_PAGE_OFFSET_MASK
282	and eax, [VA]
283	or rax, [rcx + IEMTLBENTRY.pMappingR3]
284	%ifdef VBOX_WITH_STATISTICS
285	inc qword [cTlbHits]
286	%endif
287	jmp .Done
288
289	.TlbMiss:
290	mov r8d, ACCESS_FLAGS
291	mov rdx, [VA]
292	mov rcx, [pVCpu]
293	call iemTlbTypeMiss
294	.Done:
295
296	@endcode
297	*
298	*/
299	typedef struct IEMTLBENTRY
300	{
301	/** The TLB entry tag.
302	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
303	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
304	*
305	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
306	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
307	* revision wraps around though, the tags needs to be zeroed.
308	*
309	* @note Try use SHRD instruction? After seeing
310	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
311	*/
312	uint64_t uTag;
313	/** Access flags and physical TLB revision.
314	*
315	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
316	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
317	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
318	* - Bit 3 - pgm phys/virt - not directly writable.
319	* - Bit 4 - pgm phys page - not directly readable.
320	* - Bit 5 - currently unused.
321	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
322	* - Bit 7 - tlb entry - pMappingR3 member not valid.
323	* - Bits 63 thru 8 are used for the physical TLB revision number.
324	*
325	* We're using complemented bit meanings here because it makes it easy to check
326	* whether special action is required. For instance a user mode write access
327	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
328	* non-zero result would mean special handling needed because either it wasn't
329	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
330	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
331	* need to check any PTE flag.
332	*/
333	uint64_t fFlagsAndPhysRev;
334	/** The guest physical page address. */
335	uint64_t GCPhys;
336	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
337	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
338	R3PTRTYPE(uint8_t *) pbMappingR3;
339	#else
340	R3R0PTRTYPE(uint8_t *) pbMappingR3;
341	#endif
342	#if HC_ARCH_BITS == 32
343	uint32_t u32Padding1;
344	#endif
345	} IEMTLBENTRY;
346	AssertCompileSize(IEMTLBENTRY, 32);
347	/** Pointer to an IEM TLB entry. */
348	typedef IEMTLBENTRY *PIEMTLBENTRY;
349
350	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
351	* @{ */
352	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
353	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
354	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
355	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
356	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
357	#define IEMTLBE_F_PATCH_CODE RT_BIT_64(5) /*< Code TLB: Patch code (PATM). /
358	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
359	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
360	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
361	/** @} */
362
363
364	/**
365	* An IEM TLB.
366	*
367	* We've got two of these, one for data and one for instructions.
368	*/
369	typedef struct IEMTLB
370	{
371	/** The TLB entries.
372	* We've choosen 256 because that way we can obtain the result directly from a
373	* 8-bit register without an additional AND instruction. */
374	IEMTLBENTRY aEntries[256];
375	/** The TLB revision.
376	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
377	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
378	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
379	* (The revision zero indicates an invalid TLB entry.)
380	*
381	* The initial value is choosen to cause an early wraparound. */
382	uint64_t uTlbRevision;
383	/** The TLB physical address revision - shadow of PGM variable.
384	*
385	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
386	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
387	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
388	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
389	*
390	* The initial value is choosen to cause an early wraparound. */
391	uint64_t volatile uTlbPhysRev;
392
393	/* Statistics: */
394
395	/** TLB hits (VBOX_WITH_STATISTICS only). */
396	uint64_t cTlbHits;
397	/** TLB misses. */
398	uint32_t cTlbMisses;
399	/** Slow read path. */
400	uint32_t cTlbSlowReadPath;
401	#if 0
402	/** TLB misses because of tag mismatch. */
403	uint32_t cTlbMissesTag;
404	/** TLB misses because of virtual access violation. */
405	uint32_t cTlbMissesVirtAccess;
406	/** TLB misses because of dirty bit. */
407	uint32_t cTlbMissesDirty;
408	/** TLB misses because of MMIO */
409	uint32_t cTlbMissesMmio;
410	/** TLB misses because of write access handlers. */
411	uint32_t cTlbMissesWriteHandler;
412	/** TLB misses because no r3(/r0) mapping. */
413	uint32_t cTlbMissesMapping;
414	#endif
415	/** Alignment padding. */
416	uint32_t au32Padding[3+5];
417	} IEMTLB;
418	AssertCompileSizeAlignment(IEMTLB, 64);
419	/** IEMTLB::uTlbRevision increment. */
420	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
421	/** IEMTLB::uTlbPhysRev increment. */
422	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
423
424
425	/**
426	* The per-CPU IEM state.
427	*/
428	typedef struct IEMCPU
429	{
430	/** Info status code that needs to be propagated to the IEM caller.
431	* This cannot be passed internally, as it would complicate all success
432	* checks within the interpreter making the code larger and almost impossible
433	* to get right. Instead, we'll store status codes to pass on here. Each
434	* source of these codes will perform appropriate sanity checks. */
435	int32_t rcPassUp; /* 0x00 */
436
437	/** The current CPU execution mode (CS). */
438	IEMMODE enmCpuMode; /* 0x04 */
439	/** The CPL. */
440	uint8_t uCpl; /* 0x05 */
441
442	/** Whether to bypass access handlers or not. */
443	bool fBypassHandlers; /* 0x06 */
444	/** Indicates that we're interpreting patch code - RC only! */
445	bool fInPatchCode; /* 0x07 */
446
447	/** @name Decoder state.
448	* @{ */
449	#ifdef IEM_WITH_CODE_TLB
450	/** The offset of the next instruction byte. */
451	uint32_t offInstrNextByte; /* 0x08 */
452	/** The number of bytes available at pbInstrBuf for the current instruction.
453	* This takes the max opcode length into account so that doesn't need to be
454	* checked separately. */
455	uint32_t cbInstrBuf; /* 0x0c */
456	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
457	* This can be NULL if the page isn't mappable for some reason, in which
458	* case we'll do fallback stuff.
459	*
460	* If we're executing an instruction from a user specified buffer,
461	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
462	* aligned pointer but pointer to the user data.
463	*
464	* For instructions crossing pages, this will start on the first page and be
465	* advanced to the next page by the time we've decoded the instruction. This
466	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
467	*/
468	uint8_t const pbInstrBuf; / 0x10 */
469	# if ARCH_BITS == 32
470	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
471	# endif
472	/** The program counter corresponding to pbInstrBuf.
473	* This is set to a non-canonical address when we need to invalidate it. */
474	uint64_t uInstrBufPc; /* 0x18 */
475	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
476	* This takes the CS segment limit into account. */
477	uint16_t cbInstrBufTotal; /* 0x20 */
478	/** Offset into pbInstrBuf of the first byte of the current instruction.
479	* Can be negative to efficiently handle cross page instructions. */
480	int16_t offCurInstrStart; /* 0x22 */
481
482	/** The prefix mask (IEM_OP_PRF_XXX). */
483	uint32_t fPrefixes; /* 0x24 */
484	/** The extra REX ModR/M register field bit (REX.R << 3). */
485	uint8_t uRexReg; /* 0x28 */
486	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
487	* (REX.B << 3). */
488	uint8_t uRexB; /* 0x29 */
489	/** The extra REX SIB index field bit (REX.X << 3). */
490	uint8_t uRexIndex; /* 0x2a */
491
492	/** The effective segment register (X86_SREG_XXX). */
493	uint8_t iEffSeg; /* 0x2b */
494
495	#else
496	/** The size of what has currently been fetched into abOpcodes. */
497	uint8_t cbOpcode; /* 0x08 */
498	/** The current offset into abOpcodes. */
499	uint8_t offOpcode; /* 0x09 */
500
501	/** The effective segment register (X86_SREG_XXX). */
502	uint8_t iEffSeg; /* 0x0a */
503
504	/** The extra REX ModR/M register field bit (REX.R << 3). */
505	uint8_t uRexReg; /* 0x0b */
506	/** The prefix mask (IEM_OP_PRF_XXX). */
507	uint32_t fPrefixes; /* 0x0c */
508	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
509	* (REX.B << 3). */
510	uint8_t uRexB; /* 0x10 */
511	/** The extra REX SIB index field bit (REX.X << 3). */
512	uint8_t uRexIndex; /* 0x11 */
513
514	#endif
515
516	/** The effective operand mode. */
517	IEMMODE enmEffOpSize; /* 0x2c, 0x12 */
518	/** The default addressing mode. */
519	IEMMODE enmDefAddrMode; /* 0x2d, 0x13 */
520	/** The effective addressing mode. */
521	IEMMODE enmEffAddrMode; /* 0x2e, 0x14 */
522	/** The default operand mode. */
523	IEMMODE enmDefOpSize; /* 0x2f, 0x15 */
524
525	/** Prefix index (VEX.pp) for two byte and three byte tables. */
526	uint8_t idxPrefix; /* 0x30, 0x16 */
527	/** 3rd VEX/EVEX/XOP register. */
528	uint8_t uVex3rdReg; /* 0x31, 0x17 */
529	/** The VEX/EVEX/XOP length field. */
530	uint8_t uVexLength; /* 0x32, 0x18 */
531	/** Additional EVEX stuff. */
532	uint8_t fEvexStuff; /* 0x33, 0x19 */
533
534	/** The FPU opcode (FOP). */
535	uint16_t uFpuOpcode; /* 0x34, 0x1a */
536
537	/** Explicit alignment padding. */
538	#ifdef IEM_WITH_CODE_TLB
539	uint8_t abAlignment2a[2]; /* 0x36 */
540	#endif
541
542	/** The opcode bytes. */
543	uint8_t abOpcode[15]; /* 0x48, 0x1c */
544	/** Explicit alignment padding. */
545	#ifdef IEM_WITH_CODE_TLB
546	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
547	#else
548	uint8_t abAlignment2c[0x48 - 0x2b]; /* 0x2b */
549	#endif
550	/** @} */
551
552
553	/** The flags of the current exception / interrupt. */
554	uint32_t fCurXcpt; /* 0x48, 0x48 */
555	/** The current exception / interrupt. */
556	uint8_t uCurXcpt;
557	/** Exception / interrupt recursion depth. */
558	int8_t cXcptRecursions;
559
560	/** The number of active guest memory mappings. */
561	uint8_t cActiveMappings;
562	/** The next unused mapping index. */
563	uint8_t iNextMapping;
564	/** Records for tracking guest memory mappings. */
565	struct
566	{
567	/** The address of the mapped bytes. */
568	void *pv;
569	#if defined(IN_RC) && HC_ARCH_BITS == 64
570	uint32_t u32Alignment3; /*< Alignment padding. /
571	#endif
572	/** The access flags (IEM_ACCESS_XXX).
573	* IEM_ACCESS_INVALID if the entry is unused. */
574	uint32_t fAccess;
575	#if HC_ARCH_BITS == 64
576	uint32_t u32Alignment4; /*< Alignment padding. /
577	#endif
578	} aMemMappings[3];
579
580	/** Locking records for the mapped memory. */
581	union
582	{
583	PGMPAGEMAPLOCK Lock;
584	uint64_t au64Padding[2];
585	} aMemMappingLocks[3];
586
587	/** Bounce buffer info.
588	* This runs in parallel to aMemMappings. */
589	struct
590	{
591	/** The physical address of the first byte. */
592	RTGCPHYS GCPhysFirst;
593	/** The physical address of the second page. */
594	RTGCPHYS GCPhysSecond;
595	/** The number of bytes in the first page. */
596	uint16_t cbFirst;
597	/** The number of bytes in the second page. */
598	uint16_t cbSecond;
599	/** Whether it's unassigned memory. */
600	bool fUnassigned;
601	/** Explicit alignment padding. */
602	bool afAlignment5[3];
603	} aMemBbMappings[3];
604
605	/** Bounce buffer storage.
606	* This runs in parallel to aMemMappings and aMemBbMappings. */
607	struct
608	{
609	uint8_t ab[512];
610	} aBounceBuffers[3];
611
612
613	/** Pointer set jump buffer - ring-3 context. */
614	R3PTRTYPE(jmp_buf *) pJmpBufR3;
615	/** Pointer set jump buffer - ring-0 context. */
616	R0PTRTYPE(jmp_buf *) pJmpBufR0;
617	/** Pointer set jump buffer - raw-mode context. */
618	RCPTRTYPE(jmp_buf *) pJmpBufRC;
619
620	/** @todo Should move this near @a fCurXcpt later. */
621	/** The error code for the current exception / interrupt. */
622	uint32_t uCurXcptErr;
623	/** The CR2 for the current exception / interrupt. */
624	uint64_t uCurXcptCr2;
625
626	/** @name Statistics
627	* @{ */
628	/** The number of instructions we've executed. */
629	uint32_t cInstructions;
630	/** The number of potential exits. */
631	uint32_t cPotentialExits;
632	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
633	* This may contain uncommitted writes. */
634	uint32_t cbWritten;
635	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
636	uint32_t cRetInstrNotImplemented;
637	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
638	uint32_t cRetAspectNotImplemented;
639	/** Counts informational statuses returned (other than VINF_SUCCESS). */
640	uint32_t cRetInfStatuses;
641	/** Counts other error statuses returned. */
642	uint32_t cRetErrStatuses;
643	/** Number of times rcPassUp has been used. */
644	uint32_t cRetPassUpStatus;
645	/** Number of times RZ left with instruction commit pending for ring-3. */
646	uint32_t cPendingCommit;
647	/** Number of long jumps. */
648	uint32_t cLongJumps;
649	uint32_t uAlignment6; /*< Alignment padding. /
650	#ifdef IEM_VERIFICATION_MODE_FULL
651	/** The Number of I/O port reads that has been performed. */
652	uint32_t cIOReads;
653	/** The Number of I/O port writes that has been performed. */
654	uint32_t cIOWrites;
655	/** Set if no comparison to REM is currently performed.
656	* This is used to skip past really slow bits. */
657	bool fNoRem;
658	/** Saved fNoRem flag used by #iemInitExec and #iemUninitExec. */
659	bool fNoRemSavedByExec;
660	/** Indicates that RAX and RDX differences should be ignored since RDTSC
661	* and RDTSCP are timing sensitive. */
662	bool fIgnoreRaxRdx;
663	/** Indicates that a MOVS instruction with overlapping source and destination
664	* was executed, causing the memory write records to be incorrrect. */
665	bool fOverlappingMovs;
666	/** Set if there are problematic memory accesses (MMIO, write monitored, ++). */
667	bool fProblematicMemory;
668	/** This is used to communicate a CPL changed caused by IEMInjectTrap that
669	* CPUM doesn't yet reflect. */
670	uint8_t uInjectCpl;
671	/** To prevent EMR3HmSingleInstruction from triggering endless recursion via
672	* emR3ExecuteInstruction and iemExecVerificationModeCheck. */
673	uint8_t cVerifyDepth;
674	bool afAlignment7[2];
675	/** Mask of undefined eflags.
676	* The verifier will any difference in these flags. */
677	uint32_t fUndefinedEFlags;
678	/** The CS of the instruction being interpreted. */
679	RTSEL uOldCs;
680	/** The RIP of the instruction being interpreted. */
681	uint64_t uOldRip;
682	/** The physical address corresponding to abOpcodes[0]. */
683	RTGCPHYS GCPhysOpcodes;
684	#endif
685	/** @} */
686
687	/** @name Target CPU information.
688	* @{ */
689	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
690	/** The target CPU. */
691	uint32_t uTargetCpu;
692	#else
693	uint32_t u32TargetCpuPadding;
694	#endif
695	/** The CPU vendor. */
696	CPUMCPUVENDOR enmCpuVendor;
697	/** @} */
698
699	/** @name Host CPU information.
700	* @{ */
701	/** The CPU vendor. */
702	CPUMCPUVENDOR enmHostCpuVendor;
703	/** @} */
704
705	uint32_t au32Alignment8[HC_ARCH_BITS == 64 ? 4 + 8 : 4]; /*< Alignment padding. /
706
707	/** Data TLB.
708	* @remarks Must be 64-byte aligned. */
709	IEMTLB DataTlb;
710	/** Instruction TLB.
711	* @remarks Must be 64-byte aligned. */
712	IEMTLB CodeTlb;
713
714	/** Pointer to the CPU context - ring-3 context.
715	* @todo put inside IEM_VERIFICATION_MODE_FULL++. */
716	R3PTRTYPE(PCPUMCTX) pCtxR3;
717	/** Pointer to the CPU context - ring-0 context. */
718	R0PTRTYPE(PCPUMCTX) pCtxR0;
719	/** Pointer to the CPU context - raw-mode context. */
720	RCPTRTYPE(PCPUMCTX) pCtxRC;
721
722	/** Pointer to instruction statistics for raw-mode context (same as R0). */
723	RCPTRTYPE(PIEMINSTRSTATS) pStatsRC;
724	/** Pointer to instruction statistics for ring-0 context (same as RC). */
725	R0PTRTYPE(PIEMINSTRSTATS) pStatsR0;
726	/** Pointer to instruction statistics for non-ring-3 code. */
727	R3PTRTYPE(PIEMINSTRSTATS) pStatsCCR3;
728	/** Pointer to instruction statistics for ring-3 context. */
729	R3PTRTYPE(PIEMINSTRSTATS) pStatsR3;
730
731	#ifdef IEM_VERIFICATION_MODE_FULL
732	/** The event verification records for what IEM did (LIFO). */
733	R3PTRTYPE(PIEMVERIFYEVTREC) pIemEvtRecHead;
734	/** Insertion point for pIemEvtRecHead. */
735	R3PTRTYPE(PIEMVERIFYEVTREC *) ppIemEvtRecNext;
736	/** The event verification records for what the other party did (FIFO). */
737	R3PTRTYPE(PIEMVERIFYEVTREC) pOtherEvtRecHead;
738	/** Insertion point for pOtherEvtRecHead. */
739	R3PTRTYPE(PIEMVERIFYEVTREC *) ppOtherEvtRecNext;
740	/** List of free event records. */
741	R3PTRTYPE(PIEMVERIFYEVTREC) pFreeEvtRec;
742	#endif
743	} IEMCPU;
744	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
745	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
746	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
747	/** Pointer to the per-CPU IEM state. */
748	typedef IEMCPU *PIEMCPU;
749	/** Pointer to the const per-CPU IEM state. */
750	typedef IEMCPU const *PCIEMCPU;
751
752
753	/** @def IEM_GET_CTX
754	* Gets the guest CPU context for the calling EMT.
755	* @returns PCPUMCTX
756	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
757	*/
758	#if !defined(IEM_VERIFICATION_MODE_FULL) && !defined(IEM_VERIFICATION_MODE) \
759	&& !defined(IEM_VERIFICATION_MODE_MINIMAL) && defined(VMCPU_INCL_CPUM_GST_CTX)
760	# define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
761	#else
762	# define IEM_GET_CTX(a_pVCpu) ((a_pVCpu)->iem.s.CTX_SUFF(pCtx))
763	#endif
764
765	/** Gets the current IEMTARGETCPU value.
766	* @returns IEMTARGETCPU value.
767	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
768	*/
769	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
770	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
771	#else
772	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
773	#endif
774
775	/** @def Gets the instruction length. */
776	#ifdef IEM_WITH_CODE_TLB
777	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
778	#else
779	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
780	#endif
781
782
783	/** @name IEM_ACCESS_XXX - Access details.
784	* @{ */
785	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
786	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
787	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
788	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
789	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
790	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
791	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
792	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
793	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
794	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
795	/** The writes are partial, so if initialize the bounce buffer with the
796	* orignal RAM content. */
797	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
798	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
799	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
800	/** Bounce buffer with ring-3 write pending, first page. */
801	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
802	/** Bounce buffer with ring-3 write pending, second page. */
803	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
804	/** Valid bit mask. */
805	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
806	/** Read+write data alias. */
807	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
808	/** Write data alias. */
809	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
810	/** Read data alias. */
811	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
812	/** Instruction fetch alias. */
813	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
814	/** Stack write alias. */
815	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
816	/** Stack read alias. */
817	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
818	/** Stack read+write alias. */
819	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
820	/** Read system table alias. */
821	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
822	/** Read+write system table alias. */
823	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
824	/** @} */
825
826	/** @name Prefix constants (IEMCPU::fPrefixes)
827	* @{ */
828	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
829	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
830	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
831	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
832	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
833	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
834	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
835
836	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
837	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
838	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
839
840	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
841	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
842	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
843
844	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
845	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
846	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
847	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
848	/** Mask with all the REX prefix flags.
849	* This is generally for use when needing to undo the REX prefixes when they
850	* are followed legacy prefixes and therefore does not immediately preceed
851	* the first opcode byte.
852	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
853	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
854
855	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
856	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
857	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
858	/** @} */
859
860	/** @name IEMOPFORM_XXX - Opcode forms
861	* @note These are ORed together with IEMOPHINT_XXX.
862	* @{ */
863	/** ModR/M: reg, r/m */
864	#define IEMOPFORM_RM 0
865	/** ModR/M: reg, r/m (register) */
866	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
867	/** ModR/M: reg, r/m (memory) */
868	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
869	/** ModR/M: r/m, reg */
870	#define IEMOPFORM_MR 1
871	/** ModR/M: r/m (register), reg */
872	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
873	/** ModR/M: r/m (memory), reg */
874	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
875	/** ModR/M: r/m only */
876	#define IEMOPFORM_M 2
877	/** ModR/M: r/m only (register). */
878	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
879	/** ModR/M: r/m only (memory). */
880	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
881	/** ModR/M: reg only */
882	#define IEMOPFORM_R 3
883
884	/** VEX+ModR/M: reg, r/m */
885	#define IEMOPFORM_VEX_RM 4
886	/** VEX+ModR/M: reg, r/m (register) */
887	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
888	/** VEX+ModR/M: reg, r/m (memory) */
889	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
890	/** VEX+ModR/M: r/m, reg */
891	#define IEMOPFORM_VEX_MR 5
892	/** VEX+ModR/M: r/m (register), reg */
893	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
894	/** VEX+ModR/M: r/m (memory), reg */
895	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
896	/** VEX+ModR/M: r/m only */
897	#define IEMOPFORM_VEX_M 6
898	/** VEX+ModR/M: r/m only (register). */
899	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
900	/** VEX+ModR/M: r/m only (memory). */
901	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
902	/** VEX+ModR/M: reg only */
903	#define IEMOPFORM_VEX_R 7
904	/** VEX+ModR/M: reg, vvvv, r/m */
905	#define IEMOPFORM_VEX_RVM 8
906	/** VEX+ModR/M: r/m, vvvv, reg */
907	#define IEMOPFORM_VEX_MVR 9
908
909	/** Fixed register instruction, no R/M. */
910	#define IEMOPFORM_FIXED 16
911
912	/** The r/m is a register. */
913	#define IEMOPFORM_MOD3 RT_BIT_32(8)
914	/** The r/m is a memory access. */
915	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
916	/** @} */
917
918	/** @name IEMOPHINT_XXX - Additional Opcode Hints
919	* @note These are ORed together with IEMOPFORM_XXX.
920	* @{ */
921	/** Both the operand size prefixes are ignored. */
922	#define IEMOPHINT_IGNORES_OP_SIZE RT_BIT_32(10)
923	/** Allowed with the lock prefix. */
924	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
925	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
926	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
927	/** @} */
928
929	/**
930	* Possible hardware task switch sources.
931	*/
932	typedef enum IEMTASKSWITCH
933	{
934	/** Task switch caused by an interrupt/exception. */
935	IEMTASKSWITCH_INT_XCPT = 1,
936	/** Task switch caused by a far CALL. */
937	IEMTASKSWITCH_CALL,
938	/** Task switch caused by a far JMP. */
939	IEMTASKSWITCH_JUMP,
940	/** Task switch caused by an IRET. */
941	IEMTASKSWITCH_IRET
942	} IEMTASKSWITCH;
943	AssertCompileSize(IEMTASKSWITCH, 4);
944
945
946	/**
947	* Tests if verification mode is enabled.
948	*
949	* This expands to @c false when IEM_VERIFICATION_MODE is not defined and
950	* should therefore cause the compiler to eliminate the verification branch
951	* of an if statement. */
952	#ifdef IEM_VERIFICATION_MODE_FULL
953	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
954	#elif defined(IEM_VERIFICATION_MODE_MINIMAL)
955	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (true)
956	#else
957	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (false)
958	#endif
959
960	/**
961	* Tests if full verification mode is enabled.
962	*
963	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
964	* should therefore cause the compiler to eliminate the verification branch
965	* of an if statement. */
966	#ifdef IEM_VERIFICATION_MODE_FULL
967	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
968	#else
969	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (false)
970	#endif
971
972	/**
973	* Tests if full verification mode is enabled again REM.
974	*
975	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
976	* should therefore cause the compiler to eliminate the verification branch
977	* of an if statement. */
978	#ifdef IEM_VERIFICATION_MODE_FULL
979	# ifdef IEM_VERIFICATION_MODE_FULL_HM
980	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem && !HMIsEnabled((a_pVCpu)->CTX_SUFF(pVM)))
981	# else
982	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
983	# endif
984	#else
985	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (false)
986	#endif
987
988	/** @def IEM_VERIFICATION_MODE
989	* Indicates that one of the verfication modes are enabled.
990	*/
991	#if (defined(IEM_VERIFICATION_MODE_FULL) \|\| defined(IEM_VERIFICATION_MODE_MINIMAL)) && !defined(IEM_VERIFICATION_MODE) \
992	\|\| defined(DOXYGEN_RUNNING)
993	# define IEM_VERIFICATION_MODE
994	#endif
995
996	/**
997	* Indicates to the verifier that the given flag set is undefined.
998	*
999	* Can be invoked again to add more flags.
1000	*
1001	* This is a NOOP if the verifier isn't compiled in.
1002	*/
1003	#ifdef IEM_VERIFICATION_MODE_FULL
1004	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { pVCpu->iem.s.fUndefinedEFlags \|= (a_fEfl); } while (0)
1005	#else
1006	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1007	#endif
1008
1009
1010	/** @def IEM_DECL_IMPL_TYPE
1011	* For typedef'ing an instruction implementation function.
1012	*
1013	* @param a_RetType The return type.
1014	* @param a_Name The name of the type.
1015	* @param a_ArgList The argument list enclosed in parentheses.
1016	*/
1017
1018	/** @def IEM_DECL_IMPL_DEF
1019	* For defining an instruction implementation function.
1020	*
1021	* @param a_RetType The return type.
1022	* @param a_Name The name of the type.
1023	* @param a_ArgList The argument list enclosed in parentheses.
1024	*/
1025
1026	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1027	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1028	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1029	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1030	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1031
1032	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1033	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1034	a_RetType (__fastcall a_Name) a_ArgList
1035	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1036	a_RetType __fastcall a_Name a_ArgList
1037
1038	#else
1039	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1040	a_RetType (VBOXCALL a_Name) a_ArgList
1041	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1042	a_RetType VBOXCALL a_Name a_ArgList
1043
1044	#endif
1045
1046	/** @name Arithmetic assignment operations on bytes (binary).
1047	* @{ */
1048	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1049	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1050	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1051	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1052	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1053	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1054	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1055	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1056	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1057	/** @} */
1058
1059	/** @name Arithmetic assignment operations on words (binary).
1060	* @{ */
1061	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1062	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1063	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1064	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1065	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1066	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1067	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1068	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1069	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1070	/** @} */
1071
1072	/** @name Arithmetic assignment operations on double words (binary).
1073	* @{ */
1074	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1075	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1076	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1077	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1078	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1079	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1080	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1081	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1082	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1083	/** @} */
1084
1085	/** @name Arithmetic assignment operations on quad words (binary).
1086	* @{ */
1087	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1088	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1089	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1090	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1091	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1092	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1093	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1094	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1095	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1096	/** @} */
1097
1098	/** @name Compare operations (thrown in with the binary ops).
1099	* @{ */
1100	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1101	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1102	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1103	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1104	/** @} */
1105
1106	/** @name Test operations (thrown in with the binary ops).
1107	* @{ */
1108	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1109	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1110	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1111	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1112	/** @} */
1113
1114	/** @name Bit operations operations (thrown in with the binary ops).
1115	* @{ */
1116	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1117	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1118	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1119	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1120	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1121	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1122	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1123	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1124	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1125	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1126	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1127	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1128	/** @} */
1129
1130	/** @name Exchange memory with register operations.
1131	* @{ */
1132	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
1133	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
1134	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
1135	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
1136	/** @} */
1137
1138	/** @name Exchange and add operations.
1139	* @{ */
1140	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1141	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1142	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1143	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1144	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1145	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1146	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1147	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1148	/** @} */
1149
1150	/** @name Compare and exchange.
1151	* @{ */
1152	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1153	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1154	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1155	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1156	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1157	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1158	#ifdef RT_ARCH_X86
1159	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1160	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1161	#else
1162	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1163	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1164	#endif
1165	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1166	uint32_t *pEFlags));
1167	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1168	uint32_t *pEFlags));
1169	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1170	uint32_t *pEFlags));
1171	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1172	uint32_t *pEFlags));
1173	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1174	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1175	/** @} */
1176
1177	/** @name Memory ordering
1178	* @{ */
1179	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1180	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1181	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1182	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1183	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1184	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1185	/** @} */
1186
1187	/** @name Double precision shifts
1188	* @{ */
1189	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1190	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1191	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1192	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1193	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1194	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1195	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1196	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1197	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1198	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1199	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1200	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1201	/** @} */
1202
1203
1204	/** @name Bit search operations (thrown in with the binary ops).
1205	* @{ */
1206	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1207	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1208	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1209	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1210	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1211	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1212	/** @} */
1213
1214	/** @name Signed multiplication operations (thrown in with the binary ops).
1215	* @{ */
1216	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1217	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1218	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1219	/** @} */
1220
1221	/** @name Arithmetic assignment operations on bytes (unary).
1222	* @{ */
1223	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1224	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1225	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1226	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1227	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1228	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1229	/** @} */
1230
1231	/** @name Arithmetic assignment operations on words (unary).
1232	* @{ */
1233	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1234	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1235	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1236	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1237	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1238	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1239	/** @} */
1240
1241	/** @name Arithmetic assignment operations on double words (unary).
1242	* @{ */
1243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1244	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1245	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1246	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1247	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1248	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1249	/** @} */
1250
1251	/** @name Arithmetic assignment operations on quad words (unary).
1252	* @{ */
1253	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1254	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1255	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1256	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1257	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1258	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1259	/** @} */
1260
1261
1262	/** @name Shift operations on bytes (Group 2).
1263	* @{ */
1264	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1265	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1266	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1267	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1268	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1269	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1270	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1271	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1272	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1273	/** @} */
1274
1275	/** @name Shift operations on words (Group 2).
1276	* @{ */
1277	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1278	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1279	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1280	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1281	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1282	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1283	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1284	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1285	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1286	/** @} */
1287
1288	/** @name Shift operations on double words (Group 2).
1289	* @{ */
1290	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1291	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1292	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1293	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1294	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1295	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1296	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1297	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1298	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1299	/** @} */
1300
1301	/** @name Shift operations on words (Group 2).
1302	* @{ */
1303	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1304	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1305	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1306	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1307	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1308	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1309	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1310	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1311	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1312	/** @} */
1313
1314	/** @name Multiplication and division operations.
1315	* @{ */
1316	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1317	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1318	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1319	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1320
1321	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1322	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1323	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1324	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1325
1326	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1327	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1328	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1329	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1330
1331	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1332	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1333	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1334	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1335	/** @} */
1336
1337	/** @name Byte Swap.
1338	* @{ */
1339	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1340	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1341	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1342	/** @} */
1343
1344	/** @name Misc.
1345	* @{ */
1346	FNIEMAIMPLBINU16 iemAImpl_arpl;
1347	/** @} */
1348
1349
1350	/** @name FPU operations taking a 32-bit float argument
1351	* @{ */
1352	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1353	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1354	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1355
1356	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1357	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1358	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1359
1360	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1361	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1362	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1363	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1364	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1365	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1366	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1367
1368	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1369	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1370	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1371	/** @} */
1372
1373	/** @name FPU operations taking a 64-bit float argument
1374	* @{ */
1375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1376	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1377	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1378
1379	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1380	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1381	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1382	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1383	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1384	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1385
1386	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1387	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1388	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1389	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1390	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1391	/** @} */
1392
1393	/** @name FPU operations taking a 80-bit float argument
1394	* @{ */
1395	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1396	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1397	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1398	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1399	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1400	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1401	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1402	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1403	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1404	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1405	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1406	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1407
1408	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1409	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80;
1410	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1411
1412	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1413	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1414	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1415	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1416	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1417
1418	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1419	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1420	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1421	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1422	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1423
1424	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1425	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1426	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1427	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1428	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1429	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1430	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1431	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1432	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1433
1434	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1435	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1436	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1437	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1438
1439	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1440	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1441	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1442	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1443	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1444	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1445	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1446	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1447	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1448
1449	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1450	PCRTFLOAT80U pr80Val));
1451	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1452	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1453	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1454	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1455
1456	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1457	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1458	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1459
1460	/** @} */
1461
1462	/** @name FPU operations taking a 16-bit signed integer argument
1463	* @{ */
1464	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1465	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1466	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1467
1468	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1469	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1470	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1471	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1472	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1473	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1474
1475	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1476	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1477
1478	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1479	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1480	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1481	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1482	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1483	/** @} */
1484
1485	/** @name FPU operations taking a 32-bit signed integer argument
1486	* @{ */
1487	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1488	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1489	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1490
1491	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1492	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1493	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1494	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1495	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1496	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1497
1498	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1499	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1500
1501	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1502	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1503	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1504	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1505	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1506	/** @} */
1507
1508	/** @name FPU operations taking a 64-bit signed integer argument
1509	* @{ */
1510	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1511	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1512	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1513
1514	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1515	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1516	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1517	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1518	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1519	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1520
1521	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1522	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1523
1524	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1525	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1526	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1527	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1528	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1529	/** @} */
1530
1531
1532	/** Temporary type representing a 256-bit vector register. */
1533	typedef struct {uint64_t au64[4]; } IEMVMM256;
1534	/** Temporary type pointing to a 256-bit vector register. */
1535	typedef IEMVMM256 *PIEMVMM256;
1536	/** Temporary type pointing to a const 256-bit vector register. */
1537	typedef IEMVMM256 *PCIEMVMM256;
1538
1539
1540	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1541	* @{ */
1542	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1543	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1544	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1545	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1546	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1547	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1548	/** @} */
1549
1550	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1551	* @{ */
1552	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1553	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1554	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1555	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1556	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1557	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1558	/** @} */
1559
1560	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1561	* @{ */
1562	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1563	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1564	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1565	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1566	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1567	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1568	/** @} */
1569
1570	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1571	* @{ */
1572	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1573	PCRTUINT128U pu128Src, uint8_t bEvil));
1574	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1575	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1576	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1577	/** @} */
1578
1579	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1580	* @{ */
1581	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1582	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1583	/** @} */
1584
1585	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1586	* @{ */
1587	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1588	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1589	/** @} */
1590
1591
1592	/** @name Function tables.
1593	* @{
1594	*/
1595
1596	/**
1597	* Function table for a binary operator providing implementation based on
1598	* operand size.
1599	*/
1600	typedef struct IEMOPBINSIZES
1601	{
1602	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1603	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1604	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1605	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1606	} IEMOPBINSIZES;
1607	/** Pointer to a binary operator function table. */
1608	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1609
1610
1611	/**
1612	* Function table for a unary operator providing implementation based on
1613	* operand size.
1614	*/
1615	typedef struct IEMOPUNARYSIZES
1616	{
1617	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1618	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1619	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1620	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1621	} IEMOPUNARYSIZES;
1622	/** Pointer to a unary operator function table. */
1623	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1624
1625
1626	/**
1627	* Function table for a shift operator providing implementation based on
1628	* operand size.
1629	*/
1630	typedef struct IEMOPSHIFTSIZES
1631	{
1632	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1633	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1634	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1635	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1636	} IEMOPSHIFTSIZES;
1637	/** Pointer to a shift operator function table. */
1638	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1639
1640
1641	/**
1642	* Function table for a multiplication or division operation.
1643	*/
1644	typedef struct IEMOPMULDIVSIZES
1645	{
1646	PFNIEMAIMPLMULDIVU8 pfnU8;
1647	PFNIEMAIMPLMULDIVU16 pfnU16;
1648	PFNIEMAIMPLMULDIVU32 pfnU32;
1649	PFNIEMAIMPLMULDIVU64 pfnU64;
1650	} IEMOPMULDIVSIZES;
1651	/** Pointer to a multiplication or division operation function table. */
1652	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1653
1654
1655	/**
1656	* Function table for a double precision shift operator providing implementation
1657	* based on operand size.
1658	*/
1659	typedef struct IEMOPSHIFTDBLSIZES
1660	{
1661	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1662	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1663	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1664	} IEMOPSHIFTDBLSIZES;
1665	/** Pointer to a double precision shift function table. */
1666	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1667
1668
1669	/**
1670	* Function table for media instruction taking two full sized media registers,
1671	* optionally the 2nd being a memory reference (only modifying the first op.)
1672	*/
1673	typedef struct IEMOPMEDIAF2
1674	{
1675	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1676	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1677	} IEMOPMEDIAF2;
1678	/** Pointer to a media operation function table for full sized ops. */
1679	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1680
1681	/**
1682	* Function table for media instruction taking taking one full and one lower
1683	* half media register.
1684	*/
1685	typedef struct IEMOPMEDIAF1L1
1686	{
1687	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1688	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1689	} IEMOPMEDIAF1L1;
1690	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1691	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1692
1693	/**
1694	* Function table for media instruction taking taking one full and one high half
1695	* media register.
1696	*/
1697	typedef struct IEMOPMEDIAF1H1
1698	{
1699	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1700	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1701	} IEMOPMEDIAF1H1;
1702	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1703	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1704
1705
1706	/** @} */
1707
1708
1709	/** @name C instruction implementations for anything slightly complicated.
1710	* @{ */
1711
1712	/**
1713	* For typedef'ing or declaring a C instruction implementation function taking
1714	* no extra arguments.
1715	*
1716	* @param a_Name The name of the type.
1717	*/
1718	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1719	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1720	/**
1721	* For defining a C instruction implementation function taking no extra
1722	* arguments.
1723	*
1724	* @param a_Name The name of the function
1725	*/
1726	# define IEM_CIMPL_DEF_0(a_Name) \
1727	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1728	/**
1729	* For calling a C instruction implementation function taking no extra
1730	* arguments.
1731	*
1732	* This special call macro adds default arguments to the call and allow us to
1733	* change these later.
1734	*
1735	* @param a_fn The name of the function.
1736	*/
1737	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1738
1739	/**
1740	* For typedef'ing or declaring a C instruction implementation function taking
1741	* one extra argument.
1742	*
1743	* @param a_Name The name of the type.
1744	* @param a_Type0 The argument type.
1745	* @param a_Arg0 The argument name.
1746	*/
1747	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1748	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1749	/**
1750	* For defining a C instruction implementation function taking one extra
1751	* argument.
1752	*
1753	* @param a_Name The name of the function
1754	* @param a_Type0 The argument type.
1755	* @param a_Arg0 The argument name.
1756	*/
1757	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1758	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1759	/**
1760	* For calling a C instruction implementation function taking one extra
1761	* argument.
1762	*
1763	* This special call macro adds default arguments to the call and allow us to
1764	* change these later.
1765	*
1766	* @param a_fn The name of the function.
1767	* @param a0 The name of the 1st argument.
1768	*/
1769	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1770
1771	/**
1772	* For typedef'ing or declaring a C instruction implementation function taking
1773	* two extra arguments.
1774	*
1775	* @param a_Name The name of the type.
1776	* @param a_Type0 The type of the 1st argument
1777	* @param a_Arg0 The name of the 1st argument.
1778	* @param a_Type1 The type of the 2nd argument.
1779	* @param a_Arg1 The name of the 2nd argument.
1780	*/
1781	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1782	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1783	/**
1784	* For defining a C instruction implementation function taking two extra
1785	* arguments.
1786	*
1787	* @param a_Name The name of the function.
1788	* @param a_Type0 The type of the 1st argument
1789	* @param a_Arg0 The name of the 1st argument.
1790	* @param a_Type1 The type of the 2nd argument.
1791	* @param a_Arg1 The name of the 2nd argument.
1792	*/
1793	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1794	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1795	/**
1796	* For calling a C instruction implementation function taking two extra
1797	* arguments.
1798	*
1799	* This special call macro adds default arguments to the call and allow us to
1800	* change these later.
1801	*
1802	* @param a_fn The name of the function.
1803	* @param a0 The name of the 1st argument.
1804	* @param a1 The name of the 2nd argument.
1805	*/
1806	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1807
1808	/**
1809	* For typedef'ing or declaring a C instruction implementation function taking
1810	* three extra arguments.
1811	*
1812	* @param a_Name The name of the type.
1813	* @param a_Type0 The type of the 1st argument
1814	* @param a_Arg0 The name of the 1st argument.
1815	* @param a_Type1 The type of the 2nd argument.
1816	* @param a_Arg1 The name of the 2nd argument.
1817	* @param a_Type2 The type of the 3rd argument.
1818	* @param a_Arg2 The name of the 3rd argument.
1819	*/
1820	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1821	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1822	/**
1823	* For defining a C instruction implementation function taking three extra
1824	* arguments.
1825	*
1826	* @param a_Name The name of the function.
1827	* @param a_Type0 The type of the 1st argument
1828	* @param a_Arg0 The name of the 1st argument.
1829	* @param a_Type1 The type of the 2nd argument.
1830	* @param a_Arg1 The name of the 2nd argument.
1831	* @param a_Type2 The type of the 3rd argument.
1832	* @param a_Arg2 The name of the 3rd argument.
1833	*/
1834	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1835	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1836	/**
1837	* For calling a C instruction implementation function taking three extra
1838	* arguments.
1839	*
1840	* This special call macro adds default arguments to the call and allow us to
1841	* change these later.
1842	*
1843	* @param a_fn The name of the function.
1844	* @param a0 The name of the 1st argument.
1845	* @param a1 The name of the 2nd argument.
1846	* @param a2 The name of the 3rd argument.
1847	*/
1848	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1849
1850
1851	/**
1852	* For typedef'ing or declaring a C instruction implementation function taking
1853	* four extra arguments.
1854	*
1855	* @param a_Name The name of the type.
1856	* @param a_Type0 The type of the 1st argument
1857	* @param a_Arg0 The name of the 1st argument.
1858	* @param a_Type1 The type of the 2nd argument.
1859	* @param a_Arg1 The name of the 2nd argument.
1860	* @param a_Type2 The type of the 3rd argument.
1861	* @param a_Arg2 The name of the 3rd argument.
1862	* @param a_Type3 The type of the 4th argument.
1863	* @param a_Arg3 The name of the 4th argument.
1864	*/
1865	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1866	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1867	/**
1868	* For defining a C instruction implementation function taking four extra
1869	* arguments.
1870	*
1871	* @param a_Name The name of the function.
1872	* @param a_Type0 The type of the 1st argument
1873	* @param a_Arg0 The name of the 1st argument.
1874	* @param a_Type1 The type of the 2nd argument.
1875	* @param a_Arg1 The name of the 2nd argument.
1876	* @param a_Type2 The type of the 3rd argument.
1877	* @param a_Arg2 The name of the 3rd argument.
1878	* @param a_Type3 The type of the 4th argument.
1879	* @param a_Arg3 The name of the 4th argument.
1880	*/
1881	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1882	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1883	a_Type2 a_Arg2, a_Type3 a_Arg3))
1884	/**
1885	* For calling a C instruction implementation function taking four extra
1886	* arguments.
1887	*
1888	* This special call macro adds default arguments to the call and allow us to
1889	* change these later.
1890	*
1891	* @param a_fn The name of the function.
1892	* @param a0 The name of the 1st argument.
1893	* @param a1 The name of the 2nd argument.
1894	* @param a2 The name of the 3rd argument.
1895	* @param a3 The name of the 4th argument.
1896	*/
1897	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1898
1899
1900	/**
1901	* For typedef'ing or declaring a C instruction implementation function taking
1902	* five extra arguments.
1903	*
1904	* @param a_Name The name of the type.
1905	* @param a_Type0 The type of the 1st argument
1906	* @param a_Arg0 The name of the 1st argument.
1907	* @param a_Type1 The type of the 2nd argument.
1908	* @param a_Arg1 The name of the 2nd argument.
1909	* @param a_Type2 The type of the 3rd argument.
1910	* @param a_Arg2 The name of the 3rd argument.
1911	* @param a_Type3 The type of the 4th argument.
1912	* @param a_Arg3 The name of the 4th argument.
1913	* @param a_Type4 The type of the 5th argument.
1914	* @param a_Arg4 The name of the 5th argument.
1915	*/
1916	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1917	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1918	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1919	a_Type3 a_Arg3, a_Type4 a_Arg4))
1920	/**
1921	* For defining a C instruction implementation function taking five extra
1922	* arguments.
1923	*
1924	* @param a_Name The name of the function.
1925	* @param a_Type0 The type of the 1st argument
1926	* @param a_Arg0 The name of the 1st argument.
1927	* @param a_Type1 The type of the 2nd argument.
1928	* @param a_Arg1 The name of the 2nd argument.
1929	* @param a_Type2 The type of the 3rd argument.
1930	* @param a_Arg2 The name of the 3rd argument.
1931	* @param a_Type3 The type of the 4th argument.
1932	* @param a_Arg3 The name of the 4th argument.
1933	* @param a_Type4 The type of the 5th argument.
1934	* @param a_Arg4 The name of the 5th argument.
1935	*/
1936	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1937	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1938	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1939	a_Type3 a_Arg3, a_Type4 a_Arg4))
1940	/**
1941	* For calling a C instruction implementation function taking five extra
1942	* arguments.
1943	*
1944	* This special call macro adds default arguments to the call and allow us to
1945	* change these later.
1946	*
1947	* @param a_fn The name of the function.
1948	* @param a0 The name of the 1st argument.
1949	* @param a1 The name of the 2nd argument.
1950	* @param a2 The name of the 3rd argument.
1951	* @param a3 The name of the 4th argument.
1952	* @param a4 The name of the 5th argument.
1953	*/
1954	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1955
1956	/** @} */
1957
1958
1959	/** @} */
1960
1961	RT_C_DECLS_END
1962
1963	#endif
1964

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 66471

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