IEMInternal.h@ 106329

Last change on this file since 106329 was 106329, checked in by vboxsync, 7 weeks ago
VMM/IEM: Some minor perf tweaks for iemExecMemAllocatorPrune. bugref:10720
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1	/* $Id: IEMInternal.h 106329 2024-10-15 14:19:43Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEM_WITH_ADAPTIVE_TIMER_POLLING
96	* Enables the adaptive timer polling code.
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEM_WITH_ADAPTIVE_TIMER_POLLING
100	#endif
101
102	/** @def IEM_WITH_INTRA_TB_JUMPS
103	* Enables loop-jumps within a TB (currently only to the first call).
104	*/
105	#if defined(DOXYGEN_RUNNING) \|\| 1
106	# define IEM_WITH_INTRA_TB_JUMPS
107	#endif
108
109	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
110	* Enables the delayed PC updating optimization (see @bugref{10373}).
111	*/
112	#if defined(DOXYGEN_RUNNING) \|\| 1
113	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
114	#endif
115	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
116	* Enabled delayed PC updating debugging code.
117	* This is an alternative to the ARM64-only IEMNATIVE_REG_FIXED_PC_DBG. */
118	#if defined(DOXYGEN_RUNNING) \|\| 0
119	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
120	#endif
121
122	/** Enables the SIMD register allocator @bugref{10614}. */
123	#if defined(DOXYGEN_RUNNING) \|\| 1
124	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
125	#endif
126	/** Enables access to even callee saved registers. */
127	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
128
129	#if defined(DOXYGEN_RUNNING) \|\| 1
130	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
131	* Delay the writeback or dirty registers as long as possible. */
132	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
133	#endif
134
135	/** @def IEM_WITH_TLB_STATISTICS
136	* Enables all TLB statistics. */
137	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
138	# define IEM_WITH_TLB_STATISTICS
139	#endif
140
141	/** @def IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
142	* Enable this to use native emitters for certain SIMD FP operations. */
143	#if 1 \|\| defined(DOXYGEN_RUNNING)
144	# define IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
145	#endif
146
147	/** @def VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING
148	* Enable this to create a saved state file with the threaded translation
149	* blocks fed to the native recompiler on VCPU \#0. The resulting file can
150	* then be fed into the native recompiler for code profiling purposes.
151	* This is not a feature that should be normally be enabled! */
152	#if 0 \|\| defined(DOXYGEN_RUNNING)
153	# define VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING
154	#endif
155
156	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
157	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
158	* executing native translation blocks.
159	*
160	* This exploits the fact that we save all non-volatile registers in the TB
161	* prologue and thus just need to do the same as the TB epilogue to get the
162	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
163	* non-volatile (and does something even more crazy for ARM), this probably
164	* won't work reliably on Windows. */
165	#ifdef RT_ARCH_ARM64
166	# ifndef RT_OS_WINDOWS
167	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
168	# endif
169	#endif
170	/* ASM-NOINC-START */
171	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
172	# if !defined(IN_RING3) \
173	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
174	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
175	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
176	# elif defined(RT_OS_WINDOWS)
177	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
178	# endif
179	#endif
180
181
182	/** @def IEM_DO_LONGJMP
183	*
184	* Wrapper around longjmp / throw.
185	*
186	* @param a_pVCpu The CPU handle.
187	* @param a_rc The status code jump back with / throw.
188	*/
189	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
190	# ifdef IEM_WITH_THROW_CATCH
191	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
192	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
193	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
194	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
195	throw int(a_rc); \
196	} while (0)
197	# else
198	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
199	# endif
200	# else
201	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
202	# endif
203	#endif
204
205	/** For use with IEM function that may do a longjmp (when enabled).
206	*
207	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
208	* attribute. So, we indicate that function that may be part of a longjmp may
209	* throw "exceptions" and that the compiler should definitely not generate and
210	* std::terminate calling unwind code.
211	*
212	* Here is one example of this ending in std::terminate:
213	* @code{.txt}
214	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
215	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
216	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
217	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
218	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
219	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
220	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
221	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
222	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
223	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
224	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
225	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
226	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
227	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
228	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
229	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
230	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
231	@endcode
232	*
233	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
234	*/
235	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
236	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
237	#else
238	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
239	#endif
240	/* ASM-NOINC-END */
241
242	#define IEM_IMPLEMENTS_TASKSWITCH
243
244	/** @def IEM_WITH_3DNOW
245	* Includes the 3DNow decoding. */
246	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
247	# ifndef IEM_WITHOUT_3DNOW
248	# define IEM_WITH_3DNOW
249	# endif
250	#endif
251
252	/** @def IEM_WITH_THREE_0F_38
253	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
254	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
255	# ifndef IEM_WITHOUT_THREE_0F_38
256	# define IEM_WITH_THREE_0F_38
257	# endif
258	#endif
259
260	/** @def IEM_WITH_THREE_0F_3A
261	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
262	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
263	# ifndef IEM_WITHOUT_THREE_0F_3A
264	# define IEM_WITH_THREE_0F_3A
265	# endif
266	#endif
267
268	/** @def IEM_WITH_VEX
269	* Includes the VEX decoding. */
270	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
271	# ifndef IEM_WITHOUT_VEX
272	# define IEM_WITH_VEX
273	# endif
274	#endif
275
276	/** @def IEM_CFG_TARGET_CPU
277	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
278	*
279	* By default we allow this to be configured by the user via the
280	* CPUM/GuestCpuName config string, but this comes at a slight cost during
281	* decoding. So, for applications of this code where there is no need to
282	* be dynamic wrt target CPU, just modify this define.
283	*/
284	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
285	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
286	#endif
287
288	//#define IEM_WITH_CODE_TLB // - work in progress
289	//#define IEM_WITH_DATA_TLB // - work in progress
290
291
292	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
293	* Use unaligned accesses instead of elaborate byte assembly. */
294	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
295	# define IEM_USE_UNALIGNED_DATA_ACCESS
296	#endif /ASM-NOINC/
297
298	//#define IEM_LOG_MEMORY_WRITES
299
300
301
302	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
303
304	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
305	/** Instruction statistics. */
306	typedef struct IEMINSTRSTATS
307	{
308	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
309	# include "IEMInstructionStatisticsTmpl.h"
310	# undef IEM_DO_INSTR_STAT
311	} IEMINSTRSTATS;
312	#else
313	struct IEMINSTRSTATS;
314	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
315	#endif
316	/** Pointer to IEM instruction statistics. */
317	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
318
319
320	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
321	* @{ */
322	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
323	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
324	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
325	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
326	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
327	/** Selects the right variant from a_aArray.
328	* pVCpu is implicit in the caller context. */
329	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
330	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
331	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
332	* be used because the host CPU does not support the operation. */
333	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
334	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
335	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
336	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
337	* into the two.
338	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
339	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
340	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
341	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
342	#else
343	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
344	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
345	#endif
346	/** @} */
347
348	/**
349	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
350	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
351	*
352	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
353	* indicator.
354	*
355	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
356	*/
357	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
358	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
359	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
360	#else
361	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
362	#endif
363
364	/** @name Helpers for passing C++ template arguments to an
365	* IEM_MC_NATIVE_EMIT_3/4/5 style macro.
366	* @{
367	*/
368	#define IEM_TEMPL_ARG_1(a1) <a1>
369	#define IEM_TEMPL_ARG_2(a1, a2) <a1,a2>
370	#define IEM_TEMPL_ARG_3(a1, a2, a3) <a1,a2,a3>
371	/** @} */
372
373
374	/**
375	* Branch types.
376	*/
377	typedef enum IEMBRANCH
378	{
379	IEMBRANCH_JUMP = 1,
380	IEMBRANCH_CALL,
381	IEMBRANCH_TRAP,
382	IEMBRANCH_SOFTWARE_INT,
383	IEMBRANCH_HARDWARE_INT
384	} IEMBRANCH;
385	AssertCompileSize(IEMBRANCH, 4);
386
387
388	/**
389	* INT instruction types.
390	*/
391	typedef enum IEMINT
392	{
393	/** INT n instruction (opcode 0xcd imm). */
394	IEMINT_INTN = 0,
395	/** Single byte INT3 instruction (opcode 0xcc). */
396	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
397	/** Single byte INTO instruction (opcode 0xce). */
398	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
399	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
400	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
401	} IEMINT;
402	AssertCompileSize(IEMINT, 4);
403
404
405	/**
406	* A FPU result.
407	*/
408	typedef struct IEMFPURESULT
409	{
410	/** The output value. */
411	RTFLOAT80U r80Result;
412	/** The output status. */
413	uint16_t FSW;
414	} IEMFPURESULT;
415	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
416	/** Pointer to a FPU result. */
417	typedef IEMFPURESULT *PIEMFPURESULT;
418	/** Pointer to a const FPU result. */
419	typedef IEMFPURESULT const *PCIEMFPURESULT;
420
421
422	/**
423	* A FPU result consisting of two output values and FSW.
424	*/
425	typedef struct IEMFPURESULTTWO
426	{
427	/** The first output value. */
428	RTFLOAT80U r80Result1;
429	/** The output status. */
430	uint16_t FSW;
431	/** The second output value. */
432	RTFLOAT80U r80Result2;
433	} IEMFPURESULTTWO;
434	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
435	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
436	/** Pointer to a FPU result consisting of two output values and FSW. */
437	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
438	/** Pointer to a const FPU result consisting of two output values and FSW. */
439	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
440
441
442	/**
443	* IEM TLB entry.
444	*
445	* Lookup assembly:
446	* @code{.asm}
447	; Calculate tag.
448	mov rax, [VA]
449	shl rax, 16
450	shr rax, 16 + X86_PAGE_SHIFT
451	or rax, [uTlbRevision]
452
453	; Do indexing.
454	movzx ecx, al
455	lea rcx, [pTlbEntries + rcx]
456
457	; Check tag.
458	cmp [rcx + IEMTLBENTRY.uTag], rax
459	jne .TlbMiss
460
461	; Check access.
462	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
463	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
464	cmp rax, [uTlbPhysRev]
465	jne .TlbMiss
466
467	; Calc address and we're done.
468	mov eax, X86_PAGE_OFFSET_MASK
469	and eax, [VA]
470	or rax, [rcx + IEMTLBENTRY.pMappingR3]
471	%ifdef VBOX_WITH_STATISTICS
472	inc qword [cTlbHits]
473	%endif
474	jmp .Done
475
476	.TlbMiss:
477	mov r8d, ACCESS_FLAGS
478	mov rdx, [VA]
479	mov rcx, [pVCpu]
480	call iemTlbTypeMiss
481	.Done:
482
483	@endcode
484	*
485	*/
486	typedef struct IEMTLBENTRY
487	{
488	/** The TLB entry tag.
489	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
490	* is ASSUMING a virtual address width of 48 bits.
491	*
492	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
493	*
494	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
495	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
496	* revision wraps around though, the tags needs to be zeroed.
497	*
498	* @note Try use SHRD instruction? After seeing
499	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
500	*
501	* @todo This will need to be reorganized for 57-bit wide virtual address and
502	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
503	* have to move the TLB entry versioning entirely to the
504	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
505	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
506	* consumed by PCID and ASID (12 + 6 = 18).
507	*/
508	uint64_t uTag;
509	/** Access flags and physical TLB revision.
510	*
511	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
512	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
513	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
514	* - Bit 3 - pgm phys/virt - not directly writable.
515	* - Bit 4 - pgm phys page - not directly readable.
516	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
517	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
518	* - Bit 7 - tlb entry - pMappingR3 member not valid.
519	* - Bits 63 thru 8 are used for the physical TLB revision number.
520	*
521	* We're using complemented bit meanings here because it makes it easy to check
522	* whether special action is required. For instance a user mode write access
523	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
524	* non-zero result would mean special handling needed because either it wasn't
525	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
526	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
527	* need to check any PTE flag.
528	*/
529	uint64_t fFlagsAndPhysRev;
530	/** The guest physical page address. */
531	uint64_t GCPhys;
532	/** Pointer to the ring-3 mapping. */
533	R3PTRTYPE(uint8_t *) pbMappingR3;
534	#if HC_ARCH_BITS == 32
535	uint32_t u32Padding1;
536	#endif
537	} IEMTLBENTRY;
538	AssertCompileSize(IEMTLBENTRY, 32);
539	/** Pointer to an IEM TLB entry. */
540	typedef IEMTLBENTRY *PIEMTLBENTRY;
541	/** Pointer to a const IEM TLB entry. */
542	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
543
544	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
545	* @{ */
546	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
547	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
548	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
549	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
550	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
551	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
552	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
553	#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /*< Page tables: Large 2 or 4 MiB page (for flushing). /
554	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
555	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
556	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /*< Phys page: Code page. /
557	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
558	/** @} */
559	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
560	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
561	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
562	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
563	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
564	AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
565	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
566	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
567	\| PGMIEMGCPHYS2PTR_F_NO_READ \
568	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
569	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
570	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
571	\| IEMTLBE_F_PHYS_REV )
572
573
574	/** The TLB size (power of two).
575	* We initially chose 256 because that way we can obtain the result directly
576	* from a 8-bit register without an additional AND instruction.
577	* See also @bugref{10687}. */
578	#if defined(RT_ARCH_AMD64)
579	# define IEMTLB_ENTRY_COUNT 256
580	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
581	#else
582	# define IEMTLB_ENTRY_COUNT 8192
583	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
584	#endif
585	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
586
587	/** TLB slot format spec (assumes uint32_t or unsigned value). */
588	#if IEMTLB_ENTRY_COUNT <= 0x100 / 2
589	# define IEMTLB_SLOT_FMT "%02x"
590	#elif IEMTLB_ENTRY_COUNT <= 0x1000 / 2
591	# define IEMTLB_SLOT_FMT "%03x"
592	#elif IEMTLB_ENTRY_COUNT <= 0x10000 / 2
593	# define IEMTLB_SLOT_FMT "%04x"
594	#else
595	# define IEMTLB_SLOT_FMT "%05x"
596	#endif
597
598	/** Enable the large page bitmap TLB optimization.
599	*
600	* The idea here is to avoid scanning the full 32 KB (2MB pages, 2*512 TLB
601	* entries) or 64 KB (4MB pages, 2*1024 TLB entries) worth of TLB entries during
602	* invlpg when large pages are used, and instead just scan 128 or 256 bytes of
603	* the bmLargePage bitmap to determin which TLB entires that might be containing
604	* large pages and actually require checking.
605	*
606	* There is a good posibility of false positives since we currently don't clear
607	* the bitmap when flushing the TLB, but it should help reduce the workload when
608	* the large pages aren't fully loaded into the TLB in their entirity...
609	*/
610	#define IEMTLB_WITH_LARGE_PAGE_BITMAP
611
612	/**
613	* An IEM TLB.
614	*
615	* We've got two of these, one for data and one for instructions.
616	*/
617	typedef struct IEMTLB
618	{
619	/** The non-global TLB revision.
620	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
621	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
622	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
623	* (The revision zero indicates an invalid TLB entry.)
624	*
625	* The initial value is choosen to cause an early wraparound. */
626	uint64_t uTlbRevision;
627	/** The TLB physical address revision - shadow of PGM variable.
628	*
629	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
630	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
631	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
632	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
633	*
634	* The initial value is choosen to cause an early wraparound.
635	*
636	* @note This is placed between the two TLB revisions because we
637	* load it in pair with one or the other on arm64. */
638	uint64_t volatile uTlbPhysRev;
639	/** The global TLB revision.
640	* Same as uTlbRevision, but only increased for global flushes. */
641	uint64_t uTlbRevisionGlobal;
642
643	/** Large page tag range.
644	*
645	* This is used to avoid scanning a large page's worth of TLB entries for each
646	* INVLPG instruction, and only to do so iff we've loaded any and when the
647	* address is in this range. This is kept up to date when we loading new TLB
648	* entries.
649	*/
650	struct LARGEPAGERANGE
651	{
652	/** The lowest large page address tag, UINT64_MAX if none. */
653	uint64_t uFirstTag;
654	/** The highest large page address tag (with offset mask part set), 0 if none. */
655	uint64_t uLastTag;
656	}
657	/** Large page range for non-global pages. */
658	NonGlobalLargePageRange,
659	/** Large page range for global pages. */
660	GlobalLargePageRange;
661	/** Number of non-global entries for large pages loaded since last TLB flush. */
662	uint32_t cTlbNonGlobalLargePageCurLoads;
663	/** Number of global entries for large pages loaded since last TLB flush. */
664	uint32_t cTlbGlobalLargePageCurLoads;
665
666	/* Statistics: */
667
668	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
669	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
670	* not via safe read/write path) calls to iemMemMapJmp. */
671	uint64_t cTlbCoreHits;
672	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
673	* only; data tlb only). */
674	uint64_t cTlbSafeHits;
675	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
676	uint64_t cTlbInlineCodeHits;
677
678	/** TLB misses in IEMAll.cpp code (both).
679	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
680	* not via safe read/write path) calls to iemMemMapJmp. So,
681	* for the data TLB this more like 'other misses', while for the code
682	* TLB is all misses. */
683	uint64_t cTlbCoreMisses;
684	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
685	uint64_t cTlbCoreGlobalLoads;
686	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
687	uint64_t cTlbSafeMisses;
688	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
689	uint64_t cTlbSafeGlobalLoads;
690	/** Safe read path taken (data only). */
691	uint64_t cTlbSafeReadPath;
692	/** Safe write path taken (data only). */
693	uint64_t cTlbSafeWritePath;
694
695	/** @name Details for native code TLB misses.
696	* @note These counts are included in the above counters (cTlbSafeReadPath,
697	* cTlbSafeWritePath, cTlbInlineCodeHits).
698	* @{ */
699	/** TLB misses in native code due to tag mismatch. */
700	STAMCOUNTER cTlbNativeMissTag;
701	/** TLB misses in native code due to flags or physical revision mismatch. */
702	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
703	/** TLB misses in native code due to misaligned access. */
704	STAMCOUNTER cTlbNativeMissAlignment;
705	/** TLB misses in native code due to cross page access. */
706	uint32_t cTlbNativeMissCrossPage;
707	/** TLB misses in native code due to non-canonical address. */
708	uint32_t cTlbNativeMissNonCanonical;
709	/** @} */
710
711	/** Slow read path (code only). */
712	uint32_t cTlbSlowCodeReadPath;
713
714	/** Regular TLB flush count. */
715	uint32_t cTlsFlushes;
716	/** Global TLB flush count. */
717	uint32_t cTlsGlobalFlushes;
718	/** Revision rollovers. */
719	uint32_t cTlbRevisionRollovers;
720	/** Physical revision flushes. */
721	uint32_t cTlbPhysRevFlushes;
722	/** Physical revision rollovers. */
723	uint32_t cTlbPhysRevRollovers;
724
725	/** Number of INVLPG (and similar) operations. */
726	uint32_t cTlbInvlPg;
727	/** Subset of cTlbInvlPg that involved non-global large pages. */
728	uint32_t cTlbInvlPgLargeNonGlobal;
729	/** Subset of cTlbInvlPg that involved global large pages. */
730	uint32_t cTlbInvlPgLargeGlobal;
731
732	uint32_t au32Padding[13];
733
734	/** The TLB entries.
735	* Even entries are for PTE.G=0 and uses uTlbRevision.
736	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
737	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
738	#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
739	/** Bitmap tracking TLB entries for large pages.
740	* This duplicates IEMTLBE_F_PT_LARGE_PAGE for each TLB entry. */
741	uint64_t bmLargePage[IEMTLB_ENTRY_COUNT * 2 / 64];
742	#endif
743	} IEMTLB;
744	AssertCompileSizeAlignment(IEMTLB, 64);
745	#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
746	AssertCompile(IEMTLB_ENTRY_COUNT >= 32 /* bmLargePage ASSUMPTION */);
747	#endif
748	/** The width (in bits) of the address portion of the TLB tag. */
749	#define IEMTLB_TAG_ADDR_WIDTH 36
750	/** IEMTLB::uTlbRevision increment. */
751	#define IEMTLB_REVISION_INCR RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH)
752	/** IEMTLB::uTlbRevision mask. */
753	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH) - 1))
754
755	/** IEMTLB::uTlbPhysRev increment.
756	* @sa IEMTLBE_F_PHYS_REV */
757	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
758	AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
759
760	/**
761	* Calculates the TLB tag for a virtual address but without TLB revision.
762	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
763	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
764	* the clearing of the top 16 bits won't work (if 32-bit
765	* we'll end up with mostly zeros).
766	*/
767	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
768	/**
769	* Converts a TLB tag value into a even TLB index.
770	* @returns Index into IEMTLB::aEntries.
771	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
772	*/
773	#if IEMTLB_ENTRY_COUNT == 256
774	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
775	#else
776	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
777	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
778	#endif
779	/**
780	* Converts a TLB tag value into an even TLB index.
781	* @returns Pointer into IEMTLB::aEntries corresponding to .
782	* @param a_pTlb The TLB.
783	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
784	* IEMTLB_CALC_TAG_NO_REV.
785	*/
786	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
787
788	/** Converts a GC address to an even TLB index. */
789	#define IEMTLB_ADDR_TO_EVEN_INDEX(a_GCPtr) IEMTLB_TAG_TO_EVEN_INDEX(IEMTLB_CALC_TAG_NO_REV(a_GCPtr))
790
791
792	/** @def IEM_WITH_TLB_TRACE
793	* Enables the TLB tracing.
794	* Adjust buffer size in IEMR3Init. */
795	#if defined(DOXYGEN_RUNNING) \|\| 0
796	# define IEM_WITH_TLB_TRACE
797	#endif
798
799	#ifdef IEM_WITH_TLB_TRACE
800
801	/** TLB trace entry types. */
802	typedef enum : uint8_t
803	{
804	kIemTlbTraceType_Invalid,
805	kIemTlbTraceType_InvlPg,
806	kIemTlbTraceType_EvictSlot,
807	kIemTlbTraceType_LargeEvictSlot,
808	kIemTlbTraceType_LargeScan,
809	kIemTlbTraceType_Flush,
810	kIemTlbTraceType_FlushGlobal,
811	kIemTlbTraceType_Load,
812	kIemTlbTraceType_LoadGlobal,
813	kIemTlbTraceType_Load_Cr0,
814	kIemTlbTraceType_Load_Cr3,
815	kIemTlbTraceType_Load_Cr4,
816	kIemTlbTraceType_Load_Efer,
817	kIemTlbTraceType_Irq,
818	kIemTlbTraceType_Xcpt,
819	kIemTlbTraceType_IRet,
820	kIemTlbTraceType_Tb_Compile,
821	kIemTlbTraceType_Tb_Exec_Threaded,
822	kIemTlbTraceType_Tb_Exec_Native,
823	kIemTlbTraceType_User0,
824	kIemTlbTraceType_User1,
825	kIemTlbTraceType_User2,
826	kIemTlbTraceType_User3,
827	} IEMTLBTRACETYPE;
828
829	/** TLB trace entry. */
830	typedef struct IEMTLBTRACEENTRY
831	{
832	/** The flattened RIP for the event. */
833	uint64_t rip;
834	/** The event type. */
835	IEMTLBTRACETYPE enmType;
836	/** Byte parameter - typically used as 'bool fDataTlb'. */
837	uint8_t bParam;
838	/** 16-bit parameter value. */
839	uint16_t u16Param;
840	/** 32-bit parameter value. */
841	uint32_t u32Param;
842	/** 64-bit parameter value. */
843	uint64_t u64Param;
844	/** 64-bit parameter value. */
845	uint64_t u64Param2;
846	} IEMTLBTRACEENTRY;
847	AssertCompileSize(IEMTLBTRACEENTRY, 32);
848	/** Pointer to a TLB trace entry. */
849	typedef IEMTLBTRACEENTRY *PIEMTLBTRACEENTRY;
850	/** Pointer to a const TLB trace entry. */
851	typedef IEMTLBTRACEENTRY const *PCIEMTLBTRACEENTRY;
852	#endif /* !IEM_WITH_TLB_TRACE */
853
854	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
855	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) \
856	iemTlbTrace(a_pVCpu, kIemTlbTraceType_InvlPg, a_GCPtr)
857	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
858	iemTlbTrace(a_pVCpu, kIemTlbTraceType_EvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
859	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
860	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeEvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
861	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) \
862	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeScan, 0, 0, a_fDataTlb, (uint8_t)a_fGlobal \| ((uint8_t)a_fNonGlobal << 1))
863	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) \
864	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Flush, a_uRev, 0, a_fDataTlb)
865	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) \
866	iemTlbTrace(a_pVCpu, kIemTlbTraceType_FlushGlobal, a_uRev, a_uGRev, a_fDataTlb)
867	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
868	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
869	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
870	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LoadGlobal, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
871	#else
872	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) do { } while (0)
873	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
874	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
875	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) do { } while (0)
876	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) do { } while (0)
877	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) do { } while (0)
878	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
879	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
880	#endif
881
882	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
883	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr0, a_uNew, a_uOld)
884	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr3, a_uNew, a_uOld)
885	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr4, a_uNew, a_uOld)
886	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Efer, a_uNew, a_uOld)
887	#else
888	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) do { } while (0)
889	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) do { } while (0)
890	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) do { } while (0)
891	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) do { } while (0)
892	#endif
893
894	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
895	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) \
896	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Irq, a_fEFlags, 0, a_uVector, a_fFlags)
897	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) \
898	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Xcpt, a_uErr, a_uCr2, a_uVector, a_fFlags)
899	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) \
900	iemTlbTrace(a_pVCpu, kIemTlbTraceType_IRet, a_uRetRip, a_fEFlags, 0, a_uRetCs)
901	#else
902	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) do { } while (0)
903	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) do { } while (0)
904	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) do { } while (0)
905	#endif
906
907	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
908	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) \
909	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Compile, a_GCPhysPc)
910	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) \
911	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Threaded, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
912	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) \
913	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Native, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
914	#else
915	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) do { } while (0)
916	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) do { } while (0)
917	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) do { } while (0)
918	#endif
919
920	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
921	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
922	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User0, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
923	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
924	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User1, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
925	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
926	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User2, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
927	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
928	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User3, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
929	#else
930	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
931	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
932	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
933	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
934	#endif
935
936
937	/** @name IEM_MC_F_XXX - MC block flags/clues.
938	* @todo Merge with IEM_CIMPL_F_XXX
939	* @{ */
940	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
941	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
942	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
943	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
944	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
945	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
946	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
947	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
948	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
949	#define IEM_MC_F_64BIT RT_BIT_32(6)
950	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
951	/** This is set by IEMAllN8vePython.py to indicate a variation with the
952	* flags-clearing-and-checking. */
953	#define IEM_MC_F_WITH_FLAGS RT_BIT_32(8)
954	/** This is set by IEMAllN8vePython.py to indicate a variation without the
955	* flags-clearing-and-checking, when there is also a variation with that.
956	* @note Do not set this manully, it's only for python and for testing in
957	* the native recompiler! */
958	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(9)
959	/** @} */
960
961	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
962	*
963	* These clues are mainly for the recompiler, so that it can emit correct code.
964	*
965	* They are processed by the python script and which also automatically
966	* calculates flags for MC blocks based on the statements, extending the use of
967	* these flags to describe MC block behavior to the recompiler core. The python
968	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
969	* error checking purposes. The script emits the necessary fEndTb = true and
970	* similar statements as this reduces compile time a tiny bit.
971	*
972	* @{ */
973	/** Flag set if direct branch, clear if absolute or indirect. */
974	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
975	/** Flag set if indirect branch, clear if direct or relative.
976	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
977	* as well as for return instructions (RET, IRET, RETF). */
978	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
979	/** Flag set if relative branch, clear if absolute or indirect. */
980	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
981	/** Flag set if conditional branch, clear if unconditional. */
982	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
983	/** Flag set if it's a far branch (changes CS). */
984	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
985	/** Convenience: Testing any kind of branch. */
986	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
987
988	/** Execution flags may change (IEMCPU::fExec). */
989	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
990	/** May change significant portions of RFLAGS. */
991	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
992	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
993	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
994	/** May trigger interrupt shadowing. */
995	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
996	/** May enable interrupts, so recheck IRQ immediately afterwards executing
997	* the instruction. */
998	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
999	/** May disable interrupts, so recheck IRQ immediately before executing the
1000	* instruction. */
1001	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
1002	/** Convenience: Check for IRQ both before and after an instruction. */
1003	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
1004	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
1005	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
1006	/** May modify FPU state.
1007	* @todo Not sure if this is useful yet. */
1008	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
1009	/** REP prefixed instruction which may yield before updating PC.
1010	* @todo Not sure if this is useful, REP functions now return non-zero
1011	* status if they don't update the PC. */
1012	#define IEM_CIMPL_F_REP RT_BIT_32(13)
1013	/** I/O instruction.
1014	* @todo Not sure if this is useful yet. */
1015	#define IEM_CIMPL_F_IO RT_BIT_32(14)
1016	/** Force end of TB after the instruction. */
1017	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
1018	/** Flag set if a branch may also modify the stack (push/pop return address). */
1019	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
1020	/** Flag set if a branch may also modify the stack (push/pop return address)
1021	* and switch it (load/restore SS:RSP). */
1022	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
1023	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
1024	#define IEM_CIMPL_F_XCPT \
1025	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
1026	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
1027
1028	/** The block calls a C-implementation instruction function with two implicit arguments.
1029	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
1030	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1031	* @note The python scripts will add this if missing. */
1032	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
1033	/** The block calls an ASM-implementation instruction function.
1034	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
1035	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1036	* @note The python scripts will add this if missing. */
1037	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
1038	/** The block calls an ASM-implementation instruction function with an implicit
1039	* X86FXSTATE pointer argument.
1040	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1041	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
1042	* @note The python scripts will add this if missing. */
1043	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
1044	/** The block calls an ASM-implementation instruction function with an implicit
1045	* X86XSAVEAREA pointer argument.
1046	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1047	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1048	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
1049	* @note The python scripts will add this if missing. */
1050	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
1051	/** @} */
1052
1053
1054	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
1055	*
1056	* These flags are set when entering IEM and adjusted as code is executed, such
1057	* that they will always contain the current values as instructions are
1058	* finished.
1059	*
1060	* In recompiled execution mode, (most of) these flags are included in the
1061	* translation block selection key and stored in IEMTB::fFlags alongside the
1062	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
1063	* in IEMCPU::fExec.
1064	*
1065	* @{ */
1066	/** Mode: The block target mode mask. */
1067	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
1068	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
1069	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
1070	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
1071	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
1072	* 32-bit mode (for simplifying most memory accesses). */
1073	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
1074	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
1075	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
1076	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
1077	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
1078
1079	/** X86 Mode: 16-bit on 386 or later. */
1080	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
1081	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
1082	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
1083	/** X86 Mode: 16-bit protected mode on 386 or later. */
1084	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
1085	/** X86 Mode: 16-bit protected mode on 386 or later. */
1086	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
1087	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
1088	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
1089
1090	/** X86 Mode: 32-bit on 386 or later. */
1091	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
1092	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
1093	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
1094	/** X86 Mode: 32-bit protected mode. */
1095	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
1096	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
1097	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
1098
1099	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
1100	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
1101
1102	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
1103	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
1104	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
1105	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
1106
1107	/** Bypass access handlers when set. */
1108	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
1109	/** Have pending hardware instruction breakpoints. */
1110	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
1111	/** Have pending hardware data breakpoints. */
1112	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
1113
1114	/** X86: Have pending hardware I/O breakpoints. */
1115	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
1116	/** X86: Disregard the lock prefix (implied or not) when set. */
1117	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
1118
1119	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
1120	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
1121
1122	/** Caller configurable options. */
1123	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
1124
1125	/** X86: The current protection level (CPL) shift factor. */
1126	#define IEM_F_X86_CPL_SHIFT 8
1127	/** X86: The current protection level (CPL) mask. */
1128	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
1129	/** X86: The current protection level (CPL) shifted mask. */
1130	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
1131
1132	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
1133	#define IEM_F_X86_AC UINT32_C(0x00080000)
1134
1135	/** X86 execution context.
1136	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
1137	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
1138	* mode. */
1139	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
1140	/** X86 context: Plain regular execution context. */
1141	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
1142	/** X86 context: VT-x enabled. */
1143	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
1144	/** X86 context: AMD-V enabled. */
1145	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
1146	/** X86 context: In AMD-V or VT-x guest mode. */
1147	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
1148	/** X86 context: System management mode (SMM). */
1149	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
1150
1151	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1152	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
1153	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
1154	* alread). */
1155
1156	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1157	* iemRegFinishClearingRF() most for most situations
1158	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
1159	* the IEM_F_PENDING_BRK_XXX bits alread). */
1160
1161	/** @} */
1162
1163
1164	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
1165	*
1166	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
1167	* translation block flags. The combined flag mask (subject to
1168	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
1169	*
1170	* @{ */
1171	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
1172	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
1173
1174	/** Type: The block type mask. */
1175	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
1176	/** Type: Purly threaded recompiler (via tables). */
1177	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
1178	/** Type: Native recompilation. */
1179	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
1180
1181	/** Set when we're starting the block in an "interrupt shadow".
1182	* We don't need to distingish between the two types of this mask, thus the one.
1183	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
1184	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
1185	/** Set when we're currently inhibiting NMIs
1186	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
1187	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
1188
1189	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
1190	* we're close the limit before starting a TB, as determined by
1191	* iemGetTbFlagsForCurrentPc(). */
1192	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
1193
1194	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
1195	*
1196	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
1197	* don't implement), because we don't currently generate any context
1198	* specific code - that's all handled in CIMPL functions.
1199	*
1200	* For the threaded recompiler we don't generate any CPL specific code
1201	* either, but the native recompiler does for memory access (saves getting
1202	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
1203	* Since most OSes will not share code between rings, this shouldn't
1204	* have any real effect on TB/memory/recompiling load.
1205	*/
1206	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
1207	/** @} */
1208
1209	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1210	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1211	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
1212	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
1213	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1214	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1215	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
1216	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1217	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1218	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1219	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1220	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
1221	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1222	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1223	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
1224	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1225	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
1226	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1227	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
1228
1229	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1230	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1231	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
1232	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1233	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1234	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
1235	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1236	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1237	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1238	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1239	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1240	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
1241
1242	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
1243	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
1244	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1245
1246	/** Native instruction type for use with the native code generator.
1247	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
1248	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1249	typedef uint8_t IEMNATIVEINSTR;
1250	#else
1251	typedef uint32_t IEMNATIVEINSTR;
1252	#endif
1253	/** Pointer to a native instruction unit. */
1254	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
1255	/** Pointer to a const native instruction unit. */
1256	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
1257
1258	/**
1259	* A call for the threaded call table.
1260	*/
1261	typedef struct IEMTHRDEDCALLENTRY
1262	{
1263	/** The function to call (IEMTHREADEDFUNCS). */
1264	uint16_t enmFunction;
1265
1266	/** Instruction number in the TB (for statistics). */
1267	uint8_t idxInstr;
1268	/** The opcode length. */
1269	uint8_t cbOpcode;
1270	/** Offset into IEMTB::pabOpcodes. */
1271	uint16_t offOpcode;
1272
1273	/** TB lookup table index (7 bits) and large size (1 bits).
1274	*
1275	* The default size is 1 entry, but for indirect calls and returns we set the
1276	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1277	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1278	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1279	*
1280	* By default lookup table entry 0 for a TB is reserved as a fallback for
1281	* calltable entries w/o explicit entreis, so this member will be non-zero if
1282	* there is a lookup entry associated with this call.
1283	*
1284	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1285	*/
1286	uint8_t uTbLookup;
1287
1288	/** Flags - IEMTHREADEDCALLENTRY_F_XXX. */
1289	uint8_t fFlags;
1290
1291	/** Generic parameters. */
1292	uint64_t auParams[3];
1293	} IEMTHRDEDCALLENTRY;
1294	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1295	/** Pointer to a threaded call entry. */
1296	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1297	/** Pointer to a const threaded call entry. */
1298	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1299
1300	/** The number of TB lookup table entries for a large allocation
1301	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1302	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1303	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1304	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1305	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1306	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1307	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1308	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1309	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1310
1311	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1312	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1313
1314
1315	/** The call entry is a jump target. */
1316	#define IEMTHREADEDCALLENTRY_F_JUMP_TARGET UINT8_C(0x01)
1317
1318
1319	/**
1320	* Native IEM TB 'function' typedef.
1321	*
1322	* This will throw/longjmp on occation.
1323	*
1324	* @note AMD64 doesn't have that many non-volatile registers and does sport
1325	* 32-bit address displacments, so we don't need pCtx.
1326	*
1327	* On ARM64 pCtx allows us to directly address the whole register
1328	* context without requiring a separate indexing register holding the
1329	* offset. This saves an instruction loading the offset for each guest
1330	* CPU context access, at the cost of a non-volatile register.
1331	* Fortunately, ARM64 has quite a lot more registers.
1332	*/
1333	typedef
1334	#ifdef RT_ARCH_AMD64
1335	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1336	#else
1337	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1338	#endif
1339	#if RT_CPLUSPLUS_PREREQ(201700)
1340	IEM_NOEXCEPT_MAY_LONGJMP
1341	#endif
1342	;
1343	/** Pointer to a native IEM TB entry point function.
1344	* This will throw/longjmp on occation. */
1345	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1346
1347
1348	/**
1349	* Translation block.
1350	*
1351	* The current plan is to just keep TBs and associated lookup hash table private
1352	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1353	* avoids using expensive atomic primitives for updating lists and stuff.
1354	*/
1355	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1356	typedef struct IEMTB
1357	{
1358	/** Next block with the same hash table entry. */
1359	struct IEMTB *pNext;
1360	/** Usage counter. */
1361	uint32_t cUsed;
1362	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1363	uint32_t msLastUsed;
1364
1365	/** @name What uniquely identifies the block.
1366	* @{ */
1367	RTGCPHYS GCPhysPc;
1368	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1369	uint32_t fFlags;
1370	union
1371	{
1372	struct
1373	{
1374	/*< Relevant CS X86DESCATTR_XXX bits. /
1375	uint16_t fAttr;
1376	} x86;
1377	};
1378	/** @} */
1379
1380	/** Number of opcode ranges. */
1381	uint8_t cRanges;
1382	/** Statistics: Number of instructions in the block. */
1383	uint8_t cInstructions;
1384
1385	/** Type specific info. */
1386	union
1387	{
1388	struct
1389	{
1390	/** The call sequence table. */
1391	PIEMTHRDEDCALLENTRY paCalls;
1392	/** Number of calls in paCalls. */
1393	uint16_t cCalls;
1394	/** Number of calls allocated. */
1395	uint16_t cAllocated;
1396	} Thrd;
1397	struct
1398	{
1399	/** The native instructions (PFNIEMTBNATIVE). */
1400	PIEMNATIVEINSTR paInstructions;
1401	/** Number of instructions pointed to by paInstructions. */
1402	uint32_t cInstructions;
1403	} Native;
1404	/** Generic view for zeroing when freeing. */
1405	struct
1406	{
1407	uintptr_t uPtr;
1408	uint32_t uData;
1409	} Gen;
1410	};
1411
1412	/** The allocation chunk this TB belongs to. */
1413	uint8_t idxAllocChunk;
1414	/** The number of entries in the lookup table.
1415	* Because we're out of space, the TB lookup table is located before the
1416	* opcodes pointed to by pabOpcodes. */
1417	uint8_t cTbLookupEntries;
1418
1419	/** Number of bytes of opcodes stored in pabOpcodes.
1420	* @todo this field isn't really needed, aRanges keeps the actual info. */
1421	uint16_t cbOpcodes;
1422	/** Pointer to the opcode bytes this block was recompiled from.
1423	* This also points to the TB lookup table, which starts cTbLookupEntries
1424	* entries before the opcodes (we don't have room atm for another point). */
1425	uint8_t *pabOpcodes;
1426
1427	union
1428	{
1429	/** Native recompilation debug info if enabled.
1430	* This is only generated by the native recompiler. */
1431	struct IEMTBDBG *pDbgInfo;
1432	/** For threaded TBs and natives when debug info is disabled, this is the flat
1433	* PC corresponding to GCPhysPc. */
1434	RTGCPTR FlatPc;
1435	};
1436
1437	/* --- 64 byte cache line end --- */
1438
1439	/** Opcode ranges.
1440	*
1441	* The opcode checkers and maybe TLB loading functions will use this to figure
1442	* out what to do. The parameter will specify an entry and the opcode offset to
1443	* start at and the minimum number of bytes to verify (instruction length).
1444	*
1445	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1446	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1447	* code TLB (must have a valid entry for that address) and scan the ranges to
1448	* locate the corresponding opcodes. Probably.
1449	*/
1450	struct IEMTBOPCODERANGE
1451	{
1452	/** Offset within pabOpcodes. */
1453	uint16_t offOpcodes;
1454	/** Number of bytes. */
1455	uint16_t cbOpcodes;
1456	/** The page offset. */
1457	RT_GCC_EXTENSION
1458	uint16_t offPhysPage : 12;
1459	/** Unused bits. */
1460	RT_GCC_EXTENSION
1461	uint16_t u2Unused : 2;
1462	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1463	RT_GCC_EXTENSION
1464	uint16_t idxPhysPage : 2;
1465	} aRanges[8];
1466
1467	/** Physical pages that this TB covers.
1468	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1469	RTGCPHYS aGCPhysPages[2];
1470	} IEMTB;
1471	#pragma pack()
1472	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1473	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1474	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1475	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1476	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1477	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1478	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1479	#if 1
1480	AssertCompileSize(IEMTB, 128);
1481	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1482	#else
1483	AssertCompileSize(IEMTB, 168);
1484	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1485	#endif
1486
1487	/** Pointer to a translation block. */
1488	typedef IEMTB *PIEMTB;
1489	/** Pointer to a const translation block. */
1490	typedef IEMTB const *PCIEMTB;
1491
1492	/** Gets address of the given TB lookup table entry. */
1493	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1494	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1495
1496	/**
1497	* Gets the physical address for a TB opcode range.
1498	*/
1499	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1500	{
1501	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1502	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1503	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1504	if (idxPage == 0)
1505	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1506	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1507	return pTb->aGCPhysPages[idxPage - 1];
1508	}
1509
1510
1511	/**
1512	* A chunk of memory in the TB allocator.
1513	*/
1514	typedef struct IEMTBCHUNK
1515	{
1516	/** Pointer to the translation blocks in this chunk. */
1517	PIEMTB paTbs;
1518	#ifdef IN_RING0
1519	/** Allocation handle. */
1520	RTR0MEMOBJ hMemObj;
1521	#endif
1522	} IEMTBCHUNK;
1523
1524	/**
1525	* A per-CPU translation block allocator.
1526	*
1527	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1528	* the length of the collision list, and of course also for cache line alignment
1529	* reasons, the TBs must be allocated with at least 64-byte alignment.
1530	* Memory is there therefore allocated using one of the page aligned allocators.
1531	*
1532	*
1533	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1534	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1535	* that enables us to quickly calculate the allocation bitmap position when
1536	* freeing the translation block.
1537	*/
1538	typedef struct IEMTBALLOCATOR
1539	{
1540	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1541	uint32_t uMagic;
1542
1543	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1544	/** Mask corresponding to cTbsPerChunk - 1. */
1545	uint32_t fChunkMask;
1546	/** Shift count corresponding to cTbsPerChunk. */
1547	uint8_t cChunkShift;
1548	#else
1549	uint32_t uUnused;
1550	uint8_t bUnused;
1551	#endif
1552	/** Number of chunks we're allowed to allocate. */
1553	uint8_t cMaxChunks;
1554	/** Number of chunks currently populated. */
1555	uint16_t cAllocatedChunks;
1556	/** Number of translation blocks per chunk. */
1557	uint32_t cTbsPerChunk;
1558	/** Chunk size. */
1559	uint32_t cbPerChunk;
1560
1561	/** The maximum number of TBs. */
1562	uint32_t cMaxTbs;
1563	/** Total number of TBs in the populated chunks.
1564	* (cAllocatedChunks * cTbsPerChunk) */
1565	uint32_t cTotalTbs;
1566	/** The current number of TBs in use.
1567	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1568	uint32_t cInUseTbs;
1569	/** Statistics: Number of the cInUseTbs that are native ones. */
1570	uint32_t cNativeTbs;
1571	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1572	uint32_t cThreadedTbs;
1573
1574	/** Where to start pruning TBs from when we're out.
1575	* See iemTbAllocatorAllocSlow for details. */
1576	uint32_t iPruneFrom;
1577	/** Where to start pruning native TBs from when we're out of executable memory.
1578	* See iemTbAllocatorFreeupNativeSpace for details. */
1579	uint32_t iPruneNativeFrom;
1580	uint64_t u64Padding;
1581
1582	/** Statistics: Number of TB allocation calls. */
1583	STAMCOUNTER StatAllocs;
1584	/** Statistics: Number of TB free calls. */
1585	STAMCOUNTER StatFrees;
1586	/** Statistics: Time spend pruning. */
1587	STAMPROFILE StatPrune;
1588	/** Statistics: Time spend pruning native TBs. */
1589	STAMPROFILE StatPruneNative;
1590
1591	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1592	PIEMTB pDelayedFreeHead;
1593	/* Head of the list of free TBs. */
1594	PIEMTB pTbsFreeHead;
1595
1596	/** Allocation chunks. */
1597	IEMTBCHUNK aChunks[256];
1598	} IEMTBALLOCATOR;
1599	/** Pointer to a TB allocator. */
1600	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1601
1602	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1603	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1604
1605
1606	/**
1607	* A per-CPU translation block cache (hash table).
1608	*
1609	* The hash table is allocated once during IEM initialization and size double
1610	* the max TB count, rounded up to the nearest power of two (so we can use and
1611	* AND mask rather than a rest division when hashing).
1612	*/
1613	typedef struct IEMTBCACHE
1614	{
1615	/** Magic value (IEMTBCACHE_MAGIC). */
1616	uint32_t uMagic;
1617	/** Size of the hash table. This is a power of two. */
1618	uint32_t cHash;
1619	/** The mask corresponding to cHash. */
1620	uint32_t uHashMask;
1621	uint32_t uPadding;
1622
1623	/** @name Statistics
1624	* @{ */
1625	/** Number of collisions ever. */
1626	STAMCOUNTER cCollisions;
1627
1628	/** Statistics: Number of TB lookup misses. */
1629	STAMCOUNTER cLookupMisses;
1630	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1631	STAMCOUNTER cLookupHits;
1632	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1633	STAMCOUNTER cLookupHitsViaTbLookupTable;
1634	STAMCOUNTER auPadding2[2];
1635	/** Statistics: Collision list length pruning. */
1636	STAMPROFILE StatPrune;
1637	/** @} */
1638
1639	/** The hash table itself.
1640	* @note The lower 6 bits of the pointer is used for keeping the collision
1641	* list length, so we can take action when it grows too long.
1642	* This works because TBs are allocated using a 64 byte (or
1643	* higher) alignment from page aligned chunks of memory, so the lower
1644	* 6 bits of the address will always be zero.
1645	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1646	*/
1647	RT_FLEXIBLE_ARRAY_EXTENSION
1648	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1649	} IEMTBCACHE;
1650	/** Pointer to a per-CPU translation block cahce. */
1651	typedef IEMTBCACHE *PIEMTBCACHE;
1652
1653	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1654	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1655
1656	/** The collision count mask for IEMTBCACHE::apHash entries. */
1657	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1658	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1659	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1660	/** Combine a TB pointer and a collision list length into a value for an
1661	* IEMTBCACHE::apHash entry. */
1662	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1663	/** Combine a TB pointer and a collision list length into a value for an
1664	* IEMTBCACHE::apHash entry. */
1665	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1666	/** Combine a TB pointer and a collision list length into a value for an
1667	* IEMTBCACHE::apHash entry. */
1668	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1669
1670	/**
1671	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1672	*/
1673	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1674	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1675
1676	/**
1677	* Calculates the hash table slot for a TB from physical PC address and TB
1678	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1679	*/
1680	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1681	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1682
1683
1684	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1685	*
1686	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1687	*
1688	* @{ */
1689	/** Value if no branching happened recently. */
1690	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1691	/** Flag set if direct branch, clear if absolute or indirect. */
1692	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1693	/** Flag set if indirect branch, clear if direct or relative. */
1694	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1695	/** Flag set if relative branch, clear if absolute or indirect. */
1696	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1697	/** Flag set if conditional branch, clear if unconditional. */
1698	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1699	/** Flag set if it's a far branch. */
1700	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1701	/** Flag set if the stack pointer is modified. */
1702	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1703	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1704	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1705	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1706	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1707	/** @} */
1708
1709
1710	/**
1711	* The per-CPU IEM state.
1712	*/
1713	typedef struct IEMCPU
1714	{
1715	/** Info status code that needs to be propagated to the IEM caller.
1716	* This cannot be passed internally, as it would complicate all success
1717	* checks within the interpreter making the code larger and almost impossible
1718	* to get right. Instead, we'll store status codes to pass on here. Each
1719	* source of these codes will perform appropriate sanity checks. */
1720	int32_t rcPassUp; /* 0x00 */
1721	/** Execution flag, IEM_F_XXX. */
1722	uint32_t fExec; /* 0x04 */
1723
1724	/** @name Decoder state.
1725	* @{ */
1726	#ifdef IEM_WITH_CODE_TLB
1727	/** The offset of the next instruction byte. */
1728	uint32_t offInstrNextByte; /* 0x08 */
1729	/** The number of bytes available at pbInstrBuf for the current instruction.
1730	* This takes the max opcode length into account so that doesn't need to be
1731	* checked separately. */
1732	uint32_t cbInstrBuf; /* 0x0c */
1733	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1734	* This can be NULL if the page isn't mappable for some reason, in which
1735	* case we'll do fallback stuff.
1736	*
1737	* If we're executing an instruction from a user specified buffer,
1738	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1739	* aligned pointer but pointer to the user data.
1740	*
1741	* For instructions crossing pages, this will start on the first page and be
1742	* advanced to the next page by the time we've decoded the instruction. This
1743	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1744	*/
1745	uint8_t const pbInstrBuf; / 0x10 */
1746	# if ARCH_BITS == 32
1747	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1748	# endif
1749	/** The program counter corresponding to pbInstrBuf.
1750	* This is set to a non-canonical address when we need to invalidate it. */
1751	uint64_t uInstrBufPc; /* 0x18 */
1752	/** The guest physical address corresponding to pbInstrBuf. */
1753	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1754	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1755	* This takes the CS segment limit into account.
1756	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1757	uint16_t cbInstrBufTotal; /* 0x28 */
1758	/** Offset into pbInstrBuf of the first byte of the current instruction.
1759	* Can be negative to efficiently handle cross page instructions. */
1760	int16_t offCurInstrStart; /* 0x2a */
1761
1762	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1763	/** The prefix mask (IEM_OP_PRF_XXX). */
1764	uint32_t fPrefixes; /* 0x2c */
1765	/** The extra REX ModR/M register field bit (REX.R << 3). */
1766	uint8_t uRexReg; /* 0x30 */
1767	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1768	* (REX.B << 3). */
1769	uint8_t uRexB; /* 0x31 */
1770	/** The extra REX SIB index field bit (REX.X << 3). */
1771	uint8_t uRexIndex; /* 0x32 */
1772
1773	/** The effective segment register (X86_SREG_XXX). */
1774	uint8_t iEffSeg; /* 0x33 */
1775
1776	/** The offset of the ModR/M byte relative to the start of the instruction. */
1777	uint8_t offModRm; /* 0x34 */
1778
1779	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1780	/** The current offset into abOpcode. */
1781	uint8_t offOpcode; /* 0x35 */
1782	# else
1783	uint8_t bUnused; /* 0x35 */
1784	# endif
1785	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1786	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1787	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1788
1789	#else /* !IEM_WITH_CODE_TLB */
1790	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1791	/** The size of what has currently been fetched into abOpcode. */
1792	uint8_t cbOpcode; /* 0x08 */
1793	/** The current offset into abOpcode. */
1794	uint8_t offOpcode; /* 0x09 */
1795	/** The offset of the ModR/M byte relative to the start of the instruction. */
1796	uint8_t offModRm; /* 0x0a */
1797
1798	/** The effective segment register (X86_SREG_XXX). */
1799	uint8_t iEffSeg; /* 0x0b */
1800
1801	/** The prefix mask (IEM_OP_PRF_XXX). */
1802	uint32_t fPrefixes; /* 0x0c */
1803	/** The extra REX ModR/M register field bit (REX.R << 3). */
1804	uint8_t uRexReg; /* 0x10 */
1805	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1806	* (REX.B << 3). */
1807	uint8_t uRexB; /* 0x11 */
1808	/** The extra REX SIB index field bit (REX.X << 3). */
1809	uint8_t uRexIndex; /* 0x12 */
1810
1811	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1812	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1813	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1814	#endif /* !IEM_WITH_CODE_TLB */
1815
1816	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1817	/** The effective operand mode. */
1818	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1819	/** The default addressing mode. */
1820	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1821	/** The effective addressing mode. */
1822	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1823	/** The default operand mode. */
1824	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1825
1826	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1827	uint8_t idxPrefix; /* 0x3a, 0x17 */
1828	/** 3rd VEX/EVEX/XOP register.
1829	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1830	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1831	/** The VEX/EVEX/XOP length field. */
1832	uint8_t uVexLength; /* 0x3c, 0x19 */
1833	/** Additional EVEX stuff. */
1834	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1835
1836	# ifndef IEM_WITH_CODE_TLB
1837	/** Explicit alignment padding. */
1838	uint8_t abAlignment2a[1]; /* 0x1b */
1839	# endif
1840	/** The FPU opcode (FOP). */
1841	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1842	# ifndef IEM_WITH_CODE_TLB
1843	/** Explicit alignment padding. */
1844	uint8_t abAlignment2b[2]; /* 0x1e */
1845	# endif
1846
1847	/** The opcode bytes. */
1848	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1849	/** Explicit alignment padding. */
1850	# ifdef IEM_WITH_CODE_TLB
1851	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1852	# else
1853	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1854	# endif
1855
1856	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1857	# ifdef IEM_WITH_CODE_TLB
1858	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1859	# else
1860	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1861	# endif
1862	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1863	/** @} */
1864
1865
1866	/** The number of active guest memory mappings. */
1867	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1868
1869	/** Records for tracking guest memory mappings. */
1870	struct
1871	{
1872	/** The address of the mapped bytes. */
1873	R3R0PTRTYPE(void *) pv;
1874	/** The access flags (IEM_ACCESS_XXX).
1875	* IEM_ACCESS_INVALID if the entry is unused. */
1876	uint32_t fAccess;
1877	#if HC_ARCH_BITS == 64
1878	uint32_t u32Alignment4; /*< Alignment padding. /
1879	#endif
1880	} aMemMappings[3]; /* 0x50 LB 0x30 */
1881
1882	/** Locking records for the mapped memory. */
1883	union
1884	{
1885	PGMPAGEMAPLOCK Lock;
1886	uint64_t au64Padding[2];
1887	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1888
1889	/** Bounce buffer info.
1890	* This runs in parallel to aMemMappings. */
1891	struct
1892	{
1893	/** The physical address of the first byte. */
1894	RTGCPHYS GCPhysFirst;
1895	/** The physical address of the second page. */
1896	RTGCPHYS GCPhysSecond;
1897	/** The number of bytes in the first page. */
1898	uint16_t cbFirst;
1899	/** The number of bytes in the second page. */
1900	uint16_t cbSecond;
1901	/** Whether it's unassigned memory. */
1902	bool fUnassigned;
1903	/** Explicit alignment padding. */
1904	bool afAlignment5[3];
1905	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1906
1907	/** The flags of the current exception / interrupt. */
1908	uint32_t fCurXcpt; /* 0xf8 */
1909	/** The current exception / interrupt. */
1910	uint8_t uCurXcpt; /* 0xfc */
1911	/** Exception / interrupt recursion depth. */
1912	int8_t cXcptRecursions; /* 0xfb */
1913
1914	/** The next unused mapping index.
1915	* @todo try find room for this up with cActiveMappings. */
1916	uint8_t iNextMapping; /* 0xfd */
1917	uint8_t abAlignment7[1];
1918
1919	/** Bounce buffer storage.
1920	* This runs in parallel to aMemMappings and aMemBbMappings. */
1921	struct
1922	{
1923	uint8_t ab[512];
1924	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1925
1926
1927	/** Pointer set jump buffer - ring-3 context. */
1928	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1929	/** Pointer set jump buffer - ring-0 context. */
1930	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1931
1932	/** @todo Should move this near @a fCurXcpt later. */
1933	/** The CR2 for the current exception / interrupt. */
1934	uint64_t uCurXcptCr2;
1935	/** The error code for the current exception / interrupt. */
1936	uint32_t uCurXcptErr;
1937
1938	/** @name Statistics
1939	* @{ */
1940	/** The number of instructions we've executed. */
1941	uint32_t cInstructions;
1942	/** The number of potential exits. */
1943	uint32_t cPotentialExits;
1944	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1945	* This may contain uncommitted writes. */
1946	uint32_t cbWritten;
1947	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1948	uint32_t cRetInstrNotImplemented;
1949	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1950	uint32_t cRetAspectNotImplemented;
1951	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1952	uint32_t cRetInfStatuses;
1953	/** Counts other error statuses returned. */
1954	uint32_t cRetErrStatuses;
1955	/** Number of times rcPassUp has been used. */
1956	uint32_t cRetPassUpStatus;
1957	/** Number of times RZ left with instruction commit pending for ring-3. */
1958	uint32_t cPendingCommit;
1959	/** Number of misaligned (host sense) atomic instruction accesses. */
1960	uint32_t cMisalignedAtomics;
1961	/** Number of long jumps. */
1962	uint32_t cLongJumps;
1963	/** @} */
1964
1965	/** @name Target CPU information.
1966	* @{ */
1967	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1968	/** The target CPU. */
1969	uint8_t uTargetCpu;
1970	#else
1971	uint8_t bTargetCpuPadding;
1972	#endif
1973	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1974	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1975	* native host support and the 2nd for when there is.
1976	*
1977	* The two values are typically indexed by a g_CpumHostFeatures bit.
1978	*
1979	* This is for instance used for the BSF & BSR instructions where AMD and
1980	* Intel CPUs produce different EFLAGS. */
1981	uint8_t aidxTargetCpuEflFlavour[2];
1982
1983	/** The CPU vendor. */
1984	CPUMCPUVENDOR enmCpuVendor;
1985	/** @} */
1986
1987	/** @name Host CPU information.
1988	* @{ */
1989	/** The CPU vendor. */
1990	CPUMCPUVENDOR enmHostCpuVendor;
1991	/** @} */
1992
1993	/** Counts RDMSR \#GP(0) LogRel(). */
1994	uint8_t cLogRelRdMsr;
1995	/** Counts WRMSR \#GP(0) LogRel(). */
1996	uint8_t cLogRelWrMsr;
1997	/** Alignment padding. */
1998	uint8_t abAlignment9[42];
1999
2000
2001	/** @name Recompiled Exection
2002	* @{ */
2003	/** Pointer to the current translation block.
2004	* This can either be one being executed or one being compiled. */
2005	R3PTRTYPE(PIEMTB) pCurTbR3;
2006	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
2007	/** Frame pointer for the last native TB to execute. */
2008	R3PTRTYPE(void *) pvTbFramePointerR3;
2009	#else
2010	R3PTRTYPE(void *) pvUnusedR3;
2011	#endif
2012	#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
2013	/** The saved host floating point control register (MXCSR on x86, FPCR on arm64)
2014	* needing restore when the TB finished, IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED indicates the TB
2015	* didn't modify it so we don't need to restore it. */
2016	# ifdef RT_ARCH_AMD64
2017	uint32_t uRegFpCtrl;
2018	/** Temporary copy of MXCSR for stmxcsr/ldmxcsr (so we don't have to fiddle with stack pointers). */
2019	uint32_t uRegMxcsrTmp;
2020	# elif defined(RT_ARCH_ARM64)
2021	uint64_t uRegFpCtrl;
2022	# else
2023	# error "Port me"
2024	# endif
2025	#else
2026	uint64_t u64Unused;
2027	#endif
2028	/** Pointer to the ring-3 TB cache for this EMT. */
2029	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
2030	/** Pointer to the ring-3 TB lookup entry.
2031	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
2032	* entry, thus it can always safely be used w/o NULL checking. */
2033	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
2034	#if 0 /* unused */
2035	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
2036	* The TBs are based on physical addresses, so this is needed to correleated
2037	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
2038	uint64_t uCurTbStartPc;
2039	#endif
2040
2041	/** Number of threaded TBs executed. */
2042	uint64_t cTbExecThreaded;
2043	/** Number of native TBs executed. */
2044	uint64_t cTbExecNative;
2045
2046	/** The number of IRQ/FF checks till the next timer poll call. */
2047	uint32_t cTbsTillNextTimerPoll;
2048	/** The virtual sync time at the last timer poll call in milliseconds. */
2049	uint32_t msRecompilerPollNow;
2050	/** The virtual sync time at the last timer poll call in nanoseconds. */
2051	uint64_t nsRecompilerPollNow;
2052	/** The previous cTbsTillNextTimerPoll value. */
2053	uint32_t cTbsTillNextTimerPollPrev;
2054
2055	/** The current instruction number in a native TB.
2056	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
2057	* and will be picked up by the TB execution loop. Only used when
2058	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
2059	uint8_t idxTbCurInstr;
2060	/** @} */
2061
2062	/** @name Recompilation
2063	* @{ */
2064	/** Whether we need to check the opcode bytes for the current instruction.
2065	* This is set by a previous instruction if it modified memory or similar. */
2066	bool fTbCheckOpcodes;
2067	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
2068	uint8_t fTbBranched;
2069	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
2070	bool fTbCrossedPage;
2071	/** Whether to end the current TB. */
2072	bool fEndTb;
2073	/** Indicates that the current instruction is an STI. This is set by the
2074	* iemCImpl_sti code and subsequently cleared by the recompiler. */
2075	bool fTbCurInstrIsSti;
2076	/** Spaced reserved for recompiler data / alignment. */
2077	bool afRecompilerStuff1[1];
2078	/** Number of instructions before we need emit an IRQ check call again.
2079	* This helps making sure we don't execute too long w/o checking for
2080	* interrupts and immediately following instructions that may enable
2081	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
2082	* required to make sure we check following the next instruction as well, see
2083	* fTbCurInstrIsSti. */
2084	uint8_t cInstrTillIrqCheck;
2085	/** The index of the last CheckIrq call during threaded recompilation. */
2086	uint16_t idxLastCheckIrqCallNo;
2087	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
2088	uint16_t cbOpcodesAllocated;
2089	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
2090	uint32_t uTbNativeRecompileAtUsedCount;
2091	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
2092	uint32_t fTbCurInstr;
2093	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
2094	uint32_t fTbPrevInstr;
2095	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
2096	* currently not up to date in EFLAGS. */
2097	uint32_t fSkippingEFlags;
2098	#if 0 /* unused */
2099	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
2100	RTGCPHYS GCPhysInstrBufPrev;
2101	#endif
2102
2103	/** Fixed TB used for threaded recompilation.
2104	* This is allocated once with maxed-out sizes and re-used afterwards. */
2105	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
2106	/** Pointer to the ring-3 TB allocator for this EMT. */
2107	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
2108	/** Pointer to the ring-3 executable memory allocator for this EMT. */
2109	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
2110	/** Pointer to the native recompiler state for ring-3. */
2111	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
2112	/** Dummy entry for ppTbLookupEntryR3. */
2113	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
2114	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
2115	/** The debug code advances this register as if it was CPUMCTX::rip and we
2116	* didn't do delayed PC updating. When CPUMCTX::rip is finally updated,
2117	* the result is compared with this value. */
2118	uint64_t uPcUpdatingDebug;
2119	#elif defined(VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING)
2120	/** The SSM handle used for saving threaded TBs for recompiler profiling. */
2121	R3PTRTYPE(PSSMHANDLE) pSsmThreadedTbsForProfiling;
2122	#else
2123	uint64_t u64Placeholder;
2124	#endif
2125	/**
2126	* Whether we should use the host instruction invalidation APIs of the
2127	* host OS or our own version of it (macOS). */
2128	uint8_t fHostICacheInvalidation;
2129	#define IEMNATIVE_ICACHE_F_USE_HOST_API UINT8_C(0x01) /*< Use the host API (macOS) instead of our code. /
2130	#define IEMNATIVE_ICACHE_F_END_WITH_ISH UINT8_C(0x02) /*< Whether to end with a ISH barrier (arm). /
2131	bool afRecompilerStuff2[7];
2132	/** @} */
2133
2134	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
2135	IEMTLBENTRY DataBreakpointTlbe;
2136
2137	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
2138	STAMCOUNTER StatTbThreadedExecBreaks;
2139	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
2140	STAMCOUNTER StatCheckIrqBreaks;
2141	/** Statistics: Times BltIn_CheckTimers breaks direct linking TBs. */
2142	STAMCOUNTER StatCheckTimersBreaks;
2143	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
2144	STAMCOUNTER StatCheckModeBreaks;
2145	/** Threaded TB statistics: Times execution break on call with lookup entries. */
2146	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
2147	/** Threaded TB statistics: Times execution break on call without lookup entries. */
2148	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2149	/** Statistics: Times a post jump target check missed and had to find new TB. */
2150	STAMCOUNTER StatCheckBranchMisses;
2151	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2152	STAMCOUNTER StatCheckNeedCsLimChecking;
2153	/** Statistics: Times a loop was detected within a TB. */
2154	STAMCOUNTER StatTbLoopInTbDetected;
2155	/** Statistics: Times a loop back to the start of the TB was detected. */
2156	STAMCOUNTER StatTbLoopFullTbDetected;
2157	/** Statistics: Times a loop back to the start of the TB was detected, var 2. */
2158	STAMCOUNTER StatTbLoopFullTbDetected2;
2159	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2160	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2161	/** Native TB statistics: Number of fully recompiled TBs. */
2162	STAMCOUNTER StatNativeFullyRecompiledTbs;
2163	/** TB statistics: Number of instructions per TB. */
2164	STAMPROFILE StatTbInstr;
2165	/** TB statistics: Number of TB lookup table entries per TB. */
2166	STAMPROFILE StatTbLookupEntries;
2167	/** Threaded TB statistics: Number of calls per TB. */
2168	STAMPROFILE StatTbThreadedCalls;
2169	/** Native TB statistics: Native code size per TB. */
2170	STAMPROFILE StatTbNativeCode;
2171	/** Native TB statistics: Profiling native recompilation. */
2172	STAMPROFILE StatNativeRecompilation;
2173	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2174	STAMPROFILE StatNativeCallsRecompiled;
2175	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2176	STAMPROFILE StatNativeCallsThreaded;
2177	/** Native recompiled execution: TLB hits for data fetches. */
2178	STAMCOUNTER StatNativeTlbHitsForFetch;
2179	/** Native recompiled execution: TLB hits for data stores. */
2180	STAMCOUNTER StatNativeTlbHitsForStore;
2181	/** Native recompiled execution: TLB hits for stack accesses. */
2182	STAMCOUNTER StatNativeTlbHitsForStack;
2183	/** Native recompiled execution: TLB hits for mapped accesses. */
2184	STAMCOUNTER StatNativeTlbHitsForMapped;
2185	/** Native recompiled execution: Code TLB misses for new page. */
2186	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2187	/** Native recompiled execution: Code TLB hits for new page. */
2188	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2189	/** Native recompiled execution: Code TLB misses for new page with offset. */
2190	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2191	/** Native recompiled execution: Code TLB hits for new page with offset. */
2192	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2193
2194	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2195	STAMCOUNTER StatNativeRegFindFree;
2196	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2197	* to free a variable. */
2198	STAMCOUNTER StatNativeRegFindFreeVar;
2199	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2200	* not need to free any variables. */
2201	STAMCOUNTER StatNativeRegFindFreeNoVar;
2202	/** Native recompiler: Liveness info freed shadowed guest registers in
2203	* iemNativeRegAllocFindFree. */
2204	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2205	/** Native recompiler: Liveness info helped with the allocation in
2206	* iemNativeRegAllocFindFree. */
2207	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2208
2209	/** Native recompiler: Number of times status flags calc has been skipped. */
2210	STAMCOUNTER StatNativeEflSkippedArithmetic;
2211	/** Native recompiler: Number of times status flags calc has been postponed. */
2212	STAMCOUNTER StatNativeEflPostponedArithmetic;
2213	/** Native recompiler: Total number instructions in this category. */
2214	STAMCOUNTER StatNativeEflTotalArithmetic;
2215
2216	/** Native recompiler: Number of times status flags calc has been skipped. */
2217	STAMCOUNTER StatNativeEflSkippedLogical;
2218	/** Native recompiler: Number of times status flags calc has been postponed. */
2219	STAMCOUNTER StatNativeEflPostponedLogical;
2220	/** Native recompiler: Total number instructions in this category. */
2221	STAMCOUNTER StatNativeEflTotalLogical;
2222
2223	/** Native recompiler: Number of times status flags calc has been skipped. */
2224	STAMCOUNTER StatNativeEflSkippedShift;
2225	/** Native recompiler: Number of times status flags calc has been postponed. */
2226	STAMCOUNTER StatNativeEflPostponedShift;
2227	/** Native recompiler: Total number instructions in this category. */
2228	STAMCOUNTER StatNativeEflTotalShift;
2229
2230	/** Native recompiler: Number of emits per postponement. */
2231	STAMPROFILE StatNativeEflPostponedEmits;
2232
2233	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2234	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2235	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2236	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2237	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2238	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2239	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2240	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2241	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2242	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2243	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2244	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2245	/** Native recompiler: Number of required EFLAGS.CF updates. */
2246	STAMCOUNTER StatNativeLivenessEflCfRequired;
2247	/** Native recompiler: Number of required EFLAGS.PF updates. */
2248	STAMCOUNTER StatNativeLivenessEflPfRequired;
2249	/** Native recompiler: Number of required EFLAGS.AF updates. */
2250	STAMCOUNTER StatNativeLivenessEflAfRequired;
2251	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2252	STAMCOUNTER StatNativeLivenessEflZfRequired;
2253	/** Native recompiler: Number of required EFLAGS.SF updates. */
2254	STAMCOUNTER StatNativeLivenessEflSfRequired;
2255	/** Native recompiler: Number of required EFLAGS.OF updates. */
2256	STAMCOUNTER StatNativeLivenessEflOfRequired;
2257	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2258	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2259	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2260	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2261	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2262	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2263	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2264	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2265	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2266	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2267	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2268	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2269
2270	/** Native recompiler: Number of potential PC updates in total. */
2271	STAMCOUNTER StatNativePcUpdateTotal;
2272	/** Native recompiler: Number of PC updates which could be delayed. */
2273	STAMCOUNTER StatNativePcUpdateDelayed;
2274
2275	/** Native recompiler: Number of time we had complicated dirty shadow
2276	* register situations with the other branch in IEM_MC_ENDIF. */
2277	STAMCOUNTER StatNativeEndIfOtherBranchDirty;
2278
2279	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2280	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2281	STAMCOUNTER StatNativeSimdRegFindFree;
2282	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2283	* to free a variable. */
2284	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2285	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2286	* not need to free any variables. */
2287	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2288	/** Native recompiler: Liveness info freed shadowed guest registers in
2289	* iemNativeSimdRegAllocFindFree. */
2290	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2291	/** Native recompiler: Liveness info helped with the allocation in
2292	* iemNativeSimdRegAllocFindFree. */
2293	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2294
2295	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2296	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2297	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2298	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2299	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2300	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2301	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2302	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2303
2304	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2305	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2306	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2307	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2308	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2309	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2310	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2311	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2312	//#endif
2313
2314	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2315	* Not availabe in release builds. */
2316	STAMCOUNTER StatNativeTbFinished;
2317	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2318	STAMCOUNTER StatNativeTbExitReturnBreak;
2319	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2320	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2321	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2322	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2323	/** Native recompiler: The TB finished executing with other non-zero status. */
2324	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2325	/** Native recompiler: The TB finished executing via throw / long jump. */
2326	STAMCOUNTER StatNativeTbExitLongJump;
2327	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2328	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2329	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2330	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2331	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2332	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2333	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2334	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2335	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2336	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2337	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2338	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2339
2340	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2341	STAMCOUNTER StatNativeTbExitRaiseDe;
2342	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2343	STAMCOUNTER StatNativeTbExitRaiseUd;
2344	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2345	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2346	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2347	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2348	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2349	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2350	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2351	STAMCOUNTER StatNativeTbExitRaiseNm;
2352	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2353	STAMCOUNTER StatNativeTbExitRaiseGp0;
2354	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2355	STAMCOUNTER StatNativeTbExitRaiseMf;
2356	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2357	STAMCOUNTER StatNativeTbExitRaiseXf;
2358	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2359	STAMCOUNTER StatNativeTbExitObsoleteTb;
2360
2361	/** Native recompiler: Number of full TB loops (jumps from end to start). */
2362	STAMCOUNTER StatNativeTbExitLoopFullTb;
2363
2364	/** Native recompiler: Failure situations with direct linking scenario \#1.
2365	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2366	* @{ */
2367	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2368	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2369	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2370	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2371	/** @} */
2372
2373	/** Native recompiler: Failure situations with direct linking scenario \#2.
2374	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2375	* @{ */
2376	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2377	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2378	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2379	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2380	/** @} */
2381
2382	/** iemMemMap and iemMemMapJmp statistics.
2383	* @{ */
2384	STAMCOUNTER StatMemMapJmp;
2385	STAMCOUNTER StatMemMapNoJmp;
2386	STAMCOUNTER StatMemBounceBufferCrossPage;
2387	STAMCOUNTER StatMemBounceBufferMapPhys;
2388	/** @} */
2389
2390	/** Timer polling statistics (debug only).
2391	* @{ */
2392	STAMPROFILE StatTimerPoll;
2393	STAMPROFILE StatTimerPollPoll;
2394	STAMPROFILE StatTimerPollRun;
2395	STAMCOUNTER StatTimerPollUnchanged;
2396	STAMCOUNTER StatTimerPollTiny;
2397	STAMCOUNTER StatTimerPollDefaultCalc;
2398	STAMCOUNTER StatTimerPollMax;
2399	STAMPROFILE StatTimerPollFactorDivision;
2400	STAMPROFILE StatTimerPollFactorMultiplication;
2401	/** @} */
2402
2403	#ifdef IEM_WITH_TLB_TRACE
2404	/uint64_t au64Padding[0];/
2405	#else
2406	uint64_t au64Padding[2];
2407	#endif
2408
2409	#ifdef IEM_WITH_TLB_TRACE
2410	/** The end (next) trace entry. */
2411	uint32_t idxTlbTraceEntry;
2412	/** Number of trace entries allocated expressed as a power of two. */
2413	uint32_t cTlbTraceEntriesShift;
2414	/** The trace entries. */
2415	PIEMTLBTRACEENTRY paTlbTraceEntries;
2416	#endif
2417
2418	/** Data TLB.
2419	* @remarks Must be 64-byte aligned. */
2420	IEMTLB DataTlb;
2421	/** Instruction TLB.
2422	* @remarks Must be 64-byte aligned. */
2423	IEMTLB CodeTlb;
2424
2425	/** Exception statistics. */
2426	STAMCOUNTER aStatXcpts[32];
2427	/** Interrupt statistics. */
2428	uint32_t aStatInts[256];
2429
2430	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2431	/** Instruction statistics for ring-0/raw-mode. */
2432	IEMINSTRSTATS StatsRZ;
2433	/** Instruction statistics for ring-3. */
2434	IEMINSTRSTATS StatsR3;
2435	# ifdef VBOX_WITH_IEM_RECOMPILER
2436	/** Statistics per threaded function call.
2437	* Updated by both the threaded and native recompilers. */
2438	uint32_t acThreadedFuncStats[0x6000 /24576/];
2439	# endif
2440	#endif
2441	} IEMCPU;
2442	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2443	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2444	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2445	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2446	AssertCompileMemberAlignment(IEMCPU, pCurTbR3, 64);
2447	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2448	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2449
2450	/** Pointer to the per-CPU IEM state. */
2451	typedef IEMCPU *PIEMCPU;
2452	/** Pointer to the const per-CPU IEM state. */
2453	typedef IEMCPU const *PCIEMCPU;
2454
2455	/** @def IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED
2456	* Value indicating the TB didn't modified the floating point control register.
2457	* @note Neither FPCR nor MXCSR accept this as a valid value (MXCSR is not fully populated,
2458	* FPCR has the upper 32-bit reserved), so this is safe. */
2459	#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) \|\| defined(DOXYGEN_RUNNING)
2460	# ifdef RT_ARCH_AMD64
2461	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT32_MAX
2462	# elif defined(RT_ARCH_ARM64)
2463	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT64_MAX
2464	# else
2465	# error "Port me"
2466	# endif
2467	#endif
2468
2469	/** @def IEM_GET_CTX
2470	* Gets the guest CPU context for the calling EMT.
2471	* @returns PCPUMCTX
2472	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2473	*/
2474	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2475
2476	/** @def IEM_CTX_ASSERT
2477	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2478	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2479	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2480	*/
2481	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2482	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2483	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2484	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2485
2486	/** @def IEM_CTX_IMPORT_RET
2487	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2488	*
2489	* Will call the keep to import the bits as needed.
2490	*
2491	* Returns on import failure.
2492	*
2493	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2494	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2495	*/
2496	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2497	do { \
2498	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2499	{ /* likely */ } \
2500	else \
2501	{ \
2502	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2503	AssertRCReturn(rcCtxImport, rcCtxImport); \
2504	} \
2505	} while (0)
2506
2507	/** @def IEM_CTX_IMPORT_NORET
2508	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2509	*
2510	* Will call the keep to import the bits as needed.
2511	*
2512	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2513	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2514	*/
2515	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2516	do { \
2517	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2518	{ /* likely */ } \
2519	else \
2520	{ \
2521	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2522	AssertLogRelRC(rcCtxImport); \
2523	} \
2524	} while (0)
2525
2526	/** @def IEM_CTX_IMPORT_JMP
2527	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2528	*
2529	* Will call the keep to import the bits as needed.
2530	*
2531	* Jumps on import failure.
2532	*
2533	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2534	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2535	*/
2536	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2537	do { \
2538	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2539	{ /* likely */ } \
2540	else \
2541	{ \
2542	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2543	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2544	} \
2545	} while (0)
2546
2547
2548
2549	/** @def IEM_GET_TARGET_CPU
2550	* Gets the current IEMTARGETCPU value.
2551	* @returns IEMTARGETCPU value.
2552	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2553	*/
2554	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2555	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2556	#else
2557	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2558	#endif
2559
2560	/** @def IEM_GET_INSTR_LEN
2561	* Gets the instruction length. */
2562	#ifdef IEM_WITH_CODE_TLB
2563	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2564	#else
2565	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2566	#endif
2567
2568	/** @def IEM_TRY_SETJMP
2569	* Wrapper around setjmp / try, hiding all the ugly differences.
2570	*
2571	* @note Use with extreme care as this is a fragile macro.
2572	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2573	* @param a_rcTarget The variable that should receive the status code in case
2574	* of a longjmp/throw.
2575	*/
2576	/** @def IEM_TRY_SETJMP_AGAIN
2577	* For when setjmp / try is used again in the same variable scope as a previous
2578	* IEM_TRY_SETJMP invocation.
2579	*/
2580	/** @def IEM_CATCH_LONGJMP_BEGIN
2581	* Start wrapper for catch / setjmp-else.
2582	*
2583	* This will set up a scope.
2584	*
2585	* @note Use with extreme care as this is a fragile macro.
2586	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2587	* @param a_rcTarget The variable that should receive the status code in case
2588	* of a longjmp/throw.
2589	*/
2590	/** @def IEM_CATCH_LONGJMP_END
2591	* End wrapper for catch / setjmp-else.
2592	*
2593	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2594	* state.
2595	*
2596	* @note Use with extreme care as this is a fragile macro.
2597	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2598	*/
2599	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2600	# ifdef IEM_WITH_THROW_CATCH
2601	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2602	a_rcTarget = VINF_SUCCESS; \
2603	try
2604	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2605	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2606	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2607	catch (int rcThrown) \
2608	{ \
2609	a_rcTarget = rcThrown
2610	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2611	} \
2612	((void)0)
2613	# else /* !IEM_WITH_THROW_CATCH */
2614	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2615	jmp_buf JmpBuf; \
2616	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2617	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2618	if ((rcStrict = setjmp(JmpBuf)) == 0)
2619	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2620	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2621	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2622	if ((rcStrict = setjmp(JmpBuf)) == 0)
2623	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2624	else \
2625	{ \
2626	((void)0)
2627	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2628	} \
2629	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2630	# endif /* !IEM_WITH_THROW_CATCH */
2631	#endif /* IEM_WITH_SETJMP */
2632
2633
2634	/**
2635	* Shared per-VM IEM data.
2636	*/
2637	typedef struct IEM
2638	{
2639	/** The VMX APIC-access page handler type. */
2640	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2641	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2642	/** Set if the CPUID host call functionality is enabled. */
2643	bool fCpuIdHostCall;
2644	#endif
2645	} IEM;
2646
2647
2648
2649	/** @name IEM_ACCESS_XXX - Access details.
2650	* @{ */
2651	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2652	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2653	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2654	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2655	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2656	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2657	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2658	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2659	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2660	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2661	/** The writes are partial, so if initialize the bounce buffer with the
2662	* orignal RAM content. */
2663	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2664	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2665	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2666	/** Bounce buffer with ring-3 write pending, first page. */
2667	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2668	/** Bounce buffer with ring-3 write pending, second page. */
2669	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2670	/** Not locked, accessed via the TLB. */
2671	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2672	/** Atomic access.
2673	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2674	* fallback for misaligned stuff. See @bugref{10547}. */
2675	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2676	/** Valid bit mask. */
2677	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2678	/** Shift count for the TLB flags (upper word). */
2679	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2680
2681	/** Atomic read+write data alias. */
2682	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2683	/** Read+write data alias. */
2684	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2685	/** Write data alias. */
2686	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2687	/** Read data alias. */
2688	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2689	/** Instruction fetch alias. */
2690	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2691	/** Stack write alias. */
2692	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2693	/** Stack read alias. */
2694	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2695	/** Stack read+write alias. */
2696	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2697	/** Read system table alias. */
2698	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2699	/** Read+write system table alias. */
2700	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2701	/** @} */
2702
2703	/** @name Prefix constants (IEMCPU::fPrefixes)
2704	* @{ */
2705	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2706	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2707	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2708	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2709	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2710	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2711	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2712
2713	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2714	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2715	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2716
2717	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2718	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2719	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2720
2721	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2722	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2723	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2724	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2725	/** Mask with all the REX prefix flags.
2726	* This is generally for use when needing to undo the REX prefixes when they
2727	* are followed legacy prefixes and therefore does not immediately preceed
2728	* the first opcode byte.
2729	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2730	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2731
2732	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2733	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2734	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2735	/** @} */
2736
2737	/** @name IEMOPFORM_XXX - Opcode forms
2738	* @note These are ORed together with IEMOPHINT_XXX.
2739	* @{ */
2740	/** ModR/M: reg, r/m */
2741	#define IEMOPFORM_RM 0
2742	/** ModR/M: reg, r/m (register) */
2743	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2744	/** ModR/M: reg, r/m (memory) */
2745	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2746	/** ModR/M: reg, r/m, imm */
2747	#define IEMOPFORM_RMI 1
2748	/** ModR/M: reg, r/m (register), imm */
2749	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2750	/** ModR/M: reg, r/m (memory), imm */
2751	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2752	/** ModR/M: reg, r/m, xmm0 */
2753	#define IEMOPFORM_RM0 2
2754	/** ModR/M: reg, r/m (register), xmm0 */
2755	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2756	/** ModR/M: reg, r/m (memory), xmm0 */
2757	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2758	/** ModR/M: r/m, reg */
2759	#define IEMOPFORM_MR 3
2760	/** ModR/M: r/m (register), reg */
2761	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2762	/** ModR/M: r/m (memory), reg */
2763	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2764	/** ModR/M: r/m, reg, imm */
2765	#define IEMOPFORM_MRI 4
2766	/** ModR/M: r/m (register), reg, imm */
2767	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2768	/** ModR/M: r/m (memory), reg, imm */
2769	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2770	/** ModR/M: r/m only */
2771	#define IEMOPFORM_M 5
2772	/** ModR/M: r/m only (register). */
2773	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2774	/** ModR/M: r/m only (memory). */
2775	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2776	/** ModR/M: r/m, imm */
2777	#define IEMOPFORM_MI 6
2778	/** ModR/M: r/m (register), imm */
2779	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2780	/** ModR/M: r/m (memory), imm */
2781	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2782	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2783	#define IEMOPFORM_M1 7
2784	/** ModR/M: r/m (register), 1. */
2785	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2786	/** ModR/M: r/m (memory), 1. */
2787	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2788	/** ModR/M: r/m, CL (shift and rotate instructions)
2789	* @todo This should just've been a generic fixed register. But the python
2790	* code doesn't needs more convincing. */
2791	#define IEMOPFORM_M_CL 8
2792	/** ModR/M: r/m (register), CL. */
2793	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2794	/** ModR/M: r/m (memory), CL. */
2795	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2796	/** ModR/M: reg only */
2797	#define IEMOPFORM_R 9
2798
2799	/** VEX+ModR/M: reg, r/m */
2800	#define IEMOPFORM_VEX_RM 16
2801	/** VEX+ModR/M: reg, r/m (register) */
2802	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2803	/** VEX+ModR/M: reg, r/m (memory) */
2804	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2805	/** VEX+ModR/M: r/m, reg */
2806	#define IEMOPFORM_VEX_MR 17
2807	/** VEX+ModR/M: r/m (register), reg */
2808	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2809	/** VEX+ModR/M: r/m (memory), reg */
2810	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2811	/** VEX+ModR/M: r/m, reg, imm8 */
2812	#define IEMOPFORM_VEX_MRI 18
2813	/** VEX+ModR/M: r/m (register), reg, imm8 */
2814	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2815	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2816	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2817	/** VEX+ModR/M: r/m only */
2818	#define IEMOPFORM_VEX_M 19
2819	/** VEX+ModR/M: r/m only (register). */
2820	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2821	/** VEX+ModR/M: r/m only (memory). */
2822	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2823	/** VEX+ModR/M: reg only */
2824	#define IEMOPFORM_VEX_R 20
2825	/** VEX+ModR/M: reg, vvvv, r/m */
2826	#define IEMOPFORM_VEX_RVM 21
2827	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2828	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2829	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2830	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2831	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2832	#define IEMOPFORM_VEX_RVMI 22
2833	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2834	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2835	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2836	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2837	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2838	#define IEMOPFORM_VEX_RVMR 23
2839	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2840	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2841	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2842	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2843	/** VEX+ModR/M: reg, r/m, vvvv */
2844	#define IEMOPFORM_VEX_RMV 24
2845	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2846	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2847	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2848	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2849	/** VEX+ModR/M: reg, r/m, imm8 */
2850	#define IEMOPFORM_VEX_RMI 25
2851	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2852	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2853	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2854	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2855	/** VEX+ModR/M: r/m, vvvv, reg */
2856	#define IEMOPFORM_VEX_MVR 26
2857	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2858	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2859	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2860	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2861	/** VEX+ModR/M+/n: vvvv, r/m */
2862	#define IEMOPFORM_VEX_VM 27
2863	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2864	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2865	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2866	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2867	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2868	#define IEMOPFORM_VEX_VMI 28
2869	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2870	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2871	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2872	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2873
2874	/** Fixed register instruction, no R/M. */
2875	#define IEMOPFORM_FIXED 32
2876
2877	/** The r/m is a register. */
2878	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2879	/** The r/m is a memory access. */
2880	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2881	/** @} */
2882
2883	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2884	* @note These are ORed together with IEMOPFORM_XXX.
2885	* @{ */
2886	/** Ignores the operand size prefix (66h). */
2887	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2888	/** Ignores REX.W (aka WIG). */
2889	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2890	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2891	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2892	/** Allowed with the lock prefix. */
2893	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2894	/** The VEX.L value is ignored (aka LIG). */
2895	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2896	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2897	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2898	/** The VEX.L value must be one (i.e. 256-bit width only). */
2899	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2900	/** The VEX.V value must be zero. */
2901	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2902	/** The REX.W/VEX.V value must be zero. */
2903	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2904	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2905	/** The REX.W/VEX.V value must be one. */
2906	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2907	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2908
2909	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2910	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2911	/** @} */
2912
2913	/**
2914	* Possible hardware task switch sources.
2915	*/
2916	typedef enum IEMTASKSWITCH
2917	{
2918	/** Task switch caused by an interrupt/exception. */
2919	IEMTASKSWITCH_INT_XCPT = 1,
2920	/** Task switch caused by a far CALL. */
2921	IEMTASKSWITCH_CALL,
2922	/** Task switch caused by a far JMP. */
2923	IEMTASKSWITCH_JUMP,
2924	/** Task switch caused by an IRET. */
2925	IEMTASKSWITCH_IRET
2926	} IEMTASKSWITCH;
2927	AssertCompileSize(IEMTASKSWITCH, 4);
2928
2929	/**
2930	* Possible CrX load (write) sources.
2931	*/
2932	typedef enum IEMACCESSCRX
2933	{
2934	/** CrX access caused by 'mov crX' instruction. */
2935	IEMACCESSCRX_MOV_CRX,
2936	/** CrX (CR0) write caused by 'lmsw' instruction. */
2937	IEMACCESSCRX_LMSW,
2938	/** CrX (CR0) write caused by 'clts' instruction. */
2939	IEMACCESSCRX_CLTS,
2940	/** CrX (CR0) read caused by 'smsw' instruction. */
2941	IEMACCESSCRX_SMSW
2942	} IEMACCESSCRX;
2943
2944	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2945	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2946	*
2947	* These flags provide further context to SLAT page-walk failures that could not be
2948	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2949	*
2950	* @{
2951	*/
2952	/** Translating a nested-guest linear address failed accessing a nested-guest
2953	* physical address. */
2954	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2955	/** Translating a nested-guest linear address failed accessing a
2956	* paging-structure entry or updating accessed/dirty bits. */
2957	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2958	/** @} */
2959
2960	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2961	# ifndef IN_RING3
2962	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2963	# endif
2964	#endif
2965
2966	/**
2967	* Indicates to the verifier that the given flag set is undefined.
2968	*
2969	* Can be invoked again to add more flags.
2970	*
2971	* This is a NOOP if the verifier isn't compiled in.
2972	*
2973	* @note We're temporarily keeping this until code is converted to new
2974	* disassembler style opcode handling.
2975	*/
2976	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2977
2978
2979	/** @def IEM_DECL_IMPL_TYPE
2980	* For typedef'ing an instruction implementation function.
2981	*
2982	* @param a_RetType The return type.
2983	* @param a_Name The name of the type.
2984	* @param a_ArgList The argument list enclosed in parentheses.
2985	*/
2986
2987	/** @def IEM_DECL_IMPL_DEF
2988	* For defining an instruction implementation function.
2989	*
2990	* @param a_RetType The return type.
2991	* @param a_Name The name of the type.
2992	* @param a_ArgList The argument list enclosed in parentheses.
2993	*/
2994
2995	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2996	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2997	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2998	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2999	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3000	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3001	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3002
3003	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3004	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3005	a_RetType (__fastcall a_Name) a_ArgList
3006	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3007	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3008	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3009	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3010
3011	#elif __cplusplus >= 201700 /* P0012R1 support */
3012	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3013	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
3014	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3015	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3016	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3017	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3018
3019	#else
3020	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3021	a_RetType (VBOXCALL a_Name) a_ArgList
3022	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3023	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3024	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3025	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3026
3027	#endif
3028
3029	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
3030	RT_C_DECLS_BEGIN
3031	extern uint8_t const g_afParity[256];
3032	RT_C_DECLS_END
3033
3034
3035	/** @name Arithmetic assignment operations on bytes (binary).
3036	* @{ */
3037	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
3038	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
3039	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
3040	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
3041	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
3042	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
3043	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
3044	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
3045	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
3046	/** @} */
3047
3048	/** @name Arithmetic assignment operations on words (binary).
3049	* @{ */
3050	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
3051	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
3052	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
3053	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
3054	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
3055	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
3056	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
3057	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
3058	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
3059	/** @} */
3060
3061
3062	/** @name Arithmetic assignment operations on double words (binary).
3063	* @{ */
3064	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
3065	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
3066	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
3067	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
3068	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
3069	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
3070	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
3071	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
3072	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
3073	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
3074	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
3075	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
3076	/** @} */
3077
3078	/** @name Arithmetic assignment operations on quad words (binary).
3079	* @{ */
3080	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
3081	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
3082	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
3083	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
3084	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
3085	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
3086	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
3087	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
3088	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
3089	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
3090	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
3091	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
3092	/** @} */
3093
3094	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
3095	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
3096	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
3097	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
3098	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
3099	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
3100	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
3101	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
3102
3103	/** @name Compare operations (thrown in with the binary ops).
3104	* @{ */
3105	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
3106	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
3107	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
3108	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
3109	/** @} */
3110
3111	/** @name Test operations (thrown in with the binary ops).
3112	* @{ */
3113	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
3114	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
3115	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
3116	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
3117	/** @} */
3118
3119	/** @name Bit operations operations (thrown in with the binary ops).
3120	* @{ */
3121	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
3122	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
3123	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
3124	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
3125	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
3126	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
3127	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
3128	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
3129	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
3130	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
3131	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
3132	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
3133	/** @} */
3134
3135	/** @name Arithmetic three operand operations on double words (binary).
3136	* @{ */
3137	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
3138	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
3139	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
3140	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
3141	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
3142	/** @} */
3143
3144	/** @name Arithmetic three operand operations on quad words (binary).
3145	* @{ */
3146	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
3147	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
3148	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
3149	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
3150	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
3151	/** @} */
3152
3153	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
3154	* @{ */
3155	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
3156	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
3157	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
3158	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
3159	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
3160	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
3161	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
3162	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
3163	/** @} */
3164
3165	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
3166	* @{ */
3167	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
3168	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
3169	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
3170	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
3171	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
3172	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
3173	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
3174	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
3175	/** @} */
3176
3177	/** @name MULX 32-bit and 64-bit.
3178	* @{ */
3179	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
3180	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
3181	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
3182
3183	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
3184	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
3185	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
3186	/** @} */
3187
3188
3189	/** @name Exchange memory with register operations.
3190	* @{ */
3191	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
3192	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
3193	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
3194	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
3195	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
3196	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
3197	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
3198	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
3199	/** @} */
3200
3201	/** @name Exchange and add operations.
3202	* @{ */
3203	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3204	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3205	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3206	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3207	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3208	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3209	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3210	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3211	/** @} */
3212
3213	/** @name Compare and exchange.
3214	* @{ */
3215	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3216	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3217	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3218	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3219	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3220	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3221	#if ARCH_BITS == 32
3222	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3223	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3224	#else
3225	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3226	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3227	#endif
3228	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3229	uint32_t *pEFlags));
3230	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3231	uint32_t *pEFlags));
3232	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3233	uint32_t *pEFlags));
3234	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3235	uint32_t *pEFlags));
3236	#ifndef RT_ARCH_ARM64
3237	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3238	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3239	#endif
3240	/** @} */
3241
3242	/** @name Memory ordering
3243	* @{ */
3244	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3245	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3246	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3247	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3248	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3249	#ifndef RT_ARCH_ARM64
3250	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3251	#endif
3252	/** @} */
3253
3254	/** @name Double precision shifts
3255	* @{ */
3256	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3257	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3258	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3259	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3260	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3261	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3262	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3263	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3264	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3265	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3266	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3267	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3268	/** @} */
3269
3270
3271	/** @name Bit search operations (thrown in with the binary ops).
3272	* @{ */
3273	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3274	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3275	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3276	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3277	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3278	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3279	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3280	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3281	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3282	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3283	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3284	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3285	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3286	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3287	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3288	/** @} */
3289
3290	/** @name Signed multiplication operations (thrown in with the binary ops).
3291	* @{ */
3292	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3293	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3294	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3295	/** @} */
3296
3297	/** @name Arithmetic assignment operations on bytes (unary).
3298	* @{ */
3299	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3300	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3301	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3302	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3303	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3304	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3305	/** @} */
3306
3307	/** @name Arithmetic assignment operations on words (unary).
3308	* @{ */
3309	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3310	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3311	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3312	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3313	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3314	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3315	/** @} */
3316
3317	/** @name Arithmetic assignment operations on double words (unary).
3318	* @{ */
3319	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3320	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3321	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3322	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3323	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3324	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3325	/** @} */
3326
3327	/** @name Arithmetic assignment operations on quad words (unary).
3328	* @{ */
3329	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3330	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3331	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3332	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3333	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3334	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3335	/** @} */
3336
3337
3338	/** @name Shift operations on bytes (Group 2).
3339	* @{ */
3340	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3341	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3342	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3343	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3344	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3345	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3346	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3347	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3348	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3349	/** @} */
3350
3351	/** @name Shift operations on words (Group 2).
3352	* @{ */
3353	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3354	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3355	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3356	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3357	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3358	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3359	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3360	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3361	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3362	/** @} */
3363
3364	/** @name Shift operations on double words (Group 2).
3365	* @{ */
3366	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3367	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3368	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3369	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3370	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3371	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3372	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3373	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3374	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3375	/** @} */
3376
3377	/** @name Shift operations on words (Group 2).
3378	* @{ */
3379	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3380	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3381	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3382	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3383	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3384	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3385	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3386	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3387	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3388	/** @} */
3389
3390	/** @name Multiplication and division operations.
3391	* @{ */
3392	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU8,(uint16_t *pu16AX, uint8_t u8FactorDivisor, uint32_t fEFlags));
3393	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3394	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3395	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3396	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3397	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3398
3399	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t fEFlags));
3400	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3401	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3402	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3403	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3404	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3405
3406	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t fEFlags));
3407	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3408	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3409	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3410	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3411	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3412
3413	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t fEFlags));
3414	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3415	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3416	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3417	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3418	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3419	/** @} */
3420
3421	/** @name Byte Swap.
3422	* @{ */
3423	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3424	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3425	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3426	/** @} */
3427
3428	/** @name Misc.
3429	* @{ */
3430	FNIEMAIMPLBINU16 iemAImpl_arpl;
3431	/** @} */
3432
3433	/** @name RDRAND and RDSEED
3434	* @{ */
3435	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3436	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3437	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3438	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3439	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3440	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3441
3442	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3443	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3444	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3445	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3446	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3447	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3448	/** @} */
3449
3450	/** @name ADOX and ADCX
3451	* @{ */
3452	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3453	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3454	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3455	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3456	/** @} */
3457
3458	/** @name FPU operations taking a 32-bit float argument
3459	* @{ */
3460	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3461	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3462	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3463
3464	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3465	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3466	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3467
3468	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3469	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3470	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3471	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3472	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3473	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3474	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3475
3476	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3477	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3478	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3479	/** @} */
3480
3481	/** @name FPU operations taking a 64-bit float argument
3482	* @{ */
3483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3484	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3485	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3486
3487	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3488	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3489	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3490
3491	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3492	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3493	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3494	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3495	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3496	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3497	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3498
3499	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3500	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3501	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3502	/** @} */
3503
3504	/** @name FPU operations taking a 80-bit float argument
3505	* @{ */
3506	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3507	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3508	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3509	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3510	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3511	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3512	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3513	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3514	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3515	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3516	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3517	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3518
3519	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3520	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3521	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3522
3523	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3524	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3525	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3526	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3527	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3528
3529	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3530	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3531	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3532	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3533	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3534
3535	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3536	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3537	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3538	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3539	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3540	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3541	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3542	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3543	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3544
3545	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3546	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3547	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3548	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3549
3550	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3551	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3552	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3553	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3554	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3555	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3556	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3557	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3558	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3559
3560	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3561	PCRTFLOAT80U pr80Val));
3562	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3563	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3564	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3565	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3566
3567	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3568	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3569	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3570
3571	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3572	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3573	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3574
3575	/** @} */
3576
3577	/** @name FPU operations taking a 16-bit signed integer argument
3578	* @{ */
3579	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3580	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3581	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3582	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3583	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3584	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3585
3586	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3587	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3588	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3589	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3590	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3591	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3592
3593	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3594	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3595	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3596	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3597
3598	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3599	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3600	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3601	/** @} */
3602
3603	/** @name FPU operations taking a 32-bit signed integer argument
3604	* @{ */
3605	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3606	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3607	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3608	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3609	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3610	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3611
3612	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3613	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3614	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3615	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3616	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3617	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3618
3619	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3620	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3621	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3622	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3623
3624	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3625	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3626	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3627	/** @} */
3628
3629	/** @name FPU operations taking a 64-bit signed integer argument
3630	* @{ */
3631	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3632	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3633	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3634
3635	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3636	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3637	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3638	/** @} */
3639
3640
3641	/** Temporary type representing a 256-bit vector register. */
3642	typedef struct { uint64_t au64[4]; } IEMVMM256;
3643	/** Temporary type pointing to a 256-bit vector register. */
3644	typedef IEMVMM256 *PIEMVMM256;
3645	/** Temporary type pointing to a const 256-bit vector register. */
3646	typedef IEMVMM256 *PCIEMVMM256;
3647
3648
3649	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3650	* @{ */
3651	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3652	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3653	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
3654	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3655	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc));
3656	typedef FNIEMAIMPLMEDIAF2U256 *PFNIEMAIMPLMEDIAF2U256;
3657	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3658	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3659	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3660	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3661	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3662	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3663	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3664	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3665	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3666	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3667	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3668	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3669	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3670	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3671	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3672	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3673	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3674	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3675	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3676	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3677	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3678	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3679	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3680	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3681	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3682	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3683	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3684	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3685	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3686	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3687	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3688	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3689	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3690	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3691	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3692	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3693	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3694	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3695	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3696	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3697	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3698	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3699	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3700	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3701	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3702	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3703	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3704	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3705	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3706	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3707	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3708	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3709	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3710
3711	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3712	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3713	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3714	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3715	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3716	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3717	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3718	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3719	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3720	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3721	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3722	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3723	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3724	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3725	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3726	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3727	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3728	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3729	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3730	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3731	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3732	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3733	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3734	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3735	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3736	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3737	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3738	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3739	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3740	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3741	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3742	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3743	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3744	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3745	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3746	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3747	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3748	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3749	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3750	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3751	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3752	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3753	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3754	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3755	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3756	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3757	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3758	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3759	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3760	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3761	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3762	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3763	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3764	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3765	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3766	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3767	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3768	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3769
3770	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3771	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3772	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3773	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3774	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3775	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3776	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3777	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3778	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3779	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3780	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3781	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3782	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3783	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3784	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3785	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3786	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3787	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3788	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3789	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3790	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3791	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3792	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3793	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3794	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3795	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3796	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3797	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3798	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3799	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3800	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3801	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3802	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3803	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3804	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3805	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3806	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3807	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3808	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3809	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3810	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3811	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3812	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3813	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3814	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3815	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3816	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3817	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3818	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3819	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3820	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3821	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3822	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3823	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3824	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3825	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3826	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3827	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3828	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3829	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3830	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3831	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3832	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3833	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3834	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3835	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3836	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3837	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3838	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3839	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3840	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3841	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3842	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3843	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3844
3845	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3846	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3847	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3848	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3849
3850	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3851	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3852	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3853	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3854	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3855	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3856	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3857	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3858	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3859	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3860	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3861	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3862	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3863	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3864	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3865	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3866	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3867	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3868	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3869	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3870	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3871	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3872	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3873	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3874	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3875	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3876	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3877	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3878	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3879	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3880	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3881	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3882	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3883	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3884	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3885	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3886	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3887	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3888	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3889	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3890	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3891	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3892	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3893	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3894	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3895	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3896	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3897	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3898	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3899	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3900	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3901	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3902	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3903	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3904	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3905	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3906	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3907	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3908	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3909	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3910	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3911	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3912	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3913	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3914	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3915	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3916	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3917	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3918	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3919	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3920	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3921	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3922	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3923	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3924	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermps_u256, iemAImpl_vpermps_u256_fallback;
3925	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermd_u256, iemAImpl_vpermd_u256_fallback;
3926
3927	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3928	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3929	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3930	/** @} */
3931
3932	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3933	* @{ */
3934	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3935	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3936	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3937	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3938	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3939	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3940	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3941	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3942	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3943	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3944
3945	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3946	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3947	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3948	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3949	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3950	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3951	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3952	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3953	/** @} */
3954
3955	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3956	* @{ */
3957	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3958	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3959	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3960	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3961	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3962	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3963	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3964	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3965	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3966	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3967	/** @} */
3968
3969	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3970	* @{ */
3971	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3972	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3973	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3974	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3975	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3976	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3977	#ifndef IEM_WITHOUT_ASSEMBLY
3978	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3979	#endif
3980	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3981	/** @} */
3982
3983	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3984	* @{ */
3985	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3986	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3987	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3988	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3989	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3990	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3991	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3992	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3993	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3994	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3995	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3996	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3997	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3998	/** @} */
3999
4000	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
4001	* @{ */
4002	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
4003	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
4004	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
4005	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
4006	#ifndef IEM_WITHOUT_ASSEMBLY
4007	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4008	#endif
4009	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4010	/** @} */
4011
4012	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
4013	* @{ */
4014	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
4015	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
4016	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
4017	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
4018	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
4019	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
4020
4021	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
4022	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
4023	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
4024	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
4025	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
4026	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
4027
4028	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
4029	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
4030	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
4031	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
4032	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
4033	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
4034
4035	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
4036	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
4037	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
4038	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
4039	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
4040	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
4041	/** @} */
4042
4043
4044	/** @name Media (SSE/MMX/AVX) operation: Sort this later
4045	* @{ */
4046	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4047	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4048	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4049	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4050	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4051
4052	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4053	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4054	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4055	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4056	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4057
4058	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4059	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4060	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4061	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4062	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4063
4064	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4065	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4066	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4067	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4068	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4069
4070	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4071	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4072	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4073	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4074	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4075
4076	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4077	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4078	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4079	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4080	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4081
4082	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4083	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4084	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4085	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4086	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4087
4088	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4089	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4090	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4091	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4092	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4093
4094	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4095	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4096	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4097	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4098	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4099
4100	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4101	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4102	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4103	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4104	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4105
4106	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4107	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4108	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4109	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4110	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4111
4112	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4113	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4114	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4115	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4116	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4117
4118	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4119	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4120	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4121	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4122	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4123
4124	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4125	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4126	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4127	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4128	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4129
4130	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4131	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4132
4133	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4134	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4135	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4136	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4137	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4138
4139	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4140	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4141	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4142	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4143	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4144
4145
4146	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4147	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
4148	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4149	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
4150	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4151	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
4152	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4153	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
4154
4155	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
4156	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
4157	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
4158	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
4159
4160	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
4161	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
4162	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
4163	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
4164	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
4165
4166	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
4167	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
4168	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
4169	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
4170	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
4171	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
4172	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
4173
4174	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
4175	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
4176	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
4177	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
4178	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
4179
4180	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
4181	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
4182	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
4183	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
4184	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
4185
4186	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
4187
4188	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
4189
4190	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
4191	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
4192	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
4193	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
4194	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
4195	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
4196	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4197	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4198
4199	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermq_u256, iemAImpl_vpermq_u256_fallback;
4200	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermpd_u256, iemAImpl_vpermpd_u256_fallback;
4201
4202	typedef struct IEMPCMPISTRXSRC
4203	{
4204	RTUINT128U uSrc1;
4205	RTUINT128U uSrc2;
4206	} IEMPCMPISTRXSRC;
4207	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
4208	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
4209
4210	typedef struct IEMPCMPESTRXSRC
4211	{
4212	RTUINT128U uSrc1;
4213	RTUINT128U uSrc2;
4214	uint64_t u64Rax;
4215	uint64_t u64Rdx;
4216	} IEMPCMPESTRXSRC;
4217	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
4218	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
4219
4220	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
4221	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
4222	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4223	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4224
4225	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4226	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4227	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4228	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4229
4230	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4231	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4232	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4233	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4234	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_vpcmpistri_u128, iemAImpl_vpcmpistri_u128_fallback;
4235	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_vpcmpestri_u128, iemAImpl_vpcmpestri_u128_fallback;
4236	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_vpcmpistrm_u128, iemAImpl_vpcmpistrm_u128_fallback;
4237	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_vpcmpestrm_u128, iemAImpl_vpcmpestrm_u128_fallback;
4238
4239
4240	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4241	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4242
4243	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4244	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4245	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4246
4247	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4248	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4249	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4250	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4251	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4252	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4253	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4254	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4255	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4256	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4257
4258	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4259	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4260	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4261	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4262
4263	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4264	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4265	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4266	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4267	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4268	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4269	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4270	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4271	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4272	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4273
4274	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4275	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4276	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4277	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4278
4279	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4280	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4281	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4282	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4283
4284	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4285	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4286	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4287	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4288	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4289	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4290	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4291	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4292	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4293	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4294	/** @} */
4295
4296	/** @name Media Odds and Ends
4297	* @{ */
4298	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4299	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4300	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4301	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4302	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4303	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4304	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4305	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4306
4307	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4308	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4309	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4310	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4311	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4312	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4313	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4314	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4315	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4316	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4317
4318	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4319	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4320	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4321	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4322	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4323	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4324	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4325	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4326	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R32,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT32U pr32Src));
4327	typedef FNIEMAIMPLSSEF2I32R32 *PFNIEMAIMPLSSEF2I32R32;
4328	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R32,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT32U pr32Src));
4329	typedef FNIEMAIMPLSSEF2I64R32 *PFNIEMAIMPLSSEF2I64R32;
4330	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R64,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT64U pr64Src));
4331	typedef FNIEMAIMPLSSEF2I32R64 *PFNIEMAIMPLSSEF2I32R64;
4332	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R64,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT64U pr64Src));
4333	typedef FNIEMAIMPLSSEF2I64R64 *PFNIEMAIMPLSSEF2I64R64;
4334
4335	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4336	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4337
4338	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4339	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4340
4341	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4342	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4343
4344	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4345	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4346
4347	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttss2si_i32_r32, iemAImpl_vcvttss2si_i32_r32_fallback;
4348	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttss2si_i64_r32, iemAImpl_vcvttss2si_i64_r32_fallback;
4349	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtss2si_i32_r32, iemAImpl_vcvtss2si_i32_r32_fallback;
4350	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtss2si_i64_r32, iemAImpl_vcvtss2si_i64_r32_fallback;
4351
4352	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttss2si_i32_r64, iemAImpl_vcvttss2si_i32_r64_fallback;
4353	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttss2si_i64_r64, iemAImpl_vcvttss2si_i64_r64_fallback;
4354	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtss2si_i32_r64, iemAImpl_vcvtss2si_i32_r64_fallback;
4355	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtss2si_i64_r64, iemAImpl_vcvtss2si_i64_r64_fallback;
4356
4357	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttsd2si_i32_r32, iemAImpl_vcvttsd2si_i32_r32_fallback;
4358	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttsd2si_i64_r32, iemAImpl_vcvttsd2si_i64_r32_fallback;
4359	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtsd2si_i32_r32, iemAImpl_vcvtsd2si_i32_r32_fallback;
4360	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtsd2si_i64_r32, iemAImpl_vcvtsd2si_i64_r32_fallback;
4361
4362	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttsd2si_i32_r64, iemAImpl_vcvttsd2si_i32_r64_fallback;
4363	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttsd2si_i64_r64, iemAImpl_vcvttsd2si_i64_r64_fallback;
4364	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtsd2si_i32_r64, iemAImpl_vcvtsd2si_i32_r64_fallback;
4365	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtsd2si_i64_r64, iemAImpl_vcvtsd2si_i64_r64_fallback;
4366
4367	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4368	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4369	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4370	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4371
4372	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4373	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4374
4375	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI32,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int32_t *pi32Src));
4376	typedef FNIEMAIMPLAVXF3XMMI32 *PFNIEMAIMPLAVXF3XMMI32;
4377	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI64,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int64_t *pi64Src));
4378	typedef FNIEMAIMPLAVXF3XMMI64 *PFNIEMAIMPLAVXF3XMMI64;
4379
4380	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2ss_u128_i32, iemAImpl_vcvtsi2ss_u128_i32_fallback;
4381	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2ss_u128_i64, iemAImpl_vcvtsi2ss_u128_i64_fallback;
4382
4383
4384	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4385	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4386	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4387	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4388
4389	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4390	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4391
4392	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2sd_u128_i32, iemAImpl_vcvtsi2sd_u128_i32_fallback;
4393	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2sd_u128_i64, iemAImpl_vcvtsi2sd_u128_i64_fallback;
4394
4395	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4396	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4397	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4398	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4399
4400
4401	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4402	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4403	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4404	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4405
4406
4407	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4408	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4409
4410	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4411	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4412
4413	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4414	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4415
4416	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4417	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4418
4419	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4420	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4421
4422	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4423	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4424
4425
4426	typedef struct IEMMEDIAF2XMMSRC
4427	{
4428	X86XMMREG uSrc1;
4429	X86XMMREG uSrc2;
4430	} IEMMEDIAF2XMMSRC;
4431	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4432	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4433
4434
4435	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4436	typedef FNIEMAIMPLMEDIAF3XMMIMM8 *PFNIEMAIMPLMEDIAF3XMMIMM8;
4437
4438
4439	typedef struct IEMMEDIAF2YMMSRC
4440	{
4441	X86YMMREG uSrc1;
4442	X86YMMREG uSrc2;
4443	} IEMMEDIAF2YMMSRC;
4444	typedef IEMMEDIAF2YMMSRC *PIEMMEDIAF2YMMSRC;
4445	typedef const IEMMEDIAF2YMMSRC *PCIEMMEDIAF2YMMSRC;
4446
4447
4448	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3YMMIMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCIEMMEDIAF2YMMSRC puSrc, uint8_t bEvil));
4449	typedef FNIEMAIMPLMEDIAF3YMMIMM8 *PFNIEMAIMPLMEDIAF3YMMIMM8;
4450
4451
4452	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpps_u128;
4453	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmppd_u128;
4454	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpss_u128;
4455	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpsd_u128;
4456
4457	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpps_u128, iemAImpl_vcmpps_u128_fallback;
4458	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmppd_u128, iemAImpl_vcmppd_u128_fallback;
4459	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpss_u128, iemAImpl_vcmpss_u128_fallback;
4460	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpsd_u128, iemAImpl_vcmpsd_u128_fallback;
4461
4462	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmpps_u256, iemAImpl_vcmpps_u256_fallback;
4463	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmppd_u256, iemAImpl_vcmppd_u256_fallback;
4464
4465	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundss_u128;
4466	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundsd_u128;
4467
4468	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4469	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4470
4471
4472	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128IMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, uint8_t bEvil));
4473	typedef FNIEMAIMPLMEDIAF2U128IMM8 *PFNIEMAIMPLMEDIAF2U128IMM8;
4474
4475
4476	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256IMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc, uint8_t bEvil));
4477	typedef FNIEMAIMPLMEDIAF2U256IMM8 *PFNIEMAIMPLMEDIAF2U256IMM8;
4478
4479
4480	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4481	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4482
4483	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundps_u128, iemAImpl_vroundps_u128_fallback;
4484	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundpd_u128, iemAImpl_vroundpd_u128_fallback;
4485
4486	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundps_u256, iemAImpl_vroundps_u256_fallback;
4487	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundpd_u256, iemAImpl_vroundpd_u256_fallback;
4488
4489	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundss_u128, iemAImpl_vroundss_u128_fallback;
4490	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundsd_u128, iemAImpl_vroundsd_u128_fallback;
4491
4492	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdpps_u128, iemAImpl_vdpps_u128_fallback;
4493	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdppd_u128, iemAImpl_vdppd_u128_fallback;
4494
4495	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vdpps_u256, iemAImpl_vdpps_u256_fallback;
4496
4497
4498	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4499	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4500
4501	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4502	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4503
4504	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4505	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4506
4507	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4508	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4509
4510	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4511	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4512
4513	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4514	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4515
4516	/** @} */
4517
4518
4519	/** @name Function tables.
4520	* @{
4521	*/
4522
4523	/**
4524	* Function table for a binary operator providing implementation based on
4525	* operand size.
4526	*/
4527	typedef struct IEMOPBINSIZES
4528	{
4529	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4530	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4531	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4532	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4533	} IEMOPBINSIZES;
4534	/** Pointer to a binary operator function table. */
4535	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4536
4537
4538	/**
4539	* Function table for a unary operator providing implementation based on
4540	* operand size.
4541	*/
4542	typedef struct IEMOPUNARYSIZES
4543	{
4544	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4545	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4546	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4547	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4548	} IEMOPUNARYSIZES;
4549	/** Pointer to a unary operator function table. */
4550	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4551
4552
4553	/**
4554	* Function table for a shift operator providing implementation based on
4555	* operand size.
4556	*/
4557	typedef struct IEMOPSHIFTSIZES
4558	{
4559	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4560	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4561	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4562	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4563	} IEMOPSHIFTSIZES;
4564	/** Pointer to a shift operator function table. */
4565	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4566
4567
4568	/**
4569	* Function table for a multiplication or division operation.
4570	*/
4571	typedef struct IEMOPMULDIVSIZES
4572	{
4573	PFNIEMAIMPLMULDIVU8 pfnU8;
4574	PFNIEMAIMPLMULDIVU16 pfnU16;
4575	PFNIEMAIMPLMULDIVU32 pfnU32;
4576	PFNIEMAIMPLMULDIVU64 pfnU64;
4577	} IEMOPMULDIVSIZES;
4578	/** Pointer to a multiplication or division operation function table. */
4579	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4580
4581
4582	/**
4583	* Function table for a double precision shift operator providing implementation
4584	* based on operand size.
4585	*/
4586	typedef struct IEMOPSHIFTDBLSIZES
4587	{
4588	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4589	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4590	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4591	} IEMOPSHIFTDBLSIZES;
4592	/** Pointer to a double precision shift function table. */
4593	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4594
4595
4596	/**
4597	* Function table for media instruction taking two full sized media source
4598	* registers and one full sized destination register (AVX).
4599	*/
4600	typedef struct IEMOPMEDIAF3
4601	{
4602	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4603	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4604	} IEMOPMEDIAF3;
4605	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4606	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4607
4608	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4609	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4610	* given functions as initializers. For use in AVX functions where a pair of
4611	* functions are only used once and the function table need not be public. */
4612	#ifndef TST_IEM_CHECK_MC
4613	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4614	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4615	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4616	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4617	# else
4618	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4619	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4620	# endif
4621	#else
4622	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4623	#endif
4624	/** @def IEMOPMEDIAF3_INIT_VARS
4625	* Generate AVX function tables for the @a a_InstrNm instruction.
4626	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4627	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4628	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4629	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4630
4631
4632	/**
4633	* Function table for media instruction taking one full sized media source
4634	* registers and one full sized destination register (AVX).
4635	*/
4636	typedef struct IEMOPMEDIAF2
4637	{
4638	PFNIEMAIMPLMEDIAF2U128 pfnU128;
4639	PFNIEMAIMPLMEDIAF2U256 pfnU256;
4640	} IEMOPMEDIAF2;
4641	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4642	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
4643
4644	/** @def IEMOPMEDIAF2_INIT_VARS_EX
4645	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4646	* given functions as initializers. For use in AVX functions where a pair of
4647	* functions are only used once and the function table need not be public. */
4648	#ifndef TST_IEM_CHECK_MC
4649	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4650	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4651	static IEMOPMEDIAF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4652	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4653	# else
4654	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4655	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4656	# endif
4657	#else
4658	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4659	#endif
4660	/** @def IEMOPMEDIAF2_INIT_VARS
4661	* Generate AVX function tables for the @a a_InstrNm instruction.
4662	* @sa IEMOPMEDIAF2_INIT_VARS_EX */
4663	#define IEMOPMEDIAF2_INIT_VARS(a_InstrNm) \
4664	IEMOPMEDIAF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4665	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4666
4667
4668	/**
4669	* Function table for media instruction taking two full sized media source
4670	* registers and one full sized destination register, but no additional state
4671	* (AVX).
4672	*/
4673	typedef struct IEMOPMEDIAOPTF3
4674	{
4675	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4676	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4677	} IEMOPMEDIAOPTF3;
4678	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4679	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4680
4681	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4682	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4683	* given functions as initializers. For use in AVX functions where a pair of
4684	* functions are only used once and the function table need not be public. */
4685	#ifndef TST_IEM_CHECK_MC
4686	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4687	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4688	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4689	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4690	# else
4691	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4692	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4693	# endif
4694	#else
4695	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4696	#endif
4697	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4698	* Generate AVX function tables for the @a a_InstrNm instruction.
4699	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4700	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4701	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4702	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4703
4704	/**
4705	* Function table for media instruction taking one full sized media source
4706	* registers and one full sized destination register, but no additional state
4707	* (AVX).
4708	*/
4709	typedef struct IEMOPMEDIAOPTF2
4710	{
4711	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4712	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4713	} IEMOPMEDIAOPTF2;
4714	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4715	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4716
4717	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4718	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4719	* given functions as initializers. For use in AVX functions where a pair of
4720	* functions are only used once and the function table need not be public. */
4721	#ifndef TST_IEM_CHECK_MC
4722	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4723	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4724	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4725	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4726	# else
4727	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4728	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4729	# endif
4730	#else
4731	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4732	#endif
4733	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4734	* Generate AVX function tables for the @a a_InstrNm instruction.
4735	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4736	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4737	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4738	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4739
4740
4741	/**
4742	* Function table for media instruction taking one full sized media source
4743	* register and one full sized destination register and an 8-bit immediate (AVX).
4744	*/
4745	typedef struct IEMOPMEDIAF2IMM8
4746	{
4747	PFNIEMAIMPLMEDIAF2U128IMM8 pfnU128;
4748	PFNIEMAIMPLMEDIAF2U256IMM8 pfnU256;
4749	} IEMOPMEDIAF2IMM8;
4750	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4751	typedef IEMOPMEDIAF2IMM8 const *PCIEMOPMEDIAF2IMM8;
4752
4753	/** @def IEMOPMEDIAF2IMM8_INIT_VARS_EX
4754	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4755	* given functions as initializers. For use in AVX functions where a pair of
4756	* functions are only used once and the function table need not be public. */
4757	#ifndef TST_IEM_CHECK_MC
4758	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4759	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4760	static IEMOPMEDIAF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4761	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4762	# else
4763	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4764	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4765	# endif
4766	#else
4767	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4768	#endif
4769	/** @def IEMOPMEDIAF2IMM8_INIT_VARS
4770	* Generate AVX function tables for the @a a_InstrNm instruction.
4771	* @sa IEMOPMEDIAF2IMM8_INIT_VARS_EX */
4772	#define IEMOPMEDIAF2IMM8_INIT_VARS(a_InstrNm) \
4773	IEMOPMEDIAF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4774	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4775
4776
4777	/**
4778	* Function table for media instruction taking one full sized media source
4779	* register and one full sized destination register and an 8-bit immediate, but no additional state
4780	* (AVX).
4781	*/
4782	typedef struct IEMOPMEDIAOPTF2IMM8
4783	{
4784	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4785	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4786	} IEMOPMEDIAOPTF2IMM8;
4787	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4788	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4789
4790	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4791	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4792	* given functions as initializers. For use in AVX functions where a pair of
4793	* functions are only used once and the function table need not be public. */
4794	#ifndef TST_IEM_CHECK_MC
4795	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4796	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4797	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4798	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4799	# else
4800	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4801	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4802	# endif
4803	#else
4804	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4805	#endif
4806	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4807	* Generate AVX function tables for the @a a_InstrNm instruction.
4808	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4809	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4810	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4811	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4812
4813	/**
4814	* Function table for media instruction taking two full sized media source
4815	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4816	* (AVX).
4817	*/
4818	typedef struct IEMOPMEDIAOPTF3IMM8
4819	{
4820	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4821	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4822	} IEMOPMEDIAOPTF3IMM8;
4823	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4824	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4825
4826	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4827	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4828	* given functions as initializers. For use in AVX functions where a pair of
4829	* functions are only used once and the function table need not be public. */
4830	#ifndef TST_IEM_CHECK_MC
4831	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4832	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4833	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4834	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4835	# else
4836	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4837	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4838	# endif
4839	#else
4840	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4841	#endif
4842	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4843	* Generate AVX function tables for the @a a_InstrNm instruction.
4844	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4845	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4846	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4847	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4848	/** @} */
4849
4850
4851	/**
4852	* Function table for blend type instruction taking three full sized media source
4853	* registers and one full sized destination register, but no additional state
4854	* (AVX).
4855	*/
4856	typedef struct IEMOPBLENDOP
4857	{
4858	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4859	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4860	} IEMOPBLENDOP;
4861	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4862	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4863
4864	/** @def IEMOPBLENDOP_INIT_VARS_EX
4865	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4866	* given functions as initializers. For use in AVX functions where a pair of
4867	* functions are only used once and the function table need not be public. */
4868	#ifndef TST_IEM_CHECK_MC
4869	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4870	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4871	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4872	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4873	# else
4874	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4875	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4876	# endif
4877	#else
4878	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4879	#endif
4880	/** @def IEMOPBLENDOP_INIT_VARS
4881	* Generate AVX function tables for the @a a_InstrNm instruction.
4882	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4883	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4884	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4885	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4886
4887
4888	/** @name SSE/AVX single/double precision floating point operations.
4889	* @{ */
4890	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4891	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4892	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4893	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4894	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4895	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4896
4897	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4898	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4899	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4900	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4901	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4902	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4903
4904	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4905	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4906
4907	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4908	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4909	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4910	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4911	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4912	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4913	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4914	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4915	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4916	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4917	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4918	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4919	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4920	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4921	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4922	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4923	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4924	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4925	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4926	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4927	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4928	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4929
4930	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4931	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4932
4933	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4934	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4935	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4936	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4937	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4938	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4939
4940	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4941	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4942	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4943	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4944	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4945	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4946	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4947	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4948	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4949	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4950	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4951	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4952	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4953	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4954	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4955	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4956	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4957	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4958
4959	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4960	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4961	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4962	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4963	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4964	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4965	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4966	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4967	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4968	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4969	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4970	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4971	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4972	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4973	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4974	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4975	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4976	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4977	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrsqrtps_u128, iemAImpl_vrsqrtps_u128_fallback;
4978	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrcpps_u128, iemAImpl_vrcpps_u128_fallback;
4979	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4980	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4981	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtdq2ps_u128, iemAImpl_vcvtdq2ps_u128_fallback;
4982	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtps2dq_u128, iemAImpl_vcvtps2dq_u128_fallback;
4983	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvttps2dq_u128, iemAImpl_vcvttps2dq_u128_fallback;
4984	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4985	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4986	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4987	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4988	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4989	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4990
4991
4992	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4993	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4994	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4995	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4996	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4997	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4998	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4999	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
5000	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
5001	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
5002	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
5003	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
5004	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
5005	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
5006	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrsqrtss_u128_r32, iemAImpl_vrsqrtss_u128_r32_fallback;
5007	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrcpss_u128_r32, iemAImpl_vrcpss_u128_r32_fallback;
5008	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vcvtss2sd_u128_r32, iemAImpl_vcvtss2sd_u128_r32_fallback;
5009	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vcvtsd2ss_u128_r64, iemAImpl_vcvtsd2ss_u128_r64_fallback;
5010
5011
5012	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
5013	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
5014	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
5015	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
5016	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
5017	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
5018	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
5019	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
5020	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
5021	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
5022	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
5023	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
5024	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
5025	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
5026	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
5027	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
5028	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubps_u256, iemAImpl_vaddsubps_u256_fallback;
5029	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubpd_u256, iemAImpl_vaddsubpd_u256_fallback;
5030	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtps_u256, iemAImpl_vsqrtps_u256_fallback;
5031	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtpd_u256, iemAImpl_vsqrtpd_u256_fallback;
5032	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrsqrtps_u256, iemAImpl_vrsqrtps_u256_fallback;
5033	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrcpps_u256, iemAImpl_vrcpps_u256_fallback;
5034	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtdq2ps_u256, iemAImpl_vcvtdq2ps_u256_fallback;
5035	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtps2dq_u256, iemAImpl_vcvtps2dq_u256_fallback;
5036	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvttps2dq_u256, iemAImpl_vcvttps2dq_u256_fallback;
5037	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5038	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5039	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5040	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5041	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5042	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5043	/** @} */
5044
5045	/** @name C instruction implementations for anything slightly complicated.
5046	* @{ */
5047
5048	/**
5049	* For typedef'ing or declaring a C instruction implementation function taking
5050	* no extra arguments.
5051	*
5052	* @param a_Name The name of the type.
5053	*/
5054	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
5055	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5056	/**
5057	* For defining a C instruction implementation function taking no extra
5058	* arguments.
5059	*
5060	* @param a_Name The name of the function
5061	*/
5062	# define IEM_CIMPL_DEF_0(a_Name) \
5063	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5064	/**
5065	* Prototype version of IEM_CIMPL_DEF_0.
5066	*/
5067	# define IEM_CIMPL_PROTO_0(a_Name) \
5068	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5069	/**
5070	* For calling a C instruction implementation function taking no extra
5071	* arguments.
5072	*
5073	* This special call macro adds default arguments to the call and allow us to
5074	* change these later.
5075	*
5076	* @param a_fn The name of the function.
5077	*/
5078	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
5079
5080	/** Type for a C instruction implementation function taking no extra
5081	* arguments. */
5082	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
5083	/** Function pointer type for a C instruction implementation function taking
5084	* no extra arguments. */
5085	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
5086
5087	/**
5088	* For typedef'ing or declaring a C instruction implementation function taking
5089	* one extra argument.
5090	*
5091	* @param a_Name The name of the type.
5092	* @param a_Type0 The argument type.
5093	* @param a_Arg0 The argument name.
5094	*/
5095	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
5096	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5097	/**
5098	* For defining a C instruction implementation function taking one extra
5099	* argument.
5100	*
5101	* @param a_Name The name of the function
5102	* @param a_Type0 The argument type.
5103	* @param a_Arg0 The argument name.
5104	*/
5105	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
5106	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5107	/**
5108	* Prototype version of IEM_CIMPL_DEF_1.
5109	*/
5110	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
5111	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5112	/**
5113	* For calling a C instruction implementation function taking one extra
5114	* argument.
5115	*
5116	* This special call macro adds default arguments to the call and allow us to
5117	* change these later.
5118	*
5119	* @param a_fn The name of the function.
5120	* @param a0 The name of the 1st argument.
5121	*/
5122	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
5123
5124	/**
5125	* For typedef'ing or declaring a C instruction implementation function taking
5126	* two extra arguments.
5127	*
5128	* @param a_Name The name of the type.
5129	* @param a_Type0 The type of the 1st argument
5130	* @param a_Arg0 The name of the 1st argument.
5131	* @param a_Type1 The type of the 2nd argument.
5132	* @param a_Arg1 The name of the 2nd argument.
5133	*/
5134	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5135	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5136	/**
5137	* For defining a C instruction implementation function taking two extra
5138	* arguments.
5139	*
5140	* @param a_Name The name of the function.
5141	* @param a_Type0 The type of the 1st argument
5142	* @param a_Arg0 The name of the 1st argument.
5143	* @param a_Type1 The type of the 2nd argument.
5144	* @param a_Arg1 The name of the 2nd argument.
5145	*/
5146	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5147	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5148	/**
5149	* Prototype version of IEM_CIMPL_DEF_2.
5150	*/
5151	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5152	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5153	/**
5154	* For calling a C instruction implementation function taking two extra
5155	* arguments.
5156	*
5157	* This special call macro adds default arguments to the call and allow us to
5158	* change these later.
5159	*
5160	* @param a_fn The name of the function.
5161	* @param a0 The name of the 1st argument.
5162	* @param a1 The name of the 2nd argument.
5163	*/
5164	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
5165
5166	/**
5167	* For typedef'ing or declaring a C instruction implementation function taking
5168	* three extra arguments.
5169	*
5170	* @param a_Name The name of the type.
5171	* @param a_Type0 The type of the 1st argument
5172	* @param a_Arg0 The name of the 1st argument.
5173	* @param a_Type1 The type of the 2nd argument.
5174	* @param a_Arg1 The name of the 2nd argument.
5175	* @param a_Type2 The type of the 3rd argument.
5176	* @param a_Arg2 The name of the 3rd argument.
5177	*/
5178	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5179	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5180	/**
5181	* For defining a C instruction implementation function taking three extra
5182	* arguments.
5183	*
5184	* @param a_Name The name of the function.
5185	* @param a_Type0 The type of the 1st argument
5186	* @param a_Arg0 The name of the 1st argument.
5187	* @param a_Type1 The type of the 2nd argument.
5188	* @param a_Arg1 The name of the 2nd argument.
5189	* @param a_Type2 The type of the 3rd argument.
5190	* @param a_Arg2 The name of the 3rd argument.
5191	*/
5192	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5193	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5194	/**
5195	* Prototype version of IEM_CIMPL_DEF_3.
5196	*/
5197	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5198	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5199	/**
5200	* For calling a C instruction implementation function taking three extra
5201	* arguments.
5202	*
5203	* This special call macro adds default arguments to the call and allow us to
5204	* change these later.
5205	*
5206	* @param a_fn The name of the function.
5207	* @param a0 The name of the 1st argument.
5208	* @param a1 The name of the 2nd argument.
5209	* @param a2 The name of the 3rd argument.
5210	*/
5211	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
5212
5213
5214	/**
5215	* For typedef'ing or declaring a C instruction implementation function taking
5216	* four extra arguments.
5217	*
5218	* @param a_Name The name of the type.
5219	* @param a_Type0 The type of the 1st argument
5220	* @param a_Arg0 The name of the 1st argument.
5221	* @param a_Type1 The type of the 2nd argument.
5222	* @param a_Arg1 The name of the 2nd argument.
5223	* @param a_Type2 The type of the 3rd argument.
5224	* @param a_Arg2 The name of the 3rd argument.
5225	* @param a_Type3 The type of the 4th argument.
5226	* @param a_Arg3 The name of the 4th argument.
5227	*/
5228	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5229	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
5230	/**
5231	* For defining a C instruction implementation function taking four extra
5232	* arguments.
5233	*
5234	* @param a_Name The name of the function.
5235	* @param a_Type0 The type of the 1st argument
5236	* @param a_Arg0 The name of the 1st argument.
5237	* @param a_Type1 The type of the 2nd argument.
5238	* @param a_Arg1 The name of the 2nd argument.
5239	* @param a_Type2 The type of the 3rd argument.
5240	* @param a_Arg2 The name of the 3rd argument.
5241	* @param a_Type3 The type of the 4th argument.
5242	* @param a_Arg3 The name of the 4th argument.
5243	*/
5244	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5245	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5246	a_Type2 a_Arg2, a_Type3 a_Arg3))
5247	/**
5248	* Prototype version of IEM_CIMPL_DEF_4.
5249	*/
5250	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5251	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5252	a_Type2 a_Arg2, a_Type3 a_Arg3))
5253	/**
5254	* For calling a C instruction implementation function taking four extra
5255	* arguments.
5256	*
5257	* This special call macro adds default arguments to the call and allow us to
5258	* change these later.
5259	*
5260	* @param a_fn The name of the function.
5261	* @param a0 The name of the 1st argument.
5262	* @param a1 The name of the 2nd argument.
5263	* @param a2 The name of the 3rd argument.
5264	* @param a3 The name of the 4th argument.
5265	*/
5266	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
5267
5268
5269	/**
5270	* For typedef'ing or declaring a C instruction implementation function taking
5271	* five extra arguments.
5272	*
5273	* @param a_Name The name of the type.
5274	* @param a_Type0 The type of the 1st argument
5275	* @param a_Arg0 The name of the 1st argument.
5276	* @param a_Type1 The type of the 2nd argument.
5277	* @param a_Arg1 The name of the 2nd argument.
5278	* @param a_Type2 The type of the 3rd argument.
5279	* @param a_Arg2 The name of the 3rd argument.
5280	* @param a_Type3 The type of the 4th argument.
5281	* @param a_Arg3 The name of the 4th argument.
5282	* @param a_Type4 The type of the 5th argument.
5283	* @param a_Arg4 The name of the 5th argument.
5284	*/
5285	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5286	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
5287	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
5288	a_Type3 a_Arg3, a_Type4 a_Arg4))
5289	/**
5290	* For defining a C instruction implementation function taking five extra
5291	* arguments.
5292	*
5293	* @param a_Name The name of the function.
5294	* @param a_Type0 The type of the 1st argument
5295	* @param a_Arg0 The name of the 1st argument.
5296	* @param a_Type1 The type of the 2nd argument.
5297	* @param a_Arg1 The name of the 2nd argument.
5298	* @param a_Type2 The type of the 3rd argument.
5299	* @param a_Arg2 The name of the 3rd argument.
5300	* @param a_Type3 The type of the 4th argument.
5301	* @param a_Arg3 The name of the 4th argument.
5302	* @param a_Type4 The type of the 5th argument.
5303	* @param a_Arg4 The name of the 5th argument.
5304	*/
5305	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5306	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5307	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5308	/**
5309	* Prototype version of IEM_CIMPL_DEF_5.
5310	*/
5311	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5312	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5313	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5314	/**
5315	* For calling a C instruction implementation function taking five extra
5316	* arguments.
5317	*
5318	* This special call macro adds default arguments to the call and allow us to
5319	* change these later.
5320	*
5321	* @param a_fn The name of the function.
5322	* @param a0 The name of the 1st argument.
5323	* @param a1 The name of the 2nd argument.
5324	* @param a2 The name of the 3rd argument.
5325	* @param a3 The name of the 4th argument.
5326	* @param a4 The name of the 5th argument.
5327	*/
5328	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
5329
5330	/** @} */
5331
5332
5333	/** @name Opcode Decoder Function Types.
5334	* @{ */
5335
5336	/** @typedef PFNIEMOP
5337	* Pointer to an opcode decoder function.
5338	*/
5339
5340	/** @def FNIEMOP_DEF
5341	* Define an opcode decoder function.
5342	*
5343	* We're using macors for this so that adding and removing parameters as well as
5344	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
5345	*
5346	* @param a_Name The function name.
5347	*/
5348
5349	/** @typedef PFNIEMOPRM
5350	* Pointer to an opcode decoder function with RM byte.
5351	*/
5352
5353	/** @def FNIEMOPRM_DEF
5354	* Define an opcode decoder function with RM byte.
5355	*
5356	* We're using macors for this so that adding and removing parameters as well as
5357	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
5358	*
5359	* @param a_Name The function name.
5360	*/
5361
5362	#if defined(__GNUC__) && defined(RT_ARCH_X86)
5363	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
5364	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5365	# define FNIEMOP_DEF(a_Name) \
5366	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
5367	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5368	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5369	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5370	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5371
5372	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
5373	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
5374	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5375	# define FNIEMOP_DEF(a_Name) \
5376	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5377	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5378	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5379	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5380	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5381
5382	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5383	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5384	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5385	# define FNIEMOP_DEF(a_Name) \
5386	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
5387	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5388	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5389	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5390	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5391
5392	#else
5393	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5394	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5395	# define FNIEMOP_DEF(a_Name) \
5396	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5397	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5398	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5399	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5400	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5401
5402	#endif
5403	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
5404
5405	/**
5406	* Call an opcode decoder function.
5407	*
5408	* We're using macors for this so that adding and removing parameters can be
5409	* done as we please. See FNIEMOP_DEF.
5410	*/
5411	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
5412
5413	/**
5414	* Call a common opcode decoder function taking one extra argument.
5415	*
5416	* We're using macors for this so that adding and removing parameters can be
5417	* done as we please. See FNIEMOP_DEF_1.
5418	*/
5419	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
5420
5421	/**
5422	* Call a common opcode decoder function taking one extra argument.
5423	*
5424	* We're using macors for this so that adding and removing parameters can be
5425	* done as we please. See FNIEMOP_DEF_1.
5426	*/
5427	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5428	/** @} */
5429
5430
5431	/** @name Misc Helpers
5432	* @{ */
5433
5434	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5435	* due to GCC lacking knowledge about the value range of a switch. */
5436	#if RT_CPLUSPLUS_PREREQ(202000)
5437	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5438	#else
5439	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5440	#endif
5441
5442	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5443	#if RT_CPLUSPLUS_PREREQ(202000)
5444	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5445	#else
5446	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5447	#endif
5448
5449	/**
5450	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5451	* occation.
5452	*/
5453	#ifdef LOG_ENABLED
5454	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5455	do { \
5456	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5457	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5458	} while (0)
5459	#else
5460	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5461	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5462	#endif
5463
5464	/**
5465	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5466	* occation using the supplied logger statement.
5467	*
5468	* @param a_LoggerArgs What to log on failure.
5469	*/
5470	#ifdef LOG_ENABLED
5471	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5472	do { \
5473	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5474	/LogFunc(a_LoggerArgs);/ \
5475	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5476	} while (0)
5477	#else
5478	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5479	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5480	#endif
5481
5482	/**
5483	* Gets the CPU mode (from fExec) as a IEMMODE value.
5484	*
5485	* @returns IEMMODE
5486	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5487	*/
5488	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5489
5490	/**
5491	* Check if we're currently executing in real or virtual 8086 mode.
5492	*
5493	* @returns @c true if it is, @c false if not.
5494	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5495	*/
5496	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5497	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5498
5499	/**
5500	* Check if we're currently executing in virtual 8086 mode.
5501	*
5502	* @returns @c true if it is, @c false if not.
5503	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5504	*/
5505	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5506
5507	/**
5508	* Check if we're currently executing in long mode.
5509	*
5510	* @returns @c true if it is, @c false if not.
5511	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5512	*/
5513	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5514
5515	/**
5516	* Check if we're currently executing in a 16-bit code segment.
5517	*
5518	* @returns @c true if it is, @c false if not.
5519	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5520	*/
5521	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5522
5523	/**
5524	* Check if we're currently executing in a 32-bit code segment.
5525	*
5526	* @returns @c true if it is, @c false if not.
5527	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5528	*/
5529	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5530
5531	/**
5532	* Check if we're currently executing in a 64-bit code segment.
5533	*
5534	* @returns @c true if it is, @c false if not.
5535	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5536	*/
5537	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5538
5539	/**
5540	* Check if we're currently executing in real mode.
5541	*
5542	* @returns @c true if it is, @c false if not.
5543	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5544	*/
5545	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5546
5547	/**
5548	* Gets the current protection level (CPL).
5549	*
5550	* @returns 0..3
5551	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5552	*/
5553	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5554
5555	/**
5556	* Sets the current protection level (CPL).
5557	*
5558	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5559	*/
5560	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5561	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5562
5563	/**
5564	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5565	* @returns PCCPUMFEATURES
5566	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5567	*/
5568	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5569
5570	/**
5571	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5572	* @returns PCCPUMFEATURES
5573	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5574	*/
5575	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5576
5577	/**
5578	* Evaluates to true if we're presenting an Intel CPU to the guest.
5579	*/
5580	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5581
5582	/**
5583	* Evaluates to true if we're presenting an AMD CPU to the guest.
5584	*/
5585	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5586
5587	/**
5588	* Check if the address is canonical.
5589	*/
5590	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5591
5592	/** Checks if the ModR/M byte is in register mode or not. */
5593	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5594	/** Checks if the ModR/M byte is in memory mode or not. */
5595	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5596
5597	/**
5598	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5599	*
5600	* For use during decoding.
5601	*/
5602	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5603	/**
5604	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5605	*
5606	* For use during decoding.
5607	*/
5608	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5609
5610	/**
5611	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5612	*
5613	* For use during decoding.
5614	*/
5615	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5616	/**
5617	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5618	*
5619	* For use during decoding.
5620	*/
5621	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5622
5623	/**
5624	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5625	* register index, with REX.R added in.
5626	*
5627	* For use during decoding.
5628	*
5629	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5630	*/
5631	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5632	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5633	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5634	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5635	/**
5636	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5637	* with REX.B added in.
5638	*
5639	* For use during decoding.
5640	*
5641	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5642	*/
5643	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5644	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5645	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5646	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5647
5648	/**
5649	* Combines the prefix REX and ModR/M byte for passing to
5650	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5651	*
5652	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5653	* The two bits are part of the REG sub-field, which isn't needed in
5654	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5655	*
5656	* For use during decoding/recompiling.
5657	*/
5658	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5659	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5660	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5661	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5662	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5663
5664	/**
5665	* Gets the effective VEX.VVVV value.
5666	*
5667	* The 4th bit is ignored if not 64-bit code.
5668	* @returns effective V-register value.
5669	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5670	*/
5671	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5672	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5673
5674
5675	/**
5676	* Gets the register (reg) part of a the special 4th register byte used by
5677	* vblendvps and vblendvpd.
5678	*
5679	* For use during decoding.
5680	*/
5681	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5682	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5683
5684
5685	/**
5686	* Checks if we're executing inside an AMD-V or VT-x guest.
5687	*/
5688	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5689	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5690	#else
5691	# define IEM_IS_IN_GUEST(a_pVCpu) false
5692	#endif
5693
5694
5695	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5696
5697	/**
5698	* Check if the guest has entered VMX root operation.
5699	*/
5700	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5701
5702	/**
5703	* Check if the guest has entered VMX non-root operation.
5704	*/
5705	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5706	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5707
5708	/**
5709	* Check if the nested-guest has the given Pin-based VM-execution control set.
5710	*/
5711	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5712
5713	/**
5714	* Check if the nested-guest has the given Processor-based VM-execution control set.
5715	*/
5716	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5717
5718	/**
5719	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5720	* control set.
5721	*/
5722	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5723
5724	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5725	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5726
5727	/** Whether a shadow VMCS is present for the given VCPU. */
5728	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5729
5730	/** Gets the VMXON region pointer. */
5731	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5732
5733	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5734	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5735
5736	/** Whether a current VMCS is present for the given VCPU. */
5737	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5738
5739	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5740	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5741	do \
5742	{ \
5743	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5744	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5745	} while (0)
5746
5747	/** Clears any current VMCS for the given VCPU. */
5748	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5749	do \
5750	{ \
5751	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5752	} while (0)
5753
5754	/**
5755	* Invokes the VMX VM-exit handler for an instruction intercept.
5756	*/
5757	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5758	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5759
5760	/**
5761	* Invokes the VMX VM-exit handler for an instruction intercept where the
5762	* instruction provides additional VM-exit information.
5763	*/
5764	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5765	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5766
5767	/**
5768	* Invokes the VMX VM-exit handler for a task switch.
5769	*/
5770	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5771	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5772
5773	/**
5774	* Invokes the VMX VM-exit handler for MWAIT.
5775	*/
5776	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5777	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5778
5779	/**
5780	* Invokes the VMX VM-exit handler for EPT faults.
5781	*/
5782	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5783	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5784
5785	/**
5786	* Invokes the VMX VM-exit handler.
5787	*/
5788	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5789	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5790
5791	#else
5792	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5793	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5794	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5795	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5796	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5797	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5798	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5799	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5800	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5801	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5802	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5803
5804	#endif
5805
5806	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5807	/**
5808	* Checks if we're executing a guest using AMD-V.
5809	*/
5810	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5811	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5812	/**
5813	* Check if an SVM control/instruction intercept is set.
5814	*/
5815	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5816	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5817
5818	/**
5819	* Check if an SVM read CRx intercept is set.
5820	*/
5821	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5822	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5823
5824	/**
5825	* Check if an SVM write CRx intercept is set.
5826	*/
5827	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5828	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5829
5830	/**
5831	* Check if an SVM read DRx intercept is set.
5832	*/
5833	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5834	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5835
5836	/**
5837	* Check if an SVM write DRx intercept is set.
5838	*/
5839	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5840	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5841
5842	/**
5843	* Check if an SVM exception intercept is set.
5844	*/
5845	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5846	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5847
5848	/**
5849	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5850	*/
5851	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5852	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5853
5854	/**
5855	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5856	* corresponding decode assist information.
5857	*/
5858	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5859	do \
5860	{ \
5861	uint64_t uExitInfo1; \
5862	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5863	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5864	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5865	else \
5866	uExitInfo1 = 0; \
5867	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5868	} while (0)
5869
5870	/** Check and handles SVM nested-guest instruction intercept and updates
5871	* NRIP if needed.
5872	*/
5873	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5874	do \
5875	{ \
5876	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5877	{ \
5878	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5879	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5880	} \
5881	} while (0)
5882
5883	/** Checks and handles SVM nested-guest CR0 read intercept. */
5884	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5885	do \
5886	{ \
5887	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5888	{ /* probably likely */ } \
5889	else \
5890	{ \
5891	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5892	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5893	} \
5894	} while (0)
5895
5896	/**
5897	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5898	*/
5899	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5900	do { \
5901	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5902	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5903	} while (0)
5904
5905	#else
5906	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5907	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5908	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5909	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5910	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5911	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5912	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5913	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5914	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5915	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5916	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5917	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5918
5919	#endif
5920
5921	/** @} */
5922
5923	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5924	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5925
5926
5927	/**
5928	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5929	*/
5930	typedef union IEMSELDESC
5931	{
5932	/** The legacy view. */
5933	X86DESC Legacy;
5934	/** The long mode view. */
5935	X86DESC64 Long;
5936	} IEMSELDESC;
5937	/** Pointer to a selector descriptor table entry. */
5938	typedef IEMSELDESC *PIEMSELDESC;
5939
5940	/** @name Raising Exceptions.
5941	* @{ */
5942	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5943	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5944
5945	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5946	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5947	#ifdef IEM_WITH_SETJMP
5948	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5949	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5950	#endif
5951	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5952	#ifdef IEM_WITH_SETJMP
5953	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5954	#endif
5955	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5956	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5957	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5958	#ifdef IEM_WITH_SETJMP
5959	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5960	#endif
5961	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5962	#ifdef IEM_WITH_SETJMP
5963	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5964	#endif
5965	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5966	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5967	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5968	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5969	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5970	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5971	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5972	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5973	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5974	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5975	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5976	#ifdef IEM_WITH_SETJMP
5977	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5978	#endif
5979	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5980	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5981	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5982	#ifdef IEM_WITH_SETJMP
5983	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5984	#endif
5985	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5986	#ifdef IEM_WITH_SETJMP
5987	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5988	#endif
5989	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5990	#ifdef IEM_WITH_SETJMP
5991	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5992	#endif
5993	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5994	#ifdef IEM_WITH_SETJMP
5995	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5996	#endif
5997	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5998	#ifdef IEM_WITH_SETJMP
5999	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6000	#endif
6001	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6002	#ifdef IEM_WITH_SETJMP
6003	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6004	#endif
6005	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6006	#ifdef IEM_WITH_SETJMP
6007	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6008	#endif
6009
6010	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6011	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6012
6013	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
6014	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
6015	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
6016
6017	/**
6018	* Macro for calling iemCImplRaiseDivideError().
6019	*
6020	* This is for things that will _always_ decode to an \#DE, taking the
6021	* recompiler into consideration and everything.
6022	*
6023	* @return Strict VBox status code.
6024	*/
6025	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
6026
6027	/**
6028	* Macro for calling iemCImplRaiseInvalidLockPrefix().
6029	*
6030	* This is for things that will _always_ decode to an \#UD, taking the
6031	* recompiler into consideration and everything.
6032	*
6033	* @return Strict VBox status code.
6034	*/
6035	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
6036
6037	/**
6038	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
6039	*
6040	* This is for things that will _always_ decode to an \#UD, taking the
6041	* recompiler into consideration and everything.
6042	*
6043	* @return Strict VBox status code.
6044	*/
6045	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6046
6047	/**
6048	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
6049	*
6050	* Using this macro means you've got _buggy_ _code_ and are doing things that
6051	* belongs exclusively in IEMAllCImpl.cpp during decoding.
6052	*
6053	* @return Strict VBox status code.
6054	* @see IEMOP_RAISE_INVALID_OPCODE_RET
6055	*/
6056	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6057
6058	/** @} */
6059
6060	/** @name Register Access.
6061	* @{ */
6062	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
6063	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6064	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
6065	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
6066	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6067	/** @} */
6068
6069	/** @name FPU access and helpers.
6070	* @{ */
6071	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6072	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6073	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6074	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6075	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6076	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6077	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6078	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6079	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6080	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6081	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6082	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6083	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6084	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6085	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6086	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6087	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6088	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6089	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6090	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6091	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6092	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6093	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6094	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6095	/** @} */
6096
6097	/** @name SSE+AVX SIMD access and helpers.
6098	* @{ */
6099	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
6100	/** @} */
6101
6102	/** @name Memory access.
6103	* @{ */
6104
6105	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
6106	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
6107	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
6108	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
6109	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
6110	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
6111	* Users include FXSAVE & FXRSTOR. */
6112	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
6113
6114	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
6115	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
6116	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6117	#ifndef IN_RING3
6118	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6119	#endif
6120	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6121	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
6122	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
6123	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6124	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
6125
6126	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
6127	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
6128	#ifdef IEM_WITH_CODE_TLB
6129	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
6130	#else
6131	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
6132	#endif
6133	#ifdef IEM_WITH_SETJMP
6134	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6135	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6136	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6137	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6138	#else
6139	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
6140	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6141	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6142	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6143	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6144	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6145	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6146	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6147	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6148	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6149	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6150	#endif
6151
6152	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6153	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6154	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6155	VBOXSTRICTRC iemMemFetchDataU32NoAc(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6156	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6157	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6158	VBOXSTRICTRC iemMemFetchDataU64NoAc(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6159	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6160	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6161	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6162	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6163	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6164	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6165	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6166	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6167	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6168	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
6169	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
6170	#ifdef IEM_WITH_SETJMP
6171	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6172	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6173	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6174	uint32_t iemMemFetchDataU32NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6175	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6176	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6177	uint64_t iemMemFetchDataU64NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6178	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6179	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6180	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6181	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6182	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6183	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6184	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6185	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6186	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6187	# if 0 /* these are inlined now */
6188	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6189	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6190	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6191	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6192	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6193	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6194	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6195	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6196	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6197	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6198	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6199	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6200	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6201	# endif
6202	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6203	#endif
6204
6205	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6206	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6207	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6208	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6209	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
6210
6211	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
6212	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
6213	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
6214	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
6215	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6216	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6217	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6218	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6219	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6220	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6221	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6222	#ifdef IEM_WITH_SETJMP
6223	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6224	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6225	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6226	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6227	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6228	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6229	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6230	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6231	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6232	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6233	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6234	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6235	#if 0
6236	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6237	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6238	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6239	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6240	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6241	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6242	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6243	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6244	#endif
6245	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6246	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6247	#endif
6248
6249	#ifdef IEM_WITH_SETJMP
6250	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6251	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6252	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6253	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6254	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6255	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6256	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6257	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6258	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6259	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6260	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6261	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6262	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6263	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6264	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6265	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6266	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6267	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6268	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6269	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6270	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6271	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6272	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6273	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6274	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6275	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6276
6277	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6278	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6279	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6280	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6281	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6282	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6283	#endif
6284
6285	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6286	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6287	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
6288	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
6289	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6290	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
6291	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6292	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6293	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6294	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6295	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6296	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6297	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
6298	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
6299	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6300	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
6301	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
6302	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
6303	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6304	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6305	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6306
6307	#ifdef IEM_WITH_SETJMP
6308	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6309	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6310	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6311	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6312	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6313	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6314	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6315
6316	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6317	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6318	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6319	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6320	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6321
6322	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6323	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6324	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6325	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6326
6327	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6328	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6329	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6330	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6331
6332	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6333	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6334	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6335
6336	#endif
6337
6338	/** @} */
6339
6340	/** @name IEMAllCImpl.cpp
6341	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
6342	* @{ */
6343	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6344	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6345	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6346	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
6347	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
6348	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
6349	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
6350	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
6351	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
6352	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6353	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6354	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6355	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
6356	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
6357	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
6358	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
6359	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
6360	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
6361	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
6362	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
6363	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
6364	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
6365	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
6366	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
6367	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
6368	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
6369	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
6370	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
6371	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
6372	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
6373	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
6374	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
6375	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
6376	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
6377	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
6378	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6379	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6380	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6381	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6382	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
6383	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6384	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6385	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
6386	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6387	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6388	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
6389	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6390	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6391	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
6392	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
6393	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
6394	IEM_CIMPL_PROTO_0(iemCImpl_clts);
6395	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
6396	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
6397	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
6398	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
6399	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
6400	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
6401	IEM_CIMPL_PROTO_0(iemCImpl_invd);
6402	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
6403	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
6404	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
6405	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
6406	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
6407	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
6408	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
6409	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6410	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6411	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6412	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6413	IEM_CIMPL_PROTO_0(iemCImpl_cli);
6414	IEM_CIMPL_PROTO_0(iemCImpl_sti);
6415	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
6416	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
6417	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
6418	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
6419	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
6420	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
6421	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
6422	IEM_CIMPL_PROTO_0(iemCImpl_daa);
6423	IEM_CIMPL_PROTO_0(iemCImpl_das);
6424	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
6425	IEM_CIMPL_PROTO_0(iemCImpl_aas);
6426	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
6427	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
6428	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
6429	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
6430	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
6431	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
6432	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6433	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
6434	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6435	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6436	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6437	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6438	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6439	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6440	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6441	IEM_CIMPL_PROTO_2(iemCImpl_vldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6442	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6443	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6444	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6445	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6446	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6447	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6448	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6449	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6450	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6451	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6452	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6453	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6454	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6455	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6456	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6457	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6458	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6459	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6460	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6461	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6462	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6463	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6464	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6465	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6466	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6467	IEM_CIMPL_PROTO_2(iemCImpl_vpgather_worker_xx, uint32_t, u32PackedArgs, uint32_t, u32Disp);
6468
6469	/** @} */
6470
6471	/** @name IEMAllCImplStrInstr.cpp.h
6472	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6473	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6474	* @{ */
6475	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6476	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6477	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6478	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6479	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6480	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6481	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6482	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6483	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6484	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6485	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6486
6487	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6488	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6489	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6490	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6491	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6492	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6493	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6494	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6495	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6496	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6497	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6498
6499	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6500	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6501	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6502	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6503	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6504	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6505	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6506	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6507	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6508	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6509	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6510
6511
6512	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6513	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6514	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6515	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6516	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6517	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6518	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6519	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6520	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6521	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6522	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6523
6524	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6525	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6526	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6527	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6528	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6529	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6530	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6531	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6532	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6533	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6534	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6535
6536	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6537	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6538	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6539	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6540	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6541	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6542	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6543	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6544	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6545	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6546	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6547
6548	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6549	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6550	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6551	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6552	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6553	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6554	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6555	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6556	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6557	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6558	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6559
6560
6561	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6562	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6563	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6564	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6565	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6566	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6567	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6568	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6569	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6570	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6571	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6572
6573	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6574	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6575	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6576	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6577	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6578	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6579	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6580	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6581	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6582	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6583	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6584
6585	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6586	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6587	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6588	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6589	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6590	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6591	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6592	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6593	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6594	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6595	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6596
6597	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6598	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6599	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6600	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6601	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6602	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6603	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6604	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6605	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6606	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6607	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6608	/** @} */
6609
6610	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6611	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6612	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6613	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6614	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6615	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6616	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6617	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6618	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6619	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6620	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6621	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6622	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6623	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6624	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6625	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6626	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6627	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6628	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6629	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6630	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6631	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6632	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6633	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6634	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6635	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6636	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6637	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6638	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6639	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6640	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6641	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6642	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6643	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6644	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6645	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6646	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6647	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6648	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6649	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6650	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6651	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6652	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6653	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6654	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6655	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6656	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6657	#endif
6658
6659	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6660	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6661	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6662	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6663	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6664	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6665	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6666	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6667	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6668	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6669	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6670	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6671	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6672	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6673	#endif
6674
6675	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6676	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6677	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6678
6679	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6680	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6681	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6682	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6683	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6684	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6685	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6686
6687	/*
6688	* Recompiler related stuff.
6689	*/
6690	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6691	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6692	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6693	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6694	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6695	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6696	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6697
6698	DECLHIDDEN(int) iemPollTimers(PVMCC pVM, PVMCPUCC pVCpu) RT_NOEXCEPT;
6699
6700	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6701	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6702	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6703	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6704	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6705	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6706	DECLHIDDEN(PIEMTBALLOCATOR) iemTbAllocatorFreeBulkStart(PVMCPUCC pVCpu);
6707	DECLHIDDEN(void) iemTbAllocatorFreeBulk(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator, PIEMTB pTb);
6708	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6709	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6710	#if defined(VBOX_WITH_IEM_NATIVE_RECOMPILER) && defined(VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING)
6711	DECLHIDDEN(void) iemThreadedSaveTbForProfilingCleanup(PVMCPU pVCpu);
6712	#endif
6713
6714
6715	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6716	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6717	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6718	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6719	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6720	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6721	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6722	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6723
6724	#else
6725	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6726	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6727	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6728	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6729	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6730	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6731	#endif
6732
6733
6734	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6735	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6736
6737	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6738
6739	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6740	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckTimers);
6741	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckTimersAndIrq);
6742	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6743	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6744	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6745
6746	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6747	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6748	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6749
6750	/* Branching: */
6751	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6752	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6753	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6754
6755	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6756	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6757	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6758
6759	/* Natural page crossing: */
6760	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6761	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6762	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6763
6764	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6765	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6766	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6767
6768	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6769	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6770	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6771
6772	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Jump);
6773
6774	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6775	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6776	#ifdef IEM_WITH_INTRA_TB_JUMPS
6777	DECLHIDDEN(int) iemThreadedCompileBackAtFirstInstruction(PVMCPU pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6778	#endif
6779
6780	/* Native recompiler public bits: */
6781
6782	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6783	DECLHIDDEN(void) iemNativeDisassembleTb(PVMCPU pVCpu, PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6784	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6785	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, PIEMNATIVEINSTR *ppaExec,
6786	struct IEMNATIVEPERCHUNKCTX const **ppChunkCtx) RT_NOEXCEPT;
6787	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAllocFromChunk(PVMCPU pVCpu, uint32_t idxChunk, uint32_t cbReq,
6788	PIEMNATIVEINSTR *ppaExec);
6789	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6790	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6791	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6792	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemExecMemGetTbChunkCtx(PVMCPU pVCpu, PCIEMTB pTb);
6793	DECLHIDDEN(int) iemNativeRecompileAttachExecMemChunkCtx(PVMCPU pVCpu, uint32_t idxChunk, struct IEMNATIVEPERCHUNKCTX const **ppCtx);
6794
6795	/** Packed 32-bit argument for iemCImpl_vpgather_worker_xx. */
6796	typedef union IEMGATHERARGS
6797	{
6798	/** Integer view. */
6799	uint32_t u;
6800	/** Bitfield view. */
6801	struct
6802	{
6803	uint32_t iYRegDst : 4; /*< 0 - XMM or YMM register number (destination) /
6804	uint32_t iYRegIdc : 4; /*< 4 - XMM or YMM register number (indices) /
6805	uint32_t iYRegMsk : 4; /*< 8 - XMM or YMM register number (mask) /
6806	uint32_t iGRegBase : 4; /*< 12 - general register number (base ptr) /
6807	uint32_t iScale : 2; /*< 16 - scale factor (1/2/4/8) /
6808	uint32_t enmEffOpSize : 2; /*< 18 - operand size (16/32/64/--) /
6809	uint32_t enmEffAddrMode : 2; /*< 20 - addressing mode (16/32/64/--) /
6810	uint32_t iEffSeg : 3; /*< 22 - effective segment (ES/CS/SS/DS/FS/GS) /
6811	uint32_t fVex256 : 1; /*< 25 - overall instruction width (128/256 bits) /
6812	uint32_t fIdxQword : 1; /*< 26 - individual index width (4/8 bytes) /
6813	uint32_t fValQword : 1; /*< 27 - individual value width (4/8 bytes) /
6814	} s;
6815	} IEMGATHERARGS;
6816	AssertCompileSize(IEMGATHERARGS, sizeof(uint32_t));
6817
6818	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6819
6820
6821	/** @} */
6822
6823	RT_C_DECLS_END
6824
6825	/* ASM-INC: %include "IEMInternalStruct.mac" */
6826
6827	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6828

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 106329

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