IEMInternal.h@ 106054

Last change on this file since 106054 was 105877, checked in by vboxsync, 3 months ago
VMM/IEM: Don't flush PC prior to 64-bit relative jumps, flush it when in the #GP(0) code path. bugref:10720 bugref:10373
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File size: 359.6 KB

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1	/* $Id: IEMInternal.h 105877 2024-08-27 23:17:09Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEM_WITH_ADAPTIVE_TIMER_POLLING
96	* Enables the adaptive timer polling code.
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEM_WITH_ADAPTIVE_TIMER_POLLING
100	#endif
101
102	/** @def IEM_WITH_INTRA_TB_JUMPS
103	* Enables loop-jumps within a TB (currently only to the first call).
104	*/
105	#if defined(DOXYGEN_RUNNING) \|\| 1
106	# define IEM_WITH_INTRA_TB_JUMPS
107	#endif
108
109	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
110	* Enables the delayed PC updating optimization (see @bugref{10373}).
111	*/
112	#if defined(DOXYGEN_RUNNING) \|\| 1
113	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
114	#endif
115	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
116	* Enabled delayed PC updating debugging code.
117	* This is an alternative to the ARM64-only IEMNATIVE_REG_FIXED_PC_DBG. */
118	#if defined(DOXYGEN_RUNNING) \|\| 0
119	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
120	#endif
121
122	/** Enables the SIMD register allocator @bugref{10614}. */
123	#if defined(DOXYGEN_RUNNING) \|\| 1
124	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
125	#endif
126	/** Enables access to even callee saved registers. */
127	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
128
129	#if defined(DOXYGEN_RUNNING) \|\| 1
130	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
131	* Delay the writeback or dirty registers as long as possible. */
132	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
133	#endif
134
135	/** @def IEM_WITH_TLB_STATISTICS
136	* Enables all TLB statistics. */
137	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
138	# define IEM_WITH_TLB_STATISTICS
139	#endif
140
141	/** @def IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
142	* Enable this to use native emitters for certain SIMD FP operations. */
143	#if 1 \|\| defined(DOXYGEN_RUNNING)
144	# define IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
145	#endif
146
147	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
148	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
149	* executing native translation blocks.
150	*
151	* This exploits the fact that we save all non-volatile registers in the TB
152	* prologue and thus just need to do the same as the TB epilogue to get the
153	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
154	* non-volatile (and does something even more crazy for ARM), this probably
155	* won't work reliably on Windows. */
156	#ifdef RT_ARCH_ARM64
157	# ifndef RT_OS_WINDOWS
158	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
159	# endif
160	#endif
161	/* ASM-NOINC-START */
162	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
163	# if !defined(IN_RING3) \
164	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
165	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
166	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
167	# elif defined(RT_OS_WINDOWS)
168	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
169	# endif
170	#endif
171
172
173	/** @def IEM_DO_LONGJMP
174	*
175	* Wrapper around longjmp / throw.
176	*
177	* @param a_pVCpu The CPU handle.
178	* @param a_rc The status code jump back with / throw.
179	*/
180	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
181	# ifdef IEM_WITH_THROW_CATCH
182	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
183	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
184	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
185	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
186	throw int(a_rc); \
187	} while (0)
188	# else
189	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
190	# endif
191	# else
192	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
193	# endif
194	#endif
195
196	/** For use with IEM function that may do a longjmp (when enabled).
197	*
198	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
199	* attribute. So, we indicate that function that may be part of a longjmp may
200	* throw "exceptions" and that the compiler should definitely not generate and
201	* std::terminate calling unwind code.
202	*
203	* Here is one example of this ending in std::terminate:
204	* @code{.txt}
205	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
206	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
207	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
208	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
209	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
210	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
211	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
212	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
213	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
214	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
215	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
216	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
217	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
218	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
219	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
220	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
221	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
222	@endcode
223	*
224	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
225	*/
226	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
227	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
228	#else
229	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
230	#endif
231	/* ASM-NOINC-END */
232
233	#define IEM_IMPLEMENTS_TASKSWITCH
234
235	/** @def IEM_WITH_3DNOW
236	* Includes the 3DNow decoding. */
237	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
238	# ifndef IEM_WITHOUT_3DNOW
239	# define IEM_WITH_3DNOW
240	# endif
241	#endif
242
243	/** @def IEM_WITH_THREE_0F_38
244	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
245	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
246	# ifndef IEM_WITHOUT_THREE_0F_38
247	# define IEM_WITH_THREE_0F_38
248	# endif
249	#endif
250
251	/** @def IEM_WITH_THREE_0F_3A
252	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
253	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
254	# ifndef IEM_WITHOUT_THREE_0F_3A
255	# define IEM_WITH_THREE_0F_3A
256	# endif
257	#endif
258
259	/** @def IEM_WITH_VEX
260	* Includes the VEX decoding. */
261	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
262	# ifndef IEM_WITHOUT_VEX
263	# define IEM_WITH_VEX
264	# endif
265	#endif
266
267	/** @def IEM_CFG_TARGET_CPU
268	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
269	*
270	* By default we allow this to be configured by the user via the
271	* CPUM/GuestCpuName config string, but this comes at a slight cost during
272	* decoding. So, for applications of this code where there is no need to
273	* be dynamic wrt target CPU, just modify this define.
274	*/
275	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
276	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
277	#endif
278
279	//#define IEM_WITH_CODE_TLB // - work in progress
280	//#define IEM_WITH_DATA_TLB // - work in progress
281
282
283	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
284	* Use unaligned accesses instead of elaborate byte assembly. */
285	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
286	# define IEM_USE_UNALIGNED_DATA_ACCESS
287	#endif /ASM-NOINC/
288
289	//#define IEM_LOG_MEMORY_WRITES
290
291
292
293	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
294
295	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
296	/** Instruction statistics. */
297	typedef struct IEMINSTRSTATS
298	{
299	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
300	# include "IEMInstructionStatisticsTmpl.h"
301	# undef IEM_DO_INSTR_STAT
302	} IEMINSTRSTATS;
303	#else
304	struct IEMINSTRSTATS;
305	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
306	#endif
307	/** Pointer to IEM instruction statistics. */
308	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
309
310
311	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
312	* @{ */
313	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
314	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
315	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
316	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
317	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
318	/** Selects the right variant from a_aArray.
319	* pVCpu is implicit in the caller context. */
320	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
321	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
322	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
323	* be used because the host CPU does not support the operation. */
324	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
325	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
326	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
327	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
328	* into the two.
329	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
330	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
331	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
332	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
333	#else
334	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
335	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
336	#endif
337	/** @} */
338
339	/**
340	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
341	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
342	*
343	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
344	* indicator.
345	*
346	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
347	*/
348	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
349	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
350	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
351	#else
352	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
353	#endif
354
355
356	/**
357	* Branch types.
358	*/
359	typedef enum IEMBRANCH
360	{
361	IEMBRANCH_JUMP = 1,
362	IEMBRANCH_CALL,
363	IEMBRANCH_TRAP,
364	IEMBRANCH_SOFTWARE_INT,
365	IEMBRANCH_HARDWARE_INT
366	} IEMBRANCH;
367	AssertCompileSize(IEMBRANCH, 4);
368
369
370	/**
371	* INT instruction types.
372	*/
373	typedef enum IEMINT
374	{
375	/** INT n instruction (opcode 0xcd imm). */
376	IEMINT_INTN = 0,
377	/** Single byte INT3 instruction (opcode 0xcc). */
378	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
379	/** Single byte INTO instruction (opcode 0xce). */
380	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
381	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
382	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
383	} IEMINT;
384	AssertCompileSize(IEMINT, 4);
385
386
387	/**
388	* A FPU result.
389	*/
390	typedef struct IEMFPURESULT
391	{
392	/** The output value. */
393	RTFLOAT80U r80Result;
394	/** The output status. */
395	uint16_t FSW;
396	} IEMFPURESULT;
397	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
398	/** Pointer to a FPU result. */
399	typedef IEMFPURESULT *PIEMFPURESULT;
400	/** Pointer to a const FPU result. */
401	typedef IEMFPURESULT const *PCIEMFPURESULT;
402
403
404	/**
405	* A FPU result consisting of two output values and FSW.
406	*/
407	typedef struct IEMFPURESULTTWO
408	{
409	/** The first output value. */
410	RTFLOAT80U r80Result1;
411	/** The output status. */
412	uint16_t FSW;
413	/** The second output value. */
414	RTFLOAT80U r80Result2;
415	} IEMFPURESULTTWO;
416	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
417	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
418	/** Pointer to a FPU result consisting of two output values and FSW. */
419	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
420	/** Pointer to a const FPU result consisting of two output values and FSW. */
421	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
422
423
424	/**
425	* IEM TLB entry.
426	*
427	* Lookup assembly:
428	* @code{.asm}
429	; Calculate tag.
430	mov rax, [VA]
431	shl rax, 16
432	shr rax, 16 + X86_PAGE_SHIFT
433	or rax, [uTlbRevision]
434
435	; Do indexing.
436	movzx ecx, al
437	lea rcx, [pTlbEntries + rcx]
438
439	; Check tag.
440	cmp [rcx + IEMTLBENTRY.uTag], rax
441	jne .TlbMiss
442
443	; Check access.
444	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
445	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
446	cmp rax, [uTlbPhysRev]
447	jne .TlbMiss
448
449	; Calc address and we're done.
450	mov eax, X86_PAGE_OFFSET_MASK
451	and eax, [VA]
452	or rax, [rcx + IEMTLBENTRY.pMappingR3]
453	%ifdef VBOX_WITH_STATISTICS
454	inc qword [cTlbHits]
455	%endif
456	jmp .Done
457
458	.TlbMiss:
459	mov r8d, ACCESS_FLAGS
460	mov rdx, [VA]
461	mov rcx, [pVCpu]
462	call iemTlbTypeMiss
463	.Done:
464
465	@endcode
466	*
467	*/
468	typedef struct IEMTLBENTRY
469	{
470	/** The TLB entry tag.
471	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
472	* is ASSUMING a virtual address width of 48 bits.
473	*
474	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
475	*
476	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
477	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
478	* revision wraps around though, the tags needs to be zeroed.
479	*
480	* @note Try use SHRD instruction? After seeing
481	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
482	*
483	* @todo This will need to be reorganized for 57-bit wide virtual address and
484	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
485	* have to move the TLB entry versioning entirely to the
486	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
487	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
488	* consumed by PCID and ASID (12 + 6 = 18).
489	*/
490	uint64_t uTag;
491	/** Access flags and physical TLB revision.
492	*
493	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
494	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
495	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
496	* - Bit 3 - pgm phys/virt - not directly writable.
497	* - Bit 4 - pgm phys page - not directly readable.
498	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
499	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
500	* - Bit 7 - tlb entry - pMappingR3 member not valid.
501	* - Bits 63 thru 8 are used for the physical TLB revision number.
502	*
503	* We're using complemented bit meanings here because it makes it easy to check
504	* whether special action is required. For instance a user mode write access
505	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
506	* non-zero result would mean special handling needed because either it wasn't
507	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
508	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
509	* need to check any PTE flag.
510	*/
511	uint64_t fFlagsAndPhysRev;
512	/** The guest physical page address. */
513	uint64_t GCPhys;
514	/** Pointer to the ring-3 mapping. */
515	R3PTRTYPE(uint8_t *) pbMappingR3;
516	#if HC_ARCH_BITS == 32
517	uint32_t u32Padding1;
518	#endif
519	} IEMTLBENTRY;
520	AssertCompileSize(IEMTLBENTRY, 32);
521	/** Pointer to an IEM TLB entry. */
522	typedef IEMTLBENTRY *PIEMTLBENTRY;
523	/** Pointer to a const IEM TLB entry. */
524	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
525
526	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
527	* @{ */
528	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
529	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
530	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
531	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
532	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
533	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
534	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
535	#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /*< Page tables: Large 2 or 4 MiB page (for flushing). /
536	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
537	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
538	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /*< Phys page: Code page. /
539	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
540	/** @} */
541	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
542	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
543	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
544	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
545	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
546	AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
547	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
548	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
549	\| PGMIEMGCPHYS2PTR_F_NO_READ \
550	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
551	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
552	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
553	\| IEMTLBE_F_PHYS_REV )
554
555
556	/** The TLB size (power of two).
557	* We initially chose 256 because that way we can obtain the result directly
558	* from a 8-bit register without an additional AND instruction.
559	* See also @bugref{10687}. */
560	#if defined(RT_ARCH_AMD64)
561	# define IEMTLB_ENTRY_COUNT 256
562	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
563	#else
564	# define IEMTLB_ENTRY_COUNT 8192
565	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
566	#endif
567	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
568
569	/** TLB slot format spec (assumes uint32_t or unsigned value). */
570	#if IEMTLB_ENTRY_COUNT <= 0x100 / 2
571	# define IEMTLB_SLOT_FMT "%02x"
572	#elif IEMTLB_ENTRY_COUNT <= 0x1000 / 2
573	# define IEMTLB_SLOT_FMT "%03x"
574	#elif IEMTLB_ENTRY_COUNT <= 0x10000 / 2
575	# define IEMTLB_SLOT_FMT "%04x"
576	#else
577	# define IEMTLB_SLOT_FMT "%05x"
578	#endif
579
580	/** Enable the large page bitmap TLB optimization.
581	*
582	* The idea here is to avoid scanning the full 32 KB (2MB pages, 2*512 TLB
583	* entries) or 64 KB (4MB pages, 2*1024 TLB entries) worth of TLB entries during
584	* invlpg when large pages are used, and instead just scan 128 or 256 bytes of
585	* the bmLargePage bitmap to determin which TLB entires that might be containing
586	* large pages and actually require checking.
587	*
588	* There is a good posibility of false positives since we currently don't clear
589	* the bitmap when flushing the TLB, but it should help reduce the workload when
590	* the large pages aren't fully loaded into the TLB in their entirity...
591	*/
592	#define IEMTLB_WITH_LARGE_PAGE_BITMAP
593
594	/**
595	* An IEM TLB.
596	*
597	* We've got two of these, one for data and one for instructions.
598	*/
599	typedef struct IEMTLB
600	{
601	/** The non-global TLB revision.
602	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
603	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
604	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
605	* (The revision zero indicates an invalid TLB entry.)
606	*
607	* The initial value is choosen to cause an early wraparound. */
608	uint64_t uTlbRevision;
609	/** The TLB physical address revision - shadow of PGM variable.
610	*
611	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
612	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
613	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
614	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
615	*
616	* The initial value is choosen to cause an early wraparound.
617	*
618	* @note This is placed between the two TLB revisions because we
619	* load it in pair with one or the other on arm64. */
620	uint64_t volatile uTlbPhysRev;
621	/** The global TLB revision.
622	* Same as uTlbRevision, but only increased for global flushes. */
623	uint64_t uTlbRevisionGlobal;
624
625	/** Large page tag range.
626	*
627	* This is used to avoid scanning a large page's worth of TLB entries for each
628	* INVLPG instruction, and only to do so iff we've loaded any and when the
629	* address is in this range. This is kept up to date when we loading new TLB
630	* entries.
631	*/
632	struct LARGEPAGERANGE
633	{
634	/** The lowest large page address tag, UINT64_MAX if none. */
635	uint64_t uFirstTag;
636	/** The highest large page address tag (with offset mask part set), 0 if none. */
637	uint64_t uLastTag;
638	}
639	/** Large page range for non-global pages. */
640	NonGlobalLargePageRange,
641	/** Large page range for global pages. */
642	GlobalLargePageRange;
643	/** Number of non-global entries for large pages loaded since last TLB flush. */
644	uint32_t cTlbNonGlobalLargePageCurLoads;
645	/** Number of global entries for large pages loaded since last TLB flush. */
646	uint32_t cTlbGlobalLargePageCurLoads;
647
648	/* Statistics: */
649
650	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
651	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
652	* not via safe read/write path) calls to iemMemMapJmp. */
653	uint64_t cTlbCoreHits;
654	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
655	* only; data tlb only). */
656	uint64_t cTlbSafeHits;
657	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
658	uint64_t cTlbInlineCodeHits;
659
660	/** TLB misses in IEMAll.cpp code (both).
661	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
662	* not via safe read/write path) calls to iemMemMapJmp. So,
663	* for the data TLB this more like 'other misses', while for the code
664	* TLB is all misses. */
665	uint64_t cTlbCoreMisses;
666	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
667	uint64_t cTlbCoreGlobalLoads;
668	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
669	uint64_t cTlbSafeMisses;
670	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
671	uint64_t cTlbSafeGlobalLoads;
672	/** Safe read path taken (data only). */
673	uint64_t cTlbSafeReadPath;
674	/** Safe write path taken (data only). */
675	uint64_t cTlbSafeWritePath;
676
677	/** @name Details for native code TLB misses.
678	* @note These counts are included in the above counters (cTlbSafeReadPath,
679	* cTlbSafeWritePath, cTlbInlineCodeHits).
680	* @{ */
681	/** TLB misses in native code due to tag mismatch. */
682	STAMCOUNTER cTlbNativeMissTag;
683	/** TLB misses in native code due to flags or physical revision mismatch. */
684	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
685	/** TLB misses in native code due to misaligned access. */
686	STAMCOUNTER cTlbNativeMissAlignment;
687	/** TLB misses in native code due to cross page access. */
688	uint32_t cTlbNativeMissCrossPage;
689	/** TLB misses in native code due to non-canonical address. */
690	uint32_t cTlbNativeMissNonCanonical;
691	/** @} */
692
693	/** Slow read path (code only). */
694	uint32_t cTlbSlowCodeReadPath;
695
696	/** Regular TLB flush count. */
697	uint32_t cTlsFlushes;
698	/** Global TLB flush count. */
699	uint32_t cTlsGlobalFlushes;
700	/** Revision rollovers. */
701	uint32_t cTlbRevisionRollovers;
702	/** Physical revision flushes. */
703	uint32_t cTlbPhysRevFlushes;
704	/** Physical revision rollovers. */
705	uint32_t cTlbPhysRevRollovers;
706
707	/** Number of INVLPG (and similar) operations. */
708	uint32_t cTlbInvlPg;
709	/** Subset of cTlbInvlPg that involved non-global large pages. */
710	uint32_t cTlbInvlPgLargeNonGlobal;
711	/** Subset of cTlbInvlPg that involved global large pages. */
712	uint32_t cTlbInvlPgLargeGlobal;
713
714	uint32_t au32Padding[13];
715
716	/** The TLB entries.
717	* Even entries are for PTE.G=0 and uses uTlbRevision.
718	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
719	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
720	#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
721	/** Bitmap tracking TLB entries for large pages.
722	* This duplicates IEMTLBE_F_PT_LARGE_PAGE for each TLB entry. */
723	uint64_t bmLargePage[IEMTLB_ENTRY_COUNT * 2 / 64];
724	#endif
725	} IEMTLB;
726	AssertCompileSizeAlignment(IEMTLB, 64);
727	#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
728	AssertCompile(IEMTLB_ENTRY_COUNT >= 32 /* bmLargePage ASSUMPTION */);
729	#endif
730	/** The width (in bits) of the address portion of the TLB tag. */
731	#define IEMTLB_TAG_ADDR_WIDTH 36
732	/** IEMTLB::uTlbRevision increment. */
733	#define IEMTLB_REVISION_INCR RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH)
734	/** IEMTLB::uTlbRevision mask. */
735	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH) - 1))
736
737	/** IEMTLB::uTlbPhysRev increment.
738	* @sa IEMTLBE_F_PHYS_REV */
739	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
740	AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
741
742	/**
743	* Calculates the TLB tag for a virtual address but without TLB revision.
744	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
745	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
746	* the clearing of the top 16 bits won't work (if 32-bit
747	* we'll end up with mostly zeros).
748	*/
749	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
750	/**
751	* Converts a TLB tag value into a even TLB index.
752	* @returns Index into IEMTLB::aEntries.
753	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
754	*/
755	#if IEMTLB_ENTRY_COUNT == 256
756	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
757	#else
758	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
759	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
760	#endif
761	/**
762	* Converts a TLB tag value into an even TLB index.
763	* @returns Pointer into IEMTLB::aEntries corresponding to .
764	* @param a_pTlb The TLB.
765	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
766	* IEMTLB_CALC_TAG_NO_REV.
767	*/
768	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
769
770	/** Converts a GC address to an even TLB index. */
771	#define IEMTLB_ADDR_TO_EVEN_INDEX(a_GCPtr) IEMTLB_TAG_TO_EVEN_INDEX(IEMTLB_CALC_TAG_NO_REV(a_GCPtr))
772
773
774	/** @def IEM_WITH_TLB_TRACE
775	* Enables the TLB tracing.
776	* Adjust buffer size in IEMR3Init. */
777	#if defined(DOXYGEN_RUNNING) \|\| 0
778	# define IEM_WITH_TLB_TRACE
779	#endif
780
781	#ifdef IEM_WITH_TLB_TRACE
782
783	/** TLB trace entry types. */
784	typedef enum : uint8_t
785	{
786	kIemTlbTraceType_Invalid,
787	kIemTlbTraceType_InvlPg,
788	kIemTlbTraceType_EvictSlot,
789	kIemTlbTraceType_LargeEvictSlot,
790	kIemTlbTraceType_LargeScan,
791	kIemTlbTraceType_Flush,
792	kIemTlbTraceType_FlushGlobal,
793	kIemTlbTraceType_Load,
794	kIemTlbTraceType_LoadGlobal,
795	kIemTlbTraceType_Load_Cr0,
796	kIemTlbTraceType_Load_Cr3,
797	kIemTlbTraceType_Load_Cr4,
798	kIemTlbTraceType_Load_Efer,
799	kIemTlbTraceType_Irq,
800	kIemTlbTraceType_Xcpt,
801	kIemTlbTraceType_IRet,
802	kIemTlbTraceType_Tb_Compile,
803	kIemTlbTraceType_Tb_Exec_Threaded,
804	kIemTlbTraceType_Tb_Exec_Native,
805	kIemTlbTraceType_User0,
806	kIemTlbTraceType_User1,
807	kIemTlbTraceType_User2,
808	kIemTlbTraceType_User3,
809	} IEMTLBTRACETYPE;
810
811	/** TLB trace entry. */
812	typedef struct IEMTLBTRACEENTRY
813	{
814	/** The flattened RIP for the event. */
815	uint64_t rip;
816	/** The event type. */
817	IEMTLBTRACETYPE enmType;
818	/** Byte parameter - typically used as 'bool fDataTlb'. */
819	uint8_t bParam;
820	/** 16-bit parameter value. */
821	uint16_t u16Param;
822	/** 32-bit parameter value. */
823	uint32_t u32Param;
824	/** 64-bit parameter value. */
825	uint64_t u64Param;
826	/** 64-bit parameter value. */
827	uint64_t u64Param2;
828	} IEMTLBTRACEENTRY;
829	AssertCompileSize(IEMTLBTRACEENTRY, 32);
830	/** Pointer to a TLB trace entry. */
831	typedef IEMTLBTRACEENTRY *PIEMTLBTRACEENTRY;
832	/** Pointer to a const TLB trace entry. */
833	typedef IEMTLBTRACEENTRY const *PCIEMTLBTRACEENTRY;
834	#endif /* !IEM_WITH_TLB_TRACE */
835
836	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
837	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) \
838	iemTlbTrace(a_pVCpu, kIemTlbTraceType_InvlPg, a_GCPtr)
839	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
840	iemTlbTrace(a_pVCpu, kIemTlbTraceType_EvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
841	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
842	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeEvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
843	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) \
844	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeScan, 0, 0, a_fDataTlb, (uint8_t)a_fGlobal \| ((uint8_t)a_fNonGlobal << 1))
845	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) \
846	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Flush, a_uRev, 0, a_fDataTlb)
847	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) \
848	iemTlbTrace(a_pVCpu, kIemTlbTraceType_FlushGlobal, a_uRev, a_uGRev, a_fDataTlb)
849	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
850	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
851	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
852	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LoadGlobal, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
853	#else
854	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) do { } while (0)
855	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
856	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
857	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) do { } while (0)
858	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) do { } while (0)
859	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) do { } while (0)
860	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
861	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
862	#endif
863
864	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
865	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr0, a_uNew, a_uOld)
866	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr3, a_uNew, a_uOld)
867	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr4, a_uNew, a_uOld)
868	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Efer, a_uNew, a_uOld)
869	#else
870	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) do { } while (0)
871	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) do { } while (0)
872	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) do { } while (0)
873	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) do { } while (0)
874	#endif
875
876	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
877	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) \
878	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Irq, a_fEFlags, 0, a_uVector, a_fFlags)
879	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) \
880	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Xcpt, a_uErr, a_uCr2, a_uVector, a_fFlags)
881	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) \
882	iemTlbTrace(a_pVCpu, kIemTlbTraceType_IRet, a_uRetRip, a_fEFlags, 0, a_uRetCs)
883	#else
884	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) do { } while (0)
885	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) do { } while (0)
886	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) do { } while (0)
887	#endif
888
889	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
890	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) \
891	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Compile, a_GCPhysPc)
892	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) \
893	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Threaded, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
894	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) \
895	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Native, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
896	#else
897	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) do { } while (0)
898	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) do { } while (0)
899	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) do { } while (0)
900	#endif
901
902	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
903	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
904	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User0, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
905	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
906	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User1, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
907	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
908	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User2, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
909	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
910	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User3, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
911	#else
912	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
913	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
914	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
915	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
916	#endif
917
918
919	/** @name IEM_MC_F_XXX - MC block flags/clues.
920	* @todo Merge with IEM_CIMPL_F_XXX
921	* @{ */
922	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
923	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
924	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
925	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
926	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
927	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
928	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
929	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
930	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
931	#define IEM_MC_F_64BIT RT_BIT_32(6)
932	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
933	/** This is set by IEMAllN8vePython.py to indicate a variation without the
934	* flags-clearing-and-checking, when there is also a variation with that.
935	* @note Do not use this manully, it's only for python and for testing in
936	* the native recompiler! */
937	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
938	/** @} */
939
940	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
941	*
942	* These clues are mainly for the recompiler, so that it can emit correct code.
943	*
944	* They are processed by the python script and which also automatically
945	* calculates flags for MC blocks based on the statements, extending the use of
946	* these flags to describe MC block behavior to the recompiler core. The python
947	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
948	* error checking purposes. The script emits the necessary fEndTb = true and
949	* similar statements as this reduces compile time a tiny bit.
950	*
951	* @{ */
952	/** Flag set if direct branch, clear if absolute or indirect. */
953	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
954	/** Flag set if indirect branch, clear if direct or relative.
955	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
956	* as well as for return instructions (RET, IRET, RETF). */
957	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
958	/** Flag set if relative branch, clear if absolute or indirect. */
959	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
960	/** Flag set if conditional branch, clear if unconditional. */
961	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
962	/** Flag set if it's a far branch (changes CS). */
963	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
964	/** Convenience: Testing any kind of branch. */
965	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
966
967	/** Execution flags may change (IEMCPU::fExec). */
968	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
969	/** May change significant portions of RFLAGS. */
970	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
971	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
972	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
973	/** May trigger interrupt shadowing. */
974	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
975	/** May enable interrupts, so recheck IRQ immediately afterwards executing
976	* the instruction. */
977	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
978	/** May disable interrupts, so recheck IRQ immediately before executing the
979	* instruction. */
980	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
981	/** Convenience: Check for IRQ both before and after an instruction. */
982	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
983	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
984	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
985	/** May modify FPU state.
986	* @todo Not sure if this is useful yet. */
987	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
988	/** REP prefixed instruction which may yield before updating PC.
989	* @todo Not sure if this is useful, REP functions now return non-zero
990	* status if they don't update the PC. */
991	#define IEM_CIMPL_F_REP RT_BIT_32(13)
992	/** I/O instruction.
993	* @todo Not sure if this is useful yet. */
994	#define IEM_CIMPL_F_IO RT_BIT_32(14)
995	/** Force end of TB after the instruction. */
996	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
997	/** Flag set if a branch may also modify the stack (push/pop return address). */
998	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
999	/** Flag set if a branch may also modify the stack (push/pop return address)
1000	* and switch it (load/restore SS:RSP). */
1001	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
1002	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
1003	#define IEM_CIMPL_F_XCPT \
1004	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
1005	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
1006
1007	/** The block calls a C-implementation instruction function with two implicit arguments.
1008	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
1009	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1010	* @note The python scripts will add this if missing. */
1011	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
1012	/** The block calls an ASM-implementation instruction function.
1013	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
1014	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1015	* @note The python scripts will add this if missing. */
1016	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
1017	/** The block calls an ASM-implementation instruction function with an implicit
1018	* X86FXSTATE pointer argument.
1019	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1020	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
1021	* @note The python scripts will add this if missing. */
1022	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
1023	/** The block calls an ASM-implementation instruction function with an implicit
1024	* X86XSAVEAREA pointer argument.
1025	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1026	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1027	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
1028	* @note The python scripts will add this if missing. */
1029	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
1030	/** @} */
1031
1032
1033	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
1034	*
1035	* These flags are set when entering IEM and adjusted as code is executed, such
1036	* that they will always contain the current values as instructions are
1037	* finished.
1038	*
1039	* In recompiled execution mode, (most of) these flags are included in the
1040	* translation block selection key and stored in IEMTB::fFlags alongside the
1041	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
1042	* in IEMCPU::fExec.
1043	*
1044	* @{ */
1045	/** Mode: The block target mode mask. */
1046	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
1047	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
1048	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
1049	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
1050	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
1051	* 32-bit mode (for simplifying most memory accesses). */
1052	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
1053	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
1054	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
1055	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
1056	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
1057
1058	/** X86 Mode: 16-bit on 386 or later. */
1059	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
1060	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
1061	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
1062	/** X86 Mode: 16-bit protected mode on 386 or later. */
1063	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
1064	/** X86 Mode: 16-bit protected mode on 386 or later. */
1065	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
1066	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
1067	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
1068
1069	/** X86 Mode: 32-bit on 386 or later. */
1070	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
1071	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
1072	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
1073	/** X86 Mode: 32-bit protected mode. */
1074	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
1075	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
1076	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
1077
1078	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
1079	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
1080
1081	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
1082	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
1083	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
1084	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
1085
1086	/** Bypass access handlers when set. */
1087	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
1088	/** Have pending hardware instruction breakpoints. */
1089	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
1090	/** Have pending hardware data breakpoints. */
1091	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
1092
1093	/** X86: Have pending hardware I/O breakpoints. */
1094	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
1095	/** X86: Disregard the lock prefix (implied or not) when set. */
1096	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
1097
1098	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
1099	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
1100
1101	/** Caller configurable options. */
1102	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
1103
1104	/** X86: The current protection level (CPL) shift factor. */
1105	#define IEM_F_X86_CPL_SHIFT 8
1106	/** X86: The current protection level (CPL) mask. */
1107	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
1108	/** X86: The current protection level (CPL) shifted mask. */
1109	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
1110
1111	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
1112	#define IEM_F_X86_AC UINT32_C(0x00080000)
1113
1114	/** X86 execution context.
1115	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
1116	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
1117	* mode. */
1118	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
1119	/** X86 context: Plain regular execution context. */
1120	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
1121	/** X86 context: VT-x enabled. */
1122	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
1123	/** X86 context: AMD-V enabled. */
1124	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
1125	/** X86 context: In AMD-V or VT-x guest mode. */
1126	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
1127	/** X86 context: System management mode (SMM). */
1128	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
1129
1130	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1131	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
1132	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
1133	* alread). */
1134
1135	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1136	* iemRegFinishClearingRF() most for most situations
1137	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
1138	* the IEM_F_PENDING_BRK_XXX bits alread). */
1139
1140	/** @} */
1141
1142
1143	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
1144	*
1145	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
1146	* translation block flags. The combined flag mask (subject to
1147	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
1148	*
1149	* @{ */
1150	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
1151	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
1152
1153	/** Type: The block type mask. */
1154	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
1155	/** Type: Purly threaded recompiler (via tables). */
1156	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
1157	/** Type: Native recompilation. */
1158	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
1159
1160	/** Set when we're starting the block in an "interrupt shadow".
1161	* We don't need to distingish between the two types of this mask, thus the one.
1162	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
1163	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
1164	/** Set when we're currently inhibiting NMIs
1165	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
1166	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
1167
1168	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
1169	* we're close the limit before starting a TB, as determined by
1170	* iemGetTbFlagsForCurrentPc(). */
1171	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
1172
1173	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
1174	*
1175	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
1176	* don't implement), because we don't currently generate any context
1177	* specific code - that's all handled in CIMPL functions.
1178	*
1179	* For the threaded recompiler we don't generate any CPL specific code
1180	* either, but the native recompiler does for memory access (saves getting
1181	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
1182	* Since most OSes will not share code between rings, this shouldn't
1183	* have any real effect on TB/memory/recompiling load.
1184	*/
1185	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
1186	/** @} */
1187
1188	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1189	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1190	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
1191	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
1192	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1193	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1194	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
1195	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1196	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1197	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1198	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1199	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
1200	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1201	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1202	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
1203	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1204	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
1205	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1206	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
1207
1208	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1209	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1210	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
1211	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1212	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1213	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
1214	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1215	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1216	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1217	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1218	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1219	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
1220
1221	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
1222	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
1223	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1224
1225	/** Native instruction type for use with the native code generator.
1226	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
1227	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1228	typedef uint8_t IEMNATIVEINSTR;
1229	#else
1230	typedef uint32_t IEMNATIVEINSTR;
1231	#endif
1232	/** Pointer to a native instruction unit. */
1233	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
1234	/** Pointer to a const native instruction unit. */
1235	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
1236
1237	/**
1238	* A call for the threaded call table.
1239	*/
1240	typedef struct IEMTHRDEDCALLENTRY
1241	{
1242	/** The function to call (IEMTHREADEDFUNCS). */
1243	uint16_t enmFunction;
1244
1245	/** Instruction number in the TB (for statistics). */
1246	uint8_t idxInstr;
1247	/** The opcode length. */
1248	uint8_t cbOpcode;
1249	/** Offset into IEMTB::pabOpcodes. */
1250	uint16_t offOpcode;
1251
1252	/** TB lookup table index (7 bits) and large size (1 bits).
1253	*
1254	* The default size is 1 entry, but for indirect calls and returns we set the
1255	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1256	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1257	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1258	*
1259	* By default lookup table entry 0 for a TB is reserved as a fallback for
1260	* calltable entries w/o explicit entreis, so this member will be non-zero if
1261	* there is a lookup entry associated with this call.
1262	*
1263	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1264	*/
1265	uint8_t uTbLookup;
1266
1267	/** Flags - IEMTHREADEDCALLENTRY_F_XXX. */
1268	uint8_t fFlags;
1269
1270	/** Generic parameters. */
1271	uint64_t auParams[3];
1272	} IEMTHRDEDCALLENTRY;
1273	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1274	/** Pointer to a threaded call entry. */
1275	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1276	/** Pointer to a const threaded call entry. */
1277	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1278
1279	/** The number of TB lookup table entries for a large allocation
1280	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1281	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1282	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1283	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1284	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1285	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1286	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1287	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1288	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1289
1290	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1291	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1292
1293
1294	/** The call entry is a jump target. */
1295	#define IEMTHREADEDCALLENTRY_F_JUMP_TARGET UINT8_C(0x01)
1296
1297
1298	/**
1299	* Native IEM TB 'function' typedef.
1300	*
1301	* This will throw/longjmp on occation.
1302	*
1303	* @note AMD64 doesn't have that many non-volatile registers and does sport
1304	* 32-bit address displacments, so we don't need pCtx.
1305	*
1306	* On ARM64 pCtx allows us to directly address the whole register
1307	* context without requiring a separate indexing register holding the
1308	* offset. This saves an instruction loading the offset for each guest
1309	* CPU context access, at the cost of a non-volatile register.
1310	* Fortunately, ARM64 has quite a lot more registers.
1311	*/
1312	typedef
1313	#ifdef RT_ARCH_AMD64
1314	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1315	#else
1316	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1317	#endif
1318	#if RT_CPLUSPLUS_PREREQ(201700)
1319	IEM_NOEXCEPT_MAY_LONGJMP
1320	#endif
1321	;
1322	/** Pointer to a native IEM TB entry point function.
1323	* This will throw/longjmp on occation. */
1324	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1325
1326
1327	/**
1328	* Translation block debug info entry type.
1329	*/
1330	typedef enum IEMTBDBGENTRYTYPE
1331	{
1332	kIemTbDbgEntryType_Invalid = 0,
1333	/** The entry is for marking a native code position.
1334	* Entries following this all apply to this position. */
1335	kIemTbDbgEntryType_NativeOffset,
1336	/** The entry is for a new guest instruction. */
1337	kIemTbDbgEntryType_GuestInstruction,
1338	/** Marks the start of a threaded call. */
1339	kIemTbDbgEntryType_ThreadedCall,
1340	/** Marks the location of a label. */
1341	kIemTbDbgEntryType_Label,
1342	/** Info about a host register shadowing a guest register. */
1343	kIemTbDbgEntryType_GuestRegShadowing,
1344	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1345	/** Info about a host SIMD register shadowing a guest SIMD register. */
1346	kIemTbDbgEntryType_GuestSimdRegShadowing,
1347	#endif
1348	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1349	/** Info about a delayed RIP update. */
1350	kIemTbDbgEntryType_DelayedPcUpdate,
1351	#endif
1352	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1353	/** Info about a shadowed guest register becoming dirty. */
1354	kIemTbDbgEntryType_GuestRegDirty,
1355	/** Info about register writeback/flush oepration. */
1356	kIemTbDbgEntryType_GuestRegWriteback,
1357	#endif
1358	kIemTbDbgEntryType_End
1359	} IEMTBDBGENTRYTYPE;
1360
1361	/**
1362	* Translation block debug info entry.
1363	*/
1364	typedef union IEMTBDBGENTRY
1365	{
1366	/** Plain 32-bit view. */
1367	uint32_t u;
1368
1369	/** Generic view for getting at the type field. */
1370	struct
1371	{
1372	/** IEMTBDBGENTRYTYPE */
1373	uint32_t uType : 4;
1374	uint32_t uTypeSpecific : 28;
1375	} Gen;
1376
1377	struct
1378	{
1379	/** kIemTbDbgEntryType_ThreadedCall1. */
1380	uint32_t uType : 4;
1381	/** Native code offset. */
1382	uint32_t offNative : 28;
1383	} NativeOffset;
1384
1385	struct
1386	{
1387	/** kIemTbDbgEntryType_GuestInstruction. */
1388	uint32_t uType : 4;
1389	uint32_t uUnused : 4;
1390	/** The IEM_F_XXX flags. */
1391	uint32_t fExec : 24;
1392	} GuestInstruction;
1393
1394	struct
1395	{
1396	/* kIemTbDbgEntryType_ThreadedCall. */
1397	uint32_t uType : 4;
1398	/** Set if the call was recompiled to native code, clear if just calling
1399	* threaded function. */
1400	uint32_t fRecompiled : 1;
1401	uint32_t uUnused : 11;
1402	/** The threaded call number (IEMTHREADEDFUNCS). */
1403	uint32_t enmCall : 16;
1404	} ThreadedCall;
1405
1406	struct
1407	{
1408	/* kIemTbDbgEntryType_Label. */
1409	uint32_t uType : 4;
1410	uint32_t uUnused : 4;
1411	/** The label type (IEMNATIVELABELTYPE). */
1412	uint32_t enmLabel : 8;
1413	/** The label data. */
1414	uint32_t uData : 16;
1415	} Label;
1416
1417	struct
1418	{
1419	/* kIemTbDbgEntryType_GuestRegShadowing. */
1420	uint32_t uType : 4;
1421	uint32_t uUnused : 4;
1422	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1423	uint32_t idxGstReg : 8;
1424	/** The host new register number, UINT8_MAX if dropped. */
1425	uint32_t idxHstReg : 8;
1426	/** The previous host register number, UINT8_MAX if new. */
1427	uint32_t idxHstRegPrev : 8;
1428	} GuestRegShadowing;
1429
1430	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1431	struct
1432	{
1433	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1434	uint32_t uType : 4;
1435	uint32_t uUnused : 4;
1436	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1437	uint32_t idxGstSimdReg : 8;
1438	/** The host new register number, UINT8_MAX if dropped. */
1439	uint32_t idxHstSimdReg : 8;
1440	/** The previous host register number, UINT8_MAX if new. */
1441	uint32_t idxHstSimdRegPrev : 8;
1442	} GuestSimdRegShadowing;
1443	#endif
1444
1445	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1446	struct
1447	{
1448	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1449	uint32_t uType : 4;
1450	/** Number of instructions skipped. */
1451	uint32_t cInstrSkipped : 8;
1452	/* The instruction offset added to the program counter. */
1453	int32_t offPc : 20;
1454	} DelayedPcUpdate;
1455	#endif
1456
1457	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1458	struct
1459	{
1460	/* kIemTbDbgEntryType_GuestRegDirty. */
1461	uint32_t uType : 4;
1462	uint32_t uUnused : 11;
1463	/** Flag whether this is about a SIMD (true) or general (false) register. */
1464	uint32_t fSimdReg : 1;
1465	/** The guest register index being marked as dirty. */
1466	uint32_t idxGstReg : 8;
1467	/** The host register number this register is shadowed in .*/
1468	uint32_t idxHstReg : 8;
1469	} GuestRegDirty;
1470
1471	struct
1472	{
1473	/* kIemTbDbgEntryType_GuestRegWriteback. */
1474	uint32_t uType : 4;
1475	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1476	uint32_t fSimdReg : 1;
1477	/** The mask shift. */
1478	uint32_t cShift : 2;
1479	/** The guest register mask being written back. */
1480	uint32_t fGstReg : 25;
1481	} GuestRegWriteback;
1482	#endif
1483
1484	} IEMTBDBGENTRY;
1485	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1486	/** Pointer to a debug info entry. */
1487	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1488	/** Pointer to a const debug info entry. */
1489	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1490
1491	/**
1492	* Translation block debug info.
1493	*/
1494	typedef struct IEMTBDBG
1495	{
1496	/** This is the flat PC corresponding to IEMTB::GCPhysPc. */
1497	RTGCPTR FlatPc;
1498	/** Number of entries in aEntries. */
1499	uint32_t cEntries;
1500	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1501	uint32_t offNativeLast;
1502	/** Debug info entries. */
1503	RT_FLEXIBLE_ARRAY_EXTENSION
1504	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1505	} IEMTBDBG;
1506	/** Pointer to TB debug info. */
1507	typedef IEMTBDBG *PIEMTBDBG;
1508	/** Pointer to const TB debug info. */
1509	typedef IEMTBDBG const *PCIEMTBDBG;
1510
1511
1512	/**
1513	* Translation block.
1514	*
1515	* The current plan is to just keep TBs and associated lookup hash table private
1516	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1517	* avoids using expensive atomic primitives for updating lists and stuff.
1518	*/
1519	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1520	typedef struct IEMTB
1521	{
1522	/** Next block with the same hash table entry. */
1523	struct IEMTB *pNext;
1524	/** Usage counter. */
1525	uint32_t cUsed;
1526	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1527	uint32_t msLastUsed;
1528
1529	/** @name What uniquely identifies the block.
1530	* @{ */
1531	RTGCPHYS GCPhysPc;
1532	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1533	uint32_t fFlags;
1534	union
1535	{
1536	struct
1537	{
1538	/*< Relevant CS X86DESCATTR_XXX bits. /
1539	uint16_t fAttr;
1540	} x86;
1541	};
1542	/** @} */
1543
1544	/** Number of opcode ranges. */
1545	uint8_t cRanges;
1546	/** Statistics: Number of instructions in the block. */
1547	uint8_t cInstructions;
1548
1549	/** Type specific info. */
1550	union
1551	{
1552	struct
1553	{
1554	/** The call sequence table. */
1555	PIEMTHRDEDCALLENTRY paCalls;
1556	/** Number of calls in paCalls. */
1557	uint16_t cCalls;
1558	/** Number of calls allocated. */
1559	uint16_t cAllocated;
1560	} Thrd;
1561	struct
1562	{
1563	/** The native instructions (PFNIEMTBNATIVE). */
1564	PIEMNATIVEINSTR paInstructions;
1565	/** Number of instructions pointed to by paInstructions. */
1566	uint32_t cInstructions;
1567	} Native;
1568	/** Generic view for zeroing when freeing. */
1569	struct
1570	{
1571	uintptr_t uPtr;
1572	uint32_t uData;
1573	} Gen;
1574	};
1575
1576	/** The allocation chunk this TB belongs to. */
1577	uint8_t idxAllocChunk;
1578	/** The number of entries in the lookup table.
1579	* Because we're out of space, the TB lookup table is located before the
1580	* opcodes pointed to by pabOpcodes. */
1581	uint8_t cTbLookupEntries;
1582
1583	/** Number of bytes of opcodes stored in pabOpcodes.
1584	* @todo this field isn't really needed, aRanges keeps the actual info. */
1585	uint16_t cbOpcodes;
1586	/** Pointer to the opcode bytes this block was recompiled from.
1587	* This also points to the TB lookup table, which starts cTbLookupEntries
1588	* entries before the opcodes (we don't have room atm for another point). */
1589	uint8_t *pabOpcodes;
1590
1591	union
1592	{
1593	/** Native recompilation debug info if enabled.
1594	* This is only generated by the native recompiler. */
1595	PIEMTBDBG pDbgInfo;
1596	/** For threaded TBs and natives when debug info is disabled, this is the flat
1597	* PC corresponding to GCPhysPc. */
1598	RTGCPTR FlatPc;
1599	};
1600
1601	/* --- 64 byte cache line end --- */
1602
1603	/** Opcode ranges.
1604	*
1605	* The opcode checkers and maybe TLB loading functions will use this to figure
1606	* out what to do. The parameter will specify an entry and the opcode offset to
1607	* start at and the minimum number of bytes to verify (instruction length).
1608	*
1609	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1610	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1611	* code TLB (must have a valid entry for that address) and scan the ranges to
1612	* locate the corresponding opcodes. Probably.
1613	*/
1614	struct IEMTBOPCODERANGE
1615	{
1616	/** Offset within pabOpcodes. */
1617	uint16_t offOpcodes;
1618	/** Number of bytes. */
1619	uint16_t cbOpcodes;
1620	/** The page offset. */
1621	RT_GCC_EXTENSION
1622	uint16_t offPhysPage : 12;
1623	/** Unused bits. */
1624	RT_GCC_EXTENSION
1625	uint16_t u2Unused : 2;
1626	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1627	RT_GCC_EXTENSION
1628	uint16_t idxPhysPage : 2;
1629	} aRanges[8];
1630
1631	/** Physical pages that this TB covers.
1632	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1633	RTGCPHYS aGCPhysPages[2];
1634	} IEMTB;
1635	#pragma pack()
1636	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1637	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1638	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1639	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1640	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1641	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1642	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1643	#if 1
1644	AssertCompileSize(IEMTB, 128);
1645	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1646	#else
1647	AssertCompileSize(IEMTB, 168);
1648	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1649	#endif
1650
1651	/** Pointer to a translation block. */
1652	typedef IEMTB *PIEMTB;
1653	/** Pointer to a const translation block. */
1654	typedef IEMTB const *PCIEMTB;
1655
1656	/** Gets address of the given TB lookup table entry. */
1657	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1658	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1659
1660	/**
1661	* Gets the physical address for a TB opcode range.
1662	*/
1663	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1664	{
1665	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1666	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1667	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1668	if (idxPage == 0)
1669	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1670	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1671	return pTb->aGCPhysPages[idxPage - 1];
1672	}
1673
1674
1675	/**
1676	* A chunk of memory in the TB allocator.
1677	*/
1678	typedef struct IEMTBCHUNK
1679	{
1680	/** Pointer to the translation blocks in this chunk. */
1681	PIEMTB paTbs;
1682	#ifdef IN_RING0
1683	/** Allocation handle. */
1684	RTR0MEMOBJ hMemObj;
1685	#endif
1686	} IEMTBCHUNK;
1687
1688	/**
1689	* A per-CPU translation block allocator.
1690	*
1691	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1692	* the length of the collision list, and of course also for cache line alignment
1693	* reasons, the TBs must be allocated with at least 64-byte alignment.
1694	* Memory is there therefore allocated using one of the page aligned allocators.
1695	*
1696	*
1697	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1698	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1699	* that enables us to quickly calculate the allocation bitmap position when
1700	* freeing the translation block.
1701	*/
1702	typedef struct IEMTBALLOCATOR
1703	{
1704	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1705	uint32_t uMagic;
1706
1707	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1708	/** Mask corresponding to cTbsPerChunk - 1. */
1709	uint32_t fChunkMask;
1710	/** Shift count corresponding to cTbsPerChunk. */
1711	uint8_t cChunkShift;
1712	#else
1713	uint32_t uUnused;
1714	uint8_t bUnused;
1715	#endif
1716	/** Number of chunks we're allowed to allocate. */
1717	uint8_t cMaxChunks;
1718	/** Number of chunks currently populated. */
1719	uint16_t cAllocatedChunks;
1720	/** Number of translation blocks per chunk. */
1721	uint32_t cTbsPerChunk;
1722	/** Chunk size. */
1723	uint32_t cbPerChunk;
1724
1725	/** The maximum number of TBs. */
1726	uint32_t cMaxTbs;
1727	/** Total number of TBs in the populated chunks.
1728	* (cAllocatedChunks * cTbsPerChunk) */
1729	uint32_t cTotalTbs;
1730	/** The current number of TBs in use.
1731	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1732	uint32_t cInUseTbs;
1733	/** Statistics: Number of the cInUseTbs that are native ones. */
1734	uint32_t cNativeTbs;
1735	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1736	uint32_t cThreadedTbs;
1737
1738	/** Where to start pruning TBs from when we're out.
1739	* See iemTbAllocatorAllocSlow for details. */
1740	uint32_t iPruneFrom;
1741	/** Where to start pruning native TBs from when we're out of executable memory.
1742	* See iemTbAllocatorFreeupNativeSpace for details. */
1743	uint32_t iPruneNativeFrom;
1744	uint64_t u64Padding;
1745
1746	/** Statistics: Number of TB allocation calls. */
1747	STAMCOUNTER StatAllocs;
1748	/** Statistics: Number of TB free calls. */
1749	STAMCOUNTER StatFrees;
1750	/** Statistics: Time spend pruning. */
1751	STAMPROFILE StatPrune;
1752	/** Statistics: Time spend pruning native TBs. */
1753	STAMPROFILE StatPruneNative;
1754
1755	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1756	PIEMTB pDelayedFreeHead;
1757	/* Head of the list of free TBs. */
1758	PIEMTB pTbsFreeHead;
1759
1760	/** Allocation chunks. */
1761	IEMTBCHUNK aChunks[256];
1762	} IEMTBALLOCATOR;
1763	/** Pointer to a TB allocator. */
1764	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1765
1766	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1767	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1768
1769
1770	/**
1771	* A per-CPU translation block cache (hash table).
1772	*
1773	* The hash table is allocated once during IEM initialization and size double
1774	* the max TB count, rounded up to the nearest power of two (so we can use and
1775	* AND mask rather than a rest division when hashing).
1776	*/
1777	typedef struct IEMTBCACHE
1778	{
1779	/** Magic value (IEMTBCACHE_MAGIC). */
1780	uint32_t uMagic;
1781	/** Size of the hash table. This is a power of two. */
1782	uint32_t cHash;
1783	/** The mask corresponding to cHash. */
1784	uint32_t uHashMask;
1785	uint32_t uPadding;
1786
1787	/** @name Statistics
1788	* @{ */
1789	/** Number of collisions ever. */
1790	STAMCOUNTER cCollisions;
1791
1792	/** Statistics: Number of TB lookup misses. */
1793	STAMCOUNTER cLookupMisses;
1794	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1795	STAMCOUNTER cLookupHits;
1796	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1797	STAMCOUNTER cLookupHitsViaTbLookupTable;
1798	STAMCOUNTER auPadding2[2];
1799	/** Statistics: Collision list length pruning. */
1800	STAMPROFILE StatPrune;
1801	/** @} */
1802
1803	/** The hash table itself.
1804	* @note The lower 6 bits of the pointer is used for keeping the collision
1805	* list length, so we can take action when it grows too long.
1806	* This works because TBs are allocated using a 64 byte (or
1807	* higher) alignment from page aligned chunks of memory, so the lower
1808	* 6 bits of the address will always be zero.
1809	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1810	*/
1811	RT_FLEXIBLE_ARRAY_EXTENSION
1812	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1813	} IEMTBCACHE;
1814	/** Pointer to a per-CPU translation block cahce. */
1815	typedef IEMTBCACHE *PIEMTBCACHE;
1816
1817	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1818	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1819
1820	/** The collision count mask for IEMTBCACHE::apHash entries. */
1821	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1822	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1823	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1824	/** Combine a TB pointer and a collision list length into a value for an
1825	* IEMTBCACHE::apHash entry. */
1826	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1827	/** Combine a TB pointer and a collision list length into a value for an
1828	* IEMTBCACHE::apHash entry. */
1829	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1830	/** Combine a TB pointer and a collision list length into a value for an
1831	* IEMTBCACHE::apHash entry. */
1832	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1833
1834	/**
1835	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1836	*/
1837	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1838	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1839
1840	/**
1841	* Calculates the hash table slot for a TB from physical PC address and TB
1842	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1843	*/
1844	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1845	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1846
1847
1848	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1849	*
1850	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1851	*
1852	* @{ */
1853	/** Value if no branching happened recently. */
1854	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1855	/** Flag set if direct branch, clear if absolute or indirect. */
1856	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1857	/** Flag set if indirect branch, clear if direct or relative. */
1858	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1859	/** Flag set if relative branch, clear if absolute or indirect. */
1860	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1861	/** Flag set if conditional branch, clear if unconditional. */
1862	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1863	/** Flag set if it's a far branch. */
1864	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1865	/** Flag set if the stack pointer is modified. */
1866	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1867	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1868	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1869	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1870	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1871	/** @} */
1872
1873
1874	/**
1875	* The per-CPU IEM state.
1876	*/
1877	typedef struct IEMCPU
1878	{
1879	/** Info status code that needs to be propagated to the IEM caller.
1880	* This cannot be passed internally, as it would complicate all success
1881	* checks within the interpreter making the code larger and almost impossible
1882	* to get right. Instead, we'll store status codes to pass on here. Each
1883	* source of these codes will perform appropriate sanity checks. */
1884	int32_t rcPassUp; /* 0x00 */
1885	/** Execution flag, IEM_F_XXX. */
1886	uint32_t fExec; /* 0x04 */
1887
1888	/** @name Decoder state.
1889	* @{ */
1890	#ifdef IEM_WITH_CODE_TLB
1891	/** The offset of the next instruction byte. */
1892	uint32_t offInstrNextByte; /* 0x08 */
1893	/** The number of bytes available at pbInstrBuf for the current instruction.
1894	* This takes the max opcode length into account so that doesn't need to be
1895	* checked separately. */
1896	uint32_t cbInstrBuf; /* 0x0c */
1897	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1898	* This can be NULL if the page isn't mappable for some reason, in which
1899	* case we'll do fallback stuff.
1900	*
1901	* If we're executing an instruction from a user specified buffer,
1902	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1903	* aligned pointer but pointer to the user data.
1904	*
1905	* For instructions crossing pages, this will start on the first page and be
1906	* advanced to the next page by the time we've decoded the instruction. This
1907	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1908	*/
1909	uint8_t const pbInstrBuf; / 0x10 */
1910	# if ARCH_BITS == 32
1911	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1912	# endif
1913	/** The program counter corresponding to pbInstrBuf.
1914	* This is set to a non-canonical address when we need to invalidate it. */
1915	uint64_t uInstrBufPc; /* 0x18 */
1916	/** The guest physical address corresponding to pbInstrBuf. */
1917	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1918	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1919	* This takes the CS segment limit into account.
1920	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1921	uint16_t cbInstrBufTotal; /* 0x28 */
1922	/** Offset into pbInstrBuf of the first byte of the current instruction.
1923	* Can be negative to efficiently handle cross page instructions. */
1924	int16_t offCurInstrStart; /* 0x2a */
1925
1926	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1927	/** The prefix mask (IEM_OP_PRF_XXX). */
1928	uint32_t fPrefixes; /* 0x2c */
1929	/** The extra REX ModR/M register field bit (REX.R << 3). */
1930	uint8_t uRexReg; /* 0x30 */
1931	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1932	* (REX.B << 3). */
1933	uint8_t uRexB; /* 0x31 */
1934	/** The extra REX SIB index field bit (REX.X << 3). */
1935	uint8_t uRexIndex; /* 0x32 */
1936
1937	/** The effective segment register (X86_SREG_XXX). */
1938	uint8_t iEffSeg; /* 0x33 */
1939
1940	/** The offset of the ModR/M byte relative to the start of the instruction. */
1941	uint8_t offModRm; /* 0x34 */
1942
1943	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1944	/** The current offset into abOpcode. */
1945	uint8_t offOpcode; /* 0x35 */
1946	# else
1947	uint8_t bUnused; /* 0x35 */
1948	# endif
1949	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1950	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1951	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1952
1953	#else /* !IEM_WITH_CODE_TLB */
1954	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1955	/** The size of what has currently been fetched into abOpcode. */
1956	uint8_t cbOpcode; /* 0x08 */
1957	/** The current offset into abOpcode. */
1958	uint8_t offOpcode; /* 0x09 */
1959	/** The offset of the ModR/M byte relative to the start of the instruction. */
1960	uint8_t offModRm; /* 0x0a */
1961
1962	/** The effective segment register (X86_SREG_XXX). */
1963	uint8_t iEffSeg; /* 0x0b */
1964
1965	/** The prefix mask (IEM_OP_PRF_XXX). */
1966	uint32_t fPrefixes; /* 0x0c */
1967	/** The extra REX ModR/M register field bit (REX.R << 3). */
1968	uint8_t uRexReg; /* 0x10 */
1969	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1970	* (REX.B << 3). */
1971	uint8_t uRexB; /* 0x11 */
1972	/** The extra REX SIB index field bit (REX.X << 3). */
1973	uint8_t uRexIndex; /* 0x12 */
1974
1975	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1976	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1977	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1978	#endif /* !IEM_WITH_CODE_TLB */
1979
1980	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1981	/** The effective operand mode. */
1982	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1983	/** The default addressing mode. */
1984	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1985	/** The effective addressing mode. */
1986	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1987	/** The default operand mode. */
1988	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1989
1990	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1991	uint8_t idxPrefix; /* 0x3a, 0x17 */
1992	/** 3rd VEX/EVEX/XOP register.
1993	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1994	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1995	/** The VEX/EVEX/XOP length field. */
1996	uint8_t uVexLength; /* 0x3c, 0x19 */
1997	/** Additional EVEX stuff. */
1998	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1999
2000	# ifndef IEM_WITH_CODE_TLB
2001	/** Explicit alignment padding. */
2002	uint8_t abAlignment2a[1]; /* 0x1b */
2003	# endif
2004	/** The FPU opcode (FOP). */
2005	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
2006	# ifndef IEM_WITH_CODE_TLB
2007	/** Explicit alignment padding. */
2008	uint8_t abAlignment2b[2]; /* 0x1e */
2009	# endif
2010
2011	/** The opcode bytes. */
2012	uint8_t abOpcode[15]; /* 0x40, 0x20 */
2013	/** Explicit alignment padding. */
2014	# ifdef IEM_WITH_CODE_TLB
2015	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
2016	# else
2017	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
2018	# endif
2019
2020	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
2021	# ifdef IEM_WITH_CODE_TLB
2022	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
2023	# else
2024	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
2025	# endif
2026	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
2027	/** @} */
2028
2029
2030	/** The number of active guest memory mappings. */
2031	uint8_t cActiveMappings; /* 0x4f, 0x4f */
2032
2033	/** Records for tracking guest memory mappings. */
2034	struct
2035	{
2036	/** The address of the mapped bytes. */
2037	R3R0PTRTYPE(void *) pv;
2038	/** The access flags (IEM_ACCESS_XXX).
2039	* IEM_ACCESS_INVALID if the entry is unused. */
2040	uint32_t fAccess;
2041	#if HC_ARCH_BITS == 64
2042	uint32_t u32Alignment4; /*< Alignment padding. /
2043	#endif
2044	} aMemMappings[3]; /* 0x50 LB 0x30 */
2045
2046	/** Locking records for the mapped memory. */
2047	union
2048	{
2049	PGMPAGEMAPLOCK Lock;
2050	uint64_t au64Padding[2];
2051	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
2052
2053	/** Bounce buffer info.
2054	* This runs in parallel to aMemMappings. */
2055	struct
2056	{
2057	/** The physical address of the first byte. */
2058	RTGCPHYS GCPhysFirst;
2059	/** The physical address of the second page. */
2060	RTGCPHYS GCPhysSecond;
2061	/** The number of bytes in the first page. */
2062	uint16_t cbFirst;
2063	/** The number of bytes in the second page. */
2064	uint16_t cbSecond;
2065	/** Whether it's unassigned memory. */
2066	bool fUnassigned;
2067	/** Explicit alignment padding. */
2068	bool afAlignment5[3];
2069	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
2070
2071	/** The flags of the current exception / interrupt. */
2072	uint32_t fCurXcpt; /* 0xf8 */
2073	/** The current exception / interrupt. */
2074	uint8_t uCurXcpt; /* 0xfc */
2075	/** Exception / interrupt recursion depth. */
2076	int8_t cXcptRecursions; /* 0xfb */
2077
2078	/** The next unused mapping index.
2079	* @todo try find room for this up with cActiveMappings. */
2080	uint8_t iNextMapping; /* 0xfd */
2081	uint8_t abAlignment7[1];
2082
2083	/** Bounce buffer storage.
2084	* This runs in parallel to aMemMappings and aMemBbMappings. */
2085	struct
2086	{
2087	uint8_t ab[512];
2088	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
2089
2090
2091	/** Pointer set jump buffer - ring-3 context. */
2092	R3PTRTYPE(jmp_buf *) pJmpBufR3;
2093	/** Pointer set jump buffer - ring-0 context. */
2094	R0PTRTYPE(jmp_buf *) pJmpBufR0;
2095
2096	/** @todo Should move this near @a fCurXcpt later. */
2097	/** The CR2 for the current exception / interrupt. */
2098	uint64_t uCurXcptCr2;
2099	/** The error code for the current exception / interrupt. */
2100	uint32_t uCurXcptErr;
2101
2102	/** @name Statistics
2103	* @{ */
2104	/** The number of instructions we've executed. */
2105	uint32_t cInstructions;
2106	/** The number of potential exits. */
2107	uint32_t cPotentialExits;
2108	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
2109	* This may contain uncommitted writes. */
2110	uint32_t cbWritten;
2111	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
2112	uint32_t cRetInstrNotImplemented;
2113	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
2114	uint32_t cRetAspectNotImplemented;
2115	/** Counts informational statuses returned (other than VINF_SUCCESS). */
2116	uint32_t cRetInfStatuses;
2117	/** Counts other error statuses returned. */
2118	uint32_t cRetErrStatuses;
2119	/** Number of times rcPassUp has been used. */
2120	uint32_t cRetPassUpStatus;
2121	/** Number of times RZ left with instruction commit pending for ring-3. */
2122	uint32_t cPendingCommit;
2123	/** Number of misaligned (host sense) atomic instruction accesses. */
2124	uint32_t cMisalignedAtomics;
2125	/** Number of long jumps. */
2126	uint32_t cLongJumps;
2127	/** @} */
2128
2129	/** @name Target CPU information.
2130	* @{ */
2131	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
2132	/** The target CPU. */
2133	uint8_t uTargetCpu;
2134	#else
2135	uint8_t bTargetCpuPadding;
2136	#endif
2137	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
2138	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
2139	* native host support and the 2nd for when there is.
2140	*
2141	* The two values are typically indexed by a g_CpumHostFeatures bit.
2142	*
2143	* This is for instance used for the BSF & BSR instructions where AMD and
2144	* Intel CPUs produce different EFLAGS. */
2145	uint8_t aidxTargetCpuEflFlavour[2];
2146
2147	/** The CPU vendor. */
2148	CPUMCPUVENDOR enmCpuVendor;
2149	/** @} */
2150
2151	/** @name Host CPU information.
2152	* @{ */
2153	/** The CPU vendor. */
2154	CPUMCPUVENDOR enmHostCpuVendor;
2155	/** @} */
2156
2157	/** Counts RDMSR \#GP(0) LogRel(). */
2158	uint8_t cLogRelRdMsr;
2159	/** Counts WRMSR \#GP(0) LogRel(). */
2160	uint8_t cLogRelWrMsr;
2161	/** Alignment padding. */
2162	uint8_t abAlignment9[42];
2163
2164
2165	/** @name Recompiled Exection
2166	* @{ */
2167	/** Pointer to the current translation block.
2168	* This can either be one being executed or one being compiled. */
2169	R3PTRTYPE(PIEMTB) pCurTbR3;
2170	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
2171	/** Frame pointer for the last native TB to execute. */
2172	R3PTRTYPE(void *) pvTbFramePointerR3;
2173	#else
2174	R3PTRTYPE(void *) pvUnusedR3;
2175	#endif
2176	#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
2177	/** The saved host floating point control register (MXCSR on x86, FPCR on arm64)
2178	* needing restore when the TB finished, IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED indicates the TB
2179	* didn't modify it so we don't need to restore it. */
2180	# ifdef RT_ARCH_AMD64
2181	uint32_t uRegFpCtrl;
2182	/** Temporary copy of MXCSR for stmxcsr/ldmxcsr (so we don't have to fiddle with stack pointers). */
2183	uint32_t uRegMxcsrTmp;
2184	# elif defined(RT_ARCH_ARM64)
2185	uint64_t uRegFpCtrl;
2186	# else
2187	# error "Port me"
2188	# endif
2189	#else
2190	uint64_t u64Unused;
2191	#endif
2192	/** Pointer to the ring-3 TB cache for this EMT. */
2193	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
2194	/** Pointer to the ring-3 TB lookup entry.
2195	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
2196	* entry, thus it can always safely be used w/o NULL checking. */
2197	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
2198	#if 0 /* unused */
2199	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
2200	* The TBs are based on physical addresses, so this is needed to correleated
2201	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
2202	uint64_t uCurTbStartPc;
2203	#endif
2204
2205	/** Number of threaded TBs executed. */
2206	uint64_t cTbExecThreaded;
2207	/** Number of native TBs executed. */
2208	uint64_t cTbExecNative;
2209
2210	/** The number of IRQ/FF checks till the next timer poll call. */
2211	uint32_t cTbsTillNextTimerPoll;
2212	/** The virtual sync time at the last timer poll call in milliseconds. */
2213	uint32_t msRecompilerPollNow;
2214	/** The virtual sync time at the last timer poll call in nanoseconds. */
2215	uint64_t nsRecompilerPollNow;
2216	/** The previous cTbsTillNextTimerPoll value. */
2217	uint32_t cTbsTillNextTimerPollPrev;
2218
2219	/** The current instruction number in a native TB.
2220	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
2221	* and will be picked up by the TB execution loop. Only used when
2222	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
2223	uint8_t idxTbCurInstr;
2224	/** @} */
2225
2226	/** @name Recompilation
2227	* @{ */
2228	/** Whether we need to check the opcode bytes for the current instruction.
2229	* This is set by a previous instruction if it modified memory or similar. */
2230	bool fTbCheckOpcodes;
2231	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
2232	uint8_t fTbBranched;
2233	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
2234	bool fTbCrossedPage;
2235	/** Whether to end the current TB. */
2236	bool fEndTb;
2237	/** Indicates that the current instruction is an STI. This is set by the
2238	* iemCImpl_sti code and subsequently cleared by the recompiler. */
2239	bool fTbCurInstrIsSti;
2240	/** Spaced reserved for recompiler data / alignment. */
2241	bool afRecompilerStuff1[1];
2242	/** Number of instructions before we need emit an IRQ check call again.
2243	* This helps making sure we don't execute too long w/o checking for
2244	* interrupts and immediately following instructions that may enable
2245	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
2246	* required to make sure we check following the next instruction as well, see
2247	* fTbCurInstrIsSti. */
2248	uint8_t cInstrTillIrqCheck;
2249	/** The index of the last CheckIrq call during threaded recompilation. */
2250	uint16_t idxLastCheckIrqCallNo;
2251	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
2252	uint16_t cbOpcodesAllocated;
2253	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
2254	uint32_t uTbNativeRecompileAtUsedCount;
2255	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
2256	uint32_t fTbCurInstr;
2257	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
2258	uint32_t fTbPrevInstr;
2259	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
2260	* currently not up to date in EFLAGS. */
2261	uint32_t fSkippingEFlags;
2262	#if 0 /* unused */
2263	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
2264	RTGCPHYS GCPhysInstrBufPrev;
2265	#endif
2266
2267	/** Fixed TB used for threaded recompilation.
2268	* This is allocated once with maxed-out sizes and re-used afterwards. */
2269	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
2270	/** Pointer to the ring-3 TB allocator for this EMT. */
2271	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
2272	/** Pointer to the ring-3 executable memory allocator for this EMT. */
2273	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
2274	/** Pointer to the native recompiler state for ring-3. */
2275	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
2276	/** Dummy entry for ppTbLookupEntryR3. */
2277	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
2278	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
2279	/** The debug code advances this register as if it was CPUMCTX::rip and we
2280	* didn't do delayed PC updating. When CPUMCTX::rip is finally updated,
2281	* the result is compared with this value. */
2282	uint64_t uPcUpdatingDebug;
2283	#else
2284	uint64_t u64Placeholder;
2285	#endif
2286	/** @} */
2287
2288	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
2289	IEMTLBENTRY DataBreakpointTlbe;
2290
2291	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
2292	STAMCOUNTER StatTbThreadedExecBreaks;
2293	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
2294	STAMCOUNTER StatCheckIrqBreaks;
2295	/** Statistics: Times BltIn_CheckTimers breaks direct linking TBs. */
2296	STAMCOUNTER StatCheckTimersBreaks;
2297	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
2298	STAMCOUNTER StatCheckModeBreaks;
2299	/** Threaded TB statistics: Times execution break on call with lookup entries. */
2300	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
2301	/** Threaded TB statistics: Times execution break on call without lookup entries. */
2302	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2303	/** Statistics: Times a post jump target check missed and had to find new TB. */
2304	STAMCOUNTER StatCheckBranchMisses;
2305	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2306	STAMCOUNTER StatCheckNeedCsLimChecking;
2307	/** Statistics: Times a loop was detected within a TB. */
2308	STAMCOUNTER StatTbLoopInTbDetected;
2309	/** Statistics: Times a loop back to the start of the TB was detected. */
2310	STAMCOUNTER StatTbLoopFullTbDetected;
2311	/** Statistics: Times a loop back to the start of the TB was detected, var 2. */
2312	STAMCOUNTER StatTbLoopFullTbDetected2;
2313	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2314	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2315	/** Native TB statistics: Number of fully recompiled TBs. */
2316	STAMCOUNTER StatNativeFullyRecompiledTbs;
2317	/** TB statistics: Number of instructions per TB. */
2318	STAMPROFILE StatTbInstr;
2319	/** TB statistics: Number of TB lookup table entries per TB. */
2320	STAMPROFILE StatTbLookupEntries;
2321	/** Threaded TB statistics: Number of calls per TB. */
2322	STAMPROFILE StatTbThreadedCalls;
2323	/** Native TB statistics: Native code size per TB. */
2324	STAMPROFILE StatTbNativeCode;
2325	/** Native TB statistics: Profiling native recompilation. */
2326	STAMPROFILE StatNativeRecompilation;
2327	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2328	STAMPROFILE StatNativeCallsRecompiled;
2329	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2330	STAMPROFILE StatNativeCallsThreaded;
2331	/** Native recompiled execution: TLB hits for data fetches. */
2332	STAMCOUNTER StatNativeTlbHitsForFetch;
2333	/** Native recompiled execution: TLB hits for data stores. */
2334	STAMCOUNTER StatNativeTlbHitsForStore;
2335	/** Native recompiled execution: TLB hits for stack accesses. */
2336	STAMCOUNTER StatNativeTlbHitsForStack;
2337	/** Native recompiled execution: TLB hits for mapped accesses. */
2338	STAMCOUNTER StatNativeTlbHitsForMapped;
2339	/** Native recompiled execution: Code TLB misses for new page. */
2340	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2341	/** Native recompiled execution: Code TLB hits for new page. */
2342	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2343	/** Native recompiled execution: Code TLB misses for new page with offset. */
2344	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2345	/** Native recompiled execution: Code TLB hits for new page with offset. */
2346	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2347
2348	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2349	STAMCOUNTER StatNativeRegFindFree;
2350	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2351	* to free a variable. */
2352	STAMCOUNTER StatNativeRegFindFreeVar;
2353	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2354	* not need to free any variables. */
2355	STAMCOUNTER StatNativeRegFindFreeNoVar;
2356	/** Native recompiler: Liveness info freed shadowed guest registers in
2357	* iemNativeRegAllocFindFree. */
2358	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2359	/** Native recompiler: Liveness info helped with the allocation in
2360	* iemNativeRegAllocFindFree. */
2361	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2362
2363	/** Native recompiler: Number of times status flags calc has been skipped. */
2364	STAMCOUNTER StatNativeEflSkippedArithmetic;
2365	/** Native recompiler: Number of times status flags calc has been skipped. */
2366	STAMCOUNTER StatNativeEflSkippedLogical;
2367
2368	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2369	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2370	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2371	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2372	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2373	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2374	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2375	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2376	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2377	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2378	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2379	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2380	/** Native recompiler: Number of required EFLAGS.CF updates. */
2381	STAMCOUNTER StatNativeLivenessEflCfRequired;
2382	/** Native recompiler: Number of required EFLAGS.PF updates. */
2383	STAMCOUNTER StatNativeLivenessEflPfRequired;
2384	/** Native recompiler: Number of required EFLAGS.AF updates. */
2385	STAMCOUNTER StatNativeLivenessEflAfRequired;
2386	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2387	STAMCOUNTER StatNativeLivenessEflZfRequired;
2388	/** Native recompiler: Number of required EFLAGS.SF updates. */
2389	STAMCOUNTER StatNativeLivenessEflSfRequired;
2390	/** Native recompiler: Number of required EFLAGS.OF updates. */
2391	STAMCOUNTER StatNativeLivenessEflOfRequired;
2392	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2393	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2394	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2395	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2396	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2397	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2398	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2399	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2400	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2401	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2402	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2403	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2404
2405	/** Native recompiler: Number of potential PC updates in total. */
2406	STAMCOUNTER StatNativePcUpdateTotal;
2407	/** Native recompiler: Number of PC updates which could be delayed. */
2408	STAMCOUNTER StatNativePcUpdateDelayed;
2409
2410	/** Native recompiler: Number of time we had complicated dirty shadow
2411	* register situations with the other branch in IEM_MC_ENDIF. */
2412	STAMCOUNTER StatNativeEndIfOtherBranchDirty;
2413
2414	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2415	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2416	STAMCOUNTER StatNativeSimdRegFindFree;
2417	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2418	* to free a variable. */
2419	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2420	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2421	* not need to free any variables. */
2422	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2423	/** Native recompiler: Liveness info freed shadowed guest registers in
2424	* iemNativeSimdRegAllocFindFree. */
2425	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2426	/** Native recompiler: Liveness info helped with the allocation in
2427	* iemNativeSimdRegAllocFindFree. */
2428	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2429
2430	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2431	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2432	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2433	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2434	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2435	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2436	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2437	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2438
2439	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2440	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2441	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2442	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2443	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2444	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2445	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2446	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2447	//#endif
2448
2449	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2450	* Not availabe in release builds. */
2451	STAMCOUNTER StatNativeTbFinished;
2452	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2453	STAMCOUNTER StatNativeTbExitReturnBreak;
2454	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2455	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2456	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2457	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2458	/** Native recompiler: The TB finished executing with other non-zero status. */
2459	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2460	/** Native recompiler: The TB finished executing via throw / long jump. */
2461	STAMCOUNTER StatNativeTbExitLongJump;
2462	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2463	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2464	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2465	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2466	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2467	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2468	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2469	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2470	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2471	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2472	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2473	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2474
2475	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2476	STAMCOUNTER StatNativeTbExitRaiseDe;
2477	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2478	STAMCOUNTER StatNativeTbExitRaiseUd;
2479	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2480	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2481	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2482	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2483	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2484	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2485	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2486	STAMCOUNTER StatNativeTbExitRaiseNm;
2487	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2488	STAMCOUNTER StatNativeTbExitRaiseGp0;
2489	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2490	STAMCOUNTER StatNativeTbExitRaiseMf;
2491	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2492	STAMCOUNTER StatNativeTbExitRaiseXf;
2493	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2494	STAMCOUNTER StatNativeTbExitObsoleteTb;
2495
2496	/** Native recompiler: Number of full TB loops (jumps from end to start). */
2497	STAMCOUNTER StatNativeTbExitLoopFullTb;
2498
2499	/** Native recompiler: Failure situations with direct linking scenario \#1.
2500	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2501	* @{ */
2502	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2503	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2504	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2505	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2506	/** @} */
2507
2508	/** Native recompiler: Failure situations with direct linking scenario \#2.
2509	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2510	* @{ */
2511	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2512	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2513	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2514	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2515	/** @} */
2516
2517	/** iemMemMap and iemMemMapJmp statistics.
2518	* @{ */
2519	STAMCOUNTER StatMemMapJmp;
2520	STAMCOUNTER StatMemMapNoJmp;
2521	STAMCOUNTER StatMemBounceBufferCrossPage;
2522	STAMCOUNTER StatMemBounceBufferMapPhys;
2523	/** @} */
2524
2525	/** Timer polling statistics (debug only).
2526	* @{ */
2527	STAMPROFILE StatTimerPoll;
2528	STAMPROFILE StatTimerPollPoll;
2529	STAMPROFILE StatTimerPollRun;
2530	STAMCOUNTER StatTimerPollUnchanged;
2531	STAMCOUNTER StatTimerPollTiny;
2532	STAMCOUNTER StatTimerPollDefaultCalc;
2533	STAMCOUNTER StatTimerPollMax;
2534	STAMPROFILE StatTimerPollFactorDivision;
2535	STAMPROFILE StatTimerPollFactorMultiplication;
2536	/** @} */
2537
2538	#ifdef IEM_WITH_TLB_TRACE
2539	uint64_t au64Padding[4];
2540	#else
2541	uint64_t au64Padding[6];
2542	#endif
2543
2544	#ifdef IEM_WITH_TLB_TRACE
2545	/** The end (next) trace entry. */
2546	uint32_t idxTlbTraceEntry;
2547	/** Number of trace entries allocated expressed as a power of two. */
2548	uint32_t cTlbTraceEntriesShift;
2549	/** The trace entries. */
2550	PIEMTLBTRACEENTRY paTlbTraceEntries;
2551	#endif
2552
2553	/** Data TLB.
2554	* @remarks Must be 64-byte aligned. */
2555	IEMTLB DataTlb;
2556	/** Instruction TLB.
2557	* @remarks Must be 64-byte aligned. */
2558	IEMTLB CodeTlb;
2559
2560	/** Exception statistics. */
2561	STAMCOUNTER aStatXcpts[32];
2562	/** Interrupt statistics. */
2563	uint32_t aStatInts[256];
2564
2565	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2566	/** Instruction statistics for ring-0/raw-mode. */
2567	IEMINSTRSTATS StatsRZ;
2568	/** Instruction statistics for ring-3. */
2569	IEMINSTRSTATS StatsR3;
2570	# ifdef VBOX_WITH_IEM_RECOMPILER
2571	/** Statistics per threaded function call.
2572	* Updated by both the threaded and native recompilers. */
2573	uint32_t acThreadedFuncStats[0x6000 /24576/];
2574	# endif
2575	#endif
2576	} IEMCPU;
2577	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2578	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2579	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2580	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2581	AssertCompileMemberAlignment(IEMCPU, pCurTbR3, 64);
2582	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2583	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2584
2585	/** Pointer to the per-CPU IEM state. */
2586	typedef IEMCPU *PIEMCPU;
2587	/** Pointer to the const per-CPU IEM state. */
2588	typedef IEMCPU const *PCIEMCPU;
2589
2590	/** @def IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED
2591	* Value indicating the TB didn't modified the floating point control register.
2592	* @note Neither FPCR nor MXCSR accept this as a valid value (MXCSR is not fully populated,
2593	* FPCR has the upper 32-bit reserved), so this is safe. */
2594	#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) \|\| defined(DOXYGEN_RUNNING)
2595	# ifdef RT_ARCH_AMD64
2596	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT32_MAX
2597	# elif defined(RT_ARCH_ARM64)
2598	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT64_MAX
2599	# else
2600	# error "Port me"
2601	# endif
2602	#endif
2603
2604	/** @def IEM_GET_CTX
2605	* Gets the guest CPU context for the calling EMT.
2606	* @returns PCPUMCTX
2607	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2608	*/
2609	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2610
2611	/** @def IEM_CTX_ASSERT
2612	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2613	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2614	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2615	*/
2616	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2617	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2618	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2619	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2620
2621	/** @def IEM_CTX_IMPORT_RET
2622	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2623	*
2624	* Will call the keep to import the bits as needed.
2625	*
2626	* Returns on import failure.
2627	*
2628	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2629	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2630	*/
2631	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2632	do { \
2633	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2634	{ /* likely */ } \
2635	else \
2636	{ \
2637	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2638	AssertRCReturn(rcCtxImport, rcCtxImport); \
2639	} \
2640	} while (0)
2641
2642	/** @def IEM_CTX_IMPORT_NORET
2643	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2644	*
2645	* Will call the keep to import the bits as needed.
2646	*
2647	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2648	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2649	*/
2650	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2651	do { \
2652	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2653	{ /* likely */ } \
2654	else \
2655	{ \
2656	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2657	AssertLogRelRC(rcCtxImport); \
2658	} \
2659	} while (0)
2660
2661	/** @def IEM_CTX_IMPORT_JMP
2662	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2663	*
2664	* Will call the keep to import the bits as needed.
2665	*
2666	* Jumps on import failure.
2667	*
2668	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2669	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2670	*/
2671	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2672	do { \
2673	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2674	{ /* likely */ } \
2675	else \
2676	{ \
2677	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2678	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2679	} \
2680	} while (0)
2681
2682
2683
2684	/** @def IEM_GET_TARGET_CPU
2685	* Gets the current IEMTARGETCPU value.
2686	* @returns IEMTARGETCPU value.
2687	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2688	*/
2689	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2690	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2691	#else
2692	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2693	#endif
2694
2695	/** @def IEM_GET_INSTR_LEN
2696	* Gets the instruction length. */
2697	#ifdef IEM_WITH_CODE_TLB
2698	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2699	#else
2700	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2701	#endif
2702
2703	/** @def IEM_TRY_SETJMP
2704	* Wrapper around setjmp / try, hiding all the ugly differences.
2705	*
2706	* @note Use with extreme care as this is a fragile macro.
2707	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2708	* @param a_rcTarget The variable that should receive the status code in case
2709	* of a longjmp/throw.
2710	*/
2711	/** @def IEM_TRY_SETJMP_AGAIN
2712	* For when setjmp / try is used again in the same variable scope as a previous
2713	* IEM_TRY_SETJMP invocation.
2714	*/
2715	/** @def IEM_CATCH_LONGJMP_BEGIN
2716	* Start wrapper for catch / setjmp-else.
2717	*
2718	* This will set up a scope.
2719	*
2720	* @note Use with extreme care as this is a fragile macro.
2721	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2722	* @param a_rcTarget The variable that should receive the status code in case
2723	* of a longjmp/throw.
2724	*/
2725	/** @def IEM_CATCH_LONGJMP_END
2726	* End wrapper for catch / setjmp-else.
2727	*
2728	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2729	* state.
2730	*
2731	* @note Use with extreme care as this is a fragile macro.
2732	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2733	*/
2734	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2735	# ifdef IEM_WITH_THROW_CATCH
2736	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2737	a_rcTarget = VINF_SUCCESS; \
2738	try
2739	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2740	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2741	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2742	catch (int rcThrown) \
2743	{ \
2744	a_rcTarget = rcThrown
2745	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2746	} \
2747	((void)0)
2748	# else /* !IEM_WITH_THROW_CATCH */
2749	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2750	jmp_buf JmpBuf; \
2751	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2752	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2753	if ((rcStrict = setjmp(JmpBuf)) == 0)
2754	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2755	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2756	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2757	if ((rcStrict = setjmp(JmpBuf)) == 0)
2758	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2759	else \
2760	{ \
2761	((void)0)
2762	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2763	} \
2764	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2765	# endif /* !IEM_WITH_THROW_CATCH */
2766	#endif /* IEM_WITH_SETJMP */
2767
2768
2769	/**
2770	* Shared per-VM IEM data.
2771	*/
2772	typedef struct IEM
2773	{
2774	/** The VMX APIC-access page handler type. */
2775	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2776	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2777	/** Set if the CPUID host call functionality is enabled. */
2778	bool fCpuIdHostCall;
2779	#endif
2780	} IEM;
2781
2782
2783
2784	/** @name IEM_ACCESS_XXX - Access details.
2785	* @{ */
2786	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2787	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2788	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2789	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2790	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2791	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2792	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2793	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2794	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2795	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2796	/** The writes are partial, so if initialize the bounce buffer with the
2797	* orignal RAM content. */
2798	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2799	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2800	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2801	/** Bounce buffer with ring-3 write pending, first page. */
2802	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2803	/** Bounce buffer with ring-3 write pending, second page. */
2804	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2805	/** Not locked, accessed via the TLB. */
2806	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2807	/** Atomic access.
2808	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2809	* fallback for misaligned stuff. See @bugref{10547}. */
2810	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2811	/** Valid bit mask. */
2812	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2813	/** Shift count for the TLB flags (upper word). */
2814	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2815
2816	/** Atomic read+write data alias. */
2817	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2818	/** Read+write data alias. */
2819	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2820	/** Write data alias. */
2821	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2822	/** Read data alias. */
2823	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2824	/** Instruction fetch alias. */
2825	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2826	/** Stack write alias. */
2827	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2828	/** Stack read alias. */
2829	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2830	/** Stack read+write alias. */
2831	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2832	/** Read system table alias. */
2833	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2834	/** Read+write system table alias. */
2835	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2836	/** @} */
2837
2838	/** @name Prefix constants (IEMCPU::fPrefixes)
2839	* @{ */
2840	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2841	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2842	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2843	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2844	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2845	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2846	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2847
2848	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2849	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2850	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2851
2852	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2853	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2854	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2855
2856	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2857	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2858	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2859	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2860	/** Mask with all the REX prefix flags.
2861	* This is generally for use when needing to undo the REX prefixes when they
2862	* are followed legacy prefixes and therefore does not immediately preceed
2863	* the first opcode byte.
2864	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2865	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2866
2867	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2868	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2869	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2870	/** @} */
2871
2872	/** @name IEMOPFORM_XXX - Opcode forms
2873	* @note These are ORed together with IEMOPHINT_XXX.
2874	* @{ */
2875	/** ModR/M: reg, r/m */
2876	#define IEMOPFORM_RM 0
2877	/** ModR/M: reg, r/m (register) */
2878	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2879	/** ModR/M: reg, r/m (memory) */
2880	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2881	/** ModR/M: reg, r/m, imm */
2882	#define IEMOPFORM_RMI 1
2883	/** ModR/M: reg, r/m (register), imm */
2884	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2885	/** ModR/M: reg, r/m (memory), imm */
2886	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2887	/** ModR/M: reg, r/m, xmm0 */
2888	#define IEMOPFORM_RM0 2
2889	/** ModR/M: reg, r/m (register), xmm0 */
2890	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2891	/** ModR/M: reg, r/m (memory), xmm0 */
2892	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2893	/** ModR/M: r/m, reg */
2894	#define IEMOPFORM_MR 3
2895	/** ModR/M: r/m (register), reg */
2896	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2897	/** ModR/M: r/m (memory), reg */
2898	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2899	/** ModR/M: r/m, reg, imm */
2900	#define IEMOPFORM_MRI 4
2901	/** ModR/M: r/m (register), reg, imm */
2902	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2903	/** ModR/M: r/m (memory), reg, imm */
2904	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2905	/** ModR/M: r/m only */
2906	#define IEMOPFORM_M 5
2907	/** ModR/M: r/m only (register). */
2908	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2909	/** ModR/M: r/m only (memory). */
2910	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2911	/** ModR/M: r/m, imm */
2912	#define IEMOPFORM_MI 6
2913	/** ModR/M: r/m (register), imm */
2914	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2915	/** ModR/M: r/m (memory), imm */
2916	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2917	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2918	#define IEMOPFORM_M1 7
2919	/** ModR/M: r/m (register), 1. */
2920	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2921	/** ModR/M: r/m (memory), 1. */
2922	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2923	/** ModR/M: r/m, CL (shift and rotate instructions)
2924	* @todo This should just've been a generic fixed register. But the python
2925	* code doesn't needs more convincing. */
2926	#define IEMOPFORM_M_CL 8
2927	/** ModR/M: r/m (register), CL. */
2928	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2929	/** ModR/M: r/m (memory), CL. */
2930	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2931	/** ModR/M: reg only */
2932	#define IEMOPFORM_R 9
2933
2934	/** VEX+ModR/M: reg, r/m */
2935	#define IEMOPFORM_VEX_RM 16
2936	/** VEX+ModR/M: reg, r/m (register) */
2937	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2938	/** VEX+ModR/M: reg, r/m (memory) */
2939	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2940	/** VEX+ModR/M: r/m, reg */
2941	#define IEMOPFORM_VEX_MR 17
2942	/** VEX+ModR/M: r/m (register), reg */
2943	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2944	/** VEX+ModR/M: r/m (memory), reg */
2945	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2946	/** VEX+ModR/M: r/m, reg, imm8 */
2947	#define IEMOPFORM_VEX_MRI 18
2948	/** VEX+ModR/M: r/m (register), reg, imm8 */
2949	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2950	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2951	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2952	/** VEX+ModR/M: r/m only */
2953	#define IEMOPFORM_VEX_M 19
2954	/** VEX+ModR/M: r/m only (register). */
2955	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2956	/** VEX+ModR/M: r/m only (memory). */
2957	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2958	/** VEX+ModR/M: reg only */
2959	#define IEMOPFORM_VEX_R 20
2960	/** VEX+ModR/M: reg, vvvv, r/m */
2961	#define IEMOPFORM_VEX_RVM 21
2962	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2963	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2964	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2965	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2966	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2967	#define IEMOPFORM_VEX_RVMI 22
2968	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2969	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2970	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2971	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2972	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2973	#define IEMOPFORM_VEX_RVMR 23
2974	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2975	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2976	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2977	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2978	/** VEX+ModR/M: reg, r/m, vvvv */
2979	#define IEMOPFORM_VEX_RMV 24
2980	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2981	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2982	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2983	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2984	/** VEX+ModR/M: reg, r/m, imm8 */
2985	#define IEMOPFORM_VEX_RMI 25
2986	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2987	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2988	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2989	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2990	/** VEX+ModR/M: r/m, vvvv, reg */
2991	#define IEMOPFORM_VEX_MVR 26
2992	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2993	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2994	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2995	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2996	/** VEX+ModR/M+/n: vvvv, r/m */
2997	#define IEMOPFORM_VEX_VM 27
2998	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2999	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
3000	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
3001	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
3002	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
3003	#define IEMOPFORM_VEX_VMI 28
3004	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
3005	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
3006	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
3007	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
3008
3009	/** Fixed register instruction, no R/M. */
3010	#define IEMOPFORM_FIXED 32
3011
3012	/** The r/m is a register. */
3013	#define IEMOPFORM_MOD3 RT_BIT_32(8)
3014	/** The r/m is a memory access. */
3015	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
3016	/** @} */
3017
3018	/** @name IEMOPHINT_XXX - Additional Opcode Hints
3019	* @note These are ORed together with IEMOPFORM_XXX.
3020	* @{ */
3021	/** Ignores the operand size prefix (66h). */
3022	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
3023	/** Ignores REX.W (aka WIG). */
3024	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
3025	/** Both the operand size prefixes (66h + REX.W) are ignored. */
3026	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
3027	/** Allowed with the lock prefix. */
3028	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
3029	/** The VEX.L value is ignored (aka LIG). */
3030	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
3031	/** The VEX.L value must be zero (i.e. 128-bit width only). */
3032	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
3033	/** The VEX.L value must be one (i.e. 256-bit width only). */
3034	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
3035	/** The VEX.V value must be zero. */
3036	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
3037	/** The REX.W/VEX.V value must be zero. */
3038	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
3039	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
3040	/** The REX.W/VEX.V value must be one. */
3041	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
3042	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
3043
3044	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
3045	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
3046	/** @} */
3047
3048	/**
3049	* Possible hardware task switch sources.
3050	*/
3051	typedef enum IEMTASKSWITCH
3052	{
3053	/** Task switch caused by an interrupt/exception. */
3054	IEMTASKSWITCH_INT_XCPT = 1,
3055	/** Task switch caused by a far CALL. */
3056	IEMTASKSWITCH_CALL,
3057	/** Task switch caused by a far JMP. */
3058	IEMTASKSWITCH_JUMP,
3059	/** Task switch caused by an IRET. */
3060	IEMTASKSWITCH_IRET
3061	} IEMTASKSWITCH;
3062	AssertCompileSize(IEMTASKSWITCH, 4);
3063
3064	/**
3065	* Possible CrX load (write) sources.
3066	*/
3067	typedef enum IEMACCESSCRX
3068	{
3069	/** CrX access caused by 'mov crX' instruction. */
3070	IEMACCESSCRX_MOV_CRX,
3071	/** CrX (CR0) write caused by 'lmsw' instruction. */
3072	IEMACCESSCRX_LMSW,
3073	/** CrX (CR0) write caused by 'clts' instruction. */
3074	IEMACCESSCRX_CLTS,
3075	/** CrX (CR0) read caused by 'smsw' instruction. */
3076	IEMACCESSCRX_SMSW
3077	} IEMACCESSCRX;
3078
3079	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3080	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
3081	*
3082	* These flags provide further context to SLAT page-walk failures that could not be
3083	* determined by PGM (e.g, PGM is not privy to memory access permissions).
3084	*
3085	* @{
3086	*/
3087	/** Translating a nested-guest linear address failed accessing a nested-guest
3088	* physical address. */
3089	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
3090	/** Translating a nested-guest linear address failed accessing a
3091	* paging-structure entry or updating accessed/dirty bits. */
3092	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
3093	/** @} */
3094
3095	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
3096	# ifndef IN_RING3
3097	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
3098	# endif
3099	#endif
3100
3101	/**
3102	* Indicates to the verifier that the given flag set is undefined.
3103	*
3104	* Can be invoked again to add more flags.
3105	*
3106	* This is a NOOP if the verifier isn't compiled in.
3107	*
3108	* @note We're temporarily keeping this until code is converted to new
3109	* disassembler style opcode handling.
3110	*/
3111	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
3112
3113
3114	/** @def IEM_DECL_IMPL_TYPE
3115	* For typedef'ing an instruction implementation function.
3116	*
3117	* @param a_RetType The return type.
3118	* @param a_Name The name of the type.
3119	* @param a_ArgList The argument list enclosed in parentheses.
3120	*/
3121
3122	/** @def IEM_DECL_IMPL_DEF
3123	* For defining an instruction implementation function.
3124	*
3125	* @param a_RetType The return type.
3126	* @param a_Name The name of the type.
3127	* @param a_ArgList The argument list enclosed in parentheses.
3128	*/
3129
3130	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3131	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3132	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
3133	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3134	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3135	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3136	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3137
3138	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3139	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3140	a_RetType (__fastcall a_Name) a_ArgList
3141	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3142	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3143	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3144	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3145
3146	#elif __cplusplus >= 201700 /* P0012R1 support */
3147	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3148	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
3149	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3150	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3151	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3152	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3153
3154	#else
3155	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3156	a_RetType (VBOXCALL a_Name) a_ArgList
3157	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3158	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3159	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3160	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3161
3162	#endif
3163
3164	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
3165	RT_C_DECLS_BEGIN
3166	extern uint8_t const g_afParity[256];
3167	RT_C_DECLS_END
3168
3169
3170	/** @name Arithmetic assignment operations on bytes (binary).
3171	* @{ */
3172	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
3173	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
3174	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
3175	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
3176	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
3177	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
3178	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
3179	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
3180	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
3181	/** @} */
3182
3183	/** @name Arithmetic assignment operations on words (binary).
3184	* @{ */
3185	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
3186	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
3187	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
3188	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
3189	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
3190	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
3191	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
3192	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
3193	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
3194	/** @} */
3195
3196
3197	/** @name Arithmetic assignment operations on double words (binary).
3198	* @{ */
3199	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
3200	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
3201	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
3202	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
3203	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
3204	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
3205	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
3206	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
3207	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
3208	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
3209	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
3210	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
3211	/** @} */
3212
3213	/** @name Arithmetic assignment operations on quad words (binary).
3214	* @{ */
3215	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
3216	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
3217	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
3218	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
3219	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
3220	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
3221	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
3222	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
3223	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
3224	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
3225	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
3226	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
3227	/** @} */
3228
3229	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
3230	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
3231	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
3232	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
3233	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
3234	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
3235	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
3236	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
3237
3238	/** @name Compare operations (thrown in with the binary ops).
3239	* @{ */
3240	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
3241	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
3242	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
3243	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
3244	/** @} */
3245
3246	/** @name Test operations (thrown in with the binary ops).
3247	* @{ */
3248	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
3249	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
3250	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
3251	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
3252	/** @} */
3253
3254	/** @name Bit operations operations (thrown in with the binary ops).
3255	* @{ */
3256	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
3257	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
3258	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
3259	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
3260	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
3261	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
3262	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
3263	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
3264	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
3265	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
3266	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
3267	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
3268	/** @} */
3269
3270	/** @name Arithmetic three operand operations on double words (binary).
3271	* @{ */
3272	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
3273	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
3274	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
3275	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
3276	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
3277	/** @} */
3278
3279	/** @name Arithmetic three operand operations on quad words (binary).
3280	* @{ */
3281	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
3282	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
3283	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
3284	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
3285	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
3286	/** @} */
3287
3288	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
3289	* @{ */
3290	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
3291	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
3292	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
3293	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
3294	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
3295	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
3296	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
3297	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
3298	/** @} */
3299
3300	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
3301	* @{ */
3302	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
3303	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
3304	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
3305	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
3306	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
3307	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
3308	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
3309	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
3310	/** @} */
3311
3312	/** @name MULX 32-bit and 64-bit.
3313	* @{ */
3314	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
3315	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
3316	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
3317
3318	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
3319	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
3320	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
3321	/** @} */
3322
3323
3324	/** @name Exchange memory with register operations.
3325	* @{ */
3326	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
3327	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
3328	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
3329	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
3330	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
3331	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
3332	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
3333	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
3334	/** @} */
3335
3336	/** @name Exchange and add operations.
3337	* @{ */
3338	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3339	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3340	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3341	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3342	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3343	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3344	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3345	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3346	/** @} */
3347
3348	/** @name Compare and exchange.
3349	* @{ */
3350	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3351	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3352	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3353	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3354	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3355	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3356	#if ARCH_BITS == 32
3357	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3358	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3359	#else
3360	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3361	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3362	#endif
3363	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3364	uint32_t *pEFlags));
3365	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3366	uint32_t *pEFlags));
3367	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3368	uint32_t *pEFlags));
3369	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3370	uint32_t *pEFlags));
3371	#ifndef RT_ARCH_ARM64
3372	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3373	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3374	#endif
3375	/** @} */
3376
3377	/** @name Memory ordering
3378	* @{ */
3379	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3380	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3381	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3382	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3383	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3384	#ifndef RT_ARCH_ARM64
3385	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3386	#endif
3387	/** @} */
3388
3389	/** @name Double precision shifts
3390	* @{ */
3391	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3392	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3393	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3394	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3395	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3396	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3397	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3398	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3399	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3400	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3401	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3402	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3403	/** @} */
3404
3405
3406	/** @name Bit search operations (thrown in with the binary ops).
3407	* @{ */
3408	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3409	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3410	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3411	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3412	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3413	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3414	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3415	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3416	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3417	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3418	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3419	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3420	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3421	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3422	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3423	/** @} */
3424
3425	/** @name Signed multiplication operations (thrown in with the binary ops).
3426	* @{ */
3427	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3428	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3429	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3430	/** @} */
3431
3432	/** @name Arithmetic assignment operations on bytes (unary).
3433	* @{ */
3434	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3435	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3436	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3437	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3438	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3439	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3440	/** @} */
3441
3442	/** @name Arithmetic assignment operations on words (unary).
3443	* @{ */
3444	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3445	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3446	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3447	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3448	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3449	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3450	/** @} */
3451
3452	/** @name Arithmetic assignment operations on double words (unary).
3453	* @{ */
3454	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3455	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3456	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3457	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3458	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3459	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3460	/** @} */
3461
3462	/** @name Arithmetic assignment operations on quad words (unary).
3463	* @{ */
3464	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3465	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3466	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3467	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3468	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3469	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3470	/** @} */
3471
3472
3473	/** @name Shift operations on bytes (Group 2).
3474	* @{ */
3475	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3476	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3477	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3478	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3479	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3480	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3481	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3482	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3483	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3484	/** @} */
3485
3486	/** @name Shift operations on words (Group 2).
3487	* @{ */
3488	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3489	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3490	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3491	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3492	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3493	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3494	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3495	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3496	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3497	/** @} */
3498
3499	/** @name Shift operations on double words (Group 2).
3500	* @{ */
3501	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3502	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3503	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3504	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3505	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3506	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3507	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3508	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3509	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3510	/** @} */
3511
3512	/** @name Shift operations on words (Group 2).
3513	* @{ */
3514	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3515	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3516	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3517	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3518	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3519	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3520	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3521	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3522	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3523	/** @} */
3524
3525	/** @name Multiplication and division operations.
3526	* @{ */
3527	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3528	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3529	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3530	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3531	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3532	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3533
3534	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3535	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3536	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3537	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3538	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3539	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3540
3541	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3542	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3543	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3544	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3545	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3546	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3547
3548	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3549	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3550	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3551	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3552	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3553	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3554	/** @} */
3555
3556	/** @name Byte Swap.
3557	* @{ */
3558	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3559	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3560	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3561	/** @} */
3562
3563	/** @name Misc.
3564	* @{ */
3565	FNIEMAIMPLBINU16 iemAImpl_arpl;
3566	/** @} */
3567
3568	/** @name RDRAND and RDSEED
3569	* @{ */
3570	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3571	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3572	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3573	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3574	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3575	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3576
3577	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3578	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3579	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3580	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3581	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3582	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3583	/** @} */
3584
3585	/** @name ADOX and ADCX
3586	* @{ */
3587	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3588	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3589	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3590	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3591	/** @} */
3592
3593	/** @name FPU operations taking a 32-bit float argument
3594	* @{ */
3595	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3596	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3597	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3598
3599	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3600	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3601	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3602
3603	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3604	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3605	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3606	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3607	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3608	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3609	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3610
3611	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3612	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3613	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3614	/** @} */
3615
3616	/** @name FPU operations taking a 64-bit float argument
3617	* @{ */
3618	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3619	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3620	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3621
3622	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3623	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3624	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3625
3626	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3627	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3628	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3629	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3630	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3631	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3632	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3633
3634	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3635	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3636	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3637	/** @} */
3638
3639	/** @name FPU operations taking a 80-bit float argument
3640	* @{ */
3641	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3642	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3643	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3644	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3645	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3646	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3647	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3648	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3649	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3650	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3651	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3652	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3653
3654	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3655	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3656	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3657
3658	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3659	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3660	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3661	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3662	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3663
3664	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3665	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3666	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3667	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3668	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3669
3670	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3671	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3672	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3673	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3674	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3675	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3676	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3677	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3678	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3679
3680	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3681	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3682	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3683	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3684
3685	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3686	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3687	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3688	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3689	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3690	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3691	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3692	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3693	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3694
3695	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3696	PCRTFLOAT80U pr80Val));
3697	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3698	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3699	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3700	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3701
3702	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3703	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3704	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3705
3706	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3707	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3708	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3709
3710	/** @} */
3711
3712	/** @name FPU operations taking a 16-bit signed integer argument
3713	* @{ */
3714	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3715	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3716	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3717	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3718	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3719	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3720
3721	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3722	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3723	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3724	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3725	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3726	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3727
3728	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3729	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3730	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3731	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3732
3733	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3734	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3735	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3736	/** @} */
3737
3738	/** @name FPU operations taking a 32-bit signed integer argument
3739	* @{ */
3740	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3741	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3742	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3743	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3744	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3745	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3746
3747	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3748	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3749	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3750	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3751	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3752	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3753
3754	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3755	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3756	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3757	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3758
3759	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3760	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3761	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3762	/** @} */
3763
3764	/** @name FPU operations taking a 64-bit signed integer argument
3765	* @{ */
3766	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3767	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3768	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3769
3770	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3771	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3772	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3773	/** @} */
3774
3775
3776	/** Temporary type representing a 256-bit vector register. */
3777	typedef struct { uint64_t au64[4]; } IEMVMM256;
3778	/** Temporary type pointing to a 256-bit vector register. */
3779	typedef IEMVMM256 *PIEMVMM256;
3780	/** Temporary type pointing to a const 256-bit vector register. */
3781	typedef IEMVMM256 *PCIEMVMM256;
3782
3783
3784	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3785	* @{ */
3786	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3787	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3788	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
3789	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3790	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc));
3791	typedef FNIEMAIMPLMEDIAF2U256 *PFNIEMAIMPLMEDIAF2U256;
3792	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3793	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3794	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3795	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3796	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3797	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3798	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3799	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3800	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3801	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3802	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3803	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3804	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3805	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3806	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3807	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3808	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3809	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3810	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3811	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3812	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3813	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3814	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3815	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3816	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3817	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3818	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3819	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3820	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3821	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3822	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3823	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3824	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3825	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3826	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3827	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3828	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3829	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3830	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3831	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3832	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3833	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3834	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3835	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3836	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3837	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3838	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3839	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3840	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3841	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3842	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3843	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3844	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3845
3846	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3847	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3848	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3849	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3850	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3851	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3852	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3853	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3854	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3855	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3856	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3857	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3858	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3859	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3860	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3861	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3862	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3863	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3864	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3865	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3866	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3867	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3868	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3869	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3870	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3871	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3872	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3873	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3874	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3875	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3876	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3877	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3878	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3879	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3880	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3881	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3882	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3883	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3884	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3885	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3886	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3887	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3888	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3889	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3890	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3891	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3892	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3893	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3894	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3895	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3896	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3897	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3898	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3899	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3900	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3901	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3902	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3903	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3904
3905	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3906	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3907	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3908	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3909	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3910	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3911	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3912	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3913	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3914	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3915	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3916	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3917	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3918	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3919	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3920	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3921	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3922	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3923	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3924	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3925	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3926	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3927	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3928	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3929	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3930	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3931	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3932	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3933	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3934	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3935	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3936	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3937	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3938	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3939	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3940	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3941	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3942	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3943	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3944	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3945	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3946	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3947	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3948	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3949	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3950	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3951	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3952	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3953	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3954	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3955	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3956	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3957	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3958	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3959	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3960	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3961	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3962	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3963	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3964	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3965	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3966	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3967	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3968	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3969	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3970	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3971	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3972	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3973	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3974	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3975	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3976	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3977	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3978	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3979
3980	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3981	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3982	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3983	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3984
3985	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3986	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3987	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3988	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3989	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3990	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3991	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3992	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3993	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3994	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3995	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3996	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3997	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3998	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3999	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
4000	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
4001	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
4002	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
4003	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
4004	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
4005	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
4006	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
4007	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
4008	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
4009	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
4010	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
4011	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
4012	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
4013	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
4014	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
4015	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
4016	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
4017	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
4018	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
4019	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
4020	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
4021	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
4022	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
4023	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
4024	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
4025	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
4026	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
4027	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
4028	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
4029	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
4030	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
4031	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
4032	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
4033	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
4034	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
4035	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
4036	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
4037	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
4038	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
4039	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
4040	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
4041	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
4042	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
4043	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
4044	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
4045	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
4046	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
4047	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
4048	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
4049	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
4050	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
4051	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
4052	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
4053	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
4054	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
4055	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
4056	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
4057	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
4058	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
4059	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermps_u256, iemAImpl_vpermps_u256_fallback;
4060	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermd_u256, iemAImpl_vpermd_u256_fallback;
4061
4062	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
4063	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
4064	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
4065	/** @} */
4066
4067	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
4068	* @{ */
4069	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
4070	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
4071	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
4072	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
4073	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
4074	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
4075	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
4076	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
4077	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
4078	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
4079
4080	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
4081	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
4082	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
4083	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
4084	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
4085	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
4086	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
4087	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
4088	/** @} */
4089
4090	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
4091	* @{ */
4092	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
4093	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
4094	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
4095	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
4096	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
4097	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
4098	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
4099	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
4100	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
4101	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
4102	/** @} */
4103
4104	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
4105	* @{ */
4106	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4107	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
4108	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4109	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
4110	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
4111	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
4112	#ifndef IEM_WITHOUT_ASSEMBLY
4113	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
4114	#endif
4115	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
4116	/** @} */
4117
4118	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
4119	* @{ */
4120	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
4121	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
4122	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
4123	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
4124	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
4125	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
4126	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
4127	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
4128	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
4129	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
4130	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
4131	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
4132	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
4133	/** @} */
4134
4135	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
4136	* @{ */
4137	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
4138	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
4139	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
4140	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
4141	#ifndef IEM_WITHOUT_ASSEMBLY
4142	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4143	#endif
4144	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4145	/** @} */
4146
4147	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
4148	* @{ */
4149	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
4150	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
4151	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
4152	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
4153	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
4154	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
4155
4156	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
4157	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
4158	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
4159	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
4160	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
4161	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
4162
4163	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
4164	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
4165	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
4166	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
4167	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
4168	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
4169
4170	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
4171	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
4172	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
4173	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
4174	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
4175	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
4176	/** @} */
4177
4178
4179	/** @name Media (SSE/MMX/AVX) operation: Sort this later
4180	* @{ */
4181	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4182	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4183	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4184	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4185	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4186
4187	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4188	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4189	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4190	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4191	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4192
4193	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4194	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4195	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4196	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4197	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4198
4199	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4200	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4201	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4202	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4203	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4204
4205	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4206	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4207	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4208	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4209	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4210
4211	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4212	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4213	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4214	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4215	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4216
4217	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4218	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4219	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4220	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4221	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4222
4223	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4224	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4225	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4226	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4227	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4228
4229	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4230	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4231	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4232	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4233	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4234
4235	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4236	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4237	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4238	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4239	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4240
4241	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4242	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4243	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4244	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4245	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4246
4247	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4248	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4249	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4250	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4251	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4252
4253	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4254	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4255	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4256	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4257	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4258
4259	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4260	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4261	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4262	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4263	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4264
4265	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4266	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4267
4268	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4269	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4270	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4271	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4272	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4273
4274	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4275	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4276	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4277	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4278	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4279
4280
4281	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4282	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
4283	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4284	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
4285	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4286	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
4287	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4288	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
4289
4290	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
4291	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
4292	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
4293	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
4294
4295	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
4296	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
4297	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
4298	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
4299	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
4300
4301	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
4302	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
4303	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
4304	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
4305	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
4306	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
4307	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
4308
4309	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
4310	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
4311	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
4312	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
4313	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
4314
4315	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
4316	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
4317	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
4318	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
4319	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
4320
4321	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
4322
4323	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
4324
4325	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
4326	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
4327	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
4328	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
4329	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
4330	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
4331	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4332	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4333
4334	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermq_u256, iemAImpl_vpermq_u256_fallback;
4335	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermpd_u256, iemAImpl_vpermpd_u256_fallback;
4336
4337	typedef struct IEMPCMPISTRXSRC
4338	{
4339	RTUINT128U uSrc1;
4340	RTUINT128U uSrc2;
4341	} IEMPCMPISTRXSRC;
4342	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
4343	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
4344
4345	typedef struct IEMPCMPESTRXSRC
4346	{
4347	RTUINT128U uSrc1;
4348	RTUINT128U uSrc2;
4349	uint64_t u64Rax;
4350	uint64_t u64Rdx;
4351	} IEMPCMPESTRXSRC;
4352	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
4353	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
4354
4355	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
4356	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
4357	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4358	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4359
4360	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4361	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4362	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4363	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4364
4365	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4366	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4367	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4368	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4369	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_vpcmpistri_u128, iemAImpl_vpcmpistri_u128_fallback;
4370	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_vpcmpestri_u128, iemAImpl_vpcmpestri_u128_fallback;
4371	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_vpcmpistrm_u128, iemAImpl_vpcmpistrm_u128_fallback;
4372	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_vpcmpestrm_u128, iemAImpl_vpcmpestrm_u128_fallback;
4373
4374
4375	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4376	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4377
4378	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4379	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4380	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4381
4382	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4383	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4384	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4385	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4386	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4387	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4388	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4389	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4390	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4391	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4392
4393	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4394	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4395	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4396	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4397
4398	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4399	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4400	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4401	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4402	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4403	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4404	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4405	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4406	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4407	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4408
4409	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4410	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4411	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4412	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4413
4414	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4415	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4416	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4417	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4418
4419	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4420	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4421	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4422	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4423	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4424	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4425	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4426	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4427	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4428	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4429	/** @} */
4430
4431	/** @name Media Odds and Ends
4432	* @{ */
4433	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4434	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4435	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4436	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4437	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4438	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4439	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4440	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4441
4442	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4443	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4444	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4445	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4446	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4447	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4448	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4449	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4450	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4451	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4452
4453	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4454	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4455	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4456	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4457	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4458	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4459	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4460	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4461	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R32,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT32U pr32Src));
4462	typedef FNIEMAIMPLSSEF2I32R32 *PFNIEMAIMPLSSEF2I32R32;
4463	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R32,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT32U pr32Src));
4464	typedef FNIEMAIMPLSSEF2I64R32 *PFNIEMAIMPLSSEF2I64R32;
4465	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R64,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT64U pr64Src));
4466	typedef FNIEMAIMPLSSEF2I32R64 *PFNIEMAIMPLSSEF2I32R64;
4467	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R64,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT64U pr64Src));
4468	typedef FNIEMAIMPLSSEF2I64R64 *PFNIEMAIMPLSSEF2I64R64;
4469
4470	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4471	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4472
4473	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4474	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4475
4476	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4477	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4478
4479	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4480	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4481
4482	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttss2si_i32_r32, iemAImpl_vcvttss2si_i32_r32_fallback;
4483	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttss2si_i64_r32, iemAImpl_vcvttss2si_i64_r32_fallback;
4484	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtss2si_i32_r32, iemAImpl_vcvtss2si_i32_r32_fallback;
4485	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtss2si_i64_r32, iemAImpl_vcvtss2si_i64_r32_fallback;
4486
4487	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttss2si_i32_r64, iemAImpl_vcvttss2si_i32_r64_fallback;
4488	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttss2si_i64_r64, iemAImpl_vcvttss2si_i64_r64_fallback;
4489	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtss2si_i32_r64, iemAImpl_vcvtss2si_i32_r64_fallback;
4490	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtss2si_i64_r64, iemAImpl_vcvtss2si_i64_r64_fallback;
4491
4492	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttsd2si_i32_r32, iemAImpl_vcvttsd2si_i32_r32_fallback;
4493	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttsd2si_i64_r32, iemAImpl_vcvttsd2si_i64_r32_fallback;
4494	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtsd2si_i32_r32, iemAImpl_vcvtsd2si_i32_r32_fallback;
4495	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtsd2si_i64_r32, iemAImpl_vcvtsd2si_i64_r32_fallback;
4496
4497	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttsd2si_i32_r64, iemAImpl_vcvttsd2si_i32_r64_fallback;
4498	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttsd2si_i64_r64, iemAImpl_vcvttsd2si_i64_r64_fallback;
4499	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtsd2si_i32_r64, iemAImpl_vcvtsd2si_i32_r64_fallback;
4500	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtsd2si_i64_r64, iemAImpl_vcvtsd2si_i64_r64_fallback;
4501
4502	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4503	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4504	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4505	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4506
4507	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4508	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4509
4510	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI32,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int32_t *pi32Src));
4511	typedef FNIEMAIMPLAVXF3XMMI32 *PFNIEMAIMPLAVXF3XMMI32;
4512	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI64,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int64_t *pi64Src));
4513	typedef FNIEMAIMPLAVXF3XMMI64 *PFNIEMAIMPLAVXF3XMMI64;
4514
4515	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2ss_u128_i32, iemAImpl_vcvtsi2ss_u128_i32_fallback;
4516	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2ss_u128_i64, iemAImpl_vcvtsi2ss_u128_i64_fallback;
4517
4518
4519	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4520	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4521	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4522	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4523
4524	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4525	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4526
4527	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2sd_u128_i32, iemAImpl_vcvtsi2sd_u128_i32_fallback;
4528	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2sd_u128_i64, iemAImpl_vcvtsi2sd_u128_i64_fallback;
4529
4530	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4531	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4532	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4533	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4534
4535
4536	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4537	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4538	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4539	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4540
4541
4542	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4543	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4544
4545	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4546	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4547
4548	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4549	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4550
4551	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4552	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4553
4554	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4555	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4556
4557	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4558	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4559
4560
4561	typedef struct IEMMEDIAF2XMMSRC
4562	{
4563	X86XMMREG uSrc1;
4564	X86XMMREG uSrc2;
4565	} IEMMEDIAF2XMMSRC;
4566	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4567	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4568
4569
4570	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4571	typedef FNIEMAIMPLMEDIAF3XMMIMM8 *PFNIEMAIMPLMEDIAF3XMMIMM8;
4572
4573
4574	typedef struct IEMMEDIAF2YMMSRC
4575	{
4576	X86YMMREG uSrc1;
4577	X86YMMREG uSrc2;
4578	} IEMMEDIAF2YMMSRC;
4579	typedef IEMMEDIAF2YMMSRC *PIEMMEDIAF2YMMSRC;
4580	typedef const IEMMEDIAF2YMMSRC *PCIEMMEDIAF2YMMSRC;
4581
4582
4583	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3YMMIMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCIEMMEDIAF2YMMSRC puSrc, uint8_t bEvil));
4584	typedef FNIEMAIMPLMEDIAF3YMMIMM8 *PFNIEMAIMPLMEDIAF3YMMIMM8;
4585
4586
4587	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpps_u128;
4588	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmppd_u128;
4589	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpss_u128;
4590	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpsd_u128;
4591
4592	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpps_u128, iemAImpl_vcmpps_u128_fallback;
4593	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmppd_u128, iemAImpl_vcmppd_u128_fallback;
4594	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpss_u128, iemAImpl_vcmpss_u128_fallback;
4595	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpsd_u128, iemAImpl_vcmpsd_u128_fallback;
4596
4597	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmpps_u256, iemAImpl_vcmpps_u256_fallback;
4598	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmppd_u256, iemAImpl_vcmppd_u256_fallback;
4599
4600	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundss_u128;
4601	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundsd_u128;
4602
4603	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4604	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4605
4606
4607	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128IMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, uint8_t bEvil));
4608	typedef FNIEMAIMPLMEDIAF2U128IMM8 *PFNIEMAIMPLMEDIAF2U128IMM8;
4609
4610
4611	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256IMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc, uint8_t bEvil));
4612	typedef FNIEMAIMPLMEDIAF2U256IMM8 *PFNIEMAIMPLMEDIAF2U256IMM8;
4613
4614
4615	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4616	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4617
4618	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundps_u128, iemAImpl_vroundps_u128_fallback;
4619	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundpd_u128, iemAImpl_vroundpd_u128_fallback;
4620
4621	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundps_u256, iemAImpl_vroundps_u256_fallback;
4622	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundpd_u256, iemAImpl_vroundpd_u256_fallback;
4623
4624	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundss_u128, iemAImpl_vroundss_u128_fallback;
4625	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundsd_u128, iemAImpl_vroundsd_u128_fallback;
4626
4627	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdpps_u128, iemAImpl_vdpps_u128_fallback;
4628	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdppd_u128, iemAImpl_vdppd_u128_fallback;
4629
4630	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vdpps_u256, iemAImpl_vdpps_u256_fallback;
4631
4632
4633	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4634	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4635
4636	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4637	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4638
4639	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4640	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4641
4642	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4643	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4644
4645	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4646	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4647
4648	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4649	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4650
4651	/** @} */
4652
4653
4654	/** @name Function tables.
4655	* @{
4656	*/
4657
4658	/**
4659	* Function table for a binary operator providing implementation based on
4660	* operand size.
4661	*/
4662	typedef struct IEMOPBINSIZES
4663	{
4664	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4665	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4666	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4667	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4668	} IEMOPBINSIZES;
4669	/** Pointer to a binary operator function table. */
4670	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4671
4672
4673	/**
4674	* Function table for a unary operator providing implementation based on
4675	* operand size.
4676	*/
4677	typedef struct IEMOPUNARYSIZES
4678	{
4679	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4680	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4681	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4682	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4683	} IEMOPUNARYSIZES;
4684	/** Pointer to a unary operator function table. */
4685	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4686
4687
4688	/**
4689	* Function table for a shift operator providing implementation based on
4690	* operand size.
4691	*/
4692	typedef struct IEMOPSHIFTSIZES
4693	{
4694	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4695	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4696	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4697	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4698	} IEMOPSHIFTSIZES;
4699	/** Pointer to a shift operator function table. */
4700	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4701
4702
4703	/**
4704	* Function table for a multiplication or division operation.
4705	*/
4706	typedef struct IEMOPMULDIVSIZES
4707	{
4708	PFNIEMAIMPLMULDIVU8 pfnU8;
4709	PFNIEMAIMPLMULDIVU16 pfnU16;
4710	PFNIEMAIMPLMULDIVU32 pfnU32;
4711	PFNIEMAIMPLMULDIVU64 pfnU64;
4712	} IEMOPMULDIVSIZES;
4713	/** Pointer to a multiplication or division operation function table. */
4714	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4715
4716
4717	/**
4718	* Function table for a double precision shift operator providing implementation
4719	* based on operand size.
4720	*/
4721	typedef struct IEMOPSHIFTDBLSIZES
4722	{
4723	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4724	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4725	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4726	} IEMOPSHIFTDBLSIZES;
4727	/** Pointer to a double precision shift function table. */
4728	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4729
4730
4731	/**
4732	* Function table for media instruction taking two full sized media source
4733	* registers and one full sized destination register (AVX).
4734	*/
4735	typedef struct IEMOPMEDIAF3
4736	{
4737	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4738	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4739	} IEMOPMEDIAF3;
4740	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4741	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4742
4743	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4744	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4745	* given functions as initializers. For use in AVX functions where a pair of
4746	* functions are only used once and the function table need not be public. */
4747	#ifndef TST_IEM_CHECK_MC
4748	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4749	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4750	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4751	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4752	# else
4753	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4754	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4755	# endif
4756	#else
4757	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4758	#endif
4759	/** @def IEMOPMEDIAF3_INIT_VARS
4760	* Generate AVX function tables for the @a a_InstrNm instruction.
4761	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4762	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4763	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4764	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4765
4766
4767	/**
4768	* Function table for media instruction taking one full sized media source
4769	* registers and one full sized destination register (AVX).
4770	*/
4771	typedef struct IEMOPMEDIAF2
4772	{
4773	PFNIEMAIMPLMEDIAF2U128 pfnU128;
4774	PFNIEMAIMPLMEDIAF2U256 pfnU256;
4775	} IEMOPMEDIAF2;
4776	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4777	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
4778
4779	/** @def IEMOPMEDIAF2_INIT_VARS_EX
4780	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4781	* given functions as initializers. For use in AVX functions where a pair of
4782	* functions are only used once and the function table need not be public. */
4783	#ifndef TST_IEM_CHECK_MC
4784	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4785	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4786	static IEMOPMEDIAF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4787	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4788	# else
4789	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4790	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4791	# endif
4792	#else
4793	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4794	#endif
4795	/** @def IEMOPMEDIAF2_INIT_VARS
4796	* Generate AVX function tables for the @a a_InstrNm instruction.
4797	* @sa IEMOPMEDIAF2_INIT_VARS_EX */
4798	#define IEMOPMEDIAF2_INIT_VARS(a_InstrNm) \
4799	IEMOPMEDIAF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4800	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4801
4802
4803	/**
4804	* Function table for media instruction taking two full sized media source
4805	* registers and one full sized destination register, but no additional state
4806	* (AVX).
4807	*/
4808	typedef struct IEMOPMEDIAOPTF3
4809	{
4810	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4811	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4812	} IEMOPMEDIAOPTF3;
4813	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4814	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4815
4816	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4817	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4818	* given functions as initializers. For use in AVX functions where a pair of
4819	* functions are only used once and the function table need not be public. */
4820	#ifndef TST_IEM_CHECK_MC
4821	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4822	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4823	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4824	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4825	# else
4826	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4827	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4828	# endif
4829	#else
4830	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4831	#endif
4832	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4833	* Generate AVX function tables for the @a a_InstrNm instruction.
4834	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4835	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4836	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4837	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4838
4839	/**
4840	* Function table for media instruction taking one full sized media source
4841	* registers and one full sized destination register, but no additional state
4842	* (AVX).
4843	*/
4844	typedef struct IEMOPMEDIAOPTF2
4845	{
4846	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4847	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4848	} IEMOPMEDIAOPTF2;
4849	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4850	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4851
4852	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4853	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4854	* given functions as initializers. For use in AVX functions where a pair of
4855	* functions are only used once and the function table need not be public. */
4856	#ifndef TST_IEM_CHECK_MC
4857	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4858	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4859	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4860	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4861	# else
4862	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4863	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4864	# endif
4865	#else
4866	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4867	#endif
4868	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4869	* Generate AVX function tables for the @a a_InstrNm instruction.
4870	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4871	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4872	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4873	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4874
4875
4876	/**
4877	* Function table for media instruction taking one full sized media source
4878	* register and one full sized destination register and an 8-bit immediate (AVX).
4879	*/
4880	typedef struct IEMOPMEDIAF2IMM8
4881	{
4882	PFNIEMAIMPLMEDIAF2U128IMM8 pfnU128;
4883	PFNIEMAIMPLMEDIAF2U256IMM8 pfnU256;
4884	} IEMOPMEDIAF2IMM8;
4885	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4886	typedef IEMOPMEDIAF2IMM8 const *PCIEMOPMEDIAF2IMM8;
4887
4888	/** @def IEMOPMEDIAF2IMM8_INIT_VARS_EX
4889	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4890	* given functions as initializers. For use in AVX functions where a pair of
4891	* functions are only used once and the function table need not be public. */
4892	#ifndef TST_IEM_CHECK_MC
4893	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4894	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4895	static IEMOPMEDIAF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4896	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4897	# else
4898	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4899	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4900	# endif
4901	#else
4902	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4903	#endif
4904	/** @def IEMOPMEDIAF2IMM8_INIT_VARS
4905	* Generate AVX function tables for the @a a_InstrNm instruction.
4906	* @sa IEMOPMEDIAF2IMM8_INIT_VARS_EX */
4907	#define IEMOPMEDIAF2IMM8_INIT_VARS(a_InstrNm) \
4908	IEMOPMEDIAF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4909	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4910
4911
4912	/**
4913	* Function table for media instruction taking one full sized media source
4914	* register and one full sized destination register and an 8-bit immediate, but no additional state
4915	* (AVX).
4916	*/
4917	typedef struct IEMOPMEDIAOPTF2IMM8
4918	{
4919	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4920	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4921	} IEMOPMEDIAOPTF2IMM8;
4922	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4923	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4924
4925	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4926	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4927	* given functions as initializers. For use in AVX functions where a pair of
4928	* functions are only used once and the function table need not be public. */
4929	#ifndef TST_IEM_CHECK_MC
4930	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4931	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4932	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4933	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4934	# else
4935	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4936	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4937	# endif
4938	#else
4939	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4940	#endif
4941	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4942	* Generate AVX function tables for the @a a_InstrNm instruction.
4943	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4944	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4945	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4946	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4947
4948	/**
4949	* Function table for media instruction taking two full sized media source
4950	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4951	* (AVX).
4952	*/
4953	typedef struct IEMOPMEDIAOPTF3IMM8
4954	{
4955	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4956	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4957	} IEMOPMEDIAOPTF3IMM8;
4958	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4959	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4960
4961	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4962	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4963	* given functions as initializers. For use in AVX functions where a pair of
4964	* functions are only used once and the function table need not be public. */
4965	#ifndef TST_IEM_CHECK_MC
4966	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4967	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4968	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4969	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4970	# else
4971	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4972	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4973	# endif
4974	#else
4975	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4976	#endif
4977	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4978	* Generate AVX function tables for the @a a_InstrNm instruction.
4979	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4980	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4981	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4982	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4983	/** @} */
4984
4985
4986	/**
4987	* Function table for blend type instruction taking three full sized media source
4988	* registers and one full sized destination register, but no additional state
4989	* (AVX).
4990	*/
4991	typedef struct IEMOPBLENDOP
4992	{
4993	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4994	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4995	} IEMOPBLENDOP;
4996	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4997	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4998
4999	/** @def IEMOPBLENDOP_INIT_VARS_EX
5000	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
5001	* given functions as initializers. For use in AVX functions where a pair of
5002	* functions are only used once and the function table need not be public. */
5003	#ifndef TST_IEM_CHECK_MC
5004	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
5005	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
5006	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
5007	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
5008	# else
5009	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
5010	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
5011	# endif
5012	#else
5013	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
5014	#endif
5015	/** @def IEMOPBLENDOP_INIT_VARS
5016	* Generate AVX function tables for the @a a_InstrNm instruction.
5017	* @sa IEMOPBLENDOP_INIT_VARS_EX */
5018	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
5019	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
5020	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
5021
5022
5023	/** @name SSE/AVX single/double precision floating point operations.
5024	* @{ */
5025	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
5026	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
5027	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
5028	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
5029	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
5030	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
5031
5032	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
5033	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
5034	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
5035	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
5036	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
5037	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
5038
5039	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
5040	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
5041
5042	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
5043	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
5044	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
5045	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
5046	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
5047	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
5048	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
5049	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
5050	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
5051	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
5052	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
5053	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
5054	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
5055	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
5056	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
5057	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
5058	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
5059	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
5060	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
5061	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
5062	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
5063	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
5064
5065	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
5066	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
5067
5068	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
5069	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
5070	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
5071	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
5072	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
5073	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
5074
5075	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
5076	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
5077	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
5078	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
5079	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
5080	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
5081	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
5082	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
5083	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
5084	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
5085	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
5086	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
5087	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
5088	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
5089	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
5090	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
5091	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
5092	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
5093
5094	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
5095	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
5096	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
5097	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
5098	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
5099	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
5100	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
5101	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
5102	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
5103	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
5104	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
5105	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
5106	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
5107	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
5108	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
5109	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
5110	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
5111	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
5112	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrsqrtps_u128, iemAImpl_vrsqrtps_u128_fallback;
5113	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrcpps_u128, iemAImpl_vrcpps_u128_fallback;
5114	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
5115	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
5116	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtdq2ps_u128, iemAImpl_vcvtdq2ps_u128_fallback;
5117	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtps2dq_u128, iemAImpl_vcvtps2dq_u128_fallback;
5118	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvttps2dq_u128, iemAImpl_vcvttps2dq_u128_fallback;
5119	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5120	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5121	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5122	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5123	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5124	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5125
5126
5127	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
5128	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
5129	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
5130	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
5131	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
5132	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
5133	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
5134	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
5135	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
5136	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
5137	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
5138	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
5139	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
5140	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
5141	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrsqrtss_u128_r32, iemAImpl_vrsqrtss_u128_r32_fallback;
5142	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrcpss_u128_r32, iemAImpl_vrcpss_u128_r32_fallback;
5143	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vcvtss2sd_u128_r32, iemAImpl_vcvtss2sd_u128_r32_fallback;
5144	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vcvtsd2ss_u128_r64, iemAImpl_vcvtsd2ss_u128_r64_fallback;
5145
5146
5147	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
5148	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
5149	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
5150	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
5151	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
5152	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
5153	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
5154	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
5155	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
5156	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
5157	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
5158	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
5159	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
5160	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
5161	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
5162	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
5163	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubps_u256, iemAImpl_vaddsubps_u256_fallback;
5164	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubpd_u256, iemAImpl_vaddsubpd_u256_fallback;
5165	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtps_u256, iemAImpl_vsqrtps_u256_fallback;
5166	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtpd_u256, iemAImpl_vsqrtpd_u256_fallback;
5167	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrsqrtps_u256, iemAImpl_vrsqrtps_u256_fallback;
5168	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrcpps_u256, iemAImpl_vrcpps_u256_fallback;
5169	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtdq2ps_u256, iemAImpl_vcvtdq2ps_u256_fallback;
5170	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtps2dq_u256, iemAImpl_vcvtps2dq_u256_fallback;
5171	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvttps2dq_u256, iemAImpl_vcvttps2dq_u256_fallback;
5172	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5173	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5174	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5175	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5176	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5177	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5178	/** @} */
5179
5180	/** @name C instruction implementations for anything slightly complicated.
5181	* @{ */
5182
5183	/**
5184	* For typedef'ing or declaring a C instruction implementation function taking
5185	* no extra arguments.
5186	*
5187	* @param a_Name The name of the type.
5188	*/
5189	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
5190	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5191	/**
5192	* For defining a C instruction implementation function taking no extra
5193	* arguments.
5194	*
5195	* @param a_Name The name of the function
5196	*/
5197	# define IEM_CIMPL_DEF_0(a_Name) \
5198	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5199	/**
5200	* Prototype version of IEM_CIMPL_DEF_0.
5201	*/
5202	# define IEM_CIMPL_PROTO_0(a_Name) \
5203	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5204	/**
5205	* For calling a C instruction implementation function taking no extra
5206	* arguments.
5207	*
5208	* This special call macro adds default arguments to the call and allow us to
5209	* change these later.
5210	*
5211	* @param a_fn The name of the function.
5212	*/
5213	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
5214
5215	/** Type for a C instruction implementation function taking no extra
5216	* arguments. */
5217	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
5218	/** Function pointer type for a C instruction implementation function taking
5219	* no extra arguments. */
5220	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
5221
5222	/**
5223	* For typedef'ing or declaring a C instruction implementation function taking
5224	* one extra argument.
5225	*
5226	* @param a_Name The name of the type.
5227	* @param a_Type0 The argument type.
5228	* @param a_Arg0 The argument name.
5229	*/
5230	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
5231	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5232	/**
5233	* For defining a C instruction implementation function taking one extra
5234	* argument.
5235	*
5236	* @param a_Name The name of the function
5237	* @param a_Type0 The argument type.
5238	* @param a_Arg0 The argument name.
5239	*/
5240	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
5241	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5242	/**
5243	* Prototype version of IEM_CIMPL_DEF_1.
5244	*/
5245	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
5246	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5247	/**
5248	* For calling a C instruction implementation function taking one extra
5249	* argument.
5250	*
5251	* This special call macro adds default arguments to the call and allow us to
5252	* change these later.
5253	*
5254	* @param a_fn The name of the function.
5255	* @param a0 The name of the 1st argument.
5256	*/
5257	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
5258
5259	/**
5260	* For typedef'ing or declaring a C instruction implementation function taking
5261	* two extra arguments.
5262	*
5263	* @param a_Name The name of the type.
5264	* @param a_Type0 The type of the 1st argument
5265	* @param a_Arg0 The name of the 1st argument.
5266	* @param a_Type1 The type of the 2nd argument.
5267	* @param a_Arg1 The name of the 2nd argument.
5268	*/
5269	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5270	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5271	/**
5272	* For defining a C instruction implementation function taking two extra
5273	* arguments.
5274	*
5275	* @param a_Name The name of the function.
5276	* @param a_Type0 The type of the 1st argument
5277	* @param a_Arg0 The name of the 1st argument.
5278	* @param a_Type1 The type of the 2nd argument.
5279	* @param a_Arg1 The name of the 2nd argument.
5280	*/
5281	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5282	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5283	/**
5284	* Prototype version of IEM_CIMPL_DEF_2.
5285	*/
5286	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5287	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5288	/**
5289	* For calling a C instruction implementation function taking two extra
5290	* arguments.
5291	*
5292	* This special call macro adds default arguments to the call and allow us to
5293	* change these later.
5294	*
5295	* @param a_fn The name of the function.
5296	* @param a0 The name of the 1st argument.
5297	* @param a1 The name of the 2nd argument.
5298	*/
5299	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
5300
5301	/**
5302	* For typedef'ing or declaring a C instruction implementation function taking
5303	* three extra arguments.
5304	*
5305	* @param a_Name The name of the type.
5306	* @param a_Type0 The type of the 1st argument
5307	* @param a_Arg0 The name of the 1st argument.
5308	* @param a_Type1 The type of the 2nd argument.
5309	* @param a_Arg1 The name of the 2nd argument.
5310	* @param a_Type2 The type of the 3rd argument.
5311	* @param a_Arg2 The name of the 3rd argument.
5312	*/
5313	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5314	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5315	/**
5316	* For defining a C instruction implementation function taking three extra
5317	* arguments.
5318	*
5319	* @param a_Name The name of the function.
5320	* @param a_Type0 The type of the 1st argument
5321	* @param a_Arg0 The name of the 1st argument.
5322	* @param a_Type1 The type of the 2nd argument.
5323	* @param a_Arg1 The name of the 2nd argument.
5324	* @param a_Type2 The type of the 3rd argument.
5325	* @param a_Arg2 The name of the 3rd argument.
5326	*/
5327	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5328	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5329	/**
5330	* Prototype version of IEM_CIMPL_DEF_3.
5331	*/
5332	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5333	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5334	/**
5335	* For calling a C instruction implementation function taking three extra
5336	* arguments.
5337	*
5338	* This special call macro adds default arguments to the call and allow us to
5339	* change these later.
5340	*
5341	* @param a_fn The name of the function.
5342	* @param a0 The name of the 1st argument.
5343	* @param a1 The name of the 2nd argument.
5344	* @param a2 The name of the 3rd argument.
5345	*/
5346	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
5347
5348
5349	/**
5350	* For typedef'ing or declaring a C instruction implementation function taking
5351	* four extra arguments.
5352	*
5353	* @param a_Name The name of the type.
5354	* @param a_Type0 The type of the 1st argument
5355	* @param a_Arg0 The name of the 1st argument.
5356	* @param a_Type1 The type of the 2nd argument.
5357	* @param a_Arg1 The name of the 2nd argument.
5358	* @param a_Type2 The type of the 3rd argument.
5359	* @param a_Arg2 The name of the 3rd argument.
5360	* @param a_Type3 The type of the 4th argument.
5361	* @param a_Arg3 The name of the 4th argument.
5362	*/
5363	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5364	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
5365	/**
5366	* For defining a C instruction implementation function taking four extra
5367	* arguments.
5368	*
5369	* @param a_Name The name of the function.
5370	* @param a_Type0 The type of the 1st argument
5371	* @param a_Arg0 The name of the 1st argument.
5372	* @param a_Type1 The type of the 2nd argument.
5373	* @param a_Arg1 The name of the 2nd argument.
5374	* @param a_Type2 The type of the 3rd argument.
5375	* @param a_Arg2 The name of the 3rd argument.
5376	* @param a_Type3 The type of the 4th argument.
5377	* @param a_Arg3 The name of the 4th argument.
5378	*/
5379	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5380	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5381	a_Type2 a_Arg2, a_Type3 a_Arg3))
5382	/**
5383	* Prototype version of IEM_CIMPL_DEF_4.
5384	*/
5385	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5386	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5387	a_Type2 a_Arg2, a_Type3 a_Arg3))
5388	/**
5389	* For calling a C instruction implementation function taking four extra
5390	* arguments.
5391	*
5392	* This special call macro adds default arguments to the call and allow us to
5393	* change these later.
5394	*
5395	* @param a_fn The name of the function.
5396	* @param a0 The name of the 1st argument.
5397	* @param a1 The name of the 2nd argument.
5398	* @param a2 The name of the 3rd argument.
5399	* @param a3 The name of the 4th argument.
5400	*/
5401	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
5402
5403
5404	/**
5405	* For typedef'ing or declaring a C instruction implementation function taking
5406	* five extra arguments.
5407	*
5408	* @param a_Name The name of the type.
5409	* @param a_Type0 The type of the 1st argument
5410	* @param a_Arg0 The name of the 1st argument.
5411	* @param a_Type1 The type of the 2nd argument.
5412	* @param a_Arg1 The name of the 2nd argument.
5413	* @param a_Type2 The type of the 3rd argument.
5414	* @param a_Arg2 The name of the 3rd argument.
5415	* @param a_Type3 The type of the 4th argument.
5416	* @param a_Arg3 The name of the 4th argument.
5417	* @param a_Type4 The type of the 5th argument.
5418	* @param a_Arg4 The name of the 5th argument.
5419	*/
5420	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5421	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
5422	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
5423	a_Type3 a_Arg3, a_Type4 a_Arg4))
5424	/**
5425	* For defining a C instruction implementation function taking five extra
5426	* arguments.
5427	*
5428	* @param a_Name The name of the function.
5429	* @param a_Type0 The type of the 1st argument
5430	* @param a_Arg0 The name of the 1st argument.
5431	* @param a_Type1 The type of the 2nd argument.
5432	* @param a_Arg1 The name of the 2nd argument.
5433	* @param a_Type2 The type of the 3rd argument.
5434	* @param a_Arg2 The name of the 3rd argument.
5435	* @param a_Type3 The type of the 4th argument.
5436	* @param a_Arg3 The name of the 4th argument.
5437	* @param a_Type4 The type of the 5th argument.
5438	* @param a_Arg4 The name of the 5th argument.
5439	*/
5440	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5441	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5442	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5443	/**
5444	* Prototype version of IEM_CIMPL_DEF_5.
5445	*/
5446	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5447	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5448	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5449	/**
5450	* For calling a C instruction implementation function taking five extra
5451	* arguments.
5452	*
5453	* This special call macro adds default arguments to the call and allow us to
5454	* change these later.
5455	*
5456	* @param a_fn The name of the function.
5457	* @param a0 The name of the 1st argument.
5458	* @param a1 The name of the 2nd argument.
5459	* @param a2 The name of the 3rd argument.
5460	* @param a3 The name of the 4th argument.
5461	* @param a4 The name of the 5th argument.
5462	*/
5463	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
5464
5465	/** @} */
5466
5467
5468	/** @name Opcode Decoder Function Types.
5469	* @{ */
5470
5471	/** @typedef PFNIEMOP
5472	* Pointer to an opcode decoder function.
5473	*/
5474
5475	/** @def FNIEMOP_DEF
5476	* Define an opcode decoder function.
5477	*
5478	* We're using macors for this so that adding and removing parameters as well as
5479	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
5480	*
5481	* @param a_Name The function name.
5482	*/
5483
5484	/** @typedef PFNIEMOPRM
5485	* Pointer to an opcode decoder function with RM byte.
5486	*/
5487
5488	/** @def FNIEMOPRM_DEF
5489	* Define an opcode decoder function with RM byte.
5490	*
5491	* We're using macors for this so that adding and removing parameters as well as
5492	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
5493	*
5494	* @param a_Name The function name.
5495	*/
5496
5497	#if defined(__GNUC__) && defined(RT_ARCH_X86)
5498	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
5499	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5500	# define FNIEMOP_DEF(a_Name) \
5501	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
5502	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5503	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5504	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5505	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5506
5507	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
5508	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
5509	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5510	# define FNIEMOP_DEF(a_Name) \
5511	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5512	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5513	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5514	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5515	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5516
5517	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5518	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5519	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5520	# define FNIEMOP_DEF(a_Name) \
5521	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
5522	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5523	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5524	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5525	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5526
5527	#else
5528	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5529	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5530	# define FNIEMOP_DEF(a_Name) \
5531	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5532	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5533	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5534	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5535	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5536
5537	#endif
5538	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
5539
5540	/**
5541	* Call an opcode decoder function.
5542	*
5543	* We're using macors for this so that adding and removing parameters can be
5544	* done as we please. See FNIEMOP_DEF.
5545	*/
5546	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
5547
5548	/**
5549	* Call a common opcode decoder function taking one extra argument.
5550	*
5551	* We're using macors for this so that adding and removing parameters can be
5552	* done as we please. See FNIEMOP_DEF_1.
5553	*/
5554	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
5555
5556	/**
5557	* Call a common opcode decoder function taking one extra argument.
5558	*
5559	* We're using macors for this so that adding and removing parameters can be
5560	* done as we please. See FNIEMOP_DEF_1.
5561	*/
5562	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5563	/** @} */
5564
5565
5566	/** @name Misc Helpers
5567	* @{ */
5568
5569	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5570	* due to GCC lacking knowledge about the value range of a switch. */
5571	#if RT_CPLUSPLUS_PREREQ(202000)
5572	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5573	#else
5574	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5575	#endif
5576
5577	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5578	#if RT_CPLUSPLUS_PREREQ(202000)
5579	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5580	#else
5581	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5582	#endif
5583
5584	/**
5585	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5586	* occation.
5587	*/
5588	#ifdef LOG_ENABLED
5589	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5590	do { \
5591	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5592	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5593	} while (0)
5594	#else
5595	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5596	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5597	#endif
5598
5599	/**
5600	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5601	* occation using the supplied logger statement.
5602	*
5603	* @param a_LoggerArgs What to log on failure.
5604	*/
5605	#ifdef LOG_ENABLED
5606	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5607	do { \
5608	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5609	/LogFunc(a_LoggerArgs);/ \
5610	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5611	} while (0)
5612	#else
5613	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5614	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5615	#endif
5616
5617	/**
5618	* Gets the CPU mode (from fExec) as a IEMMODE value.
5619	*
5620	* @returns IEMMODE
5621	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5622	*/
5623	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5624
5625	/**
5626	* Check if we're currently executing in real or virtual 8086 mode.
5627	*
5628	* @returns @c true if it is, @c false if not.
5629	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5630	*/
5631	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5632	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5633
5634	/**
5635	* Check if we're currently executing in virtual 8086 mode.
5636	*
5637	* @returns @c true if it is, @c false if not.
5638	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5639	*/
5640	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5641
5642	/**
5643	* Check if we're currently executing in long mode.
5644	*
5645	* @returns @c true if it is, @c false if not.
5646	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5647	*/
5648	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5649
5650	/**
5651	* Check if we're currently executing in a 16-bit code segment.
5652	*
5653	* @returns @c true if it is, @c false if not.
5654	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5655	*/
5656	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5657
5658	/**
5659	* Check if we're currently executing in a 32-bit code segment.
5660	*
5661	* @returns @c true if it is, @c false if not.
5662	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5663	*/
5664	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5665
5666	/**
5667	* Check if we're currently executing in a 64-bit code segment.
5668	*
5669	* @returns @c true if it is, @c false if not.
5670	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5671	*/
5672	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5673
5674	/**
5675	* Check if we're currently executing in real mode.
5676	*
5677	* @returns @c true if it is, @c false if not.
5678	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5679	*/
5680	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5681
5682	/**
5683	* Gets the current protection level (CPL).
5684	*
5685	* @returns 0..3
5686	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5687	*/
5688	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5689
5690	/**
5691	* Sets the current protection level (CPL).
5692	*
5693	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5694	*/
5695	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5696	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5697
5698	/**
5699	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5700	* @returns PCCPUMFEATURES
5701	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5702	*/
5703	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5704
5705	/**
5706	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5707	* @returns PCCPUMFEATURES
5708	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5709	*/
5710	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5711
5712	/**
5713	* Evaluates to true if we're presenting an Intel CPU to the guest.
5714	*/
5715	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5716
5717	/**
5718	* Evaluates to true if we're presenting an AMD CPU to the guest.
5719	*/
5720	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5721
5722	/**
5723	* Check if the address is canonical.
5724	*/
5725	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5726
5727	/** Checks if the ModR/M byte is in register mode or not. */
5728	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5729	/** Checks if the ModR/M byte is in memory mode or not. */
5730	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5731
5732	/**
5733	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5734	*
5735	* For use during decoding.
5736	*/
5737	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5738	/**
5739	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5740	*
5741	* For use during decoding.
5742	*/
5743	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5744
5745	/**
5746	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5747	*
5748	* For use during decoding.
5749	*/
5750	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5751	/**
5752	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5753	*
5754	* For use during decoding.
5755	*/
5756	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5757
5758	/**
5759	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5760	* register index, with REX.R added in.
5761	*
5762	* For use during decoding.
5763	*
5764	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5765	*/
5766	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5767	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5768	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5769	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5770	/**
5771	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5772	* with REX.B added in.
5773	*
5774	* For use during decoding.
5775	*
5776	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5777	*/
5778	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5779	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5780	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5781	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5782
5783	/**
5784	* Combines the prefix REX and ModR/M byte for passing to
5785	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5786	*
5787	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5788	* The two bits are part of the REG sub-field, which isn't needed in
5789	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5790	*
5791	* For use during decoding/recompiling.
5792	*/
5793	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5794	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5795	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5796	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5797	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5798
5799	/**
5800	* Gets the effective VEX.VVVV value.
5801	*
5802	* The 4th bit is ignored if not 64-bit code.
5803	* @returns effective V-register value.
5804	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5805	*/
5806	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5807	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5808
5809
5810	/**
5811	* Gets the register (reg) part of a the special 4th register byte used by
5812	* vblendvps and vblendvpd.
5813	*
5814	* For use during decoding.
5815	*/
5816	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5817	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5818
5819
5820	/**
5821	* Checks if we're executing inside an AMD-V or VT-x guest.
5822	*/
5823	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5824	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5825	#else
5826	# define IEM_IS_IN_GUEST(a_pVCpu) false
5827	#endif
5828
5829
5830	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5831
5832	/**
5833	* Check if the guest has entered VMX root operation.
5834	*/
5835	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5836
5837	/**
5838	* Check if the guest has entered VMX non-root operation.
5839	*/
5840	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5841	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5842
5843	/**
5844	* Check if the nested-guest has the given Pin-based VM-execution control set.
5845	*/
5846	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5847
5848	/**
5849	* Check if the nested-guest has the given Processor-based VM-execution control set.
5850	*/
5851	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5852
5853	/**
5854	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5855	* control set.
5856	*/
5857	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5858
5859	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5860	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5861
5862	/** Whether a shadow VMCS is present for the given VCPU. */
5863	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5864
5865	/** Gets the VMXON region pointer. */
5866	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5867
5868	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5869	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5870
5871	/** Whether a current VMCS is present for the given VCPU. */
5872	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5873
5874	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5875	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5876	do \
5877	{ \
5878	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5879	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5880	} while (0)
5881
5882	/** Clears any current VMCS for the given VCPU. */
5883	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5884	do \
5885	{ \
5886	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5887	} while (0)
5888
5889	/**
5890	* Invokes the VMX VM-exit handler for an instruction intercept.
5891	*/
5892	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5893	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5894
5895	/**
5896	* Invokes the VMX VM-exit handler for an instruction intercept where the
5897	* instruction provides additional VM-exit information.
5898	*/
5899	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5900	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5901
5902	/**
5903	* Invokes the VMX VM-exit handler for a task switch.
5904	*/
5905	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5906	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5907
5908	/**
5909	* Invokes the VMX VM-exit handler for MWAIT.
5910	*/
5911	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5912	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5913
5914	/**
5915	* Invokes the VMX VM-exit handler for EPT faults.
5916	*/
5917	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5918	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5919
5920	/**
5921	* Invokes the VMX VM-exit handler.
5922	*/
5923	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5924	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5925
5926	#else
5927	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5928	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5929	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5930	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5931	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5932	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5933	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5934	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5935	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5936	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5937	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5938
5939	#endif
5940
5941	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5942	/**
5943	* Checks if we're executing a guest using AMD-V.
5944	*/
5945	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5946	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5947	/**
5948	* Check if an SVM control/instruction intercept is set.
5949	*/
5950	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5951	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5952
5953	/**
5954	* Check if an SVM read CRx intercept is set.
5955	*/
5956	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5957	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5958
5959	/**
5960	* Check if an SVM write CRx intercept is set.
5961	*/
5962	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5963	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5964
5965	/**
5966	* Check if an SVM read DRx intercept is set.
5967	*/
5968	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5969	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5970
5971	/**
5972	* Check if an SVM write DRx intercept is set.
5973	*/
5974	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5975	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5976
5977	/**
5978	* Check if an SVM exception intercept is set.
5979	*/
5980	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5981	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5982
5983	/**
5984	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5985	*/
5986	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5987	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5988
5989	/**
5990	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5991	* corresponding decode assist information.
5992	*/
5993	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5994	do \
5995	{ \
5996	uint64_t uExitInfo1; \
5997	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5998	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5999	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
6000	else \
6001	uExitInfo1 = 0; \
6002	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
6003	} while (0)
6004
6005	/** Check and handles SVM nested-guest instruction intercept and updates
6006	* NRIP if needed.
6007	*/
6008	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
6009	do \
6010	{ \
6011	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
6012	{ \
6013	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
6014	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
6015	} \
6016	} while (0)
6017
6018	/** Checks and handles SVM nested-guest CR0 read intercept. */
6019	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
6020	do \
6021	{ \
6022	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
6023	{ /* probably likely */ } \
6024	else \
6025	{ \
6026	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
6027	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
6028	} \
6029	} while (0)
6030
6031	/**
6032	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
6033	*/
6034	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
6035	do { \
6036	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
6037	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
6038	} while (0)
6039
6040	#else
6041	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
6042	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
6043	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
6044	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
6045	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
6046	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
6047	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
6048	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
6049	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
6050	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
6051	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
6052	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
6053
6054	#endif
6055
6056	/** @} */
6057
6058	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
6059	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
6060
6061
6062	/**
6063	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
6064	*/
6065	typedef union IEMSELDESC
6066	{
6067	/** The legacy view. */
6068	X86DESC Legacy;
6069	/** The long mode view. */
6070	X86DESC64 Long;
6071	} IEMSELDESC;
6072	/** Pointer to a selector descriptor table entry. */
6073	typedef IEMSELDESC *PIEMSELDESC;
6074
6075	/** @name Raising Exceptions.
6076	* @{ */
6077	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
6078	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
6079
6080	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
6081	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6082	#ifdef IEM_WITH_SETJMP
6083	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
6084	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
6085	#endif
6086	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
6087	#ifdef IEM_WITH_SETJMP
6088	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6089	#endif
6090	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6091	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
6092	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
6093	#ifdef IEM_WITH_SETJMP
6094	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6095	#endif
6096	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
6097	#ifdef IEM_WITH_SETJMP
6098	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6099	#endif
6100	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6101	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
6102	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
6103	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6104	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
6105	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6106	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6107	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6108	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6109	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6110	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
6111	#ifdef IEM_WITH_SETJMP
6112	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6113	#endif
6114	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
6115	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
6116	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
6117	#ifdef IEM_WITH_SETJMP
6118	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
6119	#endif
6120	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
6121	#ifdef IEM_WITH_SETJMP
6122	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
6123	#endif
6124	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
6125	#ifdef IEM_WITH_SETJMP
6126	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
6127	#endif
6128	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
6129	#ifdef IEM_WITH_SETJMP
6130	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
6131	#endif
6132	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6133	#ifdef IEM_WITH_SETJMP
6134	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6135	#endif
6136	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6137	#ifdef IEM_WITH_SETJMP
6138	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6139	#endif
6140	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6141	#ifdef IEM_WITH_SETJMP
6142	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6143	#endif
6144
6145	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6146	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6147
6148	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
6149	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
6150	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
6151
6152	/**
6153	* Macro for calling iemCImplRaiseDivideError().
6154	*
6155	* This is for things that will _always_ decode to an \#DE, taking the
6156	* recompiler into consideration and everything.
6157	*
6158	* @return Strict VBox status code.
6159	*/
6160	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
6161
6162	/**
6163	* Macro for calling iemCImplRaiseInvalidLockPrefix().
6164	*
6165	* This is for things that will _always_ decode to an \#UD, taking the
6166	* recompiler into consideration and everything.
6167	*
6168	* @return Strict VBox status code.
6169	*/
6170	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
6171
6172	/**
6173	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
6174	*
6175	* This is for things that will _always_ decode to an \#UD, taking the
6176	* recompiler into consideration and everything.
6177	*
6178	* @return Strict VBox status code.
6179	*/
6180	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6181
6182	/**
6183	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
6184	*
6185	* Using this macro means you've got _buggy_ _code_ and are doing things that
6186	* belongs exclusively in IEMAllCImpl.cpp during decoding.
6187	*
6188	* @return Strict VBox status code.
6189	* @see IEMOP_RAISE_INVALID_OPCODE_RET
6190	*/
6191	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6192
6193	/** @} */
6194
6195	/** @name Register Access.
6196	* @{ */
6197	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
6198	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6199	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
6200	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
6201	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6202	/** @} */
6203
6204	/** @name FPU access and helpers.
6205	* @{ */
6206	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6207	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6208	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6209	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6210	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6211	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6212	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6213	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6214	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6215	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6216	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6217	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6218	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6219	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6220	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6221	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6222	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6223	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6224	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6225	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6226	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6227	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6228	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6229	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6230	/** @} */
6231
6232	/** @name SSE+AVX SIMD access and helpers.
6233	* @{ */
6234	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
6235	/** @} */
6236
6237	/** @name Memory access.
6238	* @{ */
6239
6240	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
6241	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
6242	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
6243	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
6244	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
6245	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
6246	* Users include FXSAVE & FXRSTOR. */
6247	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
6248
6249	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
6250	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
6251	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6252	#ifndef IN_RING3
6253	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6254	#endif
6255	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6256	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
6257	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
6258	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6259	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
6260
6261	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
6262	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
6263	#ifdef IEM_WITH_CODE_TLB
6264	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
6265	#else
6266	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
6267	#endif
6268	#ifdef IEM_WITH_SETJMP
6269	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6270	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6271	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6272	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6273	#else
6274	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
6275	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6276	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6277	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6278	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6279	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6280	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6281	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6282	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6283	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6284	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6285	#endif
6286
6287	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6288	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6289	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6290	VBOXSTRICTRC iemMemFetchDataU32NoAc(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6291	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6292	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6293	VBOXSTRICTRC iemMemFetchDataU64NoAc(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6294	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6295	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6296	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6297	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6298	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6299	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6300	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6301	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6302	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6303	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
6304	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
6305	#ifdef IEM_WITH_SETJMP
6306	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6307	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6308	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6309	uint32_t iemMemFetchDataU32NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6310	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6311	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6312	uint64_t iemMemFetchDataU64NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6313	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6314	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6315	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6316	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6317	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6318	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6319	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6320	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6321	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6322	# if 0 /* these are inlined now */
6323	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6324	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6325	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6326	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6327	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6328	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6329	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6330	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6331	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6332	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6333	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6334	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6335	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6336	# endif
6337	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6338	#endif
6339
6340	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6341	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6342	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6343	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6344	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
6345
6346	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
6347	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
6348	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
6349	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
6350	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6351	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6352	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6353	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6354	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6355	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6356	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6357	#ifdef IEM_WITH_SETJMP
6358	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6359	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6360	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6361	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6362	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6363	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6364	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6365	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6366	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6367	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6368	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6369	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6370	#if 0
6371	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6372	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6373	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6374	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6375	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6376	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6377	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6378	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6379	#endif
6380	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6381	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6382	#endif
6383
6384	#ifdef IEM_WITH_SETJMP
6385	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6386	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6387	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6388	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6389	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6390	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6391	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6392	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6393	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6394	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6395	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6396	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6397	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6398	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6399	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6400	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6401	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6402	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6403	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6404	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6405	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6406	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6407	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6408	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6409	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6410	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6411
6412	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6413	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6414	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6415	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6416	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6417	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6418	#endif
6419
6420	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6421	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6422	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
6423	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
6424	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6425	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
6426	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6427	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6428	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6429	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6430	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6431	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6432	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
6433	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
6434	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6435	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
6436	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
6437	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
6438	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6439	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6440	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6441
6442	#ifdef IEM_WITH_SETJMP
6443	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6444	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6445	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6446	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6447	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6448	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6449	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6450
6451	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6452	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6453	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6454	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6455	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6456
6457	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6458	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6459	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6460	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6461
6462	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6463	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6464	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6465	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6466
6467	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6468	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6469	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6470
6471	#endif
6472
6473	/** @} */
6474
6475	/** @name IEMAllCImpl.cpp
6476	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
6477	* @{ */
6478	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6479	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6480	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6481	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
6482	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
6483	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
6484	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
6485	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
6486	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
6487	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6488	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6489	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6490	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
6491	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
6492	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
6493	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
6494	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
6495	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
6496	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
6497	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
6498	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
6499	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
6500	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
6501	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
6502	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
6503	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
6504	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
6505	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
6506	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
6507	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
6508	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
6509	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
6510	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
6511	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
6512	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
6513	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6514	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6515	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6516	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6517	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
6518	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6519	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6520	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
6521	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6522	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6523	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
6524	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6525	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6526	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
6527	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
6528	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
6529	IEM_CIMPL_PROTO_0(iemCImpl_clts);
6530	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
6531	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
6532	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
6533	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
6534	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
6535	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
6536	IEM_CIMPL_PROTO_0(iemCImpl_invd);
6537	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
6538	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
6539	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
6540	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
6541	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
6542	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
6543	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
6544	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6545	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6546	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6547	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6548	IEM_CIMPL_PROTO_0(iemCImpl_cli);
6549	IEM_CIMPL_PROTO_0(iemCImpl_sti);
6550	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
6551	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
6552	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
6553	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
6554	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
6555	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
6556	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
6557	IEM_CIMPL_PROTO_0(iemCImpl_daa);
6558	IEM_CIMPL_PROTO_0(iemCImpl_das);
6559	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
6560	IEM_CIMPL_PROTO_0(iemCImpl_aas);
6561	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
6562	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
6563	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
6564	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
6565	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
6566	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
6567	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6568	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
6569	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6570	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6571	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6572	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6573	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6574	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6575	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6576	IEM_CIMPL_PROTO_2(iemCImpl_vldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6577	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6578	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6579	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6580	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6581	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6582	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6583	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6584	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6585	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6586	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6587	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6588	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6589	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6590	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6591	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6592	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6593	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6594	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6595	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6596	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6597	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6598	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6599	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6600	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6601	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6602	IEM_CIMPL_PROTO_2(iemCImpl_vpgather_worker_xx, uint32_t, u32PackedArgs, uint32_t, u32Disp);
6603
6604	/** @} */
6605
6606	/** @name IEMAllCImplStrInstr.cpp.h
6607	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6608	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6609	* @{ */
6610	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6611	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6612	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6613	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6614	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6615	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6616	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6617	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6618	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6619	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6620	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6621
6622	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6623	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6624	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6625	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6626	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6627	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6628	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6629	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6630	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6631	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6632	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6633
6634	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6635	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6636	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6637	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6638	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6639	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6640	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6641	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6642	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6643	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6644	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6645
6646
6647	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6648	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6649	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6650	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6651	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6652	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6653	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6654	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6655	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6656	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6657	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6658
6659	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6660	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6661	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6662	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6663	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6664	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6665	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6666	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6667	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6668	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6669	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6670
6671	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6672	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6673	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6674	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6675	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6676	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6677	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6678	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6679	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6680	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6681	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6682
6683	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6684	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6685	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6686	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6687	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6688	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6689	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6690	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6691	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6692	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6693	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6694
6695
6696	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6697	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6698	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6699	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6700	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6701	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6702	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6703	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6704	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6705	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6706	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6707
6708	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6709	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6710	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6711	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6712	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6713	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6714	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6715	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6716	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6717	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6718	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6719
6720	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6721	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6722	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6723	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6724	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6725	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6726	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6727	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6728	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6729	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6730	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6731
6732	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6733	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6734	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6735	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6736	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6737	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6738	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6739	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6740	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6741	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6742	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6743	/** @} */
6744
6745	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6746	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6747	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6748	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6749	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6750	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6751	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6752	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6753	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6754	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6755	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6756	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6757	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6758	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6759	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6760	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6761	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6762	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6763	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6764	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6765	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6766	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6767	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6768	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6769	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6770	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6771	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6772	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6773	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6774	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6775	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6776	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6777	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6778	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6779	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6780	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6781	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6782	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6783	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6784	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6785	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6786	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6787	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6788	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6789	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6790	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6791	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6792	#endif
6793
6794	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6795	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6796	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6797	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6798	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6799	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6800	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6801	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6802	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6803	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6804	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6805	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6806	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6807	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6808	#endif
6809
6810	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6811	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6812	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6813
6814	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6815	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6816	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6817	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6818	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6819	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6820	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6821
6822	/*
6823	* Recompiler related stuff.
6824	*/
6825	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6826	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6827	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6828	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6829	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6830	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6831	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6832
6833	DECLHIDDEN(int) iemPollTimers(PVMCC pVM, PVMCPUCC pVCpu) RT_NOEXCEPT;
6834
6835	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6836	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6837	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6838	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6839	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6840	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6841	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6842	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6843
6844
6845	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6846	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6847	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6848	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6849	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6850	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6851	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6852	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6853
6854	#else
6855	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6856	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6857	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6858	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6859	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6860	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6861	#endif
6862
6863
6864	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6865	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6866
6867	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6868
6869	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6870	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckTimers);
6871	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckTimersAndIrq);
6872	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6873	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6874	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6875
6876	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6877	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6878	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6879
6880	/* Branching: */
6881	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6882	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6883	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6884
6885	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6886	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6887	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6888
6889	/* Natural page crossing: */
6890	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6891	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6892	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6893
6894	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6895	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6896	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6897
6898	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6899	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6900	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6901
6902	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Jump);
6903
6904	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6905	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6906	#ifdef IEM_WITH_INTRA_TB_JUMPS
6907	DECLHIDDEN(int) iemThreadedCompileBackAtFirstInstruction(PVMCPU pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6908	#endif
6909
6910	/* Native recompiler public bits: */
6911
6912	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6913	DECLHIDDEN(void) iemNativeDisassembleTb(PVMCPU pVCpu, PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6914	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6915	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, PIEMNATIVEINSTR *ppaExec,
6916	struct IEMNATIVEPERCHUNKCTX const **ppChunkCtx) RT_NOEXCEPT;
6917	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAllocFromChunk(PVMCPU pVCpu, uint32_t idxChunk, uint32_t cbReq,
6918	PIEMNATIVEINSTR *ppaExec);
6919	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6920	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6921	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6922	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemExecMemGetTbChunkCtx(PVMCPU pVCpu, PCIEMTB pTb);
6923	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemNativeRecompileAttachExecMemChunkCtx(PVMCPU pVCpu, uint32_t idxChunk);
6924
6925	/** Packed 32-bit argument for iemCImpl_vpgather_worker_xx. */
6926	typedef union IEMGATHERARGS
6927	{
6928	/** Integer view. */
6929	uint32_t u;
6930	/** Bitfield view. */
6931	struct
6932	{
6933	uint32_t iYRegDst : 4; /*< 0 - XMM or YMM register number (destination) /
6934	uint32_t iYRegIdc : 4; /*< 4 - XMM or YMM register number (indices) /
6935	uint32_t iYRegMsk : 4; /*< 8 - XMM or YMM register number (mask) /
6936	uint32_t iGRegBase : 4; /*< 12 - general register number (base ptr) /
6937	uint32_t iScale : 2; /*< 16 - scale factor (1/2/4/8) /
6938	uint32_t enmEffOpSize : 2; /*< 18 - operand size (16/32/64/--) /
6939	uint32_t enmEffAddrMode : 2; /*< 20 - addressing mode (16/32/64/--) /
6940	uint32_t iEffSeg : 3; /*< 22 - effective segment (ES/CS/SS/DS/FS/GS) /
6941	uint32_t fVex256 : 1; /*< 25 - overall instruction width (128/256 bits) /
6942	uint32_t fIdxQword : 1; /*< 26 - individual index width (4/8 bytes) /
6943	uint32_t fValQword : 1; /*< 27 - individual value width (4/8 bytes) /
6944	} s;
6945	} IEMGATHERARGS;
6946	AssertCompileSize(IEMGATHERARGS, sizeof(uint32_t));
6947
6948	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6949
6950
6951	/** @} */
6952
6953	RT_C_DECLS_END
6954
6955	/* ASM-INC: %include "IEMInternalStruct.mac" */
6956
6957	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6958

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 106054

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