IEMInternal.h@ 101984

Last change on this file since 101984 was 101984, checked in by vboxsync, 16 months ago
VMM/IEM: Added a flush mask for guest register shadows to the IEM_MC_DEFER_TO_CIMPL_X_RET macros to better manage register optimizations when recompiling to native code. bugref:10371
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 284.4 KB

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1	/* $Id: IEMInternal.h 101984 2023-11-08 15:56:18Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEM_DO_LONGJMP
89	*
90	* Wrapper around longjmp / throw.
91	*
92	* @param a_pVCpu The CPU handle.
93	* @param a_rc The status code jump back with / throw.
94	*/
95	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
96	# ifdef IEM_WITH_THROW_CATCH
97	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
98	# else
99	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
100	# endif
101	#endif
102
103	/** For use with IEM function that may do a longjmp (when enabled).
104	*
105	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
106	* attribute. So, we indicate that function that may be part of a longjmp may
107	* throw "exceptions" and that the compiler should definitely not generate and
108	* std::terminate calling unwind code.
109	*
110	* Here is one example of this ending in std::terminate:
111	* @code{.txt}
112	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
113	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
114	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
115	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
116	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
117	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
118	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
119	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
120	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
121	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
122	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
123	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
124	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
125	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
126	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
127	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
128	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
129	@endcode
130	*
131	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
132	*/
133	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
134	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
135	#else
136	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
137	#endif
138
139	#define IEM_IMPLEMENTS_TASKSWITCH
140
141	/** @def IEM_WITH_3DNOW
142	* Includes the 3DNow decoding. */
143	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
144	# define IEM_WITH_3DNOW
145	#endif
146
147	/** @def IEM_WITH_THREE_0F_38
148	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
149	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
150	# define IEM_WITH_THREE_0F_38
151	#endif
152
153	/** @def IEM_WITH_THREE_0F_3A
154	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
155	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
156	# define IEM_WITH_THREE_0F_3A
157	#endif
158
159	/** @def IEM_WITH_VEX
160	* Includes the VEX decoding. */
161	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
162	# define IEM_WITH_VEX
163	#endif
164
165	/** @def IEM_CFG_TARGET_CPU
166	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
167	*
168	* By default we allow this to be configured by the user via the
169	* CPUM/GuestCpuName config string, but this comes at a slight cost during
170	* decoding. So, for applications of this code where there is no need to
171	* be dynamic wrt target CPU, just modify this define.
172	*/
173	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
174	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
175	#endif
176
177	//#define IEM_WITH_CODE_TLB // - work in progress
178	//#define IEM_WITH_DATA_TLB // - work in progress
179
180
181	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
182	* Use unaligned accesses instead of elaborate byte assembly. */
183	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
184	# define IEM_USE_UNALIGNED_DATA_ACCESS
185	#endif
186
187	//#define IEM_LOG_MEMORY_WRITES
188
189	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
190	/** Instruction statistics. */
191	typedef struct IEMINSTRSTATS
192	{
193	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
194	# include "IEMInstructionStatisticsTmpl.h"
195	# undef IEM_DO_INSTR_STAT
196	} IEMINSTRSTATS;
197	#else
198	struct IEMINSTRSTATS;
199	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
200	#endif
201	/** Pointer to IEM instruction statistics. */
202	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
203
204
205	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
206	* @{ */
207	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
211	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
212	/** Selects the right variant from a_aArray.
213	* pVCpu is implicit in the caller context. */
214	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
215	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
217	* be used because the host CPU does not support the operation. */
218	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
219	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
220	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
221	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
222	* into the two.
223	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
224	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
225	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
226	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
227	#else
228	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
229	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
230	#endif
231	/** @} */
232
233	/**
234	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
235	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
236	*
237	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
238	* indicator.
239	*
240	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
241	*/
242	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
243	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
244	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
245	#else
246	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
247	#endif
248
249
250	/**
251	* Extended operand mode that includes a representation of 8-bit.
252	*
253	* This is used for packing down modes when invoking some C instruction
254	* implementations.
255	*/
256	typedef enum IEMMODEX
257	{
258	IEMMODEX_16BIT = IEMMODE_16BIT,
259	IEMMODEX_32BIT = IEMMODE_32BIT,
260	IEMMODEX_64BIT = IEMMODE_64BIT,
261	IEMMODEX_8BIT
262	} IEMMODEX;
263	AssertCompileSize(IEMMODEX, 4);
264
265
266	/**
267	* Branch types.
268	*/
269	typedef enum IEMBRANCH
270	{
271	IEMBRANCH_JUMP = 1,
272	IEMBRANCH_CALL,
273	IEMBRANCH_TRAP,
274	IEMBRANCH_SOFTWARE_INT,
275	IEMBRANCH_HARDWARE_INT
276	} IEMBRANCH;
277	AssertCompileSize(IEMBRANCH, 4);
278
279
280	/**
281	* INT instruction types.
282	*/
283	typedef enum IEMINT
284	{
285	/** INT n instruction (opcode 0xcd imm). */
286	IEMINT_INTN = 0,
287	/** Single byte INT3 instruction (opcode 0xcc). */
288	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
289	/** Single byte INTO instruction (opcode 0xce). */
290	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
291	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
292	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
293	} IEMINT;
294	AssertCompileSize(IEMINT, 4);
295
296
297	/**
298	* A FPU result.
299	*/
300	typedef struct IEMFPURESULT
301	{
302	/** The output value. */
303	RTFLOAT80U r80Result;
304	/** The output status. */
305	uint16_t FSW;
306	} IEMFPURESULT;
307	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
308	/** Pointer to a FPU result. */
309	typedef IEMFPURESULT *PIEMFPURESULT;
310	/** Pointer to a const FPU result. */
311	typedef IEMFPURESULT const *PCIEMFPURESULT;
312
313
314	/**
315	* A FPU result consisting of two output values and FSW.
316	*/
317	typedef struct IEMFPURESULTTWO
318	{
319	/** The first output value. */
320	RTFLOAT80U r80Result1;
321	/** The output status. */
322	uint16_t FSW;
323	/** The second output value. */
324	RTFLOAT80U r80Result2;
325	} IEMFPURESULTTWO;
326	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
327	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
328	/** Pointer to a FPU result consisting of two output values and FSW. */
329	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
330	/** Pointer to a const FPU result consisting of two output values and FSW. */
331	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
332
333
334	/**
335	* IEM TLB entry.
336	*
337	* Lookup assembly:
338	* @code{.asm}
339	; Calculate tag.
340	mov rax, [VA]
341	shl rax, 16
342	shr rax, 16 + X86_PAGE_SHIFT
343	or rax, [uTlbRevision]
344
345	; Do indexing.
346	movzx ecx, al
347	lea rcx, [pTlbEntries + rcx]
348
349	; Check tag.
350	cmp [rcx + IEMTLBENTRY.uTag], rax
351	jne .TlbMiss
352
353	; Check access.
354	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
355	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
356	cmp rax, [uTlbPhysRev]
357	jne .TlbMiss
358
359	; Calc address and we're done.
360	mov eax, X86_PAGE_OFFSET_MASK
361	and eax, [VA]
362	or rax, [rcx + IEMTLBENTRY.pMappingR3]
363	%ifdef VBOX_WITH_STATISTICS
364	inc qword [cTlbHits]
365	%endif
366	jmp .Done
367
368	.TlbMiss:
369	mov r8d, ACCESS_FLAGS
370	mov rdx, [VA]
371	mov rcx, [pVCpu]
372	call iemTlbTypeMiss
373	.Done:
374
375	@endcode
376	*
377	*/
378	typedef struct IEMTLBENTRY
379	{
380	/** The TLB entry tag.
381	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
382	* is ASSUMING a virtual address width of 48 bits.
383	*
384	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
385	*
386	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
387	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
388	* revision wraps around though, the tags needs to be zeroed.
389	*
390	* @note Try use SHRD instruction? After seeing
391	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
392	*
393	* @todo This will need to be reorganized for 57-bit wide virtual address and
394	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
395	* have to move the TLB entry versioning entirely to the
396	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
397	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
398	* consumed by PCID and ASID (12 + 6 = 18).
399	*/
400	uint64_t uTag;
401	/** Access flags and physical TLB revision.
402	*
403	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
404	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
405	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
406	* - Bit 3 - pgm phys/virt - not directly writable.
407	* - Bit 4 - pgm phys page - not directly readable.
408	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
409	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
410	* - Bit 7 - tlb entry - pMappingR3 member not valid.
411	* - Bits 63 thru 8 are used for the physical TLB revision number.
412	*
413	* We're using complemented bit meanings here because it makes it easy to check
414	* whether special action is required. For instance a user mode write access
415	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
416	* non-zero result would mean special handling needed because either it wasn't
417	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
418	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
419	* need to check any PTE flag.
420	*/
421	uint64_t fFlagsAndPhysRev;
422	/** The guest physical page address. */
423	uint64_t GCPhys;
424	/** Pointer to the ring-3 mapping. */
425	R3PTRTYPE(uint8_t *) pbMappingR3;
426	#if HC_ARCH_BITS == 32
427	uint32_t u32Padding1;
428	#endif
429	} IEMTLBENTRY;
430	AssertCompileSize(IEMTLBENTRY, 32);
431	/** Pointer to an IEM TLB entry. */
432	typedef IEMTLBENTRY *PIEMTLBENTRY;
433
434	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
435	* @{ */
436	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
437	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
438	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
439	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
440	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
441	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
442	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
443	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
444	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
445	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
446	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
447	/** @} */
448
449
450	/**
451	* An IEM TLB.
452	*
453	* We've got two of these, one for data and one for instructions.
454	*/
455	typedef struct IEMTLB
456	{
457	/** The TLB entries.
458	* We've choosen 256 because that way we can obtain the result directly from a
459	* 8-bit register without an additional AND instruction. */
460	IEMTLBENTRY aEntries[256];
461	/** The TLB revision.
462	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
463	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
464	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
465	* (The revision zero indicates an invalid TLB entry.)
466	*
467	* The initial value is choosen to cause an early wraparound. */
468	uint64_t uTlbRevision;
469	/** The TLB physical address revision - shadow of PGM variable.
470	*
471	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
472	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
473	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
474	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
475	*
476	* The initial value is choosen to cause an early wraparound. */
477	uint64_t volatile uTlbPhysRev;
478
479	/* Statistics: */
480
481	/** TLB hits (VBOX_WITH_STATISTICS only). */
482	uint64_t cTlbHits;
483	/** TLB misses. */
484	uint32_t cTlbMisses;
485	/** Slow read path. */
486	uint32_t cTlbSlowReadPath;
487	/** Safe read path. */
488	uint32_t cTlbSafeReadPath;
489	/** Safe write path. */
490	uint32_t cTlbSafeWritePath;
491	#if 0
492	/** TLB misses because of tag mismatch. */
493	uint32_t cTlbMissesTag;
494	/** TLB misses because of virtual access violation. */
495	uint32_t cTlbMissesVirtAccess;
496	/** TLB misses because of dirty bit. */
497	uint32_t cTlbMissesDirty;
498	/** TLB misses because of MMIO */
499	uint32_t cTlbMissesMmio;
500	/** TLB misses because of write access handlers. */
501	uint32_t cTlbMissesWriteHandler;
502	/** TLB misses because no r3(/r0) mapping. */
503	uint32_t cTlbMissesMapping;
504	#endif
505	/** Alignment padding. */
506	uint32_t au32Padding[6];
507	} IEMTLB;
508	AssertCompileSizeAlignment(IEMTLB, 64);
509	/** IEMTLB::uTlbRevision increment. */
510	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
511	/** IEMTLB::uTlbRevision mask. */
512	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
513	/** IEMTLB::uTlbPhysRev increment.
514	* @sa IEMTLBE_F_PHYS_REV */
515	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
516	/**
517	* Calculates the TLB tag for a virtual address.
518	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
519	* @param a_pTlb The TLB.
520	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
521	* the clearing of the top 16 bits won't work (if 32-bit
522	* we'll end up with mostly zeros).
523	*/
524	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
525	/**
526	* Calculates the TLB tag for a virtual address but without TLB revision.
527	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
528	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
529	* the clearing of the top 16 bits won't work (if 32-bit
530	* we'll end up with mostly zeros).
531	*/
532	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
533	/**
534	* Converts a TLB tag value into a TLB index.
535	* @returns Index into IEMTLB::aEntries.
536	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
537	*/
538	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
539	/**
540	* Converts a TLB tag value into a TLB index.
541	* @returns Index into IEMTLB::aEntries.
542	* @param a_pTlb The TLB.
543	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
544	*/
545	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
546
547
548	/** @name IEM_MC_F_XXX - MC block flags/clues.
549	* @todo Merge with IEM_CIMPL_F_XXX
550	* @{ */
551	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
552	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
553	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
554	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
555	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
556	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
557	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
558	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
559	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
560	#define IEM_MC_F_64BIT RT_BIT_32(6)
561	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
562	/** @} */
563
564	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
565	*
566	* These clues are mainly for the recompiler, so that it can emit correct code.
567	*
568	* They are processed by the python script and which also automatically
569	* calculates flags for MC blocks based on the statements, extending the use of
570	* these flags to describe MC block behavior to the recompiler core. The python
571	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
572	* error checking purposes. The script emits the necessary fEndTb = true and
573	* similar statements as this reduces compile time a tiny bit.
574	*
575	* @{ */
576	/** Flag set if direct branch, clear if absolute or indirect. */
577	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
578	/** Flag set if indirect branch, clear if direct or relative.
579	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
580	* as well as for return instructions (RET, IRET, RETF). */
581	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
582	/** Flag set if relative branch, clear if absolute or indirect. */
583	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
584	/** Flag set if conditional branch, clear if unconditional. */
585	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
586	/** Flag set if it's a far branch (changes CS). */
587	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
588	/** Convenience: Testing any kind of branch. */
589	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
590
591	/** Execution flags may change (IEMCPU::fExec). */
592	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
593	/** May change significant portions of RFLAGS. */
594	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
595	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
596	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
597	/** May trigger interrupt shadowing. */
598	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
599	/** May enable interrupts, so recheck IRQ immediately afterwards executing
600	* the instruction. */
601	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
602	/** May disable interrupts, so recheck IRQ immediately before executing the
603	* instruction. */
604	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
605	/** Convenience: Check for IRQ both before and after an instruction. */
606	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
607	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
608	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
609	/** May modify FPU state.
610	* @todo Not sure if this is useful yet. */
611	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
612	/** REP prefixed instruction which may yield before updating PC.
613	* @todo Not sure if this is useful, REP functions now return non-zero
614	* status if they don't update the PC. */
615	#define IEM_CIMPL_F_REP RT_BIT_32(13)
616	/** I/O instruction.
617	* @todo Not sure if this is useful yet. */
618	#define IEM_CIMPL_F_IO RT_BIT_32(14)
619	/** Force end of TB after the instruction. */
620	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
621	/** Flag set if a branch may also modify the stack (push/pop return address). */
622	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
623	/** Flag set if a branch may also modify the stack (push/pop return address)
624	* and switch it (load/restore SS:RSP). */
625	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
626	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
627	#define IEM_CIMPL_F_XCPT \
628	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
629	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
630
631	/** The block calls a C-implementation instruction function with two implicit arguments.
632	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
633	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
634	* @note The python scripts will add this is missing. */
635	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
636	/** The block calls an ASM-implementation instruction function.
637	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
638	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
639	* @note The python scripts will add this is missing. */
640	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
641	/** The block calls an ASM-implementation instruction function with an implicit
642	* X86FXSTATE pointer argument.
643	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and IEM_CIMPL_F_CALLS_AIMPL.
644	* @note The python scripts will add this is missing. */
645	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
646	/** @} */
647
648
649	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
650	*
651	* These flags are set when entering IEM and adjusted as code is executed, such
652	* that they will always contain the current values as instructions are
653	* finished.
654	*
655	* In recompiled execution mode, (most of) these flags are included in the
656	* translation block selection key and stored in IEMTB::fFlags alongside the
657	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
658	* in IEMCPU::fExec.
659	*
660	* @{ */
661	/** Mode: The block target mode mask. */
662	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
663	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
664	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
665	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
666	* conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
667	* 32-bit mode (for simplifying most memory accesses). */
668	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
669	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
670	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
671	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
672	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
673
674	/** X86 Mode: 16-bit on 386 or later. */
675	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
676	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
677	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
678	/** X86 Mode: 16-bit protected mode on 386 or later. */
679	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
680	/** X86 Mode: 16-bit protected mode on 386 or later. */
681	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
682	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
683	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
684
685	/** X86 Mode: 32-bit on 386 or later. */
686	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
687	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
688	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
689	/** X86 Mode: 32-bit protected mode. */
690	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
691	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
692	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
693
694	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
695	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
696
697
698	/** Bypass access handlers when set. */
699	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
700	/** Have pending hardware instruction breakpoints. */
701	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
702	/** Have pending hardware data breakpoints. */
703	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
704
705	/** X86: Have pending hardware I/O breakpoints. */
706	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
707	/** X86: Disregard the lock prefix (implied or not) when set. */
708	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
709
710	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
711	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
712
713	/** Caller configurable options. */
714	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
715
716	/** X86: The current protection level (CPL) shift factor. */
717	#define IEM_F_X86_CPL_SHIFT 8
718	/** X86: The current protection level (CPL) mask. */
719	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
720	/** X86: The current protection level (CPL) shifted mask. */
721	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
722
723	/** X86 execution context.
724	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
725	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
726	* mode. */
727	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
728	/** X86 context: Plain regular execution context. */
729	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
730	/** X86 context: VT-x enabled. */
731	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
732	/** X86 context: AMD-V enabled. */
733	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
734	/** X86 context: In AMD-V or VT-x guest mode. */
735	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
736	/** X86 context: System management mode (SMM). */
737	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
738
739	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
740	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
741	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
742	* alread). */
743
744	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
745	* iemRegFinishClearingRF() most for most situations
746	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
747	* the IEM_F_PENDING_BRK_XXX bits alread). */
748
749	/** @} */
750
751
752	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
753	*
754	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
755	* translation block flags. The combined flag mask (subject to
756	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
757	*
758	* @{ */
759	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
760	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
761
762	/** Type: The block type mask. */
763	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
764	/** Type: Purly threaded recompiler (via tables). */
765	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
766	/** Type: Native recompilation. */
767	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
768
769	/** Set when we're starting the block in an "interrupt shadow".
770	* We don't need to distingish between the two types of this mask, thus the one.
771	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
772	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
773	/** Set when we're currently inhibiting NMIs
774	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
775	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
776
777	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
778	* we're close the limit before starting a TB, as determined by
779	* iemGetTbFlagsForCurrentPc(). */
780	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
781
782	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
783	* @note We skip the CPL as we don't currently generate ring-specific code,
784	* that's all handled in CIMPL functions.
785	*
786	* For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
787	* exception of SMM (which we don't implement). */
788	#define IEMTB_F_KEY_MASK ( (UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEM_F_X86_CPL_MASK \| IEMTB_F_TYPE_MASK)) \
789	\| IEM_F_X86_CTX_SMM)
790	/** @} */
791
792	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
793	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
794	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
795	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
796	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
797	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
798	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
799	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
800	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
801	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
802	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
803	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
804	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
805	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
806	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
807	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
808	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
809	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
810	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
811
812	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
813	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
814	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
815	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
816	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
817	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
818	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
819	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
820	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
821	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
822	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
823	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
824
825	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
826	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
827	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
828
829	/** Native instruction type for use with the native code generator.
830	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
831	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
832	typedef uint8_t IEMNATIVEINSTR;
833	#else
834	typedef uint32_t IEMNATIVEINSTR;
835	#endif
836	/** Pointer to a native instruction unit. */
837	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
838	/** Pointer to a const native instruction unit. */
839	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
840
841	/**
842	* A call for the threaded call table.
843	*/
844	typedef struct IEMTHRDEDCALLENTRY
845	{
846	/** The function to call (IEMTHREADEDFUNCS). */
847	uint16_t enmFunction;
848	/** Instruction number in the TB (for statistics). */
849	uint8_t idxInstr;
850	uint8_t uUnused0;
851
852	/** Offset into IEMTB::pabOpcodes. */
853	uint16_t offOpcode;
854	/** The opcode length. */
855	uint8_t cbOpcode;
856	/** Index in to IEMTB::aRanges. */
857	uint8_t idxRange;
858
859	/** Generic parameters. */
860	uint64_t auParams[3];
861	} IEMTHRDEDCALLENTRY;
862	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
863	/** Pointer to a threaded call entry. */
864	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
865	/** Pointer to a const threaded call entry. */
866	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
867
868	/**
869	* Native IEM TB 'function' typedef.
870	*
871	* This will throw/longjmp on occation.
872	*
873	* @note AMD64 doesn't have that many non-volatile registers and does sport
874	* 32-bit address displacments, so we don't need pCtx.
875	*
876	* On ARM64 pCtx allows us to directly address the whole register
877	* context without requiring a separate indexing register holding the
878	* offset. This saves an instruction loading the offset for each guest
879	* CPU context access, at the cost of a non-volatile register.
880	* Fortunately, ARM64 has quite a lot more registers.
881	*/
882	typedef
883	#ifdef RT_ARCH_AMD64
884	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
885	#else
886	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
887	#endif
888	#if RT_CPLUSPLUS_PREREQ(201700)
889	IEM_NOEXCEPT_MAY_LONGJMP
890	#endif
891	;
892	/** Pointer to a native IEM TB entry point function.
893	* This will throw/longjmp on occation. */
894	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
895
896
897	/**
898	* Translation block debug info entry type.
899	*/
900	typedef enum IEMTBDBGENTRYTYPE
901	{
902	kIemTbDbgEntryType_Invalid = 0,
903	/** The entry is for marking a native code position.
904	* Entries following this all apply to this position. */
905	kIemTbDbgEntryType_NativeOffset,
906	/** The entry is for a new guest instruction. */
907	kIemTbDbgEntryType_GuestInstruction,
908	/** Marks the start of a threaded call. */
909	kIemTbDbgEntryType_ThreadedCall,
910	/** Marks the location of a label. */
911	kIemTbDbgEntryType_Label,
912	/** Info about a host register shadowing a guest register. */
913	kIemTbDbgEntryType_GuestRegShadowing,
914	kIemTbDbgEntryType_End
915	} IEMTBDBGENTRYTYPE;
916
917	/**
918	* Translation block debug info entry.
919	*/
920	typedef union IEMTBDBGENTRY
921	{
922	/** Plain 32-bit view. */
923	uint32_t u;
924
925	/** Generic view for getting at the type field. */
926	struct
927	{
928	/** IEMTBDBGENTRYTYPE */
929	uint32_t uType : 4;
930	uint32_t uTypeSpecific : 28;
931	} Gen;
932
933	struct
934	{
935	/** kIemTbDbgEntryType_ThreadedCall1. */
936	uint32_t uType : 4;
937	/** Native code offset. */
938	uint32_t offNative : 28;
939	} NativeOffset;
940
941	struct
942	{
943	/** kIemTbDbgEntryType_GuestInstruction. */
944	uint32_t uType : 4;
945	uint32_t uUnused : 4;
946	/** The IEM_F_XXX flags. */
947	uint32_t fExec : 24;
948	} GuestInstruction;
949
950	struct
951	{
952	/* kIemTbDbgEntryType_ThreadedCall. */
953	uint32_t uType : 4;
954	/** Set if the call was recompiled to native code, clear if just calling
955	* threaded function. */
956	uint32_t fRecompiled : 1;
957	uint32_t uUnused : 11;
958	/** The threaded call number (IEMTHREADEDFUNCS). */
959	uint32_t enmCall : 16;
960	} ThreadedCall;
961
962	struct
963	{
964	/* kIemTbDbgEntryType_Label. */
965	uint32_t uType : 4;
966	uint32_t uUnused : 4;
967	/** The label type (IEMNATIVELABELTYPE). */
968	uint32_t enmLabel : 8;
969	/** The label data. */
970	uint32_t uData : 16;
971	} Label;
972
973	struct
974	{
975	/* kIemTbDbgEntryType_GuestRegShadowing. */
976	uint32_t uType : 4;
977	uint32_t uUnused : 4;
978	/** The guest register being shadowed (IEMNATIVEGSTREG). */
979	uint32_t idxGstReg : 8;
980	/** The host new register number, UINT8_MAX if dropped. */
981	uint32_t idxHstReg : 8;
982	/** The previous host register number, UINT8_MAX if new. */
983	uint32_t idxHstRegPrev : 8;
984	} GuestRegShadowing;
985	} IEMTBDBGENTRY;
986	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
987	/** Pointer to a debug info entry. */
988	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
989	/** Pointer to a const debug info entry. */
990	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
991
992	/**
993	* Translation block debug info.
994	*/
995	typedef struct IEMTBDBG
996	{
997	/** Number of entries in aEntries. */
998	uint32_t cEntries;
999	/** Debug info entries. */
1000	RT_FLEXIBLE_ARRAY_EXTENSION
1001	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1002	} IEMTBDBG;
1003	/** Pointer to TB debug info. */
1004	typedef IEMTBDBG *PIEMTBDBG;
1005	/** Pointer to const TB debug info. */
1006	typedef IEMTBDBG const *PCIEMTBDBG;
1007
1008
1009	/**
1010	* Translation block.
1011	*
1012	* The current plan is to just keep TBs and associated lookup hash table private
1013	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1014	* avoids using expensive atomic primitives for updating lists and stuff.
1015	*/
1016	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1017	typedef struct IEMTB
1018	{
1019	/** Next block with the same hash table entry. */
1020	struct IEMTB *pNext;
1021	/** Usage counter. */
1022	uint32_t cUsed;
1023	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1024	uint32_t msLastUsed;
1025
1026	/** @name What uniquely identifies the block.
1027	* @{ */
1028	RTGCPHYS GCPhysPc;
1029	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1030	uint32_t fFlags;
1031	union
1032	{
1033	struct
1034	{
1035	/*< Relevant CS X86DESCATTR_XXX bits. /
1036	uint16_t fAttr;
1037	} x86;
1038	};
1039	/** @} */
1040
1041	/** Number of opcode ranges. */
1042	uint8_t cRanges;
1043	/** Statistics: Number of instructions in the block. */
1044	uint8_t cInstructions;
1045
1046	/** Type specific info. */
1047	union
1048	{
1049	struct
1050	{
1051	/** The call sequence table. */
1052	PIEMTHRDEDCALLENTRY paCalls;
1053	/** Number of calls in paCalls. */
1054	uint16_t cCalls;
1055	/** Number of calls allocated. */
1056	uint16_t cAllocated;
1057	} Thrd;
1058	struct
1059	{
1060	/** The native instructions (PFNIEMTBNATIVE). */
1061	PIEMNATIVEINSTR paInstructions;
1062	/** Number of instructions pointed to by paInstructions. */
1063	uint32_t cInstructions;
1064	} Native;
1065	/** Generic view for zeroing when freeing. */
1066	struct
1067	{
1068	uintptr_t uPtr;
1069	uint32_t uData;
1070	} Gen;
1071	};
1072
1073	/** The allocation chunk this TB belongs to. */
1074	uint8_t idxAllocChunk;
1075	uint8_t bUnused;
1076
1077	/** Number of bytes of opcodes stored in pabOpcodes.
1078	* @todo this field isn't really needed, aRanges keeps the actual info. */
1079	uint16_t cbOpcodes;
1080	/** Pointer to the opcode bytes this block was recompiled from. */
1081	uint8_t *pabOpcodes;
1082
1083	/** Debug info if enabled.
1084	* This is only generated by the native recompiler. */
1085	PIEMTBDBG pDbgInfo;
1086
1087	/* --- 64 byte cache line end --- */
1088
1089	/** Opcode ranges.
1090	*
1091	* The opcode checkers and maybe TLB loading functions will use this to figure
1092	* out what to do. The parameter will specify an entry and the opcode offset to
1093	* start at and the minimum number of bytes to verify (instruction length).
1094	*
1095	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1096	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1097	* code TLB (must have a valid entry for that address) and scan the ranges to
1098	* locate the corresponding opcodes. Probably.
1099	*/
1100	struct IEMTBOPCODERANGE
1101	{
1102	/** Offset within pabOpcodes. */
1103	uint16_t offOpcodes;
1104	/** Number of bytes. */
1105	uint16_t cbOpcodes;
1106	/** The page offset. */
1107	RT_GCC_EXTENSION
1108	uint16_t offPhysPage : 12;
1109	/** Unused bits. */
1110	RT_GCC_EXTENSION
1111	uint16_t u2Unused : 2;
1112	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1113	RT_GCC_EXTENSION
1114	uint16_t idxPhysPage : 2;
1115	} aRanges[8];
1116
1117	/** Physical pages that this TB covers.
1118	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1119	RTGCPHYS aGCPhysPages[2];
1120	} IEMTB;
1121	#pragma pack()
1122	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1123	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1124	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1125	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1126	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1127	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1128	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1129	#if 1
1130	AssertCompileSize(IEMTB, 128);
1131	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1132	#else
1133	AssertCompileSize(IEMTB, 168);
1134	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1135	#endif
1136
1137	/** Pointer to a translation block. */
1138	typedef IEMTB *PIEMTB;
1139	/** Pointer to a const translation block. */
1140	typedef IEMTB const *PCIEMTB;
1141
1142	/**
1143	* A chunk of memory in the TB allocator.
1144	*/
1145	typedef struct IEMTBCHUNK
1146	{
1147	/** Pointer to the translation blocks in this chunk. */
1148	PIEMTB paTbs;
1149	#ifdef IN_RING0
1150	/** Allocation handle. */
1151	RTR0MEMOBJ hMemObj;
1152	#endif
1153	} IEMTBCHUNK;
1154
1155	/**
1156	* A per-CPU translation block allocator.
1157	*
1158	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1159	* the length of the collision list, and of course also for cache line alignment
1160	* reasons, the TBs must be allocated with at least 64-byte alignment.
1161	* Memory is there therefore allocated using one of the page aligned allocators.
1162	*
1163	*
1164	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1165	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1166	* that enables us to quickly calculate the allocation bitmap position when
1167	* freeing the translation block.
1168	*/
1169	typedef struct IEMTBALLOCATOR
1170	{
1171	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1172	uint32_t uMagic;
1173
1174	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1175	/** Mask corresponding to cTbsPerChunk - 1. */
1176	uint32_t fChunkMask;
1177	/** Shift count corresponding to cTbsPerChunk. */
1178	uint8_t cChunkShift;
1179	#else
1180	uint32_t uUnused;
1181	uint8_t bUnused;
1182	#endif
1183	/** Number of chunks we're allowed to allocate. */
1184	uint8_t cMaxChunks;
1185	/** Number of chunks currently populated. */
1186	uint16_t cAllocatedChunks;
1187	/** Number of translation blocks per chunk. */
1188	uint32_t cTbsPerChunk;
1189	/** Chunk size. */
1190	uint32_t cbPerChunk;
1191
1192	/** The maximum number of TBs. */
1193	uint32_t cMaxTbs;
1194	/** Total number of TBs in the populated chunks.
1195	* (cAllocatedChunks * cTbsPerChunk) */
1196	uint32_t cTotalTbs;
1197	/** The current number of TBs in use.
1198	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1199	uint32_t cInUseTbs;
1200	/** Statistics: Number of the cInUseTbs that are native ones. */
1201	uint32_t cNativeTbs;
1202	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1203	uint32_t cThreadedTbs;
1204
1205	/** Where to start pruning TBs from when we're out.
1206	* See iemTbAllocatorAllocSlow for details. */
1207	uint32_t iPruneFrom;
1208	/** Hint about which bit to start scanning the bitmap from. */
1209	uint32_t iStartHint;
1210
1211	/** Statistics: Number of TB allocation calls. */
1212	STAMCOUNTER StatAllocs;
1213	/** Statistics: Number of TB free calls. */
1214	STAMCOUNTER StatFrees;
1215	/** Statistics: Time spend pruning. */
1216	STAMPROFILE StatPrune;
1217
1218	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1219	PIEMTB pDelayedFreeHead;
1220
1221	/** Allocation chunks. */
1222	IEMTBCHUNK aChunks[256];
1223
1224	/** Allocation bitmap for all possible chunk chunks. */
1225	RT_FLEXIBLE_ARRAY_EXTENSION
1226	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1227	} IEMTBALLOCATOR;
1228	/** Pointer to a TB allocator. */
1229	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1230
1231	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1232	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1233
1234
1235	/**
1236	* A per-CPU translation block cache (hash table).
1237	*
1238	* The hash table is allocated once during IEM initialization and size double
1239	* the max TB count, rounded up to the nearest power of two (so we can use and
1240	* AND mask rather than a rest division when hashing).
1241	*/
1242	typedef struct IEMTBCACHE
1243	{
1244	/** Magic value (IEMTBCACHE_MAGIC). */
1245	uint32_t uMagic;
1246	/** Size of the hash table. This is a power of two. */
1247	uint32_t cHash;
1248	/** The mask corresponding to cHash. */
1249	uint32_t uHashMask;
1250	uint32_t uPadding;
1251
1252	/** @name Statistics
1253	* @{ */
1254	/** Number of collisions ever. */
1255	STAMCOUNTER cCollisions;
1256
1257	/** Statistics: Number of TB lookup misses. */
1258	STAMCOUNTER cLookupMisses;
1259	/** Statistics: Number of TB lookup hits (debug only). */
1260	STAMCOUNTER cLookupHits;
1261	STAMCOUNTER auPadding2[3];
1262	/** Statistics: Collision list length pruning. */
1263	STAMPROFILE StatPrune;
1264	/** @} */
1265
1266	/** The hash table itself.
1267	* @note The lower 6 bits of the pointer is used for keeping the collision
1268	* list length, so we can take action when it grows too long.
1269	* This works because TBs are allocated using a 64 byte (or
1270	* higher) alignment from page aligned chunks of memory, so the lower
1271	* 6 bits of the address will always be zero.
1272	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1273	*/
1274	RT_FLEXIBLE_ARRAY_EXTENSION
1275	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1276	} IEMTBCACHE;
1277	/** Pointer to a per-CPU translation block cahce. */
1278	typedef IEMTBCACHE *PIEMTBCACHE;
1279
1280	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1281	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1282
1283	/** The collision count mask for IEMTBCACHE::apHash entries. */
1284	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1285	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1286	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1287	/** Combine a TB pointer and a collision list length into a value for an
1288	* IEMTBCACHE::apHash entry. */
1289	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1290	/** Combine a TB pointer and a collision list length into a value for an
1291	* IEMTBCACHE::apHash entry. */
1292	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1293	/** Combine a TB pointer and a collision list length into a value for an
1294	* IEMTBCACHE::apHash entry. */
1295	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1296
1297	/**
1298	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1299	*/
1300	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1301	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1302
1303	/**
1304	* Calculates the hash table slot for a TB from physical PC address and TB
1305	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1306	*/
1307	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1308	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1309
1310
1311	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1312	*
1313	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1314	*
1315	* @{ */
1316	/** Value if no branching happened recently. */
1317	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1318	/** Flag set if direct branch, clear if absolute or indirect. */
1319	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1320	/** Flag set if indirect branch, clear if direct or relative. */
1321	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1322	/** Flag set if relative branch, clear if absolute or indirect. */
1323	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1324	/** Flag set if conditional branch, clear if unconditional. */
1325	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1326	/** Flag set if it's a far branch. */
1327	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1328	/** Flag set if the stack pointer is modified. */
1329	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1330	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1331	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1332	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1333	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1334	/** @} */
1335
1336
1337	/**
1338	* The per-CPU IEM state.
1339	*/
1340	typedef struct IEMCPU
1341	{
1342	/** Info status code that needs to be propagated to the IEM caller.
1343	* This cannot be passed internally, as it would complicate all success
1344	* checks within the interpreter making the code larger and almost impossible
1345	* to get right. Instead, we'll store status codes to pass on here. Each
1346	* source of these codes will perform appropriate sanity checks. */
1347	int32_t rcPassUp; /* 0x00 */
1348	/** Execution flag, IEM_F_XXX. */
1349	uint32_t fExec; /* 0x04 */
1350
1351	/** @name Decoder state.
1352	* @{ */
1353	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1354	# ifdef IEM_WITH_CODE_TLB
1355	/** The offset of the next instruction byte. */
1356	uint32_t offInstrNextByte; /* 0x08 */
1357	/** The number of bytes available at pbInstrBuf for the current instruction.
1358	* This takes the max opcode length into account so that doesn't need to be
1359	* checked separately. */
1360	uint32_t cbInstrBuf; /* 0x0c */
1361	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1362	* This can be NULL if the page isn't mappable for some reason, in which
1363	* case we'll do fallback stuff.
1364	*
1365	* If we're executing an instruction from a user specified buffer,
1366	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1367	* aligned pointer but pointer to the user data.
1368	*
1369	* For instructions crossing pages, this will start on the first page and be
1370	* advanced to the next page by the time we've decoded the instruction. This
1371	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1372	*/
1373	uint8_t const pbInstrBuf; / 0x10 */
1374	# if ARCH_BITS == 32
1375	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1376	# endif
1377	/** The program counter corresponding to pbInstrBuf.
1378	* This is set to a non-canonical address when we need to invalidate it. */
1379	uint64_t uInstrBufPc; /* 0x18 */
1380	/** The guest physical address corresponding to pbInstrBuf. */
1381	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1382	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1383	* This takes the CS segment limit into account. */
1384	uint16_t cbInstrBufTotal; /* 0x28 */
1385	/** Offset into pbInstrBuf of the first byte of the current instruction.
1386	* Can be negative to efficiently handle cross page instructions. */
1387	int16_t offCurInstrStart; /* 0x2a */
1388
1389	/** The prefix mask (IEM_OP_PRF_XXX). */
1390	uint32_t fPrefixes; /* 0x2c */
1391	/** The extra REX ModR/M register field bit (REX.R << 3). */
1392	uint8_t uRexReg; /* 0x30 */
1393	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1394	* (REX.B << 3). */
1395	uint8_t uRexB; /* 0x31 */
1396	/** The extra REX SIB index field bit (REX.X << 3). */
1397	uint8_t uRexIndex; /* 0x32 */
1398
1399	/** The effective segment register (X86_SREG_XXX). */
1400	uint8_t iEffSeg; /* 0x33 */
1401
1402	/** The offset of the ModR/M byte relative to the start of the instruction. */
1403	uint8_t offModRm; /* 0x34 */
1404
1405	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1406	/** The current offset into abOpcode. */
1407	uint8_t offOpcode; /* 0x35 */
1408	# else
1409	uint8_t bUnused; /* 0x35 */
1410	# endif
1411	# else /* !IEM_WITH_CODE_TLB */
1412	/** The size of what has currently been fetched into abOpcode. */
1413	uint8_t cbOpcode; /* 0x08 */
1414	/** The current offset into abOpcode. */
1415	uint8_t offOpcode; /* 0x09 */
1416	/** The offset of the ModR/M byte relative to the start of the instruction. */
1417	uint8_t offModRm; /* 0x0a */
1418
1419	/** The effective segment register (X86_SREG_XXX). */
1420	uint8_t iEffSeg; /* 0x0b */
1421
1422	/** The prefix mask (IEM_OP_PRF_XXX). */
1423	uint32_t fPrefixes; /* 0x0c */
1424	/** The extra REX ModR/M register field bit (REX.R << 3). */
1425	uint8_t uRexReg; /* 0x10 */
1426	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1427	* (REX.B << 3). */
1428	uint8_t uRexB; /* 0x11 */
1429	/** The extra REX SIB index field bit (REX.X << 3). */
1430	uint8_t uRexIndex; /* 0x12 */
1431
1432	# endif /* !IEM_WITH_CODE_TLB */
1433
1434	/** The effective operand mode. */
1435	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1436	/** The default addressing mode. */
1437	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1438	/** The effective addressing mode. */
1439	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1440	/** The default operand mode. */
1441	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1442
1443	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1444	uint8_t idxPrefix; /* 0x3a, 0x17 */
1445	/** 3rd VEX/EVEX/XOP register.
1446	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1447	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1448	/** The VEX/EVEX/XOP length field. */
1449	uint8_t uVexLength; /* 0x3c, 0x19 */
1450	/** Additional EVEX stuff. */
1451	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1452
1453	# ifndef IEM_WITH_CODE_TLB
1454	/** Explicit alignment padding. */
1455	uint8_t abAlignment2a[1]; /* 0x1b */
1456	# endif
1457	/** The FPU opcode (FOP). */
1458	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1459	# ifndef IEM_WITH_CODE_TLB
1460	/** Explicit alignment padding. */
1461	uint8_t abAlignment2b[2]; /* 0x1e */
1462	# endif
1463
1464	/** The opcode bytes. */
1465	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1466	/** Explicit alignment padding. */
1467	# ifdef IEM_WITH_CODE_TLB
1468	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1469	# else
1470	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1471	# endif
1472	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1473	uint8_t abOpaqueDecoder[0x4f - 0x8];
1474	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1475	/** @} */
1476
1477
1478	/** The number of active guest memory mappings. */
1479	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1480
1481	/** Records for tracking guest memory mappings. */
1482	struct
1483	{
1484	/** The address of the mapped bytes. */
1485	R3R0PTRTYPE(void *) pv;
1486	/** The access flags (IEM_ACCESS_XXX).
1487	* IEM_ACCESS_INVALID if the entry is unused. */
1488	uint32_t fAccess;
1489	#if HC_ARCH_BITS == 64
1490	uint32_t u32Alignment4; /*< Alignment padding. /
1491	#endif
1492	} aMemMappings[3]; /* 0x50 LB 0x30 */
1493
1494	/** Locking records for the mapped memory. */
1495	union
1496	{
1497	PGMPAGEMAPLOCK Lock;
1498	uint64_t au64Padding[2];
1499	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1500
1501	/** Bounce buffer info.
1502	* This runs in parallel to aMemMappings. */
1503	struct
1504	{
1505	/** The physical address of the first byte. */
1506	RTGCPHYS GCPhysFirst;
1507	/** The physical address of the second page. */
1508	RTGCPHYS GCPhysSecond;
1509	/** The number of bytes in the first page. */
1510	uint16_t cbFirst;
1511	/** The number of bytes in the second page. */
1512	uint16_t cbSecond;
1513	/** Whether it's unassigned memory. */
1514	bool fUnassigned;
1515	/** Explicit alignment padding. */
1516	bool afAlignment5[3];
1517	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1518
1519	/** The flags of the current exception / interrupt. */
1520	uint32_t fCurXcpt; /* 0xf8 */
1521	/** The current exception / interrupt. */
1522	uint8_t uCurXcpt; /* 0xfc */
1523	/** Exception / interrupt recursion depth. */
1524	int8_t cXcptRecursions; /* 0xfb */
1525
1526	/** The next unused mapping index.
1527	* @todo try find room for this up with cActiveMappings. */
1528	uint8_t iNextMapping; /* 0xfd */
1529	uint8_t abAlignment7[1];
1530
1531	/** Bounce buffer storage.
1532	* This runs in parallel to aMemMappings and aMemBbMappings. */
1533	struct
1534	{
1535	uint8_t ab[512];
1536	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1537
1538
1539	/** Pointer set jump buffer - ring-3 context. */
1540	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1541	/** Pointer set jump buffer - ring-0 context. */
1542	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1543
1544	/** @todo Should move this near @a fCurXcpt later. */
1545	/** The CR2 for the current exception / interrupt. */
1546	uint64_t uCurXcptCr2;
1547	/** The error code for the current exception / interrupt. */
1548	uint32_t uCurXcptErr;
1549
1550	/** @name Statistics
1551	* @{ */
1552	/** The number of instructions we've executed. */
1553	uint32_t cInstructions;
1554	/** The number of potential exits. */
1555	uint32_t cPotentialExits;
1556	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1557	* This may contain uncommitted writes. */
1558	uint32_t cbWritten;
1559	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1560	uint32_t cRetInstrNotImplemented;
1561	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1562	uint32_t cRetAspectNotImplemented;
1563	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1564	uint32_t cRetInfStatuses;
1565	/** Counts other error statuses returned. */
1566	uint32_t cRetErrStatuses;
1567	/** Number of times rcPassUp has been used. */
1568	uint32_t cRetPassUpStatus;
1569	/** Number of times RZ left with instruction commit pending for ring-3. */
1570	uint32_t cPendingCommit;
1571	/** Number of long jumps. */
1572	uint32_t cLongJumps;
1573	/** @} */
1574
1575	/** @name Target CPU information.
1576	* @{ */
1577	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1578	/** The target CPU. */
1579	uint8_t uTargetCpu;
1580	#else
1581	uint8_t bTargetCpuPadding;
1582	#endif
1583	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1584	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1585	* native host support and the 2nd for when there is.
1586	*
1587	* The two values are typically indexed by a g_CpumHostFeatures bit.
1588	*
1589	* This is for instance used for the BSF & BSR instructions where AMD and
1590	* Intel CPUs produce different EFLAGS. */
1591	uint8_t aidxTargetCpuEflFlavour[2];
1592
1593	/** The CPU vendor. */
1594	CPUMCPUVENDOR enmCpuVendor;
1595	/** @} */
1596
1597	/** @name Host CPU information.
1598	* @{ */
1599	/** The CPU vendor. */
1600	CPUMCPUVENDOR enmHostCpuVendor;
1601	/** @} */
1602
1603	/** Counts RDMSR \#GP(0) LogRel(). */
1604	uint8_t cLogRelRdMsr;
1605	/** Counts WRMSR \#GP(0) LogRel(). */
1606	uint8_t cLogRelWrMsr;
1607	/** Alignment padding. */
1608	uint8_t abAlignment9[46];
1609
1610	/** @name Recompilation
1611	* @{ */
1612	/** Pointer to the current translation block.
1613	* This can either be one being executed or one being compiled. */
1614	R3PTRTYPE(PIEMTB) pCurTbR3;
1615	/** Fixed TB used for threaded recompilation.
1616	* This is allocated once with maxed-out sizes and re-used afterwards. */
1617	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1618	/** Pointer to the ring-3 TB cache for this EMT. */
1619	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1620	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1621	* The TBs are based on physical addresses, so this is needed to correleated
1622	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1623	uint64_t uCurTbStartPc;
1624	/** Number of threaded TBs executed. */
1625	uint64_t cTbExecThreaded;
1626	/** Number of native TBs executed. */
1627	uint64_t cTbExecNative;
1628	/** Whether we need to check the opcode bytes for the current instruction.
1629	* This is set by a previous instruction if it modified memory or similar. */
1630	bool fTbCheckOpcodes;
1631	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1632	uint8_t fTbBranched;
1633	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1634	bool fTbCrossedPage;
1635	/** Whether to end the current TB. */
1636	bool fEndTb;
1637	/** Number of instructions before we need emit an IRQ check call again.
1638	* This helps making sure we don't execute too long w/o checking for
1639	* interrupts and immediately following instructions that may enable
1640	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1641	* required to make sure we check following the next instruction as well, see
1642	* fTbCurInstrIsSti. */
1643	uint8_t cInstrTillIrqCheck;
1644	/** Indicates that the current instruction is an STI. This is set by the
1645	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1646	bool fTbCurInstrIsSti;
1647	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1648	uint16_t cbOpcodesAllocated;
1649	/** Spaced reserved for recompiler data / alignment. */
1650	bool afRecompilerStuff1[4];
1651	/** The virtual sync time at the last timer poll call. */
1652	uint32_t msRecompilerPollNow;
1653	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1654	uint32_t fTbCurInstr;
1655	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1656	uint32_t fTbPrevInstr;
1657	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1658	RTGCPHYS GCPhysInstrBufPrev;
1659	/** Copy of IEMCPU::GCPhysInstrBuf after decoding a branch instruction.
1660	* This is used together with fTbBranched and GCVirtTbBranchSrcBuf to determin
1661	* whether a branch instruction jumps to a new page or stays within the
1662	* current one. */
1663	RTGCPHYS GCPhysTbBranchSrcBuf;
1664	/** Copy of IEMCPU::uInstrBufPc after decoding a branch instruction. */
1665	uint64_t GCVirtTbBranchSrcBuf;
1666	/** Pointer to the ring-3 TB allocator for this EMT. */
1667	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1668	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1669	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1670	/** Pointer to the native recompiler state for ring-3. */
1671	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1672	/** Alignment padding. */
1673	uint64_t auAlignment10[4];
1674	/** Statistics: Times TB execution was broken off before reaching the end. */
1675	STAMCOUNTER StatTbExecBreaks;
1676	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1677	STAMCOUNTER StatCheckIrqBreaks;
1678	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1679	STAMCOUNTER StatCheckModeBreaks;
1680	/** Statistics: Times a post jump target check missed and had to find new TB. */
1681	STAMCOUNTER StatCheckBranchMisses;
1682	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1683	STAMCOUNTER StatCheckNeedCsLimChecking;
1684	/** Threaded TB statistics: Number of instructions per TB. */
1685	STAMPROFILE StatTbThreadedInstr;
1686	/** Threaded TB statistics: Number of calls per TB. */
1687	STAMPROFILE StatTbThreadedCalls;
1688	/** Native TB statistics: Native code size per TB. */
1689	STAMPROFILE StatTbNativeCode;
1690	/** Native TB statistics: Profiling native recompilation. */
1691	STAMPROFILE StatNativeRecompilation;
1692	/** @} */
1693
1694	/** Data TLB.
1695	* @remarks Must be 64-byte aligned. */
1696	IEMTLB DataTlb;
1697	/** Instruction TLB.
1698	* @remarks Must be 64-byte aligned. */
1699	IEMTLB CodeTlb;
1700
1701	/** Exception statistics. */
1702	STAMCOUNTER aStatXcpts[32];
1703	/** Interrupt statistics. */
1704	uint32_t aStatInts[256];
1705
1706	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1707	/** Instruction statistics for ring-0/raw-mode. */
1708	IEMINSTRSTATS StatsRZ;
1709	/** Instruction statistics for ring-3. */
1710	IEMINSTRSTATS StatsR3;
1711	#endif
1712	} IEMCPU;
1713	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1714	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1715	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1716	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1717	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1718	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1719
1720	/** Pointer to the per-CPU IEM state. */
1721	typedef IEMCPU *PIEMCPU;
1722	/** Pointer to the const per-CPU IEM state. */
1723	typedef IEMCPU const *PCIEMCPU;
1724
1725
1726	/** @def IEM_GET_CTX
1727	* Gets the guest CPU context for the calling EMT.
1728	* @returns PCPUMCTX
1729	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1730	*/
1731	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1732
1733	/** @def IEM_CTX_ASSERT
1734	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1735	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1736	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1737	*/
1738	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
1739	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1740	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
1741	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
1742
1743	/** @def IEM_CTX_IMPORT_RET
1744	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1745	*
1746	* Will call the keep to import the bits as needed.
1747	*
1748	* Returns on import failure.
1749	*
1750	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1751	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1752	*/
1753	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1754	do { \
1755	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1756	{ /* likely */ } \
1757	else \
1758	{ \
1759	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1760	AssertRCReturn(rcCtxImport, rcCtxImport); \
1761	} \
1762	} while (0)
1763
1764	/** @def IEM_CTX_IMPORT_NORET
1765	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1766	*
1767	* Will call the keep to import the bits as needed.
1768	*
1769	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1770	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1771	*/
1772	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1773	do { \
1774	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1775	{ /* likely */ } \
1776	else \
1777	{ \
1778	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1779	AssertLogRelRC(rcCtxImport); \
1780	} \
1781	} while (0)
1782
1783	/** @def IEM_CTX_IMPORT_JMP
1784	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1785	*
1786	* Will call the keep to import the bits as needed.
1787	*
1788	* Jumps on import failure.
1789	*
1790	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1791	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1792	*/
1793	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1794	do { \
1795	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1796	{ /* likely */ } \
1797	else \
1798	{ \
1799	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1800	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1801	} \
1802	} while (0)
1803
1804
1805
1806	/** @def IEM_GET_TARGET_CPU
1807	* Gets the current IEMTARGETCPU value.
1808	* @returns IEMTARGETCPU value.
1809	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1810	*/
1811	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1812	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1813	#else
1814	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1815	#endif
1816
1817	/** @def IEM_GET_INSTR_LEN
1818	* Gets the instruction length. */
1819	#ifdef IEM_WITH_CODE_TLB
1820	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1821	#else
1822	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1823	#endif
1824
1825	/** @def IEM_TRY_SETJMP
1826	* Wrapper around setjmp / try, hiding all the ugly differences.
1827	*
1828	* @note Use with extreme care as this is a fragile macro.
1829	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1830	* @param a_rcTarget The variable that should receive the status code in case
1831	* of a longjmp/throw.
1832	*/
1833	/** @def IEM_TRY_SETJMP_AGAIN
1834	* For when setjmp / try is used again in the same variable scope as a previous
1835	* IEM_TRY_SETJMP invocation.
1836	*/
1837	/** @def IEM_CATCH_LONGJMP_BEGIN
1838	* Start wrapper for catch / setjmp-else.
1839	*
1840	* This will set up a scope.
1841	*
1842	* @note Use with extreme care as this is a fragile macro.
1843	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1844	* @param a_rcTarget The variable that should receive the status code in case
1845	* of a longjmp/throw.
1846	*/
1847	/** @def IEM_CATCH_LONGJMP_END
1848	* End wrapper for catch / setjmp-else.
1849	*
1850	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1851	* state.
1852	*
1853	* @note Use with extreme care as this is a fragile macro.
1854	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1855	*/
1856	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1857	# ifdef IEM_WITH_THROW_CATCH
1858	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1859	a_rcTarget = VINF_SUCCESS; \
1860	try
1861	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1862	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1863	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1864	catch (int rcThrown) \
1865	{ \
1866	a_rcTarget = rcThrown
1867	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1868	} \
1869	((void)0)
1870	# else /* !IEM_WITH_THROW_CATCH */
1871	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1872	jmp_buf JmpBuf; \
1873	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
1874	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1875	if ((rcStrict = setjmp(JmpBuf)) == 0)
1876	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1877	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
1878	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1879	if ((rcStrict = setjmp(JmpBuf)) == 0)
1880	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1881	else \
1882	{ \
1883	((void)0)
1884	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1885	} \
1886	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1887	# endif /* !IEM_WITH_THROW_CATCH */
1888	#endif /* IEM_WITH_SETJMP */
1889
1890
1891	/**
1892	* Shared per-VM IEM data.
1893	*/
1894	typedef struct IEM
1895	{
1896	/** The VMX APIC-access page handler type. */
1897	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1898	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1899	/** Set if the CPUID host call functionality is enabled. */
1900	bool fCpuIdHostCall;
1901	#endif
1902	} IEM;
1903
1904
1905
1906	/** @name IEM_ACCESS_XXX - Access details.
1907	* @{ */
1908	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1909	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1910	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1911	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1912	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1913	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1914	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1915	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1916	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1917	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1918	/** The writes are partial, so if initialize the bounce buffer with the
1919	* orignal RAM content. */
1920	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1921	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1922	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1923	/** Bounce buffer with ring-3 write pending, first page. */
1924	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1925	/** Bounce buffer with ring-3 write pending, second page. */
1926	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1927	/** Not locked, accessed via the TLB. */
1928	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1929	/** Valid bit mask. */
1930	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1931	/** Shift count for the TLB flags (upper word). */
1932	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1933
1934	/** Read+write data alias. */
1935	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1936	/** Write data alias. */
1937	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1938	/** Read data alias. */
1939	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1940	/** Instruction fetch alias. */
1941	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1942	/** Stack write alias. */
1943	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1944	/** Stack read alias. */
1945	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1946	/** Stack read+write alias. */
1947	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1948	/** Read system table alias. */
1949	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1950	/** Read+write system table alias. */
1951	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1952	/** @} */
1953
1954	/** @name Prefix constants (IEMCPU::fPrefixes)
1955	* @{ */
1956	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1957	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1958	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1959	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1960	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1961	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1962	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1963
1964	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1965	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1966	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1967
1968	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1969	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1970	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1971
1972	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1973	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1974	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1975	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1976	/** Mask with all the REX prefix flags.
1977	* This is generally for use when needing to undo the REX prefixes when they
1978	* are followed legacy prefixes and therefore does not immediately preceed
1979	* the first opcode byte.
1980	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1981	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1982
1983	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1984	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1985	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1986	/** @} */
1987
1988	/** @name IEMOPFORM_XXX - Opcode forms
1989	* @note These are ORed together with IEMOPHINT_XXX.
1990	* @{ */
1991	/** ModR/M: reg, r/m */
1992	#define IEMOPFORM_RM 0
1993	/** ModR/M: reg, r/m (register) */
1994	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1995	/** ModR/M: reg, r/m (memory) */
1996	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1997	/** ModR/M: reg, r/m */
1998	#define IEMOPFORM_RMI 1
1999	/** ModR/M: reg, r/m (register) */
2000	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2001	/** ModR/M: reg, r/m (memory) */
2002	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2003	/** ModR/M: r/m, reg */
2004	#define IEMOPFORM_MR 2
2005	/** ModR/M: r/m (register), reg */
2006	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2007	/** ModR/M: r/m (memory), reg */
2008	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2009	/** ModR/M: r/m, reg */
2010	#define IEMOPFORM_MRI 3
2011	/** ModR/M: r/m (register), reg */
2012	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2013	/** ModR/M: r/m (memory), reg */
2014	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2015	/** ModR/M: r/m only */
2016	#define IEMOPFORM_M 4
2017	/** ModR/M: r/m only (register). */
2018	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2019	/** ModR/M: r/m only (memory). */
2020	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2021	/** ModR/M: reg only */
2022	#define IEMOPFORM_R 5
2023
2024	/** VEX+ModR/M: reg, r/m */
2025	#define IEMOPFORM_VEX_RM 8
2026	/** VEX+ModR/M: reg, r/m (register) */
2027	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2028	/** VEX+ModR/M: reg, r/m (memory) */
2029	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2030	/** VEX+ModR/M: r/m, reg */
2031	#define IEMOPFORM_VEX_MR 9
2032	/** VEX+ModR/M: r/m (register), reg */
2033	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2034	/** VEX+ModR/M: r/m (memory), reg */
2035	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2036	/** VEX+ModR/M: r/m only */
2037	#define IEMOPFORM_VEX_M 10
2038	/** VEX+ModR/M: r/m only (register). */
2039	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2040	/** VEX+ModR/M: r/m only (memory). */
2041	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2042	/** VEX+ModR/M: reg only */
2043	#define IEMOPFORM_VEX_R 11
2044	/** VEX+ModR/M: reg, vvvv, r/m */
2045	#define IEMOPFORM_VEX_RVM 12
2046	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2047	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2048	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2049	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2050	/** VEX+ModR/M: reg, r/m, vvvv */
2051	#define IEMOPFORM_VEX_RMV 13
2052	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2053	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2054	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2055	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2056	/** VEX+ModR/M: reg, r/m, imm8 */
2057	#define IEMOPFORM_VEX_RMI 14
2058	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2059	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2060	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2061	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2062	/** VEX+ModR/M: r/m, vvvv, reg */
2063	#define IEMOPFORM_VEX_MVR 15
2064	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2065	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2066	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2067	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2068	/** VEX+ModR/M+/n: vvvv, r/m */
2069	#define IEMOPFORM_VEX_VM 16
2070	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2071	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2072	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2073	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2074
2075	/** Fixed register instruction, no R/M. */
2076	#define IEMOPFORM_FIXED 32
2077
2078	/** The r/m is a register. */
2079	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2080	/** The r/m is a memory access. */
2081	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2082	/** @} */
2083
2084	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2085	* @note These are ORed together with IEMOPFORM_XXX.
2086	* @{ */
2087	/** Ignores the operand size prefix (66h). */
2088	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2089	/** Ignores REX.W (aka WIG). */
2090	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2091	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2092	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2093	/** Allowed with the lock prefix. */
2094	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2095	/** The VEX.L value is ignored (aka LIG). */
2096	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2097	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2098	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2099	/** The VEX.V value must be zero. */
2100	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
2101
2102	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2103	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2104	/** @} */
2105
2106	/**
2107	* Possible hardware task switch sources.
2108	*/
2109	typedef enum IEMTASKSWITCH
2110	{
2111	/** Task switch caused by an interrupt/exception. */
2112	IEMTASKSWITCH_INT_XCPT = 1,
2113	/** Task switch caused by a far CALL. */
2114	IEMTASKSWITCH_CALL,
2115	/** Task switch caused by a far JMP. */
2116	IEMTASKSWITCH_JUMP,
2117	/** Task switch caused by an IRET. */
2118	IEMTASKSWITCH_IRET
2119	} IEMTASKSWITCH;
2120	AssertCompileSize(IEMTASKSWITCH, 4);
2121
2122	/**
2123	* Possible CrX load (write) sources.
2124	*/
2125	typedef enum IEMACCESSCRX
2126	{
2127	/** CrX access caused by 'mov crX' instruction. */
2128	IEMACCESSCRX_MOV_CRX,
2129	/** CrX (CR0) write caused by 'lmsw' instruction. */
2130	IEMACCESSCRX_LMSW,
2131	/** CrX (CR0) write caused by 'clts' instruction. */
2132	IEMACCESSCRX_CLTS,
2133	/** CrX (CR0) read caused by 'smsw' instruction. */
2134	IEMACCESSCRX_SMSW
2135	} IEMACCESSCRX;
2136
2137	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2138	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2139	*
2140	* These flags provide further context to SLAT page-walk failures that could not be
2141	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2142	*
2143	* @{
2144	*/
2145	/** Translating a nested-guest linear address failed accessing a nested-guest
2146	* physical address. */
2147	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2148	/** Translating a nested-guest linear address failed accessing a
2149	* paging-structure entry or updating accessed/dirty bits. */
2150	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2151	/** @} */
2152
2153	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2154	# ifndef IN_RING3
2155	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2156	# endif
2157	#endif
2158
2159	/**
2160	* Indicates to the verifier that the given flag set is undefined.
2161	*
2162	* Can be invoked again to add more flags.
2163	*
2164	* This is a NOOP if the verifier isn't compiled in.
2165	*
2166	* @note We're temporarily keeping this until code is converted to new
2167	* disassembler style opcode handling.
2168	*/
2169	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2170
2171
2172	/** @def IEM_DECL_IMPL_TYPE
2173	* For typedef'ing an instruction implementation function.
2174	*
2175	* @param a_RetType The return type.
2176	* @param a_Name The name of the type.
2177	* @param a_ArgList The argument list enclosed in parentheses.
2178	*/
2179
2180	/** @def IEM_DECL_IMPL_DEF
2181	* For defining an instruction implementation function.
2182	*
2183	* @param a_RetType The return type.
2184	* @param a_Name The name of the type.
2185	* @param a_ArgList The argument list enclosed in parentheses.
2186	*/
2187
2188	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2189	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2190	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2191	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2192	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2193	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2194	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2195
2196	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2197	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2198	a_RetType (__fastcall a_Name) a_ArgList
2199	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2200	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2201	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2202	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2203
2204	#elif __cplusplus >= 201700 /* P0012R1 support */
2205	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2206	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2207	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2208	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2209	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2210	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2211
2212	#else
2213	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2214	a_RetType (VBOXCALL a_Name) a_ArgList
2215	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2216	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2217	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2218	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2219
2220	#endif
2221
2222	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2223	RT_C_DECLS_BEGIN
2224	extern uint8_t const g_afParity[256];
2225	RT_C_DECLS_END
2226
2227
2228	/** @name Arithmetic assignment operations on bytes (binary).
2229	* @{ */
2230	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2231	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2232	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2233	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2234	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2235	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2236	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2237	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2238	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2239	/** @} */
2240
2241	/** @name Arithmetic assignment operations on words (binary).
2242	* @{ */
2243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2244	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2245	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2246	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2247	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2248	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2249	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2250	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2251	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2252	/** @} */
2253
2254	/** @name Arithmetic assignment operations on double words (binary).
2255	* @{ */
2256	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2257	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2258	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2259	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2260	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2261	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2262	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2263	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2264	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2265	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2266	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2267	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2268	/** @} */
2269
2270	/** @name Arithmetic assignment operations on quad words (binary).
2271	* @{ */
2272	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2273	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2274	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2275	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2276	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2277	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2278	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2279	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2280	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2281	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2282	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2283	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2284	/** @} */
2285
2286	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2287	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2288	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2289	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2290	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2291	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2292	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2293	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2294
2295	/** @name Compare operations (thrown in with the binary ops).
2296	* @{ */
2297	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2298	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2299	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2300	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2301	/** @} */
2302
2303	/** @name Test operations (thrown in with the binary ops).
2304	* @{ */
2305	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2306	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2307	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2308	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2309	/** @} */
2310
2311	/** @name Bit operations operations (thrown in with the binary ops).
2312	* @{ */
2313	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2314	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2315	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2316	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2317	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2318	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2319	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2320	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2321	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2322	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2323	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2324	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2325	/** @} */
2326
2327	/** @name Arithmetic three operand operations on double words (binary).
2328	* @{ */
2329	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2330	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2331	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2332	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2333	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2334	/** @} */
2335
2336	/** @name Arithmetic three operand operations on quad words (binary).
2337	* @{ */
2338	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2339	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2340	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2341	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2342	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2343	/** @} */
2344
2345	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2346	* @{ */
2347	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2348	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2349	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2350	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2351	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2352	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2353	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2354	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2355	/** @} */
2356
2357	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2358	* @{ */
2359	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2360	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2361	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2362	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2363	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2364	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2365	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2366	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2367	/** @} */
2368
2369	/** @name MULX 32-bit and 64-bit.
2370	* @{ */
2371	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2372	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2373	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2374
2375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2376	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2377	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2378	/** @} */
2379
2380
2381	/** @name Exchange memory with register operations.
2382	* @{ */
2383	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2384	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2385	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2386	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2387	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2388	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2389	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2390	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2391	/** @} */
2392
2393	/** @name Exchange and add operations.
2394	* @{ */
2395	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2396	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2397	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2398	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2399	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2400	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2401	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2402	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2403	/** @} */
2404
2405	/** @name Compare and exchange.
2406	* @{ */
2407	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2408	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2409	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2410	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2411	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2412	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2413	#if ARCH_BITS == 32
2414	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2415	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2416	#else
2417	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2418	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2419	#endif
2420	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2421	uint32_t *pEFlags));
2422	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2423	uint32_t *pEFlags));
2424	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2425	uint32_t *pEFlags));
2426	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2427	uint32_t *pEFlags));
2428	#ifndef RT_ARCH_ARM64
2429	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2430	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2431	#endif
2432	/** @} */
2433
2434	/** @name Memory ordering
2435	* @{ */
2436	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2437	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2438	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2439	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2440	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2441	#ifndef RT_ARCH_ARM64
2442	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2443	#endif
2444	/** @} */
2445
2446	/** @name Double precision shifts
2447	* @{ */
2448	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2449	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2450	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2451	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2452	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2453	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2454	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2455	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2456	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2457	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2458	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2459	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2460	/** @} */
2461
2462
2463	/** @name Bit search operations (thrown in with the binary ops).
2464	* @{ */
2465	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2466	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2467	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2468	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2469	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2470	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2471	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2472	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2473	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2474	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2475	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2476	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2477	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2478	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2479	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2480	/** @} */
2481
2482	/** @name Signed multiplication operations (thrown in with the binary ops).
2483	* @{ */
2484	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2485	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2486	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2487	/** @} */
2488
2489	/** @name Arithmetic assignment operations on bytes (unary).
2490	* @{ */
2491	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2492	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2493	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2494	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2495	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2496	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2497	/** @} */
2498
2499	/** @name Arithmetic assignment operations on words (unary).
2500	* @{ */
2501	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2502	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2503	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2504	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2505	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2506	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2507	/** @} */
2508
2509	/** @name Arithmetic assignment operations on double words (unary).
2510	* @{ */
2511	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2512	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2513	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2514	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2515	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2516	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2517	/** @} */
2518
2519	/** @name Arithmetic assignment operations on quad words (unary).
2520	* @{ */
2521	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2522	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2523	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2524	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2525	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2526	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2527	/** @} */
2528
2529
2530	/** @name Shift operations on bytes (Group 2).
2531	* @{ */
2532	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
2533	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2534	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2535	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2536	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2537	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2538	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2539	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2540	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2541	/** @} */
2542
2543	/** @name Shift operations on words (Group 2).
2544	* @{ */
2545	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
2546	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2547	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2548	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2549	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2550	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2551	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2552	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2553	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2554	/** @} */
2555
2556	/** @name Shift operations on double words (Group 2).
2557	* @{ */
2558	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2559	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2560	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2561	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2562	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2563	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2564	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2565	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2566	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2567	/** @} */
2568
2569	/** @name Shift operations on words (Group 2).
2570	* @{ */
2571	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2572	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2573	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2574	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2575	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2576	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2577	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2578	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2579	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2580	/** @} */
2581
2582	/** @name Multiplication and division operations.
2583	* @{ */
2584	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2585	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2586	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2587	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2588	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2589	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2590
2591	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2592	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2593	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2594	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2595	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2596	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2597
2598	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2599	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2600	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2601	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2602	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2603	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2604
2605	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2606	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2607	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2608	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2609	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2610	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2611	/** @} */
2612
2613	/** @name Byte Swap.
2614	* @{ */
2615	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2616	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2617	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2618	/** @} */
2619
2620	/** @name Misc.
2621	* @{ */
2622	FNIEMAIMPLBINU16 iemAImpl_arpl;
2623	/** @} */
2624
2625	/** @name RDRAND and RDSEED
2626	* @{ */
2627	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2628	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2629	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2630	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
2631	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
2632	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
2633
2634	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2635	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2636	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2637	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2638	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2639	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2640	/** @} */
2641
2642	/** @name ADOX and ADCX
2643	* @{ */
2644	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
2645	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
2646	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
2647	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
2648
2649	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2650	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2651	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2652	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2653	/** @} */
2654
2655	/** @name FPU operations taking a 32-bit float argument
2656	* @{ */
2657	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2658	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2659	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2660
2661	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2662	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2663	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2664
2665	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2666	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2667	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2668	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2669	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2670	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2671	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2672
2673	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2674	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2675	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2676	/** @} */
2677
2678	/** @name FPU operations taking a 64-bit float argument
2679	* @{ */
2680	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2681	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2682	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2683
2684	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2685	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2686	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2687
2688	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2689	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2690	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2691	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2692	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2693	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2694	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2695
2696	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2697	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2698	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2699	/** @} */
2700
2701	/** @name FPU operations taking a 80-bit float argument
2702	* @{ */
2703	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2704	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2705	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2706	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2707	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2708	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2709	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2710	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2711	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2712	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2713	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2714	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2715
2716	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2717	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2718	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2719
2720	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2721	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2722	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2723	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2724	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2725
2726	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2727	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2728	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2729	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2730	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2731
2732	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2733	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2734	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2735	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2736	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2737	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2738	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2739	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2740	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2741
2742	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2743	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2744	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2745	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2746
2747	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2748	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2749	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2750	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2751	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2752	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2753	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2754	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2755	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2756
2757	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2758	PCRTFLOAT80U pr80Val));
2759	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2760	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2761	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2762	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2763
2764	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2765	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2766	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2767
2768	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2769	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2770	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2771
2772	/** @} */
2773
2774	/** @name FPU operations taking a 16-bit signed integer argument
2775	* @{ */
2776	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2777	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2778	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2779	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2780	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2781	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2782
2783	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2784	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2785	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2786	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2787	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2788	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2789
2790	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2791	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2792	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2793	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2794
2795	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2796	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2797	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2798	/** @} */
2799
2800	/** @name FPU operations taking a 32-bit signed integer argument
2801	* @{ */
2802	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2803	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2804	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2805	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2806	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2807	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2808
2809	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2810	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2811	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2812	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2813	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2814	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2815
2816	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2817	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2818	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2819	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2820
2821	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2822	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2823	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2824	/** @} */
2825
2826	/** @name FPU operations taking a 64-bit signed integer argument
2827	* @{ */
2828	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2829	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2830	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2831
2832	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2833	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2834	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2835	/** @} */
2836
2837
2838	/** Temporary type representing a 256-bit vector register. */
2839	typedef struct { uint64_t au64[4]; } IEMVMM256;
2840	/** Temporary type pointing to a 256-bit vector register. */
2841	typedef IEMVMM256 *PIEMVMM256;
2842	/** Temporary type pointing to a const 256-bit vector register. */
2843	typedef IEMVMM256 *PCIEMVMM256;
2844
2845
2846	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2847	* @{ */
2848	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2849	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2850	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2851	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2852	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2853	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2854	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2855	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2856	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2857	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2858	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2859	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2860	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2861	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2862	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2863	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2864	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2865	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2866	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2867	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2868	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2869	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2870	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2871	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2872	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2873	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2874	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2875	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2876	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2877	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2878	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2879	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2880	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2881	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2882	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2883	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2884	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2885	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2886	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2887	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2888	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2889	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2890	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2891	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2892	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2893	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2894	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2895	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2896	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2897	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2898	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2899	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2900	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2901	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2902	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2903	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2904	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2905
2906	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2907	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2908	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2909	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2910	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2911	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2912	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2913	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2914	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2915	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2916	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2917	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2918	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2919	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2920	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2921	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2922	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2923	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2924	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2925	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2926	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2927	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2928	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2929	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2930	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2931	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2932	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2933	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2934	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2935	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2936	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2937	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2938	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2939	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2940	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2941	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2942	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2943	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2944	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2945	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2946	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2947	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2948	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2949	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2950	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2951	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2952	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2953	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2954	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2955	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2956	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2957	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2958	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2959	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2960	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2961	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2962	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2963
2964	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2965	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2966	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2967	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2968	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2969	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2970	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2971	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2972	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2973	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2974	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2975	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2976	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2977	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2978	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2979	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2980	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2981	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2982	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2983	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2984	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2985	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2986	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2987	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2988	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2989	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2990	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2991	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2992	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2993	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2994	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2995	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2996	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2997	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2998	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2999	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3000	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3001	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3002	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3003	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3004	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3005	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3006	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3007	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3008	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3009	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3010	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3011	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3012	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3013	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3014	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3015	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3016	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3017	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3018	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3019	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3020	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3021	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3022	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3023	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3024	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3025	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3026	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3027	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3028	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3029
3030	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3031	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3032	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3033	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3034
3035	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3036	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3037	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3038	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3039	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3040	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3041	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3042	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3043	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3044	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3045	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3046	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3047	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3048	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3049	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3050	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3051	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3052	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3053	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3054	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3055	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3056	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3057	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3058	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3059	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3060	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3061	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3062	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3063	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3064	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3065	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3066	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3067	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3068	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3069	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3070	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3071	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3072	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3073	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3074	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3075	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3076	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3077	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3078	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3079	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3080	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3081	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3082	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3083	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3084	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3085	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3086	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3087	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3088	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3089	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3090	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3091	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3092	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3093	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3094	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3095	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3096	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3097	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3098	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3099	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3100
3101	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3102	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3103	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3104	/** @} */
3105
3106	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3107	* @{ */
3108	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3109	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3110	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3111	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3112	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3113	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3114	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3115	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3116	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3117	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3118
3119	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3120	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3121	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3122	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3123	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3124	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3125	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3126	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3127	/** @} */
3128
3129	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3130	* @{ */
3131	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3132	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3133	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3134	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3135	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3136	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3137	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3138	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3139	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3140	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3141	/** @} */
3142
3143	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3144	* @{ */
3145	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3146	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3147	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3148	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3149	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3150	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3151	#ifndef IEM_WITHOUT_ASSEMBLY
3152	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3153	#endif
3154	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3155	/** @} */
3156
3157	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3158	* @{ */
3159	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3160	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3161	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3162	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3163	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3164	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3165	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3166	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3167	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3168	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3169	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3170	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3171	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3172	/** @} */
3173
3174	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3175	* @{ */
3176	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3177	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3178	#ifndef IEM_WITHOUT_ASSEMBLY
3179	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3180	#endif
3181	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3182	/** @} */
3183
3184	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3185	* @{ */
3186	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3187	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3188	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3189	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3190	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3191	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3192
3193	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3194	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3195	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3196	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3197	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3198	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3199
3200	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3201	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3202	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3203	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3204	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3205	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3206
3207	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3208	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3209	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3210	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3211	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3212	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3213	/** @} */
3214
3215
3216	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3217	* @{ */
3218	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3219	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3220	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3221	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3222	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3223	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3224
3225	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3226	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3227	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3228	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3229	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3230
3231	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3232	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3233	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3234	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3235	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3236
3237	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3238	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3239	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3240	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3241	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3242
3243	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3244	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3245	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3246	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3247	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3248
3249	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3250	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3251	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3252	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3253	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3254
3255	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3256	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3257	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3258	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3259	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3260
3261	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3262	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3263	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3264	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3265	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3266
3267	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3268	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3269	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3270	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3271	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3272
3273	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3274	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3275	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3276	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3277	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3278
3279	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3280	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3281	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3282	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3283	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3284
3285	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3286	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3287	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3288	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3289	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3290
3291	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3292	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3293	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3294	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3295	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3296
3297	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3298	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3299	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3300	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3301	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3302
3303	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3304	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3305	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3306	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3307	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3308
3309	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3310	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3311
3312	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
3313	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
3314	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3315	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3316
3317	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
3318	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3319	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3320	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3321
3322	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3323	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3324	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3325	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3326	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3327
3328	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3329	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3330	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3331	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3332	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3333
3334
3335	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3336	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3337	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3338	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3339	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3340	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3341
3342	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3343	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3344	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3345	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3346
3347	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3348	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3349	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3350	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3351
3352	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3353	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3354	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3355	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3356	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3357	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3358
3359	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3360	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3361	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3362	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3363	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3364
3365	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3366	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3367	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3368	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3369	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3370
3371	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3372
3373	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3374
3375	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3376	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3377	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3378	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3379	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3380	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3381	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3382	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3383
3384	typedef struct IEMPCMPISTRXSRC
3385	{
3386	RTUINT128U uSrc1;
3387	RTUINT128U uSrc2;
3388	} IEMPCMPISTRXSRC;
3389	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3390	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3391
3392	typedef struct IEMPCMPESTRXSRC
3393	{
3394	RTUINT128U uSrc1;
3395	RTUINT128U uSrc2;
3396	uint64_t u64Rax;
3397	uint64_t u64Rdx;
3398	} IEMPCMPESTRXSRC;
3399	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3400	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3401
3402	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3403	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3404	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3405	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3406
3407	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3408	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3409	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3410	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3411
3412	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3413	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3414	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3415	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3416
3417	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3418	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3419
3420	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3421	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3422	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3423	/** @} */
3424
3425	/** @name Media Odds and Ends
3426	* @{ */
3427	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3428	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3429	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3430	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3431	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3432	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3433	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3434	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3435
3436	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3437	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3438	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3439	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3440
3441	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3442	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3443	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3444	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3445	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3446	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3447	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3448	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3449
3450	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3451	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3452
3453	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3454	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3455
3456	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3457	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3458
3459	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3460	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3461
3462	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
3463	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3464	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
3465	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3466
3467	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3468	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3469
3470	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
3471	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3472	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
3473	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3474
3475	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3476	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3477
3478
3479	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3480	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3481
3482	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3483	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3484
3485	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3486	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3487
3488	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3489	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3490
3491	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3492	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3493
3494
3495	typedef struct IEMMEDIAF2XMMSRC
3496	{
3497	X86XMMREG uSrc1;
3498	X86XMMREG uSrc2;
3499	} IEMMEDIAF2XMMSRC;
3500	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3501	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3502
3503	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3504	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3505
3506	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3507	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3508	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3509	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3510	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3511	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3512
3513	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3514	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3515
3516	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3517	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3518
3519	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
3520	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3521
3522	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3523	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3524
3525	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3526	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3527
3528	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3529	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3530
3531	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
3532	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3533
3534	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3535	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3536
3537	/** @} */
3538
3539
3540	/** @name Function tables.
3541	* @{
3542	*/
3543
3544	/**
3545	* Function table for a binary operator providing implementation based on
3546	* operand size.
3547	*/
3548	typedef struct IEMOPBINSIZES
3549	{
3550	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3551	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3552	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3553	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3554	} IEMOPBINSIZES;
3555	/** Pointer to a binary operator function table. */
3556	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3557
3558
3559	/**
3560	* Function table for a unary operator providing implementation based on
3561	* operand size.
3562	*/
3563	typedef struct IEMOPUNARYSIZES
3564	{
3565	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3566	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3567	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3568	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3569	} IEMOPUNARYSIZES;
3570	/** Pointer to a unary operator function table. */
3571	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3572
3573
3574	/**
3575	* Function table for a shift operator providing implementation based on
3576	* operand size.
3577	*/
3578	typedef struct IEMOPSHIFTSIZES
3579	{
3580	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3581	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3582	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3583	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3584	} IEMOPSHIFTSIZES;
3585	/** Pointer to a shift operator function table. */
3586	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3587
3588
3589	/**
3590	* Function table for a multiplication or division operation.
3591	*/
3592	typedef struct IEMOPMULDIVSIZES
3593	{
3594	PFNIEMAIMPLMULDIVU8 pfnU8;
3595	PFNIEMAIMPLMULDIVU16 pfnU16;
3596	PFNIEMAIMPLMULDIVU32 pfnU32;
3597	PFNIEMAIMPLMULDIVU64 pfnU64;
3598	} IEMOPMULDIVSIZES;
3599	/** Pointer to a multiplication or division operation function table. */
3600	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3601
3602
3603	/**
3604	* Function table for a double precision shift operator providing implementation
3605	* based on operand size.
3606	*/
3607	typedef struct IEMOPSHIFTDBLSIZES
3608	{
3609	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3610	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3611	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3612	} IEMOPSHIFTDBLSIZES;
3613	/** Pointer to a double precision shift function table. */
3614	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3615
3616
3617	/**
3618	* Function table for media instruction taking two full sized media source
3619	* registers and one full sized destination register (AVX).
3620	*/
3621	typedef struct IEMOPMEDIAF3
3622	{
3623	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3624	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3625	} IEMOPMEDIAF3;
3626	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3627	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3628
3629	/** @def IEMOPMEDIAF3_INIT_VARS_EX
3630	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3631	* given functions as initializers. For use in AVX functions where a pair of
3632	* functions are only used once and the function table need not be public. */
3633	#ifndef TST_IEM_CHECK_MC
3634	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3635	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3636	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3637	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3638	# else
3639	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3640	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3641	# endif
3642	#else
3643	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3644	#endif
3645	/** @def IEMOPMEDIAF3_INIT_VARS
3646	* Generate AVX function tables for the @a a_InstrNm instruction.
3647	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
3648	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
3649	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3650	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3651
3652	/**
3653	* Function table for media instruction taking two full sized media source
3654	* registers and one full sized destination register, but no additional state
3655	* (AVX).
3656	*/
3657	typedef struct IEMOPMEDIAOPTF3
3658	{
3659	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
3660	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
3661	} IEMOPMEDIAOPTF3;
3662	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3663	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
3664
3665	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
3666	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3667	* given functions as initializers. For use in AVX functions where a pair of
3668	* functions are only used once and the function table need not be public. */
3669	#ifndef TST_IEM_CHECK_MC
3670	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3671	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3672	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3673	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3674	# else
3675	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3676	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3677	# endif
3678	#else
3679	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3680	#endif
3681	/** @def IEMOPMEDIAOPTF3_INIT_VARS
3682	* Generate AVX function tables for the @a a_InstrNm instruction.
3683	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
3684	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
3685	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3686	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3687
3688	/**
3689	* Function table for media instruction taking one full sized media source
3690	* registers and one full sized destination register, but no additional state
3691	* (AVX).
3692	*/
3693	typedef struct IEMOPMEDIAOPTF2
3694	{
3695	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
3696	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
3697	} IEMOPMEDIAOPTF2;
3698	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
3699	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
3700
3701	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3702	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3703	* given functions as initializers. For use in AVX functions where a pair of
3704	* functions are only used once and the function table need not be public. */
3705	#ifndef TST_IEM_CHECK_MC
3706	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3707	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3708	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3709	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3710	# else
3711	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3712	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3713	# endif
3714	#else
3715	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3716	#endif
3717	/** @def IEMOPMEDIAOPTF2_INIT_VARS
3718	* Generate AVX function tables for the @a a_InstrNm instruction.
3719	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3720	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3721	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3722	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3723
3724	/**
3725	* Function table for media instruction taking two full sized media source
3726	* registers and one full sized destination register and an 8-bit immediate, but no additional state
3727	* (AVX).
3728	*/
3729	typedef struct IEMOPMEDIAOPTF3IMM8
3730	{
3731	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3732	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3733	} IEMOPMEDIAOPTF3IMM8;
3734	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3735	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3736
3737	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3738	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3739	* given functions as initializers. For use in AVX functions where a pair of
3740	* functions are only used once and the function table need not be public. */
3741	#ifndef TST_IEM_CHECK_MC
3742	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3743	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3744	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3745	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3746	# else
3747	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3748	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3749	# endif
3750	#else
3751	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3752	#endif
3753	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3754	* Generate AVX function tables for the @a a_InstrNm instruction.
3755	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3756	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3757	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3758	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3759	/** @} */
3760
3761
3762	/**
3763	* Function table for blend type instruction taking three full sized media source
3764	* registers and one full sized destination register, but no additional state
3765	* (AVX).
3766	*/
3767	typedef struct IEMOPBLENDOP
3768	{
3769	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3770	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3771	} IEMOPBLENDOP;
3772	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3773	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3774
3775	/** @def IEMOPBLENDOP_INIT_VARS_EX
3776	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3777	* given functions as initializers. For use in AVX functions where a pair of
3778	* functions are only used once and the function table need not be public. */
3779	#ifndef TST_IEM_CHECK_MC
3780	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3781	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3782	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3783	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3784	# else
3785	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3786	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3787	# endif
3788	#else
3789	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3790	#endif
3791	/** @def IEMOPBLENDOP_INIT_VARS
3792	* Generate AVX function tables for the @a a_InstrNm instruction.
3793	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3794	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3795	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3796	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3797
3798
3799	/** @name SSE/AVX single/double precision floating point operations.
3800	* @{ */
3801	/**
3802	* A SSE result.
3803	*/
3804	typedef struct IEMSSERESULT
3805	{
3806	/** The output value. */
3807	X86XMMREG uResult;
3808	/** The output status. */
3809	uint32_t MXCSR;
3810	} IEMSSERESULT;
3811	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3812	/** Pointer to a SSE result. */
3813	typedef IEMSSERESULT *PIEMSSERESULT;
3814	/** Pointer to a const SSE result. */
3815	typedef IEMSSERESULT const *PCIEMSSERESULT;
3816
3817
3818	/**
3819	* A AVX128 result.
3820	*/
3821	typedef struct IEMAVX128RESULT
3822	{
3823	/** The output value. */
3824	X86XMMREG uResult;
3825	/** The output status. */
3826	uint32_t MXCSR;
3827	} IEMAVX128RESULT;
3828	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3829	/** Pointer to a AVX128 result. */
3830	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3831	/** Pointer to a const AVX128 result. */
3832	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3833
3834
3835	/**
3836	* A AVX256 result.
3837	*/
3838	typedef struct IEMAVX256RESULT
3839	{
3840	/** The output value. */
3841	X86YMMREG uResult;
3842	/** The output status. */
3843	uint32_t MXCSR;
3844	} IEMAVX256RESULT;
3845	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3846	/** Pointer to a AVX256 result. */
3847	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3848	/** Pointer to a const AVX256 result. */
3849	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3850
3851
3852	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3853	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3854	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3855	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3856	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3857	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3858
3859	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3860	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3861	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3862	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3863	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3864	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3865
3866	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3867	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3868
3869	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3870	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3871	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3872	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3873	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3874	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3875	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3876	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3877	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3878	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3879	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3880	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3881	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3882	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3883	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3884	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3885	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3886	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3887	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3888	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3889	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3890	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3891	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3892
3893	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3894	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3895	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3896	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3897	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3898	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3899
3900	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3901	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3902	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3903	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3904	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3905	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3906	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3907	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3908	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3909	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3910	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3911	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3912	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3913	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3914	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3915	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3916	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3917
3918	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3919	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3920	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3921	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3922	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3923	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3924	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3925	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3926	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3927	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3928	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3929	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3930	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3931	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3932	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3933	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3934	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3935	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3936	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3937	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3938	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3939	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3940
3941	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3942	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3943	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3944	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3945	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3946	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3947	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3948	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3949	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3950	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3951	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3952	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3953	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3954	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3955
3956	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3957	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3958	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3959	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3960	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3961	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3962	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3963	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3964	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3965	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3966	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3967	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3968	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3969	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3970	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3971	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3972	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3973	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3974	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3975	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3976	/** @} */
3977
3978	/** @name C instruction implementations for anything slightly complicated.
3979	* @{ */
3980
3981	/**
3982	* For typedef'ing or declaring a C instruction implementation function taking
3983	* no extra arguments.
3984	*
3985	* @param a_Name The name of the type.
3986	*/
3987	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3988	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3989	/**
3990	* For defining a C instruction implementation function taking no extra
3991	* arguments.
3992	*
3993	* @param a_Name The name of the function
3994	*/
3995	# define IEM_CIMPL_DEF_0(a_Name) \
3996	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3997	/**
3998	* Prototype version of IEM_CIMPL_DEF_0.
3999	*/
4000	# define IEM_CIMPL_PROTO_0(a_Name) \
4001	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4002	/**
4003	* For calling a C instruction implementation function taking no extra
4004	* arguments.
4005	*
4006	* This special call macro adds default arguments to the call and allow us to
4007	* change these later.
4008	*
4009	* @param a_fn The name of the function.
4010	*/
4011	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4012
4013	/** Type for a C instruction implementation function taking no extra
4014	* arguments. */
4015	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4016	/** Function pointer type for a C instruction implementation function taking
4017	* no extra arguments. */
4018	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4019
4020	/**
4021	* For typedef'ing or declaring a C instruction implementation function taking
4022	* one extra argument.
4023	*
4024	* @param a_Name The name of the type.
4025	* @param a_Type0 The argument type.
4026	* @param a_Arg0 The argument name.
4027	*/
4028	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4029	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4030	/**
4031	* For defining a C instruction implementation function taking one extra
4032	* argument.
4033	*
4034	* @param a_Name The name of the function
4035	* @param a_Type0 The argument type.
4036	* @param a_Arg0 The argument name.
4037	*/
4038	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4039	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4040	/**
4041	* Prototype version of IEM_CIMPL_DEF_1.
4042	*/
4043	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4044	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4045	/**
4046	* For calling a C instruction implementation function taking one extra
4047	* argument.
4048	*
4049	* This special call macro adds default arguments to the call and allow us to
4050	* change these later.
4051	*
4052	* @param a_fn The name of the function.
4053	* @param a0 The name of the 1st argument.
4054	*/
4055	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4056
4057	/**
4058	* For typedef'ing or declaring a C instruction implementation function taking
4059	* two extra arguments.
4060	*
4061	* @param a_Name The name of the type.
4062	* @param a_Type0 The type of the 1st argument
4063	* @param a_Arg0 The name of the 1st argument.
4064	* @param a_Type1 The type of the 2nd argument.
4065	* @param a_Arg1 The name of the 2nd argument.
4066	*/
4067	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4068	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4069	/**
4070	* For defining a C instruction implementation function taking two extra
4071	* arguments.
4072	*
4073	* @param a_Name The name of the function.
4074	* @param a_Type0 The type of the 1st argument
4075	* @param a_Arg0 The name of the 1st argument.
4076	* @param a_Type1 The type of the 2nd argument.
4077	* @param a_Arg1 The name of the 2nd argument.
4078	*/
4079	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4080	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4081	/**
4082	* Prototype version of IEM_CIMPL_DEF_2.
4083	*/
4084	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4085	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4086	/**
4087	* For calling a C instruction implementation function taking two extra
4088	* arguments.
4089	*
4090	* This special call macro adds default arguments to the call and allow us to
4091	* change these later.
4092	*
4093	* @param a_fn The name of the function.
4094	* @param a0 The name of the 1st argument.
4095	* @param a1 The name of the 2nd argument.
4096	*/
4097	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4098
4099	/**
4100	* For typedef'ing or declaring a C instruction implementation function taking
4101	* three extra arguments.
4102	*
4103	* @param a_Name The name of the type.
4104	* @param a_Type0 The type of the 1st argument
4105	* @param a_Arg0 The name of the 1st argument.
4106	* @param a_Type1 The type of the 2nd argument.
4107	* @param a_Arg1 The name of the 2nd argument.
4108	* @param a_Type2 The type of the 3rd argument.
4109	* @param a_Arg2 The name of the 3rd argument.
4110	*/
4111	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4112	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4113	/**
4114	* For defining a C instruction implementation function taking three extra
4115	* arguments.
4116	*
4117	* @param a_Name The name of the function.
4118	* @param a_Type0 The type of the 1st argument
4119	* @param a_Arg0 The name of the 1st argument.
4120	* @param a_Type1 The type of the 2nd argument.
4121	* @param a_Arg1 The name of the 2nd argument.
4122	* @param a_Type2 The type of the 3rd argument.
4123	* @param a_Arg2 The name of the 3rd argument.
4124	*/
4125	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4126	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4127	/**
4128	* Prototype version of IEM_CIMPL_DEF_3.
4129	*/
4130	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4131	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4132	/**
4133	* For calling a C instruction implementation function taking three extra
4134	* arguments.
4135	*
4136	* This special call macro adds default arguments to the call and allow us to
4137	* change these later.
4138	*
4139	* @param a_fn The name of the function.
4140	* @param a0 The name of the 1st argument.
4141	* @param a1 The name of the 2nd argument.
4142	* @param a2 The name of the 3rd argument.
4143	*/
4144	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4145
4146
4147	/**
4148	* For typedef'ing or declaring a C instruction implementation function taking
4149	* four extra arguments.
4150	*
4151	* @param a_Name The name of the type.
4152	* @param a_Type0 The type of the 1st argument
4153	* @param a_Arg0 The name of the 1st argument.
4154	* @param a_Type1 The type of the 2nd argument.
4155	* @param a_Arg1 The name of the 2nd argument.
4156	* @param a_Type2 The type of the 3rd argument.
4157	* @param a_Arg2 The name of the 3rd argument.
4158	* @param a_Type3 The type of the 4th argument.
4159	* @param a_Arg3 The name of the 4th argument.
4160	*/
4161	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4162	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4163	/**
4164	* For defining a C instruction implementation function taking four extra
4165	* arguments.
4166	*
4167	* @param a_Name The name of the function.
4168	* @param a_Type0 The type of the 1st argument
4169	* @param a_Arg0 The name of the 1st argument.
4170	* @param a_Type1 The type of the 2nd argument.
4171	* @param a_Arg1 The name of the 2nd argument.
4172	* @param a_Type2 The type of the 3rd argument.
4173	* @param a_Arg2 The name of the 3rd argument.
4174	* @param a_Type3 The type of the 4th argument.
4175	* @param a_Arg3 The name of the 4th argument.
4176	*/
4177	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4178	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4179	a_Type2 a_Arg2, a_Type3 a_Arg3))
4180	/**
4181	* Prototype version of IEM_CIMPL_DEF_4.
4182	*/
4183	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4184	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4185	a_Type2 a_Arg2, a_Type3 a_Arg3))
4186	/**
4187	* For calling a C instruction implementation function taking four extra
4188	* arguments.
4189	*
4190	* This special call macro adds default arguments to the call and allow us to
4191	* change these later.
4192	*
4193	* @param a_fn The name of the function.
4194	* @param a0 The name of the 1st argument.
4195	* @param a1 The name of the 2nd argument.
4196	* @param a2 The name of the 3rd argument.
4197	* @param a3 The name of the 4th argument.
4198	*/
4199	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4200
4201
4202	/**
4203	* For typedef'ing or declaring a C instruction implementation function taking
4204	* five extra arguments.
4205	*
4206	* @param a_Name The name of the type.
4207	* @param a_Type0 The type of the 1st argument
4208	* @param a_Arg0 The name of the 1st argument.
4209	* @param a_Type1 The type of the 2nd argument.
4210	* @param a_Arg1 The name of the 2nd argument.
4211	* @param a_Type2 The type of the 3rd argument.
4212	* @param a_Arg2 The name of the 3rd argument.
4213	* @param a_Type3 The type of the 4th argument.
4214	* @param a_Arg3 The name of the 4th argument.
4215	* @param a_Type4 The type of the 5th argument.
4216	* @param a_Arg4 The name of the 5th argument.
4217	*/
4218	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4219	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4220	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4221	a_Type3 a_Arg3, a_Type4 a_Arg4))
4222	/**
4223	* For defining a C instruction implementation function taking five extra
4224	* arguments.
4225	*
4226	* @param a_Name The name of the function.
4227	* @param a_Type0 The type of the 1st argument
4228	* @param a_Arg0 The name of the 1st argument.
4229	* @param a_Type1 The type of the 2nd argument.
4230	* @param a_Arg1 The name of the 2nd argument.
4231	* @param a_Type2 The type of the 3rd argument.
4232	* @param a_Arg2 The name of the 3rd argument.
4233	* @param a_Type3 The type of the 4th argument.
4234	* @param a_Arg3 The name of the 4th argument.
4235	* @param a_Type4 The type of the 5th argument.
4236	* @param a_Arg4 The name of the 5th argument.
4237	*/
4238	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4239	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4240	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4241	/**
4242	* Prototype version of IEM_CIMPL_DEF_5.
4243	*/
4244	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4245	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4246	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4247	/**
4248	* For calling a C instruction implementation function taking five extra
4249	* arguments.
4250	*
4251	* This special call macro adds default arguments to the call and allow us to
4252	* change these later.
4253	*
4254	* @param a_fn The name of the function.
4255	* @param a0 The name of the 1st argument.
4256	* @param a1 The name of the 2nd argument.
4257	* @param a2 The name of the 3rd argument.
4258	* @param a3 The name of the 4th argument.
4259	* @param a4 The name of the 5th argument.
4260	*/
4261	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4262
4263	/** @} */
4264
4265
4266	/** @name Opcode Decoder Function Types.
4267	* @{ */
4268
4269	/** @typedef PFNIEMOP
4270	* Pointer to an opcode decoder function.
4271	*/
4272
4273	/** @def FNIEMOP_DEF
4274	* Define an opcode decoder function.
4275	*
4276	* We're using macors for this so that adding and removing parameters as well as
4277	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4278	*
4279	* @param a_Name The function name.
4280	*/
4281
4282	/** @typedef PFNIEMOPRM
4283	* Pointer to an opcode decoder function with RM byte.
4284	*/
4285
4286	/** @def FNIEMOPRM_DEF
4287	* Define an opcode decoder function with RM byte.
4288	*
4289	* We're using macors for this so that adding and removing parameters as well as
4290	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4291	*
4292	* @param a_Name The function name.
4293	*/
4294
4295	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4296	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4297	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4298	# define FNIEMOP_DEF(a_Name) \
4299	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4300	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4301	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4302	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4303	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4304
4305	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4306	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4307	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4308	# define FNIEMOP_DEF(a_Name) \
4309	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4310	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4311	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4312	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4313	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4314
4315	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4316	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4317	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4318	# define FNIEMOP_DEF(a_Name) \
4319	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4320	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4321	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4322	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4323	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4324
4325	#else
4326	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4327	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4328	# define FNIEMOP_DEF(a_Name) \
4329	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4330	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4331	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4332	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4333	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4334
4335	#endif
4336	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4337
4338	/**
4339	* Call an opcode decoder function.
4340	*
4341	* We're using macors for this so that adding and removing parameters can be
4342	* done as we please. See FNIEMOP_DEF.
4343	*/
4344	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4345
4346	/**
4347	* Call a common opcode decoder function taking one extra argument.
4348	*
4349	* We're using macors for this so that adding and removing parameters can be
4350	* done as we please. See FNIEMOP_DEF_1.
4351	*/
4352	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4353
4354	/**
4355	* Call a common opcode decoder function taking one extra argument.
4356	*
4357	* We're using macors for this so that adding and removing parameters can be
4358	* done as we please. See FNIEMOP_DEF_1.
4359	*/
4360	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4361	/** @} */
4362
4363
4364	/** @name Misc Helpers
4365	* @{ */
4366
4367	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4368	* due to GCC lacking knowledge about the value range of a switch. */
4369	#if RT_CPLUSPLUS_PREREQ(202000)
4370	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4371	#else
4372	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4373	#endif
4374
4375	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4376	#if RT_CPLUSPLUS_PREREQ(202000)
4377	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4378	#else
4379	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4380	#endif
4381
4382	/**
4383	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4384	* occation.
4385	*/
4386	#ifdef LOG_ENABLED
4387	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4388	do { \
4389	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4390	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4391	} while (0)
4392	#else
4393	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4394	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4395	#endif
4396
4397	/**
4398	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4399	* occation using the supplied logger statement.
4400	*
4401	* @param a_LoggerArgs What to log on failure.
4402	*/
4403	#ifdef LOG_ENABLED
4404	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4405	do { \
4406	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4407	/LogFunc(a_LoggerArgs);/ \
4408	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4409	} while (0)
4410	#else
4411	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4412	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4413	#endif
4414
4415	/**
4416	* Gets the CPU mode (from fExec) as a IEMMODE value.
4417	*
4418	* @returns IEMMODE
4419	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4420	*/
4421	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4422
4423	/**
4424	* Check if we're currently executing in real or virtual 8086 mode.
4425	*
4426	* @returns @c true if it is, @c false if not.
4427	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4428	*/
4429	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4430	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
4431
4432	/**
4433	* Check if we're currently executing in virtual 8086 mode.
4434	*
4435	* @returns @c true if it is, @c false if not.
4436	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4437	*/
4438	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4439
4440	/**
4441	* Check if we're currently executing in long mode.
4442	*
4443	* @returns @c true if it is, @c false if not.
4444	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4445	*/
4446	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4447
4448	/**
4449	* Check if we're currently executing in a 16-bit code segment.
4450	*
4451	* @returns @c true if it is, @c false if not.
4452	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4453	*/
4454	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4455
4456	/**
4457	* Check if we're currently executing in a 32-bit code segment.
4458	*
4459	* @returns @c true if it is, @c false if not.
4460	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4461	*/
4462	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4463
4464	/**
4465	* Check if we're currently executing in a 64-bit code segment.
4466	*
4467	* @returns @c true if it is, @c false if not.
4468	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4469	*/
4470	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4471
4472	/**
4473	* Check if we're currently executing in real mode.
4474	*
4475	* @returns @c true if it is, @c false if not.
4476	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4477	*/
4478	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4479
4480	/**
4481	* Gets the current protection level (CPL).
4482	*
4483	* @returns 0..3
4484	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4485	*/
4486	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4487
4488	/**
4489	* Sets the current protection level (CPL).
4490	*
4491	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4492	*/
4493	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4494	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4495
4496	/**
4497	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4498	* @returns PCCPUMFEATURES
4499	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4500	*/
4501	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4502
4503	/**
4504	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4505	* @returns PCCPUMFEATURES
4506	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4507	*/
4508	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4509
4510	/**
4511	* Evaluates to true if we're presenting an Intel CPU to the guest.
4512	*/
4513	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4514
4515	/**
4516	* Evaluates to true if we're presenting an AMD CPU to the guest.
4517	*/
4518	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4519
4520	/**
4521	* Check if the address is canonical.
4522	*/
4523	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4524
4525	/** Checks if the ModR/M byte is in register mode or not. */
4526	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4527	/** Checks if the ModR/M byte is in memory mode or not. */
4528	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4529
4530	/**
4531	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4532	*
4533	* For use during decoding.
4534	*/
4535	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
4536	/**
4537	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4538	*
4539	* For use during decoding.
4540	*/
4541	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
4542
4543	/**
4544	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
4545	*
4546	* For use during decoding.
4547	*/
4548	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4549	/**
4550	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4551	*
4552	* For use during decoding.
4553	*/
4554	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4555
4556	/**
4557	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4558	* register index, with REX.R added in.
4559	*
4560	* For use during decoding.
4561	*
4562	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4563	*/
4564	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4565	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4566	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4567	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4568	/**
4569	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4570	* with REX.B added in.
4571	*
4572	* For use during decoding.
4573	*
4574	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4575	*/
4576	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4577	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4578	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4579	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4580
4581	/**
4582	* Combines the prefix REX and ModR/M byte for passing to
4583	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4584	*
4585	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4586	* The two bits are part of the REG sub-field, which isn't needed in
4587	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4588	*
4589	* For use during decoding/recompiling.
4590	*/
4591	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4592	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4593	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
4594	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
4595	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
4596
4597	/**
4598	* Gets the effective VEX.VVVV value.
4599	*
4600	* The 4th bit is ignored if not 64-bit code.
4601	* @returns effective V-register value.
4602	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4603	*/
4604	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4605	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4606
4607
4608	/**
4609	* Checks if we're executing inside an AMD-V or VT-x guest.
4610	*/
4611	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
4612	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
4613	#else
4614	# define IEM_IS_IN_GUEST(a_pVCpu) false
4615	#endif
4616
4617
4618	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4619
4620	/**
4621	* Check if the guest has entered VMX root operation.
4622	*/
4623	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
4624
4625	/**
4626	* Check if the guest has entered VMX non-root operation.
4627	*/
4628	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
4629	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
4630
4631	/**
4632	* Check if the nested-guest has the given Pin-based VM-execution control set.
4633	*/
4634	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
4635
4636	/**
4637	* Check if the nested-guest has the given Processor-based VM-execution control set.
4638	*/
4639	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
4640
4641	/**
4642	* Check if the nested-guest has the given Secondary Processor-based VM-execution
4643	* control set.
4644	*/
4645	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
4646
4647	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
4648	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
4649
4650	/** Whether a shadow VMCS is present for the given VCPU. */
4651	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4652
4653	/** Gets the VMXON region pointer. */
4654	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
4655
4656	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
4657	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
4658
4659	/** Whether a current VMCS is present for the given VCPU. */
4660	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4661
4662	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
4663	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
4664	do \
4665	{ \
4666	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
4667	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
4668	} while (0)
4669
4670	/** Clears any current VMCS for the given VCPU. */
4671	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
4672	do \
4673	{ \
4674	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
4675	} while (0)
4676
4677	/**
4678	* Invokes the VMX VM-exit handler for an instruction intercept.
4679	*/
4680	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
4681	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
4682
4683	/**
4684	* Invokes the VMX VM-exit handler for an instruction intercept where the
4685	* instruction provides additional VM-exit information.
4686	*/
4687	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
4688	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
4689
4690	/**
4691	* Invokes the VMX VM-exit handler for a task switch.
4692	*/
4693	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
4694	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
4695
4696	/**
4697	* Invokes the VMX VM-exit handler for MWAIT.
4698	*/
4699	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
4700	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
4701
4702	/**
4703	* Invokes the VMX VM-exit handler for EPT faults.
4704	*/
4705	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
4706	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
4707
4708	/**
4709	* Invokes the VMX VM-exit handler.
4710	*/
4711	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4712	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4713
4714	#else
4715	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4716	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4717	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4718	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4719	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4720	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4721	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4722	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4723	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4724	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4725	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4726
4727	#endif
4728
4729	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4730	/**
4731	* Checks if we're executing a guest using AMD-V.
4732	*/
4733	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
4734	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
4735	/**
4736	* Check if an SVM control/instruction intercept is set.
4737	*/
4738	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4739	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4740
4741	/**
4742	* Check if an SVM read CRx intercept is set.
4743	*/
4744	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4745	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4746
4747	/**
4748	* Check if an SVM write CRx intercept is set.
4749	*/
4750	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4751	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4752
4753	/**
4754	* Check if an SVM read DRx intercept is set.
4755	*/
4756	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4757	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4758
4759	/**
4760	* Check if an SVM write DRx intercept is set.
4761	*/
4762	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4763	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4764
4765	/**
4766	* Check if an SVM exception intercept is set.
4767	*/
4768	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4769	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4770
4771	/**
4772	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4773	*/
4774	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4775	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4776
4777	/**
4778	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4779	* corresponding decode assist information.
4780	*/
4781	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4782	do \
4783	{ \
4784	uint64_t uExitInfo1; \
4785	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4786	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4787	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4788	else \
4789	uExitInfo1 = 0; \
4790	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4791	} while (0)
4792
4793	/** Check and handles SVM nested-guest instruction intercept and updates
4794	* NRIP if needed.
4795	*/
4796	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4797	do \
4798	{ \
4799	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4800	{ \
4801	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4802	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4803	} \
4804	} while (0)
4805
4806	/** Checks and handles SVM nested-guest CR0 read intercept. */
4807	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4808	do \
4809	{ \
4810	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4811	{ /* probably likely */ } \
4812	else \
4813	{ \
4814	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4815	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4816	} \
4817	} while (0)
4818
4819	/**
4820	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4821	*/
4822	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4823	do { \
4824	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4825	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4826	} while (0)
4827
4828	#else
4829	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4830	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4831	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4832	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4833	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4834	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4835	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4836	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4837	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4838	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4839	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4840	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4841
4842	#endif
4843
4844	/** @} */
4845
4846	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4847	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4848
4849
4850	/**
4851	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4852	*/
4853	typedef union IEMSELDESC
4854	{
4855	/** The legacy view. */
4856	X86DESC Legacy;
4857	/** The long mode view. */
4858	X86DESC64 Long;
4859	} IEMSELDESC;
4860	/** Pointer to a selector descriptor table entry. */
4861	typedef IEMSELDESC *PIEMSELDESC;
4862
4863	/** @name Raising Exceptions.
4864	* @{ */
4865	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4866	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4867
4868	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4869	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4870	#ifdef IEM_WITH_SETJMP
4871	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4872	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4873	#endif
4874	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4875	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4876	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4877	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4878	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4879	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4880	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4881	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4882	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4883	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4884	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4885	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4886	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4887	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4888	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4889	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4890	#ifdef IEM_WITH_SETJMP
4891	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4892	#endif
4893	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4894	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4895	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4896	#ifdef IEM_WITH_SETJMP
4897	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4898	#endif
4899	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4900	#ifdef IEM_WITH_SETJMP
4901	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4902	#endif
4903	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4904	#ifdef IEM_WITH_SETJMP
4905	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4906	#endif
4907	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4908	#ifdef IEM_WITH_SETJMP
4909	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4910	#endif
4911	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4912	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4913	#ifdef IEM_WITH_SETJMP
4914	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4915	#endif
4916	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4917
4918	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
4919
4920	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4921	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4922	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4923
4924	/**
4925	* Macro for calling iemCImplRaiseDivideError().
4926	*
4927	* This is for things that will _always_ decode to an \#DE, taking the
4928	* recompiler into consideration and everything.
4929	*
4930	* @return Strict VBox status code.
4931	*/
4932	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
4933
4934	/**
4935	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4936	*
4937	* This is for things that will _always_ decode to an \#UD, taking the
4938	* recompiler into consideration and everything.
4939	*
4940	* @return Strict VBox status code.
4941	*/
4942	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
4943
4944	/**
4945	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
4946	*
4947	* This is for things that will _always_ decode to an \#UD, taking the
4948	* recompiler into consideration and everything.
4949	*
4950	* @return Strict VBox status code.
4951	*/
4952	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
4953
4954	/**
4955	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
4956	*
4957	* Using this macro means you've got _buggy_ _code_ and are doing things that
4958	* belongs exclusively in IEMAllCImpl.cpp during decoding.
4959	*
4960	* @return Strict VBox status code.
4961	* @see IEMOP_RAISE_INVALID_OPCODE_RET
4962	*/
4963	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
4964
4965	/** @} */
4966
4967	/** @name Register Access.
4968	* @{ */
4969	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4970	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4971	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4972	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4973	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4974	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4975	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4976	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4977	/** @} */
4978
4979	/** @name FPU access and helpers.
4980	* @{ */
4981	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4982	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4983	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4984	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4985	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4986	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4987	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4988	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4989	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4990	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4991	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4992	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4993	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4994	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4995	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4996	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4997	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4998	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4999	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5000	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5001	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5002	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5003	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5004	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5005	/** @} */
5006
5007	/** @name SSE+AVX SIMD access and helpers.
5008	* @{ */
5009	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
5010	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5011	/** @} */
5012
5013	/** @name Memory access.
5014	* @{ */
5015
5016	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5017	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5018	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5019	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5020	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5021	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5022	* Users include FXSAVE & FXRSTOR. */
5023	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5024
5025	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5026	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5027	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
5028	#ifndef IN_RING3
5029	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
5030	#endif
5031	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5032	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5033	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5034	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5035
5036	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5037	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5038	#ifdef IEM_WITH_CODE_TLB
5039	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5040	#else
5041	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5042	#endif
5043	#ifdef IEM_WITH_SETJMP
5044	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5045	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5046	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5047	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5048	#else
5049	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5050	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5051	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5052	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5053	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5054	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5055	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5056	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5057	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5058	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5059	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5060	#endif
5061
5062	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5063	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5064	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5065	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5066	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5067	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5068	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5069	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5070	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5071	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5072	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5073	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5074	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5075	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5076	#ifdef IEM_WITH_SETJMP
5077	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5078	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5079	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5080	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5081	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5082	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5083	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5084	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5085	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5086	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5087	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5088	void iemMemFetchDataU256AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5089	# if 0 /* these are inlined now */
5090	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5091	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5092	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5093	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5094	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5095	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5096	# endif
5097	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5098	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5099	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5100	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5101	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5102	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5103	#endif
5104
5105	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5106	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5107	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5108	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5109	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5110
5111	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5112	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5113	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5114	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5115	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5116	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5117	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5118	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5119	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5120	#ifdef IEM_WITH_SETJMP
5121	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5122	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5123	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5124	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5125	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5126	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5127	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5128	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5129	#if 0
5130	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5131	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5132	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5133	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5134	#endif
5135	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5136	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5137	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5138	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5139	#endif
5140
5141	#ifdef IEM_WITH_SETJMP
5142	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5143	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5144	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5145	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5146	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5147	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5148	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5149	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5150	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5151	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5152	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5153	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5154
5155	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5156	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5157	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, const void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5158	#endif
5159
5160	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5161	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
5162	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
5163	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5164	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5165	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5166	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5167	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5168	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5169	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5170	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5171	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
5172	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5173	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
5174	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
5175	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5176	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5177	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5178	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5179	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5180	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5181
5182	#ifdef IEM_WITH_SETJMP
5183	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5184	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5185	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5186	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5187	uint16_t iemMemStackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5188	uint32_t iemMemStackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5189	uint64_t iemMemStackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5190
5191	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5192	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5193	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5194	uint16_t iemMemFlat32StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5195	uint32_t iemMemFlat32StackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5196
5197	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5198	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5199	uint16_t iemMemFlat64StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5200	uint64_t iemMemFlat64StackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5201	#endif
5202
5203	/** @} */
5204
5205	/** @name IEMAllCImpl.cpp
5206	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5207	* @{ */
5208	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5209	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5210	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5211	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5212	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5213	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5214	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5215	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5216	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5217	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
5218	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
5219	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
5220	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
5221	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
5222	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
5223	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5224	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5225	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5226	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5227	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5228	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
5229	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5230	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5231	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5232	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5233	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5234	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5235	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5236	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5237	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5238	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5239	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5240	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5241	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5242	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5243	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5244	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5245	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5246	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5247	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5248	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5249	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5250	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5251	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5252	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5253	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5254	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5255	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5256	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5257	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5258	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5259	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5260	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5261	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5262	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5263	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5264	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5265	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5266	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5267	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5268	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5269	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5270	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5271	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5272	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5273	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5274	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5275	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5276	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5277	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5278	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5279	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5280	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5281	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5282	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5283	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5284	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5285	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5286	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5287	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5288	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5289	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5290	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5291	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5292	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5293	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5294	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5295	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5296	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5297	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5298	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5299	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5300	IEM_CIMPL_PROTO_0(iemCImpl_das);
5301	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5302	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5303	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5304	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5305	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5306	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5307	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5308	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
5309	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5310	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5311	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5312	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5313	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5314	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5315	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5316	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5317	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5318	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5319	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5320	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5321	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5322	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5323	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5324	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5325	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5326	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5327	/** @} */
5328
5329	/** @name IEMAllCImplStrInstr.cpp.h
5330	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5331	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5332	* @{ */
5333	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5334	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5335	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5336	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5337	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5338	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5339	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5340	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5341	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5342	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5343	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5344
5345	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5346	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5347	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5348	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5349	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5350	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5351	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5352	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5353	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5354	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5355	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5356
5357	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5358	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5359	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5360	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5361	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5362	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5363	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5364	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5365	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5366	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5367	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5368
5369
5370	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5371	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5372	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5373	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5374	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5375	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5376	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5377	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5378	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5379	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5380	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5381
5382	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5383	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5384	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5385	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5386	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5387	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5388	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5389	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5390	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5391	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5392	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5393
5394	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5395	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5396	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5397	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5398	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5399	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5400	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5401	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5402	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5403	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5404	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5405
5406	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5407	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5408	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5409	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5410	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5411	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5412	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5413	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5414	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5415	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5416	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5417
5418
5419	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
5420	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
5421	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
5422	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
5423	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
5424	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
5425	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
5426	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
5427	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
5428	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5429	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5430
5431	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
5432	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
5433	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
5434	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
5435	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
5436	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
5437	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
5438	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
5439	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
5440	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5441	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5442
5443	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
5444	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
5445	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
5446	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
5447	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
5448	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
5449	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
5450	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
5451	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
5452	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5453	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5454
5455	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
5456	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
5457	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
5458	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
5459	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
5460	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
5461	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
5462	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
5463	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
5464	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5465	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5466	/** @} */
5467
5468	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5469	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
5470	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
5471	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
5472	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
5473	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
5474	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5475	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
5476	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
5477	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
5478	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
5479	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
5480	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
5481	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
5482	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5483	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5484	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5485	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5486	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5487	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5488	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
5489	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
5490	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
5491	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
5492	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
5493	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
5494	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
5495	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
5496	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
5497	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
5498	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
5499	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
5500	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5501	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5502	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5503	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5504	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5505	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5506	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5507	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5508	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5509	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5510	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5511	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5512	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5513	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5514	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5515	#endif
5516
5517	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5518	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5519	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5520	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5521	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5522	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
5523	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
5524	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
5525	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
5526	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
5527	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
5528	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
5529	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
5530	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
5531	#endif
5532
5533	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
5534	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
5535	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
5536
5537	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
5538	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
5539	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
5540	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
5541	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
5542	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
5543	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
5544
5545	/*
5546	* Recompiler related stuff.
5547	*/
5548	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
5549	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
5550	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
5551	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
5552	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
5553	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
5554	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
5555
5556	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
5557	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
5558	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
5559	void iemTbAllocatorProcessDelayedFrees(PVMCPU pVCpu, PIEMTBALLOCATOR pTbAllocator);
5560
5561
5562	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
5563	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5564	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5565	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5566	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5567	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5568	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5569	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5570
5571	#else
5572	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5573	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5574	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5575	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5576	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5577	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5578	#endif
5579
5580
5581	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
5582
5583	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
5584	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
5585	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
5586	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
5587
5588	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
5589	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
5590	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
5591
5592	/* Branching: */
5593	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
5594	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
5595	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
5596
5597	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
5598	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
5599	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
5600
5601	/* Natural page crossing: */
5602	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
5603	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
5604	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
5605
5606	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
5607	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
5608	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
5609
5610	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
5611	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
5612	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
5613
5614	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
5615	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
5616
5617	/* Native recompiler public bits: */
5618	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
5619	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk);
5620	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb);
5621
5622
5623	/** @} */
5624
5625	RT_C_DECLS_END
5626
5627	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
5628

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 101984

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