IEMInternal.h@ 100140

Last change on this file since 100140 was 100072, checked in by vboxsync, 18 months ago
VMM/IEM: Reworked all the IEM_MC_CALL/DEFER_TO_CIMPL macros to include some clues about what they may end up doing. The IEM_MC_DEFER_TO_CIMPL_X macros now returns implictly and is renamed to IEM_MC_DEFER_TO_CIMPL_X_RET - this will ease adding more code/whatever to follow the return from the call when recompiling and such. Also fixed buggy POP CS in 8086 mode. bugref:10369
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 240.1 KB

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1	/* $Id: IEMInternal.h 100072 2023-06-05 15:17:42Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	/** @def IEM_WITH_THROW_CATCH
70	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71	* mode code when IEM_WITH_SETJMP is in effect.
72	*
73	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
75	* result value improving by more than 1%. (Best out of three.)
76	*
77	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
78	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
79	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
80	* Linux, but it should be quite a bit faster for normal code.
81	*/
82	#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
83	\|\| defined(DOXYGEN_RUNNING)
84	# define IEM_WITH_THROW_CATCH
85	#endif
86
87	/** @def IEM_DO_LONGJMP
88	*
89	* Wrapper around longjmp / throw.
90	*
91	* @param a_pVCpu The CPU handle.
92	* @param a_rc The status code jump back with / throw.
93	*/
94	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
95	# ifdef IEM_WITH_THROW_CATCH
96	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
97	# else
98	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
99	# endif
100	#endif
101
102	/** For use with IEM function that may do a longjmp (when enabled).
103	*
104	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
105	* attribute. So, we indicate that function that may be part of a longjmp may
106	* throw "exceptions" and that the compiler should definitely not generate and
107	* std::terminate calling unwind code.
108	*
109	* Here is one example of this ending in std::terminate:
110	* @code{.txt}
111	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
112	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
113	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
114	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
115	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
116	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
117	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
118	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
119	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
120	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
121	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
122	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
123	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
124	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
125	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
126	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
127	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
128	@endcode
129	*
130	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
131	*/
132	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
133	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
134	#else
135	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
136	#endif
137
138	#define IEM_IMPLEMENTS_TASKSWITCH
139
140	/** @def IEM_WITH_3DNOW
141	* Includes the 3DNow decoding. */
142	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
143	# define IEM_WITH_3DNOW
144	#endif
145
146	/** @def IEM_WITH_THREE_0F_38
147	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
148	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
149	# define IEM_WITH_THREE_0F_38
150	#endif
151
152	/** @def IEM_WITH_THREE_0F_3A
153	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
154	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
155	# define IEM_WITH_THREE_0F_3A
156	#endif
157
158	/** @def IEM_WITH_VEX
159	* Includes the VEX decoding. */
160	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
161	# define IEM_WITH_VEX
162	#endif
163
164	/** @def IEM_CFG_TARGET_CPU
165	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
166	*
167	* By default we allow this to be configured by the user via the
168	* CPUM/GuestCpuName config string, but this comes at a slight cost during
169	* decoding. So, for applications of this code where there is no need to
170	* be dynamic wrt target CPU, just modify this define.
171	*/
172	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
173	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
174	#endif
175
176	//#define IEM_WITH_CODE_TLB // - work in progress
177	//#define IEM_WITH_DATA_TLB // - work in progress
178
179
180	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
181	* Use unaligned accesses instead of elaborate byte assembly. */
182	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
183	# define IEM_USE_UNALIGNED_DATA_ACCESS
184	#endif
185
186	//#define IEM_LOG_MEMORY_WRITES
187
188	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
189	/** Instruction statistics. */
190	typedef struct IEMINSTRSTATS
191	{
192	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
193	# include "IEMInstructionStatisticsTmpl.h"
194	# undef IEM_DO_INSTR_STAT
195	} IEMINSTRSTATS;
196	#else
197	struct IEMINSTRSTATS;
198	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
199	#endif
200	/** Pointer to IEM instruction statistics. */
201	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
202
203
204	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
205	* @{ */
206	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
207	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
211	/** Selects the right variant from a_aArray.
212	* pVCpu is implicit in the caller context. */
213	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
214	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
215	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
216	* be used because the host CPU does not support the operation. */
217	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
218	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
219	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
220	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
221	* into the two.
222	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
223	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
224	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
225	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
226	#else
227	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
228	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
229	#endif
230	/** @} */
231
232	/**
233	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
234	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
235	*
236	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
237	* indicator.
238	*
239	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
240	*/
241	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
242	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
243	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
244	#else
245	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
246	#endif
247
248
249	/**
250	* Extended operand mode that includes a representation of 8-bit.
251	*
252	* This is used for packing down modes when invoking some C instruction
253	* implementations.
254	*/
255	typedef enum IEMMODEX
256	{
257	IEMMODEX_16BIT = IEMMODE_16BIT,
258	IEMMODEX_32BIT = IEMMODE_32BIT,
259	IEMMODEX_64BIT = IEMMODE_64BIT,
260	IEMMODEX_8BIT
261	} IEMMODEX;
262	AssertCompileSize(IEMMODEX, 4);
263
264
265	/**
266	* Branch types.
267	*/
268	typedef enum IEMBRANCH
269	{
270	IEMBRANCH_JUMP = 1,
271	IEMBRANCH_CALL,
272	IEMBRANCH_TRAP,
273	IEMBRANCH_SOFTWARE_INT,
274	IEMBRANCH_HARDWARE_INT
275	} IEMBRANCH;
276	AssertCompileSize(IEMBRANCH, 4);
277
278
279	/**
280	* INT instruction types.
281	*/
282	typedef enum IEMINT
283	{
284	/** INT n instruction (opcode 0xcd imm). */
285	IEMINT_INTN = 0,
286	/** Single byte INT3 instruction (opcode 0xcc). */
287	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
288	/** Single byte INTO instruction (opcode 0xce). */
289	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
290	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
291	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
292	} IEMINT;
293	AssertCompileSize(IEMINT, 4);
294
295
296	/**
297	* A FPU result.
298	*/
299	typedef struct IEMFPURESULT
300	{
301	/** The output value. */
302	RTFLOAT80U r80Result;
303	/** The output status. */
304	uint16_t FSW;
305	} IEMFPURESULT;
306	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
307	/** Pointer to a FPU result. */
308	typedef IEMFPURESULT *PIEMFPURESULT;
309	/** Pointer to a const FPU result. */
310	typedef IEMFPURESULT const *PCIEMFPURESULT;
311
312
313	/**
314	* A FPU result consisting of two output values and FSW.
315	*/
316	typedef struct IEMFPURESULTTWO
317	{
318	/** The first output value. */
319	RTFLOAT80U r80Result1;
320	/** The output status. */
321	uint16_t FSW;
322	/** The second output value. */
323	RTFLOAT80U r80Result2;
324	} IEMFPURESULTTWO;
325	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
326	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
327	/** Pointer to a FPU result consisting of two output values and FSW. */
328	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
329	/** Pointer to a const FPU result consisting of two output values and FSW. */
330	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
331
332
333	/**
334	* IEM TLB entry.
335	*
336	* Lookup assembly:
337	* @code{.asm}
338	; Calculate tag.
339	mov rax, [VA]
340	shl rax, 16
341	shr rax, 16 + X86_PAGE_SHIFT
342	or rax, [uTlbRevision]
343
344	; Do indexing.
345	movzx ecx, al
346	lea rcx, [pTlbEntries + rcx]
347
348	; Check tag.
349	cmp [rcx + IEMTLBENTRY.uTag], rax
350	jne .TlbMiss
351
352	; Check access.
353	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
354	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
355	cmp rax, [uTlbPhysRev]
356	jne .TlbMiss
357
358	; Calc address and we're done.
359	mov eax, X86_PAGE_OFFSET_MASK
360	and eax, [VA]
361	or rax, [rcx + IEMTLBENTRY.pMappingR3]
362	%ifdef VBOX_WITH_STATISTICS
363	inc qword [cTlbHits]
364	%endif
365	jmp .Done
366
367	.TlbMiss:
368	mov r8d, ACCESS_FLAGS
369	mov rdx, [VA]
370	mov rcx, [pVCpu]
371	call iemTlbTypeMiss
372	.Done:
373
374	@endcode
375	*
376	*/
377	typedef struct IEMTLBENTRY
378	{
379	/** The TLB entry tag.
380	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
381	* is ASSUMING a virtual address width of 48 bits.
382	*
383	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
384	*
385	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
386	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
387	* revision wraps around though, the tags needs to be zeroed.
388	*
389	* @note Try use SHRD instruction? After seeing
390	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
391	*
392	* @todo This will need to be reorganized for 57-bit wide virtual address and
393	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
394	* have to move the TLB entry versioning entirely to the
395	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
396	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
397	* consumed by PCID and ASID (12 + 6 = 18).
398	*/
399	uint64_t uTag;
400	/** Access flags and physical TLB revision.
401	*
402	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
403	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
404	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
405	* - Bit 3 - pgm phys/virt - not directly writable.
406	* - Bit 4 - pgm phys page - not directly readable.
407	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
408	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
409	* - Bit 7 - tlb entry - pMappingR3 member not valid.
410	* - Bits 63 thru 8 are used for the physical TLB revision number.
411	*
412	* We're using complemented bit meanings here because it makes it easy to check
413	* whether special action is required. For instance a user mode write access
414	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
415	* non-zero result would mean special handling needed because either it wasn't
416	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
417	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
418	* need to check any PTE flag.
419	*/
420	uint64_t fFlagsAndPhysRev;
421	/** The guest physical page address. */
422	uint64_t GCPhys;
423	/** Pointer to the ring-3 mapping. */
424	R3PTRTYPE(uint8_t *) pbMappingR3;
425	#if HC_ARCH_BITS == 32
426	uint32_t u32Padding1;
427	#endif
428	} IEMTLBENTRY;
429	AssertCompileSize(IEMTLBENTRY, 32);
430	/** Pointer to an IEM TLB entry. */
431	typedef IEMTLBENTRY *PIEMTLBENTRY;
432
433	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
434	* @{ */
435	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
436	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
437	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
438	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
439	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
440	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
441	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
442	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
443	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
444	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
445	/** @} */
446
447
448	/**
449	* An IEM TLB.
450	*
451	* We've got two of these, one for data and one for instructions.
452	*/
453	typedef struct IEMTLB
454	{
455	/** The TLB entries.
456	* We've choosen 256 because that way we can obtain the result directly from a
457	* 8-bit register without an additional AND instruction. */
458	IEMTLBENTRY aEntries[256];
459	/** The TLB revision.
460	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
461	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
462	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
463	* (The revision zero indicates an invalid TLB entry.)
464	*
465	* The initial value is choosen to cause an early wraparound. */
466	uint64_t uTlbRevision;
467	/** The TLB physical address revision - shadow of PGM variable.
468	*
469	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
470	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
471	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
472	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
473	*
474	* The initial value is choosen to cause an early wraparound. */
475	uint64_t volatile uTlbPhysRev;
476
477	/* Statistics: */
478
479	/** TLB hits (VBOX_WITH_STATISTICS only). */
480	uint64_t cTlbHits;
481	/** TLB misses. */
482	uint32_t cTlbMisses;
483	/** Slow read path. */
484	uint32_t cTlbSlowReadPath;
485	#if 0
486	/** TLB misses because of tag mismatch. */
487	uint32_t cTlbMissesTag;
488	/** TLB misses because of virtual access violation. */
489	uint32_t cTlbMissesVirtAccess;
490	/** TLB misses because of dirty bit. */
491	uint32_t cTlbMissesDirty;
492	/** TLB misses because of MMIO */
493	uint32_t cTlbMissesMmio;
494	/** TLB misses because of write access handlers. */
495	uint32_t cTlbMissesWriteHandler;
496	/** TLB misses because no r3(/r0) mapping. */
497	uint32_t cTlbMissesMapping;
498	#endif
499	/** Alignment padding. */
500	uint32_t au32Padding[3+5];
501	} IEMTLB;
502	AssertCompileSizeAlignment(IEMTLB, 64);
503	/** IEMTLB::uTlbRevision increment. */
504	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
505	/** IEMTLB::uTlbRevision mask. */
506	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
507	/** IEMTLB::uTlbPhysRev increment.
508	* @sa IEMTLBE_F_PHYS_REV */
509	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
510	/**
511	* Calculates the TLB tag for a virtual address.
512	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
513	* @param a_pTlb The TLB.
514	* @param a_GCPtr The virtual address.
515	*/
516	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
517	/**
518	* Calculates the TLB tag for a virtual address but without TLB revision.
519	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
520	* @param a_GCPtr The virtual address.
521	*/
522	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
523	/**
524	* Converts a TLB tag value into a TLB index.
525	* @returns Index into IEMTLB::aEntries.
526	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
527	*/
528	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
529	/**
530	* Converts a TLB tag value into a TLB index.
531	* @returns Index into IEMTLB::aEntries.
532	* @param a_pTlb The TLB.
533	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
534	*/
535	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
536
537
538	/** Pointer to a translation block. */
539	typedef struct IEMTB *PIEMTB;
540
541	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
542	*
543	* These flags are set when entering IEM and adjusted as code is executed, such
544	* that they will always contain the current values as instructions are
545	* finished.
546	*
547	* In recompiled execution mode, (most of) these flags are included in the
548	* translation block selection key and stored in IEMTB::fFlags alongside the
549	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
550	* in IEMCPU::fExec.
551	*
552	* @{ */
553	/** Mode: The block target mode mask. */
554	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
555	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
556	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
557	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
558	* conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
559	* 32-bit mode (for simplifying most memory accesses). */
560	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
561	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
562	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
563	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
564	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
565
566	/** X86 Mode: 16-bit on 386 or later. */
567	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
568	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
569	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
570	/** X86 Mode: 16-bit protected mode on 386 or later. */
571	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
572	/** X86 Mode: 16-bit protected mode on 386 or later. */
573	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
574	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
575	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
576
577	/** X86 Mode: 32-bit on 386 or later. */
578	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
579	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
580	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
581	/** X86 Mode: 32-bit protected mode. */
582	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
583	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
584	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
585
586	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
587	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
588
589
590	/** Bypass access handlers when set. */
591	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
592	/** Have pending hardware instruction breakpoints. */
593	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
594	/** Have pending hardware data breakpoints. */
595	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
596
597	/** X86: Have pending hardware I/O breakpoints. */
598	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
599	/** X86: Disregard the lock prefix (implied or not) when set. */
600	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
601
602	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
603	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
604
605	/** Caller configurable options. */
606	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
607
608	/** X86: The current protection level (CPL) shift factor. */
609	#define IEM_F_X86_CPL_SHIFT 8
610	/** X86: The current protection level (CPL) mask. */
611	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
612	/** X86: The current protection level (CPL) shifted mask. */
613	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
614
615	/** X86 execution context.
616	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
617	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
618	* mode. */
619	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
620	/** X86 context: Plain regular execution context. */
621	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
622	/** X86 context: VT-x enabled. */
623	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
624	/** X86 context: AMD-V enabled. */
625	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
626	/** X86 context: In AMD-V or VT-x guest mode. */
627	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
628	/** X86 context: System management mode (SMM). */
629	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
630
631	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
632	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
633	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
634	* alread). */
635
636	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
637	* iemRegFinishClearingRF() most for most situations
638	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
639	* the IEM_F_PENDING_BRK_XXX bits alread). */
640
641	/** @} */
642
643
644	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
645	*
646	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
647	* translation block flags. The combined flag mask (subject to
648	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
649	*
650	* @{ */
651	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
652	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
653
654	/** Type: The block type mask. */
655	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
656	/** Type: Purly threaded recompiler (via tables). */
657	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
658	/** Type: Native recompilation. */
659	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
660
661	/** State mask. */
662	#define IEMTB_F_STATE_MASK UINT32_C(0x0c000000)
663	/** State: Compiling. */
664	#define IEMTB_F_STATE_COMPILING UINT32_C(0x04000000)
665	/** State: Ready. */
666	#define IEMTB_F_STATE_READY UINT32_C(0x08000000)
667	/** State: Obsolete, can be deleted when we're sure it's not used any longer. */
668	#define IEMTB_F_STATE_OBSOLETE UINT32_C(0x0c000000)
669
670	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
671	* @note We don't */
672	#define IEMTB_F_KEY_MASK ((UINT32_C(0xffffffff) & ~IEM_F_X86_CTX_MASK) \| IEM_F_X86_CTX_SMM)
673	/** @} */
674
675	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
676	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
677	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
678	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
679	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
680	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
681	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
682	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
683	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
684	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
685	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
686	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
687	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
688	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
689	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
690	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
691	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
692	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
693	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
694
695	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
696	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
697	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
698	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
699	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
700	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
701	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
702	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
703	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
704	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
705	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
706	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
707
708	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
709	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
710	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
711
712
713	/**
714	* The per-CPU IEM state.
715	*/
716	typedef struct IEMCPU
717	{
718	/** Info status code that needs to be propagated to the IEM caller.
719	* This cannot be passed internally, as it would complicate all success
720	* checks within the interpreter making the code larger and almost impossible
721	* to get right. Instead, we'll store status codes to pass on here. Each
722	* source of these codes will perform appropriate sanity checks. */
723	int32_t rcPassUp; /* 0x00 */
724	/** Execution flag, IEM_F_XXX. */
725	uint32_t fExec; /* 0x04 */
726
727	/** @name Decoder state.
728	* @{ */
729	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
730	# ifdef IEM_WITH_CODE_TLB
731	/** The offset of the next instruction byte. */
732	uint32_t offInstrNextByte; /* 0x08 */
733	/** The number of bytes available at pbInstrBuf for the current instruction.
734	* This takes the max opcode length into account so that doesn't need to be
735	* checked separately. */
736	uint32_t cbInstrBuf; /* 0x0c */
737	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
738	* This can be NULL if the page isn't mappable for some reason, in which
739	* case we'll do fallback stuff.
740	*
741	* If we're executing an instruction from a user specified buffer,
742	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
743	* aligned pointer but pointer to the user data.
744	*
745	* For instructions crossing pages, this will start on the first page and be
746	* advanced to the next page by the time we've decoded the instruction. This
747	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
748	*/
749	uint8_t const pbInstrBuf; / 0x10 */
750	# if ARCH_BITS == 32
751	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
752	# endif
753	/** The program counter corresponding to pbInstrBuf.
754	* This is set to a non-canonical address when we need to invalidate it. */
755	uint64_t uInstrBufPc; /* 0x18 */
756	/** The guest physical address corresponding to pbInstrBuf. */
757	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
758	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
759	* This takes the CS segment limit into account. */
760	uint16_t cbInstrBufTotal; /* 0x28 */
761	/** Offset into pbInstrBuf of the first byte of the current instruction.
762	* Can be negative to efficiently handle cross page instructions. */
763	int16_t offCurInstrStart; /* 0x2a */
764
765	/** The prefix mask (IEM_OP_PRF_XXX). */
766	uint32_t fPrefixes; /* 0x2c */
767	/** The extra REX ModR/M register field bit (REX.R << 3). */
768	uint8_t uRexReg; /* 0x30 */
769	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
770	* (REX.B << 3). */
771	uint8_t uRexB; /* 0x31 */
772	/** The extra REX SIB index field bit (REX.X << 3). */
773	uint8_t uRexIndex; /* 0x32 */
774
775	/** The effective segment register (X86_SREG_XXX). */
776	uint8_t iEffSeg; /* 0x33 */
777
778	/** The offset of the ModR/M byte relative to the start of the instruction. */
779	uint8_t offModRm; /* 0x34 */
780	# else /* !IEM_WITH_CODE_TLB */
781	/** The size of what has currently been fetched into abOpcode. */
782	uint8_t cbOpcode; /* 0x08 */
783	/** The current offset into abOpcode. */
784	uint8_t offOpcode; /* 0x09 */
785	/** The offset of the ModR/M byte relative to the start of the instruction. */
786	uint8_t offModRm; /* 0x0a */
787
788	/** The effective segment register (X86_SREG_XXX). */
789	uint8_t iEffSeg; /* 0x0b */
790
791	/** The prefix mask (IEM_OP_PRF_XXX). */
792	uint32_t fPrefixes; /* 0x0c */
793	/** The extra REX ModR/M register field bit (REX.R << 3). */
794	uint8_t uRexReg; /* 0x10 */
795	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
796	* (REX.B << 3). */
797	uint8_t uRexB; /* 0x11 */
798	/** The extra REX SIB index field bit (REX.X << 3). */
799	uint8_t uRexIndex; /* 0x12 */
800
801	# endif /* !IEM_WITH_CODE_TLB */
802
803	/** The effective operand mode. */
804	IEMMODE enmEffOpSize; /* 0x35, 0x13 */
805	/** The default addressing mode. */
806	IEMMODE enmDefAddrMode; /* 0x36, 0x14 */
807	/** The effective addressing mode. */
808	IEMMODE enmEffAddrMode; /* 0x37, 0x15 */
809	/** The default operand mode. */
810	IEMMODE enmDefOpSize; /* 0x38, 0x16 */
811
812	/** Prefix index (VEX.pp) for two byte and three byte tables. */
813	uint8_t idxPrefix; /* 0x39, 0x17 */
814	/** 3rd VEX/EVEX/XOP register.
815	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
816	uint8_t uVex3rdReg; /* 0x3a, 0x18 */
817	/** The VEX/EVEX/XOP length field. */
818	uint8_t uVexLength; /* 0x3b, 0x19 */
819	/** Additional EVEX stuff. */
820	uint8_t fEvexStuff; /* 0x3c, 0x1a */
821
822	/** Explicit alignment padding. */
823	uint8_t abAlignment2a[1]; /* 0x3d, 0x1b */
824	/** The FPU opcode (FOP). */
825	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
826	# ifndef IEM_WITH_CODE_TLB
827	/** Explicit alignment padding. */
828	uint8_t abAlignment2b[2]; /* 0x1e */
829	# endif
830
831	/** The opcode bytes. */
832	uint8_t abOpcode[15]; /* 0x40, 0x20 */
833	/** Explicit alignment padding. */
834	# ifdef IEM_WITH_CODE_TLB
835	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
836	# else
837	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
838	# endif
839	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
840	uint8_t abOpaqueDecoder[0x4f - 0x8];
841	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
842	/** @} */
843
844
845	/** The number of active guest memory mappings. */
846	uint8_t cActiveMappings; /* 0x4f, 0x4f */
847
848	/** Records for tracking guest memory mappings. */
849	struct
850	{
851	/** The address of the mapped bytes. */
852	R3R0PTRTYPE(void *) pv;
853	/** The access flags (IEM_ACCESS_XXX).
854	* IEM_ACCESS_INVALID if the entry is unused. */
855	uint32_t fAccess;
856	#if HC_ARCH_BITS == 64
857	uint32_t u32Alignment4; /*< Alignment padding. /
858	#endif
859	} aMemMappings[3]; /* 0x50 LB 0x30 */
860
861	/** Locking records for the mapped memory. */
862	union
863	{
864	PGMPAGEMAPLOCK Lock;
865	uint64_t au64Padding[2];
866	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
867
868	/** Bounce buffer info.
869	* This runs in parallel to aMemMappings. */
870	struct
871	{
872	/** The physical address of the first byte. */
873	RTGCPHYS GCPhysFirst;
874	/** The physical address of the second page. */
875	RTGCPHYS GCPhysSecond;
876	/** The number of bytes in the first page. */
877	uint16_t cbFirst;
878	/** The number of bytes in the second page. */
879	uint16_t cbSecond;
880	/** Whether it's unassigned memory. */
881	bool fUnassigned;
882	/** Explicit alignment padding. */
883	bool afAlignment5[3];
884	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
885
886	/** The flags of the current exception / interrupt. */
887	uint32_t fCurXcpt; /* 0xf8 */
888	/** The current exception / interrupt. */
889	uint8_t uCurXcpt; /* 0xfc */
890	/** Exception / interrupt recursion depth. */
891	int8_t cXcptRecursions; /* 0xfb */
892
893	/** The next unused mapping index.
894	* @todo try find room for this up with cActiveMappings. */
895	uint8_t iNextMapping; /* 0xfd */
896	uint8_t abAlignment7[1];
897
898	/** Bounce buffer storage.
899	* This runs in parallel to aMemMappings and aMemBbMappings. */
900	struct
901	{
902	uint8_t ab[512];
903	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
904
905
906	/** Pointer set jump buffer - ring-3 context. */
907	R3PTRTYPE(jmp_buf *) pJmpBufR3;
908	/** Pointer set jump buffer - ring-0 context. */
909	R0PTRTYPE(jmp_buf *) pJmpBufR0;
910
911	/** @todo Should move this near @a fCurXcpt later. */
912	/** The CR2 for the current exception / interrupt. */
913	uint64_t uCurXcptCr2;
914	/** The error code for the current exception / interrupt. */
915	uint32_t uCurXcptErr;
916
917	/** @name Statistics
918	* @{ */
919	/** The number of instructions we've executed. */
920	uint32_t cInstructions;
921	/** The number of potential exits. */
922	uint32_t cPotentialExits;
923	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
924	* This may contain uncommitted writes. */
925	uint32_t cbWritten;
926	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
927	uint32_t cRetInstrNotImplemented;
928	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
929	uint32_t cRetAspectNotImplemented;
930	/** Counts informational statuses returned (other than VINF_SUCCESS). */
931	uint32_t cRetInfStatuses;
932	/** Counts other error statuses returned. */
933	uint32_t cRetErrStatuses;
934	/** Number of times rcPassUp has been used. */
935	uint32_t cRetPassUpStatus;
936	/** Number of times RZ left with instruction commit pending for ring-3. */
937	uint32_t cPendingCommit;
938	/** Number of long jumps. */
939	uint32_t cLongJumps;
940	/** @} */
941
942	/** @name Target CPU information.
943	* @{ */
944	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
945	/** The target CPU. */
946	uint8_t uTargetCpu;
947	#else
948	uint8_t bTargetCpuPadding;
949	#endif
950	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
951	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
952	* native host support and the 2nd for when there is.
953	*
954	* The two values are typically indexed by a g_CpumHostFeatures bit.
955	*
956	* This is for instance used for the BSF & BSR instructions where AMD and
957	* Intel CPUs produce different EFLAGS. */
958	uint8_t aidxTargetCpuEflFlavour[2];
959
960	/** The CPU vendor. */
961	CPUMCPUVENDOR enmCpuVendor;
962	/** @} */
963
964	/** @name Host CPU information.
965	* @{ */
966	/** The CPU vendor. */
967	CPUMCPUVENDOR enmHostCpuVendor;
968	/** @} */
969
970	/** Counts RDMSR \#GP(0) LogRel(). */
971	uint8_t cLogRelRdMsr;
972	/** Counts WRMSR \#GP(0) LogRel(). */
973	uint8_t cLogRelWrMsr;
974	/** Alignment padding. */
975	uint8_t abAlignment9[46];
976
977	/** @name Recompilation
978	* @{ */
979	/** Pointer to the current translation block.
980	* This can either be one being executed or one being compiled. */
981	R3PTRTYPE(PIEMTB) pCurTbR3;
982	/** Spaced reserved for recompiler data / alignment. */
983	uint64_t auRecompilerStuff[7];
984	/** @} */
985
986	/** Data TLB.
987	* @remarks Must be 64-byte aligned. */
988	IEMTLB DataTlb;
989	/** Instruction TLB.
990	* @remarks Must be 64-byte aligned. */
991	IEMTLB CodeTlb;
992
993	/** Exception statistics. */
994	STAMCOUNTER aStatXcpts[32];
995	/** Interrupt statistics. */
996	uint32_t aStatInts[256];
997
998	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
999	/** Instruction statistics for ring-0/raw-mode. */
1000	IEMINSTRSTATS StatsRZ;
1001	/** Instruction statistics for ring-3. */
1002	IEMINSTRSTATS StatsR3;
1003	#endif
1004	} IEMCPU;
1005	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1006	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1007	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1008	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1009	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1010	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1011
1012	/** Pointer to the per-CPU IEM state. */
1013	typedef IEMCPU *PIEMCPU;
1014	/** Pointer to the const per-CPU IEM state. */
1015	typedef IEMCPU const *PCIEMCPU;
1016
1017
1018	/** @def IEM_GET_CTX
1019	* Gets the guest CPU context for the calling EMT.
1020	* @returns PCPUMCTX
1021	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1022	*/
1023	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1024
1025	/** @def IEM_CTX_ASSERT
1026	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1027	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1028	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1029	*/
1030	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1031	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
1032	(a_fExtrnMbz)))
1033
1034	/** @def IEM_CTX_IMPORT_RET
1035	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1036	*
1037	* Will call the keep to import the bits as needed.
1038	*
1039	* Returns on import failure.
1040	*
1041	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1042	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1043	*/
1044	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1045	do { \
1046	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1047	{ /* likely */ } \
1048	else \
1049	{ \
1050	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1051	AssertRCReturn(rcCtxImport, rcCtxImport); \
1052	} \
1053	} while (0)
1054
1055	/** @def IEM_CTX_IMPORT_NORET
1056	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1057	*
1058	* Will call the keep to import the bits as needed.
1059	*
1060	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1061	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1062	*/
1063	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1064	do { \
1065	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1066	{ /* likely */ } \
1067	else \
1068	{ \
1069	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1070	AssertLogRelRC(rcCtxImport); \
1071	} \
1072	} while (0)
1073
1074	/** @def IEM_CTX_IMPORT_JMP
1075	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1076	*
1077	* Will call the keep to import the bits as needed.
1078	*
1079	* Jumps on import failure.
1080	*
1081	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1082	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1083	*/
1084	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1085	do { \
1086	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1087	{ /* likely */ } \
1088	else \
1089	{ \
1090	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1091	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1092	} \
1093	} while (0)
1094
1095
1096
1097	/** @def IEM_GET_TARGET_CPU
1098	* Gets the current IEMTARGETCPU value.
1099	* @returns IEMTARGETCPU value.
1100	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1101	*/
1102	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1103	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1104	#else
1105	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1106	#endif
1107
1108	/** @def IEM_GET_INSTR_LEN
1109	* Gets the instruction length. */
1110	#ifdef IEM_WITH_CODE_TLB
1111	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1112	#else
1113	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1114	#endif
1115
1116	/** @def IEM_TRY_SETJMP
1117	* Wrapper around setjmp / try, hiding all the ugly differences.
1118	*
1119	* @note Use with extreme care as this is a fragile macro.
1120	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1121	* @param a_rcTarget The variable that should receive the status code in case
1122	* of a longjmp/throw.
1123	*/
1124	/** @def IEM_TRY_SETJMP_AGAIN
1125	* For when setjmp / try is used again in the same variable scope as a previous
1126	* IEM_TRY_SETJMP invocation.
1127	*/
1128	/** @def IEM_CATCH_LONGJMP_BEGIN
1129	* Start wrapper for catch / setjmp-else.
1130	*
1131	* This will set up a scope.
1132	*
1133	* @note Use with extreme care as this is a fragile macro.
1134	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1135	* @param a_rcTarget The variable that should receive the status code in case
1136	* of a longjmp/throw.
1137	*/
1138	/** @def IEM_CATCH_LONGJMP_END
1139	* End wrapper for catch / setjmp-else.
1140	*
1141	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1142	* state.
1143	*
1144	* @note Use with extreme care as this is a fragile macro.
1145	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1146	*/
1147	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1148	# ifdef IEM_WITH_THROW_CATCH
1149	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1150	a_rcTarget = VINF_SUCCESS; \
1151	try
1152	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1153	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1154	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1155	catch (int rcThrown) \
1156	{ \
1157	a_rcTarget = rcThrown
1158	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1159	} \
1160	((void)0)
1161	# else /* !IEM_WITH_THROW_CATCH */
1162	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1163	jmp_buf JmpBuf; \
1164	jmp_buf * volatile pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1165	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1166	if ((rcStrict = setjmp(JmpBuf)) == 0)
1167	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1168	pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1169	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1170	if ((rcStrict = setjmp(JmpBuf)) == 0)
1171	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1172	else \
1173	{ \
1174	((void)0)
1175	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1176	} \
1177	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1178	# endif /* !IEM_WITH_THROW_CATCH */
1179	#endif /* IEM_WITH_SETJMP */
1180
1181
1182	/**
1183	* Shared per-VM IEM data.
1184	*/
1185	typedef struct IEM
1186	{
1187	/** The VMX APIC-access page handler type. */
1188	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1189	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1190	/** Set if the CPUID host call functionality is enabled. */
1191	bool fCpuIdHostCall;
1192	#endif
1193	} IEM;
1194
1195
1196
1197	/** @name IEM_ACCESS_XXX - Access details.
1198	* @{ */
1199	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1200	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1201	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1202	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1203	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1204	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1205	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1206	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1207	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1208	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1209	/** The writes are partial, so if initialize the bounce buffer with the
1210	* orignal RAM content. */
1211	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1212	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1213	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1214	/** Bounce buffer with ring-3 write pending, first page. */
1215	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1216	/** Bounce buffer with ring-3 write pending, second page. */
1217	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1218	/** Not locked, accessed via the TLB. */
1219	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1220	/** Valid bit mask. */
1221	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1222	/** Shift count for the TLB flags (upper word). */
1223	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1224
1225	/** Read+write data alias. */
1226	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1227	/** Write data alias. */
1228	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1229	/** Read data alias. */
1230	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1231	/** Instruction fetch alias. */
1232	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1233	/** Stack write alias. */
1234	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1235	/** Stack read alias. */
1236	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1237	/** Stack read+write alias. */
1238	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1239	/** Read system table alias. */
1240	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1241	/** Read+write system table alias. */
1242	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1243	/** @} */
1244
1245	/** @name Prefix constants (IEMCPU::fPrefixes)
1246	* @{ */
1247	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1248	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1249	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1250	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1251	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1252	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1253	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1254
1255	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1256	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1257	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1258
1259	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1260	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1261	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1262
1263	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1264	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1265	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1266	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1267	/** Mask with all the REX prefix flags.
1268	* This is generally for use when needing to undo the REX prefixes when they
1269	* are followed legacy prefixes and therefore does not immediately preceed
1270	* the first opcode byte.
1271	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1272	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1273
1274	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1275	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1276	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1277	/** @} */
1278
1279	/** @name IEMOPFORM_XXX - Opcode forms
1280	* @note These are ORed together with IEMOPHINT_XXX.
1281	* @{ */
1282	/** ModR/M: reg, r/m */
1283	#define IEMOPFORM_RM 0
1284	/** ModR/M: reg, r/m (register) */
1285	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1286	/** ModR/M: reg, r/m (memory) */
1287	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1288	/** ModR/M: reg, r/m */
1289	#define IEMOPFORM_RMI 1
1290	/** ModR/M: reg, r/m (register) */
1291	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1292	/** ModR/M: reg, r/m (memory) */
1293	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1294	/** ModR/M: r/m, reg */
1295	#define IEMOPFORM_MR 2
1296	/** ModR/M: r/m (register), reg */
1297	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1298	/** ModR/M: r/m (memory), reg */
1299	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1300	/** ModR/M: r/m, reg */
1301	#define IEMOPFORM_MRI 3
1302	/** ModR/M: r/m (register), reg */
1303	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1304	/** ModR/M: r/m (memory), reg */
1305	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1306	/** ModR/M: r/m only */
1307	#define IEMOPFORM_M 4
1308	/** ModR/M: r/m only (register). */
1309	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1310	/** ModR/M: r/m only (memory). */
1311	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1312	/** ModR/M: reg only */
1313	#define IEMOPFORM_R 5
1314
1315	/** VEX+ModR/M: reg, r/m */
1316	#define IEMOPFORM_VEX_RM 8
1317	/** VEX+ModR/M: reg, r/m (register) */
1318	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1319	/** VEX+ModR/M: reg, r/m (memory) */
1320	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1321	/** VEX+ModR/M: r/m, reg */
1322	#define IEMOPFORM_VEX_MR 9
1323	/** VEX+ModR/M: r/m (register), reg */
1324	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1325	/** VEX+ModR/M: r/m (memory), reg */
1326	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1327	/** VEX+ModR/M: r/m only */
1328	#define IEMOPFORM_VEX_M 10
1329	/** VEX+ModR/M: r/m only (register). */
1330	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1331	/** VEX+ModR/M: r/m only (memory). */
1332	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1333	/** VEX+ModR/M: reg only */
1334	#define IEMOPFORM_VEX_R 11
1335	/** VEX+ModR/M: reg, vvvv, r/m */
1336	#define IEMOPFORM_VEX_RVM 12
1337	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1338	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1339	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1340	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1341	/** VEX+ModR/M: reg, r/m, vvvv */
1342	#define IEMOPFORM_VEX_RMV 13
1343	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1344	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1345	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1346	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1347	/** VEX+ModR/M: reg, r/m, imm8 */
1348	#define IEMOPFORM_VEX_RMI 14
1349	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1350	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1351	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1352	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1353	/** VEX+ModR/M: r/m, vvvv, reg */
1354	#define IEMOPFORM_VEX_MVR 15
1355	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1356	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1357	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1358	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1359	/** VEX+ModR/M+/n: vvvv, r/m */
1360	#define IEMOPFORM_VEX_VM 16
1361	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1362	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1363	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1364	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1365
1366	/** Fixed register instruction, no R/M. */
1367	#define IEMOPFORM_FIXED 32
1368
1369	/** The r/m is a register. */
1370	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1371	/** The r/m is a memory access. */
1372	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1373	/** @} */
1374
1375	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1376	* @note These are ORed together with IEMOPFORM_XXX.
1377	* @{ */
1378	/** Ignores the operand size prefix (66h). */
1379	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1380	/** Ignores REX.W (aka WIG). */
1381	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1382	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1383	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1384	/** Allowed with the lock prefix. */
1385	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1386	/** The VEX.L value is ignored (aka LIG). */
1387	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1388	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1389	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1390	/** The VEX.V value must be zero. */
1391	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1392
1393	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1394	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1395	/** @} */
1396
1397	/**
1398	* Possible hardware task switch sources.
1399	*/
1400	typedef enum IEMTASKSWITCH
1401	{
1402	/** Task switch caused by an interrupt/exception. */
1403	IEMTASKSWITCH_INT_XCPT = 1,
1404	/** Task switch caused by a far CALL. */
1405	IEMTASKSWITCH_CALL,
1406	/** Task switch caused by a far JMP. */
1407	IEMTASKSWITCH_JUMP,
1408	/** Task switch caused by an IRET. */
1409	IEMTASKSWITCH_IRET
1410	} IEMTASKSWITCH;
1411	AssertCompileSize(IEMTASKSWITCH, 4);
1412
1413	/**
1414	* Possible CrX load (write) sources.
1415	*/
1416	typedef enum IEMACCESSCRX
1417	{
1418	/** CrX access caused by 'mov crX' instruction. */
1419	IEMACCESSCRX_MOV_CRX,
1420	/** CrX (CR0) write caused by 'lmsw' instruction. */
1421	IEMACCESSCRX_LMSW,
1422	/** CrX (CR0) write caused by 'clts' instruction. */
1423	IEMACCESSCRX_CLTS,
1424	/** CrX (CR0) read caused by 'smsw' instruction. */
1425	IEMACCESSCRX_SMSW
1426	} IEMACCESSCRX;
1427
1428	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1429	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1430	*
1431	* These flags provide further context to SLAT page-walk failures that could not be
1432	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1433	*
1434	* @{
1435	*/
1436	/** Translating a nested-guest linear address failed accessing a nested-guest
1437	* physical address. */
1438	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1439	/** Translating a nested-guest linear address failed accessing a
1440	* paging-structure entry or updating accessed/dirty bits. */
1441	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1442	/** @} */
1443
1444	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1445	# ifndef IN_RING3
1446	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1447	# endif
1448	#endif
1449
1450	/**
1451	* Indicates to the verifier that the given flag set is undefined.
1452	*
1453	* Can be invoked again to add more flags.
1454	*
1455	* This is a NOOP if the verifier isn't compiled in.
1456	*
1457	* @note We're temporarily keeping this until code is converted to new
1458	* disassembler style opcode handling.
1459	*/
1460	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1461
1462
1463	/** @def IEM_DECL_IMPL_TYPE
1464	* For typedef'ing an instruction implementation function.
1465	*
1466	* @param a_RetType The return type.
1467	* @param a_Name The name of the type.
1468	* @param a_ArgList The argument list enclosed in parentheses.
1469	*/
1470
1471	/** @def IEM_DECL_IMPL_DEF
1472	* For defining an instruction implementation function.
1473	*
1474	* @param a_RetType The return type.
1475	* @param a_Name The name of the type.
1476	* @param a_ArgList The argument list enclosed in parentheses.
1477	*/
1478
1479	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1480	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1481	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1482	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1483	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1484	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1485	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1486
1487	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1488	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1489	a_RetType (__fastcall a_Name) a_ArgList
1490	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1491	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1492	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1493	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1494
1495	#elif __cplusplus >= 201700 /* P0012R1 support */
1496	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1497	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1498	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1499	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1500	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1501	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1502
1503	#else
1504	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1505	a_RetType (VBOXCALL a_Name) a_ArgList
1506	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1507	a_RetType VBOXCALL a_Name a_ArgList
1508	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1509	a_RetType VBOXCALL a_Name a_ArgList
1510
1511	#endif
1512
1513	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1514	RT_C_DECLS_BEGIN
1515	extern uint8_t const g_afParity[256];
1516	RT_C_DECLS_END
1517
1518
1519	/** @name Arithmetic assignment operations on bytes (binary).
1520	* @{ */
1521	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1522	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1523	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1524	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1525	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1526	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1527	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1528	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1529	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1530	/** @} */
1531
1532	/** @name Arithmetic assignment operations on words (binary).
1533	* @{ */
1534	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1535	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1536	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1537	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1538	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1539	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1540	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1541	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1542	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1543	/** @} */
1544
1545	/** @name Arithmetic assignment operations on double words (binary).
1546	* @{ */
1547	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1548	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1549	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1550	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1551	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1552	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1553	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1554	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1555	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1556	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1557	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1558	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1559	/** @} */
1560
1561	/** @name Arithmetic assignment operations on quad words (binary).
1562	* @{ */
1563	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1564	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1565	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1566	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1567	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1568	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1569	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1570	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1571	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1572	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1573	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1574	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1575	/** @} */
1576
1577	/** @name Compare operations (thrown in with the binary ops).
1578	* @{ */
1579	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1580	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1581	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1582	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1583	/** @} */
1584
1585	/** @name Test operations (thrown in with the binary ops).
1586	* @{ */
1587	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1588	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1589	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1590	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1591	/** @} */
1592
1593	/** @name Bit operations operations (thrown in with the binary ops).
1594	* @{ */
1595	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1596	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1597	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1598	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1599	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1600	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1601	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1602	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1603	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1604	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1605	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1606	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1607	/** @} */
1608
1609	/** @name Arithmetic three operand operations on double words (binary).
1610	* @{ */
1611	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1612	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1613	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1614	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1615	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1616	/** @} */
1617
1618	/** @name Arithmetic three operand operations on quad words (binary).
1619	* @{ */
1620	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1621	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1622	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1623	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1624	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1625	/** @} */
1626
1627	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1628	* @{ */
1629	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1630	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1631	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1632	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1633	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1634	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1635	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1636	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1637	/** @} */
1638
1639	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1640	* @{ */
1641	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1642	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1643	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1644	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1645	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1646	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1647	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1648	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1649	/** @} */
1650
1651	/** @name MULX 32-bit and 64-bit.
1652	* @{ */
1653	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1654	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1655	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1656
1657	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1658	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1659	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1660	/** @} */
1661
1662
1663	/** @name Exchange memory with register operations.
1664	* @{ */
1665	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1666	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1667	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1668	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1669	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1670	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1671	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1672	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1673	/** @} */
1674
1675	/** @name Exchange and add operations.
1676	* @{ */
1677	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1678	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1679	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1680	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1681	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1682	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1683	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1684	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1685	/** @} */
1686
1687	/** @name Compare and exchange.
1688	* @{ */
1689	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1690	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1691	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1692	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1693	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1694	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1695	#if ARCH_BITS == 32
1696	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1697	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1698	#else
1699	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1700	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1701	#endif
1702	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1703	uint32_t *pEFlags));
1704	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1705	uint32_t *pEFlags));
1706	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1707	uint32_t *pEFlags));
1708	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1709	uint32_t *pEFlags));
1710	#ifndef RT_ARCH_ARM64
1711	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1712	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1713	#endif
1714	/** @} */
1715
1716	/** @name Memory ordering
1717	* @{ */
1718	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1719	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1720	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1721	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1722	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1723	#ifndef RT_ARCH_ARM64
1724	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1725	#endif
1726	/** @} */
1727
1728	/** @name Double precision shifts
1729	* @{ */
1730	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1731	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1732	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1733	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1734	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1735	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1736	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1737	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1738	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1739	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1740	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1741	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1742	/** @} */
1743
1744
1745	/** @name Bit search operations (thrown in with the binary ops).
1746	* @{ */
1747	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1748	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1749	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1750	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1751	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1752	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1753	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1754	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1755	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1756	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1757	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1758	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1759	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1760	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1761	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1762	/** @} */
1763
1764	/** @name Signed multiplication operations (thrown in with the binary ops).
1765	* @{ */
1766	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1767	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1768	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1769	/** @} */
1770
1771	/** @name Arithmetic assignment operations on bytes (unary).
1772	* @{ */
1773	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1774	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1775	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1776	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1777	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1778	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1779	/** @} */
1780
1781	/** @name Arithmetic assignment operations on words (unary).
1782	* @{ */
1783	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1784	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1785	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1786	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1787	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1788	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1789	/** @} */
1790
1791	/** @name Arithmetic assignment operations on double words (unary).
1792	* @{ */
1793	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1794	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1795	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1796	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1797	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1798	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1799	/** @} */
1800
1801	/** @name Arithmetic assignment operations on quad words (unary).
1802	* @{ */
1803	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1804	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1805	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1806	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1807	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1808	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1809	/** @} */
1810
1811
1812	/** @name Shift operations on bytes (Group 2).
1813	* @{ */
1814	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1815	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1816	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1817	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1818	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1819	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1820	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1821	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1822	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1823	/** @} */
1824
1825	/** @name Shift operations on words (Group 2).
1826	* @{ */
1827	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1828	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1829	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1830	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1831	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1832	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1833	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1834	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1835	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1836	/** @} */
1837
1838	/** @name Shift operations on double words (Group 2).
1839	* @{ */
1840	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1841	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1842	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1843	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1844	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1845	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1846	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1847	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1848	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1849	/** @} */
1850
1851	/** @name Shift operations on words (Group 2).
1852	* @{ */
1853	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1854	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1855	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1856	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1857	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1858	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1859	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1860	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1861	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1862	/** @} */
1863
1864	/** @name Multiplication and division operations.
1865	* @{ */
1866	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1867	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1868	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1869	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1870	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1871	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1872
1873	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1874	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1875	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1876	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1877	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1878	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1879
1880	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1881	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1882	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1883	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1884	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1885	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1886
1887	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1888	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1889	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1890	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1891	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1892	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1893	/** @} */
1894
1895	/** @name Byte Swap.
1896	* @{ */
1897	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1898	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1899	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1900	/** @} */
1901
1902	/** @name Misc.
1903	* @{ */
1904	FNIEMAIMPLBINU16 iemAImpl_arpl;
1905	/** @} */
1906
1907	/** @name RDRAND and RDSEED
1908	* @{ */
1909	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
1910	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
1911	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
1912	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
1913	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
1914	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
1915
1916	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
1917	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
1918	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
1919	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
1920	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
1921	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
1922	/** @} */
1923
1924	/** @name ADOX and ADCX
1925	* @{ */
1926	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
1927	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
1928	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
1929	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
1930
1931	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
1932	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
1933	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
1934	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
1935	/** @} */
1936
1937	/** @name FPU operations taking a 32-bit float argument
1938	* @{ */
1939	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1940	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1941	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1942
1943	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1944	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1945	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1946
1947	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1948	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1949	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1950	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1951	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1952	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1953	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1954
1955	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1956	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1957	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1958	/** @} */
1959
1960	/** @name FPU operations taking a 64-bit float argument
1961	* @{ */
1962	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1963	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1964	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1965
1966	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1967	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1968	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1969
1970	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1971	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1972	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1973	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1974	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1975	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1976	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1977
1978	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1979	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1980	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1981	/** @} */
1982
1983	/** @name FPU operations taking a 80-bit float argument
1984	* @{ */
1985	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1986	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1987	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1988	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1989	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1990	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1991	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1992	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1993	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1994	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1995	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1996	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1997
1998	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1999	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2000	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2001
2002	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2003	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2004	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2005	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2006	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2007
2008	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2009	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2010	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2011	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2012	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2013
2014	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2015	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2016	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2017	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2018	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2019	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2020	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2021	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2022	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2023
2024	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2025	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2026	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2027	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2028
2029	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2030	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2031	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2032	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2033	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2034	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2035	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2036	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2037	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2038
2039	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2040	PCRTFLOAT80U pr80Val));
2041	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2042	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2043	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2044	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2045
2046	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2047	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2048	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2049
2050	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2051	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2052	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2053
2054	/** @} */
2055
2056	/** @name FPU operations taking a 16-bit signed integer argument
2057	* @{ */
2058	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2059	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2060	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2061	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2062	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2063	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2064
2065	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2066	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2067	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2068	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2069	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2070	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2071
2072	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2073	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2074	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2075	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2076
2077	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2078	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2079	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2080	/** @} */
2081
2082	/** @name FPU operations taking a 32-bit signed integer argument
2083	* @{ */
2084	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2085	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2086	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2087	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2088	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2089	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2090
2091	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2092	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2093	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2094	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2095	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2096	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2097
2098	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2099	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2100	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2101	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2102
2103	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2104	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2105	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2106	/** @} */
2107
2108	/** @name FPU operations taking a 64-bit signed integer argument
2109	* @{ */
2110	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2111	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2112	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2113
2114	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2115	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2116	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2117	/** @} */
2118
2119
2120	/** Temporary type representing a 256-bit vector register. */
2121	typedef struct { uint64_t au64[4]; } IEMVMM256;
2122	/** Temporary type pointing to a 256-bit vector register. */
2123	typedef IEMVMM256 *PIEMVMM256;
2124	/** Temporary type pointing to a const 256-bit vector register. */
2125	typedef IEMVMM256 *PCIEMVMM256;
2126
2127
2128	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2129	* @{ */
2130	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2131	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2132	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2133	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2134	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2135	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2136	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2137	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2138	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2139	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2140	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2141	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2142	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2143	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2144	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2145	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2146	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2147	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2148	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2149	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2150	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2151	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2152	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2153	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2154	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2155	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2156	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2157	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2158	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2159	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2160	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2161	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2162	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2163	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2164	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2165	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2166	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2167	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2168	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2169	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2170	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2171	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2172	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2173	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2174	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2175	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2176	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2177	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2178	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2179	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2180	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2181	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2182	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2183	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2184	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2185	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2186	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2187
2188	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2189	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2190	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2191	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2192	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2193	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2194	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2195	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2196	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2197	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2198	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2199	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2200	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2201	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2202	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2203	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2204	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2205	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2206	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2207	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2208	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2209	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2210	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2211	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2212	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2213	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2214	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2215	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2216	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2217	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2218	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2219	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2220	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2221	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2222	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2223	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2224	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2225	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2226	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2227	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2228	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2229	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2230	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2231	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2232	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2233	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2234	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2235	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2236	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2237	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2238	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2239	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2240	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2241	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2242	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2243	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2244	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2245
2246	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2247	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2248	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2249	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2250	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2251	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2252	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2253	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2254	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2255	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2256	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2257	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2258	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2259	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2260	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2261	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2262	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2263	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2264	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2265	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2266	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2267	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2268	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2269	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2270	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2271	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2272	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2273	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2274	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2275	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2276	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2277	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2278	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2279	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2280	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2281	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2282	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2283	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2284	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2285	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2286	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2287	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2288	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2289	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2290	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2291	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2292	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2293	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2294	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2295	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2296	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2297	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2298	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2299	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2300	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2301	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2302	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2303
2304	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2305	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2306	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2307	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2308
2309	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2310	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2311	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2312	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2313	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2314	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2315	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2316	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2317	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2318	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2319	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2320	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2321	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2322	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2323	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2324	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2325	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2326	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2327	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2328	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2329	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2330	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2331	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2332	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2333	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2334	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2335	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2336	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2337	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2338	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2339	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2340	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2341	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2342	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2343	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2344	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2345	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2346	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2347	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2348	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2349	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2350	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2351	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2352	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2353	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2354	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2355	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2356	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2357	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2358	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2359	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2360	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2361	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2362	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2363	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2364	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2365	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2366
2367	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2368	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2369	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2370	/** @} */
2371
2372	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2373	* @{ */
2374	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2375	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2376	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2377	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2378	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2379	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2380	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2381	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2382	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2383	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2384
2385	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2386	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2387	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2388	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2389	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2390	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2391	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2392	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2393	/** @} */
2394
2395	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2396	* @{ */
2397	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2398	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2399	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2400	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2401	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2402	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2403	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2404	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2405	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2406	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2407	/** @} */
2408
2409	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2410	* @{ */
2411	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2412	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2413	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2414	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2415	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2416	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2417	#ifndef IEM_WITHOUT_ASSEMBLY
2418	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2419	#endif
2420	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2421	/** @} */
2422
2423	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2424	* @{ */
2425	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2426	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2427	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2428	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2429	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2430	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2431	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2432	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2433	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2434	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2435	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2436	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2437	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2438	/** @} */
2439
2440	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2441	* @{ */
2442	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2443	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2444	#ifndef IEM_WITHOUT_ASSEMBLY
2445	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2446	#endif
2447	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2448	/** @} */
2449
2450	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2451	* @{ */
2452	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2453	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2454	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2455	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2456	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2457	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2458
2459	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2460	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2461	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2462	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2463	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2464	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2465
2466	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2467	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2468	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2469	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2470	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2471	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2472
2473	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2474	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2475	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2476	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2477	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2478	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2479	/** @} */
2480
2481
2482	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2483	* @{ */
2484	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2485	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2486	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2487	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2488	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2489	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2490
2491	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2492	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2493	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2494	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2495	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2496
2497	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2498	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2499	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2500	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2501	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2502
2503	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2504	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2505	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2506	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2507	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2508
2509	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2510	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2511	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2512	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2513	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2514
2515	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2516	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2517	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2518	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2519	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2520
2521	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2522	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2523	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2524	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2525	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2526
2527	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2528	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2529	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2530	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2531	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2532
2533	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2534	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2535	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2536	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2537	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2538
2539	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2540	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2541	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2542	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2543	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2544
2545	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2546	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2547	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2548	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2549	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2550
2551	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2552	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2553	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2554	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2555	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2556
2557	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2558	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2559	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2560	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2561	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2562
2563	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2564	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2565	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2566	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2567	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2568
2569	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2570	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2571	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2572	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2573	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2574
2575	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2576	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2577
2578	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2579	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2580	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2581	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2582
2583	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2584	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2585	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2586	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2587
2588	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2589	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2590	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2591	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2592	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2593
2594	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2595	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2596	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2597	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2598	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2599
2600
2601	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2602	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2603	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2604	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2605	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2606	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2607
2608	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2609	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2610	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2611	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2612
2613	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2614	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2615	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2616	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2617
2618	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2619	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2620	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2621	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2622
2623	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2624	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2625	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2626	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2627	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2628
2629	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2630	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2631	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2632	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2633	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2634
2635	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2636
2637	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2638
2639	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
2640	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
2641	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
2642	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
2643	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
2644	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
2645	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2646	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2647
2648	typedef struct IEMPCMPISTRXSRC
2649	{
2650	RTUINT128U uSrc1;
2651	RTUINT128U uSrc2;
2652	} IEMPCMPISTRXSRC;
2653	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
2654	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
2655
2656	typedef struct IEMPCMPESTRXSRC
2657	{
2658	RTUINT128U uSrc1;
2659	RTUINT128U uSrc2;
2660	uint64_t u64Rax;
2661	uint64_t u64Rdx;
2662	} IEMPCMPESTRXSRC;
2663	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
2664	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
2665
2666	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2667	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
2668	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2669	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
2670
2671	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2672	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
2673	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2674	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
2675
2676	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
2677	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
2678	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
2679	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
2680
2681	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2682	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2683
2684	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
2685	/** @} */
2686
2687	/** @name Media Odds and Ends
2688	* @{ */
2689	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2690	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2691	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2692	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2693	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2694	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2695	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2696	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2697
2698	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2699	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2700	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2701	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2702
2703	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2704	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2705	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2706	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2707	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2708	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2709	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2710	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2711
2712	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2713	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2714
2715	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2716	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2717
2718	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2719	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2720
2721	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2722	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2723
2724	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2725	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2726	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2727	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2728
2729	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2730	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2731
2732	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2733	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2734	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2735	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2736
2737	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2738	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2739
2740
2741	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2742	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2743
2744	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2745	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2746
2747	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2748	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2749
2750	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2751	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2752
2753	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2754	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2755
2756
2757	typedef struct IEMMEDIAF2XMMSRC
2758	{
2759	X86XMMREG uSrc1;
2760	X86XMMREG uSrc2;
2761	} IEMMEDIAF2XMMSRC;
2762	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2763	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2764
2765	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2766	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2767
2768	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2769	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2770	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2771	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2772	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
2773	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
2774
2775	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
2776	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
2777
2778	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
2779	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
2780
2781	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
2782	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2783
2784	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2785	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2786
2787	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2788	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2789
2790	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2791	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2792
2793	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
2794	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2795
2796	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2797	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2798
2799	/** @} */
2800
2801
2802	/** @name Function tables.
2803	* @{
2804	*/
2805
2806	/**
2807	* Function table for a binary operator providing implementation based on
2808	* operand size.
2809	*/
2810	typedef struct IEMOPBINSIZES
2811	{
2812	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2813	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2814	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2815	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2816	} IEMOPBINSIZES;
2817	/** Pointer to a binary operator function table. */
2818	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2819
2820
2821	/**
2822	* Function table for a unary operator providing implementation based on
2823	* operand size.
2824	*/
2825	typedef struct IEMOPUNARYSIZES
2826	{
2827	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2828	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2829	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2830	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2831	} IEMOPUNARYSIZES;
2832	/** Pointer to a unary operator function table. */
2833	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2834
2835
2836	/**
2837	* Function table for a shift operator providing implementation based on
2838	* operand size.
2839	*/
2840	typedef struct IEMOPSHIFTSIZES
2841	{
2842	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2843	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2844	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2845	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2846	} IEMOPSHIFTSIZES;
2847	/** Pointer to a shift operator function table. */
2848	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2849
2850
2851	/**
2852	* Function table for a multiplication or division operation.
2853	*/
2854	typedef struct IEMOPMULDIVSIZES
2855	{
2856	PFNIEMAIMPLMULDIVU8 pfnU8;
2857	PFNIEMAIMPLMULDIVU16 pfnU16;
2858	PFNIEMAIMPLMULDIVU32 pfnU32;
2859	PFNIEMAIMPLMULDIVU64 pfnU64;
2860	} IEMOPMULDIVSIZES;
2861	/** Pointer to a multiplication or division operation function table. */
2862	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2863
2864
2865	/**
2866	* Function table for a double precision shift operator providing implementation
2867	* based on operand size.
2868	*/
2869	typedef struct IEMOPSHIFTDBLSIZES
2870	{
2871	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2872	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2873	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2874	} IEMOPSHIFTDBLSIZES;
2875	/** Pointer to a double precision shift function table. */
2876	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2877
2878
2879	/**
2880	* Function table for media instruction taking two full sized media source
2881	* registers and one full sized destination register (AVX).
2882	*/
2883	typedef struct IEMOPMEDIAF3
2884	{
2885	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2886	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2887	} IEMOPMEDIAF3;
2888	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2889	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2890
2891	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2892	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2893	* given functions as initializers. For use in AVX functions where a pair of
2894	* functions are only used once and the function table need not be public. */
2895	#ifndef TST_IEM_CHECK_MC
2896	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2897	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2898	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2899	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2900	# else
2901	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2902	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2903	# endif
2904	#else
2905	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2906	#endif
2907	/** @def IEMOPMEDIAF3_INIT_VARS
2908	* Generate AVX function tables for the @a a_InstrNm instruction.
2909	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2910	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2911	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2912	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2913
2914	/**
2915	* Function table for media instruction taking two full sized media source
2916	* registers and one full sized destination register, but no additional state
2917	* (AVX).
2918	*/
2919	typedef struct IEMOPMEDIAOPTF3
2920	{
2921	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2922	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2923	} IEMOPMEDIAOPTF3;
2924	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2925	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2926
2927	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2928	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2929	* given functions as initializers. For use in AVX functions where a pair of
2930	* functions are only used once and the function table need not be public. */
2931	#ifndef TST_IEM_CHECK_MC
2932	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2933	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2934	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2935	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2936	# else
2937	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2938	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2939	# endif
2940	#else
2941	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2942	#endif
2943	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2944	* Generate AVX function tables for the @a a_InstrNm instruction.
2945	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2946	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2947	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2948	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2949
2950	/**
2951	* Function table for media instruction taking one full sized media source
2952	* registers and one full sized destination register, but no additional state
2953	* (AVX).
2954	*/
2955	typedef struct IEMOPMEDIAOPTF2
2956	{
2957	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2958	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2959	} IEMOPMEDIAOPTF2;
2960	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2961	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2962
2963	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2964	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2965	* given functions as initializers. For use in AVX functions where a pair of
2966	* functions are only used once and the function table need not be public. */
2967	#ifndef TST_IEM_CHECK_MC
2968	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2969	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2970	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2971	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2972	# else
2973	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2974	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2975	# endif
2976	#else
2977	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2978	#endif
2979	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2980	* Generate AVX function tables for the @a a_InstrNm instruction.
2981	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2982	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2983	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2984	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2985
2986	/**
2987	* Function table for media instruction taking two full sized media source
2988	* registers and one full sized destination register and an 8-bit immediate, but no additional state
2989	* (AVX).
2990	*/
2991	typedef struct IEMOPMEDIAOPTF3IMM8
2992	{
2993	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
2994	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
2995	} IEMOPMEDIAOPTF3IMM8;
2996	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2997	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
2998
2999	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3000	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3001	* given functions as initializers. For use in AVX functions where a pair of
3002	* functions are only used once and the function table need not be public. */
3003	#ifndef TST_IEM_CHECK_MC
3004	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3005	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3006	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3007	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3008	# else
3009	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3010	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3011	# endif
3012	#else
3013	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3014	#endif
3015	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3016	* Generate AVX function tables for the @a a_InstrNm instruction.
3017	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3018	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3019	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3020	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3021	/** @} */
3022
3023
3024	/**
3025	* Function table for blend type instruction taking three full sized media source
3026	* registers and one full sized destination register, but no additional state
3027	* (AVX).
3028	*/
3029	typedef struct IEMOPBLENDOP
3030	{
3031	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3032	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3033	} IEMOPBLENDOP;
3034	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3035	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3036
3037	/** @def IEMOPBLENDOP_INIT_VARS_EX
3038	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3039	* given functions as initializers. For use in AVX functions where a pair of
3040	* functions are only used once and the function table need not be public. */
3041	#ifndef TST_IEM_CHECK_MC
3042	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3043	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3044	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3045	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3046	# else
3047	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3048	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3049	# endif
3050	#else
3051	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3052	#endif
3053	/** @def IEMOPBLENDOP_INIT_VARS
3054	* Generate AVX function tables for the @a a_InstrNm instruction.
3055	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3056	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3057	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3058	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3059
3060
3061	/** @name SSE/AVX single/double precision floating point operations.
3062	* @{ */
3063	/**
3064	* A SSE result.
3065	*/
3066	typedef struct IEMSSERESULT
3067	{
3068	/** The output value. */
3069	X86XMMREG uResult;
3070	/** The output status. */
3071	uint32_t MXCSR;
3072	} IEMSSERESULT;
3073	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3074	/** Pointer to a SSE result. */
3075	typedef IEMSSERESULT *PIEMSSERESULT;
3076	/** Pointer to a const SSE result. */
3077	typedef IEMSSERESULT const *PCIEMSSERESULT;
3078
3079
3080	/**
3081	* A AVX128 result.
3082	*/
3083	typedef struct IEMAVX128RESULT
3084	{
3085	/** The output value. */
3086	X86XMMREG uResult;
3087	/** The output status. */
3088	uint32_t MXCSR;
3089	} IEMAVX128RESULT;
3090	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3091	/** Pointer to a AVX128 result. */
3092	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3093	/** Pointer to a const AVX128 result. */
3094	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3095
3096
3097	/**
3098	* A AVX256 result.
3099	*/
3100	typedef struct IEMAVX256RESULT
3101	{
3102	/** The output value. */
3103	X86YMMREG uResult;
3104	/** The output status. */
3105	uint32_t MXCSR;
3106	} IEMAVX256RESULT;
3107	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3108	/** Pointer to a AVX256 result. */
3109	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3110	/** Pointer to a const AVX256 result. */
3111	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3112
3113
3114	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3115	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3116	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3117	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3118	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3119	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3120
3121	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3122	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3123	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3124	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3125	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3126	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3127
3128	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3129	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3130
3131	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3132	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3133	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3134	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3135	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3136	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3137	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3138	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3139	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3140	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3141	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3142	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3143	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3144	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3145	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3146	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3147	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3148	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3149	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3150	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3151	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3152	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3153	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3154
3155	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3156	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3157	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3158	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3159	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3160	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3161
3162	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3163	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3164	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3165	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3166	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3167	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3168	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3169	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3170	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3171	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3172	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3173	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3174	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3175	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3176	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3177	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3178	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3179
3180	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3181	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3182	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3183	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3184	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3185	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3186	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3187	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3188	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3189	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3190	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3191	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3192	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3193	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3194	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3195	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3196	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3197	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3198	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3199	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3200	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3201	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3202
3203	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3204	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3205	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3206	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3207	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3208	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3209	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3210	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3211	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3212	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3213	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3214	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3215	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3216	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3217
3218	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3219	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3220	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3221	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3222	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3223	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3224	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3225	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3226	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3227	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3228	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3229	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3230	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3231	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3232	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3233	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3234	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3235	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3236	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3237	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3238	/** @} */
3239
3240	/** @name C instruction implementations for anything slightly complicated.
3241	* @{ */
3242
3243	/**
3244	* For typedef'ing or declaring a C instruction implementation function taking
3245	* no extra arguments.
3246	*
3247	* @param a_Name The name of the type.
3248	*/
3249	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3250	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3251	/**
3252	* For defining a C instruction implementation function taking no extra
3253	* arguments.
3254	*
3255	* @param a_Name The name of the function
3256	*/
3257	# define IEM_CIMPL_DEF_0(a_Name) \
3258	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3259	/**
3260	* Prototype version of IEM_CIMPL_DEF_0.
3261	*/
3262	# define IEM_CIMPL_PROTO_0(a_Name) \
3263	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3264	/**
3265	* For calling a C instruction implementation function taking no extra
3266	* arguments.
3267	*
3268	* This special call macro adds default arguments to the call and allow us to
3269	* change these later.
3270	*
3271	* @param a_fn The name of the function.
3272	*/
3273	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3274
3275	/**
3276	* For typedef'ing or declaring a C instruction implementation function taking
3277	* one extra argument.
3278	*
3279	* @param a_Name The name of the type.
3280	* @param a_Type0 The argument type.
3281	* @param a_Arg0 The argument name.
3282	*/
3283	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3284	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3285	/**
3286	* For defining a C instruction implementation function taking one extra
3287	* argument.
3288	*
3289	* @param a_Name The name of the function
3290	* @param a_Type0 The argument type.
3291	* @param a_Arg0 The argument name.
3292	*/
3293	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3294	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3295	/**
3296	* Prototype version of IEM_CIMPL_DEF_1.
3297	*/
3298	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3299	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3300	/**
3301	* For calling a C instruction implementation function taking one extra
3302	* argument.
3303	*
3304	* This special call macro adds default arguments to the call and allow us to
3305	* change these later.
3306	*
3307	* @param a_fn The name of the function.
3308	* @param a0 The name of the 1st argument.
3309	*/
3310	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3311
3312	/**
3313	* For typedef'ing or declaring a C instruction implementation function taking
3314	* two extra arguments.
3315	*
3316	* @param a_Name The name of the type.
3317	* @param a_Type0 The type of the 1st argument
3318	* @param a_Arg0 The name of the 1st argument.
3319	* @param a_Type1 The type of the 2nd argument.
3320	* @param a_Arg1 The name of the 2nd argument.
3321	*/
3322	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3323	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3324	/**
3325	* For defining a C instruction implementation function taking two extra
3326	* arguments.
3327	*
3328	* @param a_Name The name of the function.
3329	* @param a_Type0 The type of the 1st argument
3330	* @param a_Arg0 The name of the 1st argument.
3331	* @param a_Type1 The type of the 2nd argument.
3332	* @param a_Arg1 The name of the 2nd argument.
3333	*/
3334	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3335	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3336	/**
3337	* Prototype version of IEM_CIMPL_DEF_2.
3338	*/
3339	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3340	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3341	/**
3342	* For calling a C instruction implementation function taking two extra
3343	* arguments.
3344	*
3345	* This special call macro adds default arguments to the call and allow us to
3346	* change these later.
3347	*
3348	* @param a_fn The name of the function.
3349	* @param a0 The name of the 1st argument.
3350	* @param a1 The name of the 2nd argument.
3351	*/
3352	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3353
3354	/**
3355	* For typedef'ing or declaring a C instruction implementation function taking
3356	* three extra arguments.
3357	*
3358	* @param a_Name The name of the type.
3359	* @param a_Type0 The type of the 1st argument
3360	* @param a_Arg0 The name of the 1st argument.
3361	* @param a_Type1 The type of the 2nd argument.
3362	* @param a_Arg1 The name of the 2nd argument.
3363	* @param a_Type2 The type of the 3rd argument.
3364	* @param a_Arg2 The name of the 3rd argument.
3365	*/
3366	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3367	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3368	/**
3369	* For defining a C instruction implementation function taking three extra
3370	* arguments.
3371	*
3372	* @param a_Name The name of the function.
3373	* @param a_Type0 The type of the 1st argument
3374	* @param a_Arg0 The name of the 1st argument.
3375	* @param a_Type1 The type of the 2nd argument.
3376	* @param a_Arg1 The name of the 2nd argument.
3377	* @param a_Type2 The type of the 3rd argument.
3378	* @param a_Arg2 The name of the 3rd argument.
3379	*/
3380	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3381	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3382	/**
3383	* Prototype version of IEM_CIMPL_DEF_3.
3384	*/
3385	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3386	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3387	/**
3388	* For calling a C instruction implementation function taking three extra
3389	* arguments.
3390	*
3391	* This special call macro adds default arguments to the call and allow us to
3392	* change these later.
3393	*
3394	* @param a_fn The name of the function.
3395	* @param a0 The name of the 1st argument.
3396	* @param a1 The name of the 2nd argument.
3397	* @param a2 The name of the 3rd argument.
3398	*/
3399	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3400
3401
3402	/**
3403	* For typedef'ing or declaring a C instruction implementation function taking
3404	* four extra arguments.
3405	*
3406	* @param a_Name The name of the type.
3407	* @param a_Type0 The type of the 1st argument
3408	* @param a_Arg0 The name of the 1st argument.
3409	* @param a_Type1 The type of the 2nd argument.
3410	* @param a_Arg1 The name of the 2nd argument.
3411	* @param a_Type2 The type of the 3rd argument.
3412	* @param a_Arg2 The name of the 3rd argument.
3413	* @param a_Type3 The type of the 4th argument.
3414	* @param a_Arg3 The name of the 4th argument.
3415	*/
3416	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3417	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3418	/**
3419	* For defining a C instruction implementation function taking four extra
3420	* arguments.
3421	*
3422	* @param a_Name The name of the function.
3423	* @param a_Type0 The type of the 1st argument
3424	* @param a_Arg0 The name of the 1st argument.
3425	* @param a_Type1 The type of the 2nd argument.
3426	* @param a_Arg1 The name of the 2nd argument.
3427	* @param a_Type2 The type of the 3rd argument.
3428	* @param a_Arg2 The name of the 3rd argument.
3429	* @param a_Type3 The type of the 4th argument.
3430	* @param a_Arg3 The name of the 4th argument.
3431	*/
3432	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3433	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3434	a_Type2 a_Arg2, a_Type3 a_Arg3))
3435	/**
3436	* Prototype version of IEM_CIMPL_DEF_4.
3437	*/
3438	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3439	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3440	a_Type2 a_Arg2, a_Type3 a_Arg3))
3441	/**
3442	* For calling a C instruction implementation function taking four extra
3443	* arguments.
3444	*
3445	* This special call macro adds default arguments to the call and allow us to
3446	* change these later.
3447	*
3448	* @param a_fn The name of the function.
3449	* @param a0 The name of the 1st argument.
3450	* @param a1 The name of the 2nd argument.
3451	* @param a2 The name of the 3rd argument.
3452	* @param a3 The name of the 4th argument.
3453	*/
3454	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3455
3456
3457	/**
3458	* For typedef'ing or declaring a C instruction implementation function taking
3459	* five extra arguments.
3460	*
3461	* @param a_Name The name of the type.
3462	* @param a_Type0 The type of the 1st argument
3463	* @param a_Arg0 The name of the 1st argument.
3464	* @param a_Type1 The type of the 2nd argument.
3465	* @param a_Arg1 The name of the 2nd argument.
3466	* @param a_Type2 The type of the 3rd argument.
3467	* @param a_Arg2 The name of the 3rd argument.
3468	* @param a_Type3 The type of the 4th argument.
3469	* @param a_Arg3 The name of the 4th argument.
3470	* @param a_Type4 The type of the 5th argument.
3471	* @param a_Arg4 The name of the 5th argument.
3472	*/
3473	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3474	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3475	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3476	a_Type3 a_Arg3, a_Type4 a_Arg4))
3477	/**
3478	* For defining a C instruction implementation function taking five extra
3479	* arguments.
3480	*
3481	* @param a_Name The name of the function.
3482	* @param a_Type0 The type of the 1st argument
3483	* @param a_Arg0 The name of the 1st argument.
3484	* @param a_Type1 The type of the 2nd argument.
3485	* @param a_Arg1 The name of the 2nd argument.
3486	* @param a_Type2 The type of the 3rd argument.
3487	* @param a_Arg2 The name of the 3rd argument.
3488	* @param a_Type3 The type of the 4th argument.
3489	* @param a_Arg3 The name of the 4th argument.
3490	* @param a_Type4 The type of the 5th argument.
3491	* @param a_Arg4 The name of the 5th argument.
3492	*/
3493	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3494	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3495	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3496	/**
3497	* Prototype version of IEM_CIMPL_DEF_5.
3498	*/
3499	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3500	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3501	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3502	/**
3503	* For calling a C instruction implementation function taking five extra
3504	* arguments.
3505	*
3506	* This special call macro adds default arguments to the call and allow us to
3507	* change these later.
3508	*
3509	* @param a_fn The name of the function.
3510	* @param a0 The name of the 1st argument.
3511	* @param a1 The name of the 2nd argument.
3512	* @param a2 The name of the 3rd argument.
3513	* @param a3 The name of the 4th argument.
3514	* @param a4 The name of the 5th argument.
3515	*/
3516	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3517
3518	/** @} */
3519
3520
3521	/** @name Opcode Decoder Function Types.
3522	* @{ */
3523
3524	/** @typedef PFNIEMOP
3525	* Pointer to an opcode decoder function.
3526	*/
3527
3528	/** @def FNIEMOP_DEF
3529	* Define an opcode decoder function.
3530	*
3531	* We're using macors for this so that adding and removing parameters as well as
3532	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3533	*
3534	* @param a_Name The function name.
3535	*/
3536
3537	/** @typedef PFNIEMOPRM
3538	* Pointer to an opcode decoder function with RM byte.
3539	*/
3540
3541	/** @def FNIEMOPRM_DEF
3542	* Define an opcode decoder function with RM byte.
3543	*
3544	* We're using macors for this so that adding and removing parameters as well as
3545	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3546	*
3547	* @param a_Name The function name.
3548	*/
3549
3550	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3551	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3552	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3553	# define FNIEMOP_DEF(a_Name) \
3554	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3555	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3556	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3557	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3558	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3559
3560	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3561	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3562	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3563	# define FNIEMOP_DEF(a_Name) \
3564	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3565	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3566	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3567	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3568	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3569
3570	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
3571	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3572	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3573	# define FNIEMOP_DEF(a_Name) \
3574	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3575	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3576	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3577	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3578	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3579
3580	#else
3581	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3582	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3583	# define FNIEMOP_DEF(a_Name) \
3584	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3585	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3586	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3587	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3588	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3589
3590	#endif
3591	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3592
3593	/**
3594	* Call an opcode decoder function.
3595	*
3596	* We're using macors for this so that adding and removing parameters can be
3597	* done as we please. See FNIEMOP_DEF.
3598	*/
3599	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3600
3601	/**
3602	* Call a common opcode decoder function taking one extra argument.
3603	*
3604	* We're using macors for this so that adding and removing parameters can be
3605	* done as we please. See FNIEMOP_DEF_1.
3606	*/
3607	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3608
3609	/**
3610	* Call a common opcode decoder function taking one extra argument.
3611	*
3612	* We're using macors for this so that adding and removing parameters can be
3613	* done as we please. See FNIEMOP_DEF_1.
3614	*/
3615	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3616	/** @} */
3617
3618
3619	/** @name Misc Helpers
3620	* @{ */
3621
3622	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3623	* due to GCC lacking knowledge about the value range of a switch. */
3624	#if RT_CPLUSPLUS_PREREQ(202000)
3625	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3626	#else
3627	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3628	#endif
3629
3630	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3631	#if RT_CPLUSPLUS_PREREQ(202000)
3632	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3633	#else
3634	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3635	#endif
3636
3637	/**
3638	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3639	* occation.
3640	*/
3641	#ifdef LOG_ENABLED
3642	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3643	do { \
3644	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3645	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3646	} while (0)
3647	#else
3648	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3649	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3650	#endif
3651
3652	/**
3653	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3654	* occation using the supplied logger statement.
3655	*
3656	* @param a_LoggerArgs What to log on failure.
3657	*/
3658	#ifdef LOG_ENABLED
3659	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3660	do { \
3661	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3662	/LogFunc(a_LoggerArgs);/ \
3663	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3664	} while (0)
3665	#else
3666	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3667	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3668	#endif
3669
3670	/**
3671	* Gets the CPU mode (from fExec) as a IEMMODE value.
3672	*
3673	* @returns IEMMODE
3674	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3675	*/
3676	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
3677
3678	/**
3679	* Check if we're currently executing in real or virtual 8086 mode.
3680	*
3681	* @returns @c true if it is, @c false if not.
3682	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3683	*/
3684	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
3685	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
3686
3687	/**
3688	* Check if we're currently executing in virtual 8086 mode.
3689	*
3690	* @returns @c true if it is, @c false if not.
3691	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3692	*/
3693	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
3694
3695	/**
3696	* Check if we're currently executing in long mode.
3697	*
3698	* @returns @c true if it is, @c false if not.
3699	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3700	*/
3701	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3702
3703	/**
3704	* Check if we're currently executing in a 16-bit code segment.
3705	*
3706	* @returns @c true if it is, @c false if not.
3707	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3708	*/
3709	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
3710
3711	/**
3712	* Check if we're currently executing in a 32-bit code segment.
3713	*
3714	* @returns @c true if it is, @c false if not.
3715	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3716	*/
3717	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
3718
3719	/**
3720	* Check if we're currently executing in a 64-bit code segment.
3721	*
3722	* @returns @c true if it is, @c false if not.
3723	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3724	*/
3725	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
3726
3727	/**
3728	* Check if we're currently executing in real mode.
3729	*
3730	* @returns @c true if it is, @c false if not.
3731	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3732	*/
3733	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
3734
3735	/**
3736	* Gets the current protection level (CPL).
3737	*
3738	* @returns 0..3
3739	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3740	*/
3741	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
3742
3743	/**
3744	* Sets the current protection level (CPL).
3745	*
3746	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3747	*/
3748	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
3749	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
3750
3751	/**
3752	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3753	* @returns PCCPUMFEATURES
3754	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3755	*/
3756	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3757
3758	/**
3759	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3760	* @returns PCCPUMFEATURES
3761	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3762	*/
3763	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3764
3765	/**
3766	* Evaluates to true if we're presenting an Intel CPU to the guest.
3767	*/
3768	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3769
3770	/**
3771	* Evaluates to true if we're presenting an AMD CPU to the guest.
3772	*/
3773	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3774
3775	/**
3776	* Check if the address is canonical.
3777	*/
3778	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3779
3780	/** Checks if the ModR/M byte is in register mode or not. */
3781	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3782	/** Checks if the ModR/M byte is in memory mode or not. */
3783	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3784
3785	/**
3786	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3787	*
3788	* For use during decoding.
3789	*/
3790	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3791	/**
3792	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3793	*
3794	* For use during decoding.
3795	*/
3796	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3797
3798	/**
3799	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3800	*
3801	* For use during decoding.
3802	*/
3803	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3804	/**
3805	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3806	*
3807	* For use during decoding.
3808	*/
3809	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3810
3811	/**
3812	* Combines the prefix REX and ModR/M byte for passing to
3813	* iemOpHlpCalcRmEffAddrThreadedAddr64().
3814	*
3815	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
3816	* The two bits are part of the REG sub-field, which isn't needed in
3817	* iemOpHlpCalcRmEffAddrThreadedAddr64().
3818	*
3819	* For use during decoding/recompiling.
3820	*/
3821	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
3822	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
3823	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
3824	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
3825	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
3826
3827	/**
3828	* Gets the effective VEX.VVVV value.
3829	*
3830	* The 4th bit is ignored if not 64-bit code.
3831	* @returns effective V-register value.
3832	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3833	*/
3834	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3835	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3836
3837
3838	/**
3839	* Checks if we're executing inside an AMD-V or VT-x guest.
3840	*/
3841	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
3842	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
3843	#else
3844	# define IEM_IS_IN_GUEST(a_pVCpu) false
3845	#endif
3846
3847
3848	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3849
3850	/**
3851	* Check if the guest has entered VMX root operation.
3852	*/
3853	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3854
3855	/**
3856	* Check if the guest has entered VMX non-root operation.
3857	*/
3858	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
3859	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
3860
3861	/**
3862	* Check if the nested-guest has the given Pin-based VM-execution control set.
3863	*/
3864	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3865
3866	/**
3867	* Check if the nested-guest has the given Processor-based VM-execution control set.
3868	*/
3869	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3870
3871	/**
3872	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3873	* control set.
3874	*/
3875	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3876
3877	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3878	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3879
3880	/** Whether a shadow VMCS is present for the given VCPU. */
3881	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3882
3883	/** Gets the VMXON region pointer. */
3884	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3885
3886	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3887	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3888
3889	/** Whether a current VMCS is present for the given VCPU. */
3890	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3891
3892	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3893	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3894	do \
3895	{ \
3896	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3897	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3898	} while (0)
3899
3900	/** Clears any current VMCS for the given VCPU. */
3901	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3902	do \
3903	{ \
3904	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3905	} while (0)
3906
3907	/**
3908	* Invokes the VMX VM-exit handler for an instruction intercept.
3909	*/
3910	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3911	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3912
3913	/**
3914	* Invokes the VMX VM-exit handler for an instruction intercept where the
3915	* instruction provides additional VM-exit information.
3916	*/
3917	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3918	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3919
3920	/**
3921	* Invokes the VMX VM-exit handler for a task switch.
3922	*/
3923	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3924	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3925
3926	/**
3927	* Invokes the VMX VM-exit handler for MWAIT.
3928	*/
3929	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3930	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3931
3932	/**
3933	* Invokes the VMX VM-exit handler for EPT faults.
3934	*/
3935	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3936	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3937
3938	/**
3939	* Invokes the VMX VM-exit handler.
3940	*/
3941	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3942	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3943
3944	#else
3945	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3946	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3947	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3948	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3949	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3950	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3951	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3952	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3953	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3954	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3955	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3956
3957	#endif
3958
3959	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3960	/**
3961	* Checks if we're executing a guest using AMD-V.
3962	*/
3963	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
3964	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
3965	/**
3966	* Check if an SVM control/instruction intercept is set.
3967	*/
3968	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3969	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3970
3971	/**
3972	* Check if an SVM read CRx intercept is set.
3973	*/
3974	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3975	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3976
3977	/**
3978	* Check if an SVM write CRx intercept is set.
3979	*/
3980	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3981	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3982
3983	/**
3984	* Check if an SVM read DRx intercept is set.
3985	*/
3986	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3987	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3988
3989	/**
3990	* Check if an SVM write DRx intercept is set.
3991	*/
3992	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3993	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3994
3995	/**
3996	* Check if an SVM exception intercept is set.
3997	*/
3998	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3999	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4000
4001	/**
4002	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4003	*/
4004	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4005	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4006
4007	/**
4008	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4009	* corresponding decode assist information.
4010	*/
4011	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4012	do \
4013	{ \
4014	uint64_t uExitInfo1; \
4015	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4016	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4017	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4018	else \
4019	uExitInfo1 = 0; \
4020	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4021	} while (0)
4022
4023	/** Check and handles SVM nested-guest instruction intercept and updates
4024	* NRIP if needed.
4025	*/
4026	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4027	do \
4028	{ \
4029	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4030	{ \
4031	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4032	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4033	} \
4034	} while (0)
4035
4036	/** Checks and handles SVM nested-guest CR0 read intercept. */
4037	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4038	do \
4039	{ \
4040	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4041	{ /* probably likely */ } \
4042	else \
4043	{ \
4044	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4045	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4046	} \
4047	} while (0)
4048
4049	/**
4050	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4051	*/
4052	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4053	do { \
4054	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4055	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4056	} while (0)
4057
4058	#else
4059	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4060	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4061	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4062	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4063	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4064	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4065	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4066	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4067	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4068	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4069	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4070	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4071
4072	#endif
4073
4074	/** @} */
4075
4076	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4077
4078
4079	/**
4080	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4081	*/
4082	typedef union IEMSELDESC
4083	{
4084	/** The legacy view. */
4085	X86DESC Legacy;
4086	/** The long mode view. */
4087	X86DESC64 Long;
4088	} IEMSELDESC;
4089	/** Pointer to a selector descriptor table entry. */
4090	typedef IEMSELDESC *PIEMSELDESC;
4091
4092	/** @name Raising Exceptions.
4093	* @{ */
4094	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4095	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4096
4097	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4098	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4099	#ifdef IEM_WITH_SETJMP
4100	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4101	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4102	#endif
4103	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4104	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4105	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4106	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4107	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4108	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4109	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4110	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4111	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4112	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4113	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4114	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4115	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4116	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4117	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4118	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4119	#ifdef IEM_WITH_SETJMP
4120	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4121	#endif
4122	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4123	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4124	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4125	#ifdef IEM_WITH_SETJMP
4126	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4127	#endif
4128	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4129	#ifdef IEM_WITH_SETJMP
4130	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4131	#endif
4132	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4133	#ifdef IEM_WITH_SETJMP
4134	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4135	#endif
4136	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4137	#ifdef IEM_WITH_SETJMP
4138	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4139	#endif
4140	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4141	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4142	#ifdef IEM_WITH_SETJMP
4143	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4144	#endif
4145	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4146
4147	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4148	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4149	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4150
4151	/**
4152	* Macro for calling iemCImplRaiseDivideError().
4153	*
4154	* This enables us to add/remove arguments and force different levels of
4155	* inlining as we wish.
4156	*
4157	* @return Strict VBox status code.
4158	*/
4159	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseDivideError)
4160
4161	/**
4162	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4163	*
4164	* This enables us to add/remove arguments and force different levels of
4165	* inlining as we wish.
4166	*
4167	* @return Strict VBox status code.
4168	*/
4169	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidLockPrefix)
4170
4171	/**
4172	* Macro for calling iemCImplRaiseInvalidOpcode().
4173	*
4174	* This enables us to add/remove arguments and force different levels of
4175	* inlining as we wish.
4176	*
4177	* @return Strict VBox status code.
4178	*/
4179	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4180	/** @} */
4181
4182	/** @name Register Access.
4183	* @{ */
4184	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4185	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4186	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4187	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4188	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4189	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4190	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4191	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4192	/** @} */
4193
4194	/** @name FPU access and helpers.
4195	* @{ */
4196	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
4197	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4198	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
4199	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
4200	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
4201	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4202	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4203	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4204	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4205	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
4206	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
4207	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
4208	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4209	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
4210	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4211	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
4212	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4213	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
4214	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4215	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
4216	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
4217	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
4218	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
4219	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4220	/** @} */
4221
4222	/** @name SSE+AVX SIMD access and helpers.
4223	* @{ */
4224	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
4225	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
4226	/** @} */
4227
4228	/** @name Memory access.
4229	* @{ */
4230
4231	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
4232	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
4233	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
4234	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
4235	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
4236	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
4237	* Users include FXSAVE & FXRSTOR. */
4238	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
4239
4240	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
4241	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
4242	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4243	#ifndef IN_RING3
4244	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4245	#endif
4246	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
4247	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
4248	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4249	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
4250
4251	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
4252	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
4253	#ifdef IEM_WITH_CODE_TLB
4254	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
4255	#else
4256	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
4257	#endif
4258	#ifdef IEM_WITH_SETJMP
4259	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4260	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4261	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4262	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4263	#else
4264	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
4265	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4266	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4267	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4268	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4269	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4270	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4271	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4272	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4273	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4274	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4275	#endif
4276
4277	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4278	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4279	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4280	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4281	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4282	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4283	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4284	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4285	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4286	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4287	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4288	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4289	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
4290	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
4291	#ifdef IEM_WITH_SETJMP
4292	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4293	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4294	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4295	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4296	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4297	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4298	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4299	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4300	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4301	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4302	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4303	#endif
4304
4305	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4306	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4307	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4308	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4309	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
4310
4311	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
4312	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
4313	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4314	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4315	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4316	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4317	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4318	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4319	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4320	#ifdef IEM_WITH_SETJMP
4321	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4322	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4323	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4324	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4325	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4326	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4327	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4328	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4329	#endif
4330
4331	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4332	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4333	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
4334	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
4335	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4336	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
4337	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4338	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4339	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4340	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4341	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4342	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4343	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4344	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4345	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4346	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4347	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4348	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4349	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4350	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4351	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4352	/** @} */
4353
4354	/** @name IEMAllCImpl.cpp
4355	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4356	* @{ */
4357	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4358	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4359	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4360	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4361	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4362	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4363	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4364	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4365	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4366	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4367	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4368	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4369	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4370	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4371	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4372	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
4373	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4374	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4375	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
4376	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
4377	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
4378	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
4379	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
4380	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
4381	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
4382	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
4383	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
4384	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
4385	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
4386	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
4387	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
4388	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4389	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4390	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4391	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
4392	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4393	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4394	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4395	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4396	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4397	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4398	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4399	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4400	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4401	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4402	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4403	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4404	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4405	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4406	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4407	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4408	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4409	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4410	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4411	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4412	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4413	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4414	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4415	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4416	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4417	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4418	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4419	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4420	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4421	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4422	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4423	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4424	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4425	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4426	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4427	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4428	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4429	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4430	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4431	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4432	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4433	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4434	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4435	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4436	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4437	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4438	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4439	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4440	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4441	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4442	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4443	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4444	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4445	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4446	IEM_CIMPL_PROTO_0(iemCImpl_das);
4447	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4448	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4449	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4450	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4451	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4452	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4453	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4454	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4455	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4456	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4457	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4458	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4459	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4460	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4461	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4462	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4463	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4464	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4465	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4466	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4467	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4468	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4469	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
4470	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, uint32_t, uPopAndFpuOpcode);
4471	/** @} */
4472
4473	/** @name IEMAllCImplStrInstr.cpp.h
4474	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4475	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4476	* @{ */
4477	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4478	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4479	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4480	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4481	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4482	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4483	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4484	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4485	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4486	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4487	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4488
4489	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4490	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4491	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4492	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4493	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4494	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4495	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4496	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4497	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4498	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4499	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4500
4501	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4502	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4503	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4504	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4505	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4506	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4507	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4508	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4509	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4510	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4511	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4512
4513
4514	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4515	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4516	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4517	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4518	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4519	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4520	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4521	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4522	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4523	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4524	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4525
4526	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4527	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4528	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4529	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4530	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4531	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4532	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4533	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4534	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4535	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4536	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4537
4538	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4539	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4540	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4541	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4542	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4543	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4544	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4545	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4546	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4547	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4548	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4549
4550	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4551	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4552	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4553	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4554	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4555	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4556	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4557	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4558	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4559	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4560	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4561
4562
4563	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4564	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4565	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4566	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4567	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4568	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4569	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4570	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4571	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4572	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4573	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4574
4575	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4576	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4577	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4578	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4579	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4580	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4581	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4582	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4583	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4584	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4585	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4586
4587	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4588	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4589	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4590	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4591	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4592	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4593	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4594	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4595	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4596	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4597	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4598
4599	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4600	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4601	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4602	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4603	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4604	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4605	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4606	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4607	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4608	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4609	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4610	/** @} */
4611
4612	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4613	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4614	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4615	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4616	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4617	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4618	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4619	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4620	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4621	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4622	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4623	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4624	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4625	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4626	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4627	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4628	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4629	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4630	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4631	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4632	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4633	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4634	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4635	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4636	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4637	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4638	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4639	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4640	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4641	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4642	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4643	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4644	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4645	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4646	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4647	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4648	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4649	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4650	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4651	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4652	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4653	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
4654	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4655	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4656	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4657	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4658	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4659	#endif
4660
4661	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4662	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4663	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4664	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4665	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4666	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
4667	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4668	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4669	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4670	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4671	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4672	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4673	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4674	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4675	#endif
4676
4677	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4678	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4679	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4680
4681
4682	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
4683
4684	/** @} */
4685
4686	RT_C_DECLS_END
4687
4688	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4689

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 100140

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