IEMInternal.h@ 80651

Last change on this file since 80651 was 80268, checked in by vboxsync, 5 years ago
VMM: Refactoring VMMAll/* to use VMCC & VMMCPUCC. bugref:9217
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1	/* $Id: IEMInternal.h 80268 2019-08-14 11:25:13Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
19	#define VMM_INCLUDED_SRC_include_IEMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/param.h>
29
30	#include <setjmp.h>
31
32
33	RT_C_DECLS_BEGIN
34
35
36	/** @defgroup grp_iem_int Internals
37	* @ingroup grp_iem
38	* @internal
39	* @{
40	*/
41
42	/** For expanding symbol in slickedit and other products tagging and
43	* crossreferencing IEM symbols. */
44	#ifndef IEM_STATIC
45	# define IEM_STATIC static
46	#endif
47
48	/** @def IEM_WITH_3DNOW
49	* Includes the 3DNow decoding. */
50	#define IEM_WITH_3DNOW
51
52	/** @def IEM_WITH_THREE_0F_38
53	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
54	#define IEM_WITH_THREE_0F_38
55
56	/** @def IEM_WITH_THREE_0F_3A
57	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
58	#define IEM_WITH_THREE_0F_3A
59
60	/** @def IEM_WITH_VEX
61	* Includes the VEX decoding. */
62	#define IEM_WITH_VEX
63
64	/** @def IEM_CFG_TARGET_CPU
65	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
66	*
67	* By default we allow this to be configured by the user via the
68	* CPUM/GuestCpuName config string, but this comes at a slight cost during
69	* decoding. So, for applications of this code where there is no need to
70	* be dynamic wrt target CPU, just modify this define.
71	*/
72	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
73	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
74	#endif
75
76
77	//#define IEM_WITH_CODE_TLB// - work in progress
78
79
80	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
81	/** Instruction statistics. */
82	typedef struct IEMINSTRSTATS
83	{
84	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
85	# include "IEMInstructionStatisticsTmpl.h"
86	# undef IEM_DO_INSTR_STAT
87	} IEMINSTRSTATS;
88	#else
89	struct IEMINSTRSTATS;
90	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
91	#endif
92	/** Pointer to IEM instruction statistics. */
93	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
94
95	/** Finish and move to types.h */
96	typedef union
97	{
98	uint32_t u32;
99	} RTFLOAT32U;
100	typedef RTFLOAT32U *PRTFLOAT32U;
101	typedef RTFLOAT32U const *PCRTFLOAT32U;
102
103
104	/**
105	* Extended operand mode that includes a representation of 8-bit.
106	*
107	* This is used for packing down modes when invoking some C instruction
108	* implementations.
109	*/
110	typedef enum IEMMODEX
111	{
112	IEMMODEX_16BIT = IEMMODE_16BIT,
113	IEMMODEX_32BIT = IEMMODE_32BIT,
114	IEMMODEX_64BIT = IEMMODE_64BIT,
115	IEMMODEX_8BIT
116	} IEMMODEX;
117	AssertCompileSize(IEMMODEX, 4);
118
119
120	/**
121	* Branch types.
122	*/
123	typedef enum IEMBRANCH
124	{
125	IEMBRANCH_JUMP = 1,
126	IEMBRANCH_CALL,
127	IEMBRANCH_TRAP,
128	IEMBRANCH_SOFTWARE_INT,
129	IEMBRANCH_HARDWARE_INT
130	} IEMBRANCH;
131	AssertCompileSize(IEMBRANCH, 4);
132
133
134	/**
135	* INT instruction types.
136	*/
137	typedef enum IEMINT
138	{
139	/** INT n instruction (opcode 0xcd imm). */
140	IEMINT_INTN = 0,
141	/** Single byte INT3 instruction (opcode 0xcc). */
142	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
143	/** Single byte INTO instruction (opcode 0xce). */
144	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
145	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
146	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
147	} IEMINT;
148	AssertCompileSize(IEMINT, 4);
149
150
151	/**
152	* A FPU result.
153	*/
154	typedef struct IEMFPURESULT
155	{
156	/** The output value. */
157	RTFLOAT80U r80Result;
158	/** The output status. */
159	uint16_t FSW;
160	} IEMFPURESULT;
161	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
162	/** Pointer to a FPU result. */
163	typedef IEMFPURESULT *PIEMFPURESULT;
164	/** Pointer to a const FPU result. */
165	typedef IEMFPURESULT const *PCIEMFPURESULT;
166
167
168	/**
169	* A FPU result consisting of two output values and FSW.
170	*/
171	typedef struct IEMFPURESULTTWO
172	{
173	/** The first output value. */
174	RTFLOAT80U r80Result1;
175	/** The output status. */
176	uint16_t FSW;
177	/** The second output value. */
178	RTFLOAT80U r80Result2;
179	} IEMFPURESULTTWO;
180	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
181	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
182	/** Pointer to a FPU result consisting of two output values and FSW. */
183	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
184	/** Pointer to a const FPU result consisting of two output values and FSW. */
185	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
186
187
188	/**
189	* IEM TLB entry.
190	*
191	* Lookup assembly:
192	* @code{.asm}
193	; Calculate tag.
194	mov rax, [VA]
195	shl rax, 16
196	shr rax, 16 + X86_PAGE_SHIFT
197	or rax, [uTlbRevision]
198
199	; Do indexing.
200	movzx ecx, al
201	lea rcx, [pTlbEntries + rcx]
202
203	; Check tag.
204	cmp [rcx + IEMTLBENTRY.uTag], rax
205	jne .TlbMiss
206
207	; Check access.
208	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
209	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
210	cmp rax, [uTlbPhysRev]
211	jne .TlbMiss
212
213	; Calc address and we're done.
214	mov eax, X86_PAGE_OFFSET_MASK
215	and eax, [VA]
216	or rax, [rcx + IEMTLBENTRY.pMappingR3]
217	%ifdef VBOX_WITH_STATISTICS
218	inc qword [cTlbHits]
219	%endif
220	jmp .Done
221
222	.TlbMiss:
223	mov r8d, ACCESS_FLAGS
224	mov rdx, [VA]
225	mov rcx, [pVCpu]
226	call iemTlbTypeMiss
227	.Done:
228
229	@endcode
230	*
231	*/
232	typedef struct IEMTLBENTRY
233	{
234	/** The TLB entry tag.
235	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
236	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
237	*
238	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
239	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
240	* revision wraps around though, the tags needs to be zeroed.
241	*
242	* @note Try use SHRD instruction? After seeing
243	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
244	*/
245	uint64_t uTag;
246	/** Access flags and physical TLB revision.
247	*
248	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
249	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
250	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
251	* - Bit 3 - pgm phys/virt - not directly writable.
252	* - Bit 4 - pgm phys page - not directly readable.
253	* - Bit 5 - currently unused.
254	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
255	* - Bit 7 - tlb entry - pMappingR3 member not valid.
256	* - Bits 63 thru 8 are used for the physical TLB revision number.
257	*
258	* We're using complemented bit meanings here because it makes it easy to check
259	* whether special action is required. For instance a user mode write access
260	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
261	* non-zero result would mean special handling needed because either it wasn't
262	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
263	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
264	* need to check any PTE flag.
265	*/
266	uint64_t fFlagsAndPhysRev;
267	/** The guest physical page address. */
268	uint64_t GCPhys;
269	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
270	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
271	R3PTRTYPE(uint8_t *) pbMappingR3;
272	#else
273	R3R0PTRTYPE(uint8_t *) pbMappingR3;
274	#endif
275	#if HC_ARCH_BITS == 32
276	uint32_t u32Padding1;
277	#endif
278	} IEMTLBENTRY;
279	AssertCompileSize(IEMTLBENTRY, 32);
280	/** Pointer to an IEM TLB entry. */
281	typedef IEMTLBENTRY *PIEMTLBENTRY;
282
283	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
284	* @{ */
285	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
286	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
287	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
288	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
289	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
290	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(5) /*< Page tables: Not dirty (needs to be made dirty on write). /
291	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(6) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
292	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
293	/** @} */
294
295
296	/**
297	* An IEM TLB.
298	*
299	* We've got two of these, one for data and one for instructions.
300	*/
301	typedef struct IEMTLB
302	{
303	/** The TLB entries.
304	* We've choosen 256 because that way we can obtain the result directly from a
305	* 8-bit register without an additional AND instruction. */
306	IEMTLBENTRY aEntries[256];
307	/** The TLB revision.
308	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
309	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
310	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
311	* (The revision zero indicates an invalid TLB entry.)
312	*
313	* The initial value is choosen to cause an early wraparound. */
314	uint64_t uTlbRevision;
315	/** The TLB physical address revision - shadow of PGM variable.
316	*
317	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
318	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
319	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
320	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
321	*
322	* The initial value is choosen to cause an early wraparound. */
323	uint64_t volatile uTlbPhysRev;
324
325	/* Statistics: */
326
327	/** TLB hits (VBOX_WITH_STATISTICS only). */
328	uint64_t cTlbHits;
329	/** TLB misses. */
330	uint32_t cTlbMisses;
331	/** Slow read path. */
332	uint32_t cTlbSlowReadPath;
333	#if 0
334	/** TLB misses because of tag mismatch. */
335	uint32_t cTlbMissesTag;
336	/** TLB misses because of virtual access violation. */
337	uint32_t cTlbMissesVirtAccess;
338	/** TLB misses because of dirty bit. */
339	uint32_t cTlbMissesDirty;
340	/** TLB misses because of MMIO */
341	uint32_t cTlbMissesMmio;
342	/** TLB misses because of write access handlers. */
343	uint32_t cTlbMissesWriteHandler;
344	/** TLB misses because no r3(/r0) mapping. */
345	uint32_t cTlbMissesMapping;
346	#endif
347	/** Alignment padding. */
348	uint32_t au32Padding[3+5];
349	} IEMTLB;
350	AssertCompileSizeAlignment(IEMTLB, 64);
351	/** IEMTLB::uTlbRevision increment. */
352	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
353	/** IEMTLB::uTlbPhysRev increment. */
354	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
355
356
357	/**
358	* The per-CPU IEM state.
359	*/
360	typedef struct IEMCPU
361	{
362	/** Info status code that needs to be propagated to the IEM caller.
363	* This cannot be passed internally, as it would complicate all success
364	* checks within the interpreter making the code larger and almost impossible
365	* to get right. Instead, we'll store status codes to pass on here. Each
366	* source of these codes will perform appropriate sanity checks. */
367	int32_t rcPassUp; /* 0x00 */
368
369	/** The current CPU execution mode (CS). */
370	IEMMODE enmCpuMode; /* 0x04 */
371	/** The CPL. */
372	uint8_t uCpl; /* 0x05 */
373
374	/** Whether to bypass access handlers or not. */
375	bool fBypassHandlers; /* 0x06 */
376	bool fUnusedWasInPatchCode; /* 0x07 */
377
378	/** @name Decoder state.
379	* @{ */
380	#ifdef IEM_WITH_CODE_TLB
381	/** The offset of the next instruction byte. */
382	uint32_t offInstrNextByte; /* 0x08 */
383	/** The number of bytes available at pbInstrBuf for the current instruction.
384	* This takes the max opcode length into account so that doesn't need to be
385	* checked separately. */
386	uint32_t cbInstrBuf; /* 0x0c */
387	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
388	* This can be NULL if the page isn't mappable for some reason, in which
389	* case we'll do fallback stuff.
390	*
391	* If we're executing an instruction from a user specified buffer,
392	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
393	* aligned pointer but pointer to the user data.
394	*
395	* For instructions crossing pages, this will start on the first page and be
396	* advanced to the next page by the time we've decoded the instruction. This
397	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
398	*/
399	uint8_t const pbInstrBuf; / 0x10 */
400	# if ARCH_BITS == 32
401	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
402	# endif
403	/** The program counter corresponding to pbInstrBuf.
404	* This is set to a non-canonical address when we need to invalidate it. */
405	uint64_t uInstrBufPc; /* 0x18 */
406	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
407	* This takes the CS segment limit into account. */
408	uint16_t cbInstrBufTotal; /* 0x20 */
409	/** Offset into pbInstrBuf of the first byte of the current instruction.
410	* Can be negative to efficiently handle cross page instructions. */
411	int16_t offCurInstrStart; /* 0x22 */
412
413	/** The prefix mask (IEM_OP_PRF_XXX). */
414	uint32_t fPrefixes; /* 0x24 */
415	/** The extra REX ModR/M register field bit (REX.R << 3). */
416	uint8_t uRexReg; /* 0x28 */
417	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
418	* (REX.B << 3). */
419	uint8_t uRexB; /* 0x29 */
420	/** The extra REX SIB index field bit (REX.X << 3). */
421	uint8_t uRexIndex; /* 0x2a */
422
423	/** The effective segment register (X86_SREG_XXX). */
424	uint8_t iEffSeg; /* 0x2b */
425
426	/** The offset of the ModR/M byte relative to the start of the instruction. */
427	uint8_t offModRm; /* 0x2c */
428	#else
429	/** The size of what has currently been fetched into abOpcode. */
430	uint8_t cbOpcode; /* 0x08 */
431	/** The current offset into abOpcode. */
432	uint8_t offOpcode; /* 0x09 */
433	/** The offset of the ModR/M byte relative to the start of the instruction. */
434	uint8_t offModRm; /* 0x0a */
435
436	/** The effective segment register (X86_SREG_XXX). */
437	uint8_t iEffSeg; /* 0x0b */
438
439	/** The prefix mask (IEM_OP_PRF_XXX). */
440	uint32_t fPrefixes; /* 0x0c */
441	/** The extra REX ModR/M register field bit (REX.R << 3). */
442	uint8_t uRexReg; /* 0x10 */
443	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
444	* (REX.B << 3). */
445	uint8_t uRexB; /* 0x11 */
446	/** The extra REX SIB index field bit (REX.X << 3). */
447	uint8_t uRexIndex; /* 0x12 */
448
449	#endif
450
451	/** The effective operand mode. */
452	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
453	/** The default addressing mode. */
454	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
455	/** The effective addressing mode. */
456	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
457	/** The default operand mode. */
458	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
459
460	/** Prefix index (VEX.pp) for two byte and three byte tables. */
461	uint8_t idxPrefix; /* 0x31, 0x17 */
462	/** 3rd VEX/EVEX/XOP register.
463	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
464	uint8_t uVex3rdReg; /* 0x32, 0x18 */
465	/** The VEX/EVEX/XOP length field. */
466	uint8_t uVexLength; /* 0x33, 0x19 */
467	/** Additional EVEX stuff. */
468	uint8_t fEvexStuff; /* 0x34, 0x1a */
469
470	/** Explicit alignment padding. */
471	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
472	/** The FPU opcode (FOP). */
473	uint16_t uFpuOpcode; /* 0x36, 0x1c */
474	#ifndef IEM_WITH_CODE_TLB
475	/** Explicit alignment padding. */
476	uint8_t abAlignment2b[2]; /* 0x1e */
477	#endif
478
479	/** The opcode bytes. */
480	uint8_t abOpcode[15]; /* 0x48, 0x20 */
481	/** Explicit alignment padding. */
482	#ifdef IEM_WITH_CODE_TLB
483	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
484	#else
485	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
486	#endif
487	/** @} */
488
489
490	/** The flags of the current exception / interrupt. */
491	uint32_t fCurXcpt; /* 0x48, 0x48 */
492	/** The current exception / interrupt. */
493	uint8_t uCurXcpt;
494	/** Exception / interrupt recursion depth. */
495	int8_t cXcptRecursions;
496
497	/** The number of active guest memory mappings. */
498	uint8_t cActiveMappings;
499	/** The next unused mapping index. */
500	uint8_t iNextMapping;
501	/** Records for tracking guest memory mappings. */
502	struct
503	{
504	/** The address of the mapped bytes. */
505	void *pv;
506	/** The access flags (IEM_ACCESS_XXX).
507	* IEM_ACCESS_INVALID if the entry is unused. */
508	uint32_t fAccess;
509	#if HC_ARCH_BITS == 64
510	uint32_t u32Alignment4; /*< Alignment padding. /
511	#endif
512	} aMemMappings[3];
513
514	/** Locking records for the mapped memory. */
515	union
516	{
517	PGMPAGEMAPLOCK Lock;
518	uint64_t au64Padding[2];
519	} aMemMappingLocks[3];
520
521	/** Bounce buffer info.
522	* This runs in parallel to aMemMappings. */
523	struct
524	{
525	/** The physical address of the first byte. */
526	RTGCPHYS GCPhysFirst;
527	/** The physical address of the second page. */
528	RTGCPHYS GCPhysSecond;
529	/** The number of bytes in the first page. */
530	uint16_t cbFirst;
531	/** The number of bytes in the second page. */
532	uint16_t cbSecond;
533	/** Whether it's unassigned memory. */
534	bool fUnassigned;
535	/** Explicit alignment padding. */
536	bool afAlignment5[3];
537	} aMemBbMappings[3];
538
539	/** Bounce buffer storage.
540	* This runs in parallel to aMemMappings and aMemBbMappings. */
541	struct
542	{
543	uint8_t ab[512];
544	} aBounceBuffers[3];
545
546
547	/** Pointer set jump buffer - ring-3 context. */
548	R3PTRTYPE(jmp_buf *) pJmpBufR3;
549	/** Pointer set jump buffer - ring-0 context. */
550	R0PTRTYPE(jmp_buf *) pJmpBufR0;
551
552	/** @todo Should move this near @a fCurXcpt later. */
553	/** The CR2 for the current exception / interrupt. */
554	uint64_t uCurXcptCr2;
555	/** The error code for the current exception / interrupt. */
556	uint32_t uCurXcptErr;
557	/** The VMX APIC-access page handler type. */
558	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
559
560	/** @name Statistics
561	* @{ */
562	/** The number of instructions we've executed. */
563	uint32_t cInstructions;
564	/** The number of potential exits. */
565	uint32_t cPotentialExits;
566	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
567	* This may contain uncommitted writes. */
568	uint32_t cbWritten;
569	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
570	uint32_t cRetInstrNotImplemented;
571	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
572	uint32_t cRetAspectNotImplemented;
573	/** Counts informational statuses returned (other than VINF_SUCCESS). */
574	uint32_t cRetInfStatuses;
575	/** Counts other error statuses returned. */
576	uint32_t cRetErrStatuses;
577	/** Number of times rcPassUp has been used. */
578	uint32_t cRetPassUpStatus;
579	/** Number of times RZ left with instruction commit pending for ring-3. */
580	uint32_t cPendingCommit;
581	/** Number of long jumps. */
582	uint32_t cLongJumps;
583	/** @} */
584
585	/** @name Target CPU information.
586	* @{ */
587	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
588	/** The target CPU. */
589	uint32_t uTargetCpu;
590	#else
591	uint32_t u32TargetCpuPadding;
592	#endif
593	/** The CPU vendor. */
594	CPUMCPUVENDOR enmCpuVendor;
595	/** @} */
596
597	/** @name Host CPU information.
598	* @{ */
599	/** The CPU vendor. */
600	CPUMCPUVENDOR enmHostCpuVendor;
601	/** @} */
602
603	/** Counts RDMSR \#GP(0) LogRel(). */
604	uint8_t cLogRelRdMsr;
605	/** Counts WRMSR \#GP(0) LogRel(). */
606	uint8_t cLogRelWrMsr;
607	/** Alignment padding. */
608	uint8_t abAlignment8[50];
609
610	/** Data TLB.
611	* @remarks Must be 64-byte aligned. */
612	IEMTLB DataTlb;
613	/** Instruction TLB.
614	* @remarks Must be 64-byte aligned. */
615	IEMTLB CodeTlb;
616
617	/** Pointer to instruction statistics for ring-0 context. */
618	R0PTRTYPE(PIEMINSTRSTATS) pStatsR0;
619	/** Ring-3 pointer to instruction statistics for non-ring-3 code. */
620	R3PTRTYPE(PIEMINSTRSTATS) pStatsCCR3;
621	/** Pointer to instruction statistics for ring-3 context. */
622	R3PTRTYPE(PIEMINSTRSTATS) pStatsR3;
623	} IEMCPU;
624	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
625	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
626	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
627	/** Pointer to the per-CPU IEM state. */
628	typedef IEMCPU *PIEMCPU;
629	/** Pointer to the const per-CPU IEM state. */
630	typedef IEMCPU const *PCIEMCPU;
631
632
633	/** @def IEM_GET_CTX
634	* Gets the guest CPU context for the calling EMT.
635	* @returns PCPUMCTX
636	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
637	*/
638	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
639
640	/** @def IEM_CTX_ASSERT
641	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
642	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
643	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
644	*/
645	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
646	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
647	(a_fExtrnMbz)))
648
649	/** @def IEM_CTX_IMPORT_RET
650	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
651	*
652	* Will call the keep to import the bits as needed.
653	*
654	* Returns on import failure.
655	*
656	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
657	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
658	*/
659	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
660	do { \
661	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
662	{ /* likely */ } \
663	else \
664	{ \
665	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
666	AssertRCReturn(rcCtxImport, rcCtxImport); \
667	} \
668	} while (0)
669
670	/** @def IEM_CTX_IMPORT_NORET
671	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
672	*
673	* Will call the keep to import the bits as needed.
674	*
675	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
676	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
677	*/
678	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
679	do { \
680	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
681	{ /* likely */ } \
682	else \
683	{ \
684	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
685	AssertLogRelRC(rcCtxImport); \
686	} \
687	} while (0)
688
689	/** @def IEM_CTX_IMPORT_JMP
690	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
691	*
692	* Will call the keep to import the bits as needed.
693	*
694	* Jumps on import failure.
695	*
696	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
697	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
698	*/
699	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
700	do { \
701	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
702	{ /* likely */ } \
703	else \
704	{ \
705	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
706	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
707	} \
708	} while (0)
709
710
711
712	/** Gets the current IEMTARGETCPU value.
713	* @returns IEMTARGETCPU value.
714	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
715	*/
716	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
717	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
718	#else
719	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
720	#endif
721
722	/** @def Gets the instruction length. */
723	#ifdef IEM_WITH_CODE_TLB
724	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
725	#else
726	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
727	#endif
728
729
730	/** @name IEM_ACCESS_XXX - Access details.
731	* @{ */
732	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
733	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
734	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
735	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
736	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
737	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
738	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
739	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
740	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
741	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
742	/** The writes are partial, so if initialize the bounce buffer with the
743	* orignal RAM content. */
744	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
745	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
746	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
747	/** Bounce buffer with ring-3 write pending, first page. */
748	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
749	/** Bounce buffer with ring-3 write pending, second page. */
750	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
751	/** Valid bit mask. */
752	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
753	/** Read+write data alias. */
754	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
755	/** Write data alias. */
756	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
757	/** Read data alias. */
758	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
759	/** Instruction fetch alias. */
760	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
761	/** Stack write alias. */
762	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
763	/** Stack read alias. */
764	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
765	/** Stack read+write alias. */
766	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
767	/** Read system table alias. */
768	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
769	/** Read+write system table alias. */
770	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
771	/** @} */
772
773	/** @name Prefix constants (IEMCPU::fPrefixes)
774	* @{ */
775	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
776	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
777	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
778	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
779	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
780	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
781	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
782
783	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
784	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
785	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
786
787	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
788	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
789	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
790
791	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
792	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
793	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
794	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
795	/** Mask with all the REX prefix flags.
796	* This is generally for use when needing to undo the REX prefixes when they
797	* are followed legacy prefixes and therefore does not immediately preceed
798	* the first opcode byte.
799	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
800	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
801
802	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
803	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
804	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
805	/** @} */
806
807	/** @name IEMOPFORM_XXX - Opcode forms
808	* @note These are ORed together with IEMOPHINT_XXX.
809	* @{ */
810	/** ModR/M: reg, r/m */
811	#define IEMOPFORM_RM 0
812	/** ModR/M: reg, r/m (register) */
813	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
814	/** ModR/M: reg, r/m (memory) */
815	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
816	/** ModR/M: r/m, reg */
817	#define IEMOPFORM_MR 1
818	/** ModR/M: r/m (register), reg */
819	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
820	/** ModR/M: r/m (memory), reg */
821	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
822	/** ModR/M: r/m only */
823	#define IEMOPFORM_M 2
824	/** ModR/M: r/m only (register). */
825	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
826	/** ModR/M: r/m only (memory). */
827	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
828	/** ModR/M: reg only */
829	#define IEMOPFORM_R 3
830
831	/** VEX+ModR/M: reg, r/m */
832	#define IEMOPFORM_VEX_RM 4
833	/** VEX+ModR/M: reg, r/m (register) */
834	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
835	/** VEX+ModR/M: reg, r/m (memory) */
836	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
837	/** VEX+ModR/M: r/m, reg */
838	#define IEMOPFORM_VEX_MR 5
839	/** VEX+ModR/M: r/m (register), reg */
840	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
841	/** VEX+ModR/M: r/m (memory), reg */
842	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
843	/** VEX+ModR/M: r/m only */
844	#define IEMOPFORM_VEX_M 6
845	/** VEX+ModR/M: r/m only (register). */
846	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
847	/** VEX+ModR/M: r/m only (memory). */
848	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
849	/** VEX+ModR/M: reg only */
850	#define IEMOPFORM_VEX_R 7
851	/** VEX+ModR/M: reg, vvvv, r/m */
852	#define IEMOPFORM_VEX_RVM 8
853	/** VEX+ModR/M: reg, vvvv, r/m (register). */
854	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
855	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
856	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
857	/** VEX+ModR/M: r/m, vvvv, reg */
858	#define IEMOPFORM_VEX_MVR 9
859	/** VEX+ModR/M: r/m, vvvv, reg (register) */
860	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
861	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
862	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
863
864	/** Fixed register instruction, no R/M. */
865	#define IEMOPFORM_FIXED 16
866
867	/** The r/m is a register. */
868	#define IEMOPFORM_MOD3 RT_BIT_32(8)
869	/** The r/m is a memory access. */
870	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
871	/** @} */
872
873	/** @name IEMOPHINT_XXX - Additional Opcode Hints
874	* @note These are ORed together with IEMOPFORM_XXX.
875	* @{ */
876	/** Ignores the operand size prefix (66h). */
877	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
878	/** Ignores REX.W (aka WIG). */
879	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
880	/** Both the operand size prefixes (66h + REX.W) are ignored. */
881	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
882	/** Allowed with the lock prefix. */
883	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
884	/** The VEX.L value is ignored (aka LIG). */
885	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
886	/** The VEX.L value must be zero (i.e. 128-bit width only). */
887	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
888
889	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
890	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
891	/** @} */
892
893	/**
894	* Possible hardware task switch sources.
895	*/
896	typedef enum IEMTASKSWITCH
897	{
898	/** Task switch caused by an interrupt/exception. */
899	IEMTASKSWITCH_INT_XCPT = 1,
900	/** Task switch caused by a far CALL. */
901	IEMTASKSWITCH_CALL,
902	/** Task switch caused by a far JMP. */
903	IEMTASKSWITCH_JUMP,
904	/** Task switch caused by an IRET. */
905	IEMTASKSWITCH_IRET
906	} IEMTASKSWITCH;
907	AssertCompileSize(IEMTASKSWITCH, 4);
908
909	/**
910	* Possible CrX load (write) sources.
911	*/
912	typedef enum IEMACCESSCRX
913	{
914	/** CrX access caused by 'mov crX' instruction. */
915	IEMACCESSCRX_MOV_CRX,
916	/** CrX (CR0) write caused by 'lmsw' instruction. */
917	IEMACCESSCRX_LMSW,
918	/** CrX (CR0) write caused by 'clts' instruction. */
919	IEMACCESSCRX_CLTS,
920	/** CrX (CR0) read caused by 'smsw' instruction. */
921	IEMACCESSCRX_SMSW
922	} IEMACCESSCRX;
923
924	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX
925	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
926	# endif
927
928	/**
929	* Indicates to the verifier that the given flag set is undefined.
930	*
931	* Can be invoked again to add more flags.
932	*
933	* This is a NOOP if the verifier isn't compiled in.
934	*
935	* @note We're temporarily keeping this until code is converted to new
936	* disassembler style opcode handling.
937	*/
938	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
939
940
941	/** @def IEM_DECL_IMPL_TYPE
942	* For typedef'ing an instruction implementation function.
943	*
944	* @param a_RetType The return type.
945	* @param a_Name The name of the type.
946	* @param a_ArgList The argument list enclosed in parentheses.
947	*/
948
949	/** @def IEM_DECL_IMPL_DEF
950	* For defining an instruction implementation function.
951	*
952	* @param a_RetType The return type.
953	* @param a_Name The name of the type.
954	* @param a_ArgList The argument list enclosed in parentheses.
955	*/
956
957	#if defined(__GNUC__) && defined(RT_ARCH_X86)
958	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
959	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
960	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
961	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
962
963	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
964	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
965	a_RetType (__fastcall a_Name) a_ArgList
966	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
967	a_RetType __fastcall a_Name a_ArgList
968
969	#else
970	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
971	a_RetType (VBOXCALL a_Name) a_ArgList
972	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
973	a_RetType VBOXCALL a_Name a_ArgList
974
975	#endif
976
977	/** @name Arithmetic assignment operations on bytes (binary).
978	* @{ */
979	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
980	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
981	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
982	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
983	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
984	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
985	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
986	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
987	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
988	/** @} */
989
990	/** @name Arithmetic assignment operations on words (binary).
991	* @{ */
992	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
993	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
994	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
995	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
996	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
997	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
998	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
999	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1000	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1001	/** @} */
1002
1003	/** @name Arithmetic assignment operations on double words (binary).
1004	* @{ */
1005	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1006	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1007	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1008	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1009	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1010	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1011	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1012	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1013	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1014	/** @} */
1015
1016	/** @name Arithmetic assignment operations on quad words (binary).
1017	* @{ */
1018	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1019	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1020	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1021	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1022	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1023	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1024	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1025	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1026	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1027	/** @} */
1028
1029	/** @name Compare operations (thrown in with the binary ops).
1030	* @{ */
1031	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1032	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1033	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1034	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1035	/** @} */
1036
1037	/** @name Test operations (thrown in with the binary ops).
1038	* @{ */
1039	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1040	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1041	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1042	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1043	/** @} */
1044
1045	/** @name Bit operations operations (thrown in with the binary ops).
1046	* @{ */
1047	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1048	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1049	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1050	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1051	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1052	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1053	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1054	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1055	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1056	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1057	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1058	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1059	/** @} */
1060
1061	/** @name Exchange memory with register operations.
1062	* @{ */
1063	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
1064	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
1065	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
1066	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
1067	/** @} */
1068
1069	/** @name Exchange and add operations.
1070	* @{ */
1071	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1072	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1073	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1074	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1075	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1076	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1077	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1078	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1079	/** @} */
1080
1081	/** @name Compare and exchange.
1082	* @{ */
1083	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1084	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1085	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1086	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1087	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1088	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1089	#ifdef RT_ARCH_X86
1090	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1091	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1092	#else
1093	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1094	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1095	#endif
1096	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1097	uint32_t *pEFlags));
1098	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1099	uint32_t *pEFlags));
1100	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1101	uint32_t *pEFlags));
1102	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1103	uint32_t *pEFlags));
1104	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1105	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1106	/** @} */
1107
1108	/** @name Memory ordering
1109	* @{ */
1110	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1111	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1112	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1113	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1114	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1115	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1116	/** @} */
1117
1118	/** @name Double precision shifts
1119	* @{ */
1120	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1121	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1122	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1123	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1124	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1125	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1126	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1127	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1128	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1129	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1130	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1131	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1132	/** @} */
1133
1134
1135	/** @name Bit search operations (thrown in with the binary ops).
1136	* @{ */
1137	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1138	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1139	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1140	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1141	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1142	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1143	/** @} */
1144
1145	/** @name Signed multiplication operations (thrown in with the binary ops).
1146	* @{ */
1147	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1148	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1149	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1150	/** @} */
1151
1152	/** @name Arithmetic assignment operations on bytes (unary).
1153	* @{ */
1154	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1155	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1156	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1157	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1158	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1159	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1160	/** @} */
1161
1162	/** @name Arithmetic assignment operations on words (unary).
1163	* @{ */
1164	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1165	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1166	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1167	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1168	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1169	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1170	/** @} */
1171
1172	/** @name Arithmetic assignment operations on double words (unary).
1173	* @{ */
1174	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1175	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1176	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1177	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1178	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1179	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1180	/** @} */
1181
1182	/** @name Arithmetic assignment operations on quad words (unary).
1183	* @{ */
1184	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1185	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1186	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1187	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1188	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1189	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1190	/** @} */
1191
1192
1193	/** @name Shift operations on bytes (Group 2).
1194	* @{ */
1195	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1196	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1197	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1198	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1199	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1200	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1201	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1202	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1203	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1204	/** @} */
1205
1206	/** @name Shift operations on words (Group 2).
1207	* @{ */
1208	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1209	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1210	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1211	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1212	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1213	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1214	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1215	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1216	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1217	/** @} */
1218
1219	/** @name Shift operations on double words (Group 2).
1220	* @{ */
1221	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1222	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1223	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1224	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1225	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1226	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1227	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1228	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1229	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1230	/** @} */
1231
1232	/** @name Shift operations on words (Group 2).
1233	* @{ */
1234	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1235	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1236	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1237	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1238	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1239	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1240	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1241	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1242	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1243	/** @} */
1244
1245	/** @name Multiplication and division operations.
1246	* @{ */
1247	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1248	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1249	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1250	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1251
1252	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1253	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1254	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1255	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1256
1257	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1258	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1259	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1260	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1261
1262	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1263	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1264	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1265	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1266	/** @} */
1267
1268	/** @name Byte Swap.
1269	* @{ */
1270	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1271	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1272	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1273	/** @} */
1274
1275	/** @name Misc.
1276	* @{ */
1277	FNIEMAIMPLBINU16 iemAImpl_arpl;
1278	/** @} */
1279
1280
1281	/** @name FPU operations taking a 32-bit float argument
1282	* @{ */
1283	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1284	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1285	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1286
1287	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1288	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1289	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1290
1291	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1292	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1293	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1294	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1295	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1296	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1297	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1298
1299	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1300	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1301	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1302	/** @} */
1303
1304	/** @name FPU operations taking a 64-bit float argument
1305	* @{ */
1306	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1307	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1308	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1309
1310	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1311	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1312	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1313	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1314	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1315	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1316
1317	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1318	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1319	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1320	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1321	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1322	/** @} */
1323
1324	/** @name FPU operations taking a 80-bit float argument
1325	* @{ */
1326	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1327	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1328	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1329	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1330	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1331	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1332	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1333	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1334	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1335	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1336	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1337	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1338
1339	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1340	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80;
1341	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1342
1343	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1344	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1345	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1346	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1347	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1348
1349	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1350	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1351	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1352	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1353	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1354
1355	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1356	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1357	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1358	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1359	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1360	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1361	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1362	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1363	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1364
1365	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1366	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1367	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1368	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1369
1370	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1371	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1372	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1373	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1374	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1375	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1376	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1377	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1378	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1379
1380	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1381	PCRTFLOAT80U pr80Val));
1382	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1383	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1384	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1385	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1386
1387	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1388	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1389	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1390
1391	/** @} */
1392
1393	/** @name FPU operations taking a 16-bit signed integer argument
1394	* @{ */
1395	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1396	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1397	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1398
1399	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1400	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1401	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1402	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1403	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1404	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1405
1406	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1407	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1408
1409	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1410	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1411	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1412	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1413	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1414	/** @} */
1415
1416	/** @name FPU operations taking a 32-bit signed integer argument
1417	* @{ */
1418	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1419	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1420	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1421
1422	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1423	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1424	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1425	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1426	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1427	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1428
1429	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1430	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1431
1432	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1433	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1434	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1435	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1436	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1437	/** @} */
1438
1439	/** @name FPU operations taking a 64-bit signed integer argument
1440	* @{ */
1441	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1442	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1443	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1444
1445	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1446	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1447	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1448	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1449	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1450	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1451
1452	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1453	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1454
1455	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1456	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1457	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1458	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1459	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1460	/** @} */
1461
1462
1463	/** Temporary type representing a 256-bit vector register. */
1464	typedef struct {uint64_t au64[4]; } IEMVMM256;
1465	/** Temporary type pointing to a 256-bit vector register. */
1466	typedef IEMVMM256 *PIEMVMM256;
1467	/** Temporary type pointing to a const 256-bit vector register. */
1468	typedef IEMVMM256 *PCIEMVMM256;
1469
1470
1471	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1472	* @{ */
1473	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1474	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1475	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1476	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1477	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1478	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1479	/** @} */
1480
1481	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1482	* @{ */
1483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1484	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1485	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1486	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1487	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1488	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1489	/** @} */
1490
1491	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1492	* @{ */
1493	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1494	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1495	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1496	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1497	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1498	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1499	/** @} */
1500
1501	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1502	* @{ */
1503	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1504	PCRTUINT128U pu128Src, uint8_t bEvil));
1505	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1506	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1507	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1508	/** @} */
1509
1510	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1511	* @{ */
1512	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1513	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1514	/** @} */
1515
1516	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1517	* @{ */
1518	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1519	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1520	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1521
1522	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1523	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1524	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1525	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1526
1527	/** @} */
1528
1529
1530	/** @name Function tables.
1531	* @{
1532	*/
1533
1534	/**
1535	* Function table for a binary operator providing implementation based on
1536	* operand size.
1537	*/
1538	typedef struct IEMOPBINSIZES
1539	{
1540	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1541	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1542	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1543	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1544	} IEMOPBINSIZES;
1545	/** Pointer to a binary operator function table. */
1546	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1547
1548
1549	/**
1550	* Function table for a unary operator providing implementation based on
1551	* operand size.
1552	*/
1553	typedef struct IEMOPUNARYSIZES
1554	{
1555	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1556	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1557	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1558	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1559	} IEMOPUNARYSIZES;
1560	/** Pointer to a unary operator function table. */
1561	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1562
1563
1564	/**
1565	* Function table for a shift operator providing implementation based on
1566	* operand size.
1567	*/
1568	typedef struct IEMOPSHIFTSIZES
1569	{
1570	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1571	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1572	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1573	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1574	} IEMOPSHIFTSIZES;
1575	/** Pointer to a shift operator function table. */
1576	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1577
1578
1579	/**
1580	* Function table for a multiplication or division operation.
1581	*/
1582	typedef struct IEMOPMULDIVSIZES
1583	{
1584	PFNIEMAIMPLMULDIVU8 pfnU8;
1585	PFNIEMAIMPLMULDIVU16 pfnU16;
1586	PFNIEMAIMPLMULDIVU32 pfnU32;
1587	PFNIEMAIMPLMULDIVU64 pfnU64;
1588	} IEMOPMULDIVSIZES;
1589	/** Pointer to a multiplication or division operation function table. */
1590	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1591
1592
1593	/**
1594	* Function table for a double precision shift operator providing implementation
1595	* based on operand size.
1596	*/
1597	typedef struct IEMOPSHIFTDBLSIZES
1598	{
1599	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1600	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1601	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1602	} IEMOPSHIFTDBLSIZES;
1603	/** Pointer to a double precision shift function table. */
1604	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1605
1606
1607	/**
1608	* Function table for media instruction taking two full sized media registers,
1609	* optionally the 2nd being a memory reference (only modifying the first op.)
1610	*/
1611	typedef struct IEMOPMEDIAF2
1612	{
1613	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1614	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1615	} IEMOPMEDIAF2;
1616	/** Pointer to a media operation function table for full sized ops. */
1617	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1618
1619	/**
1620	* Function table for media instruction taking taking one full and one lower
1621	* half media register.
1622	*/
1623	typedef struct IEMOPMEDIAF1L1
1624	{
1625	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1626	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1627	} IEMOPMEDIAF1L1;
1628	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1629	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1630
1631	/**
1632	* Function table for media instruction taking taking one full and one high half
1633	* media register.
1634	*/
1635	typedef struct IEMOPMEDIAF1H1
1636	{
1637	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1638	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1639	} IEMOPMEDIAF1H1;
1640	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1641	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1642
1643
1644	/** @} */
1645
1646
1647	/** @name C instruction implementations for anything slightly complicated.
1648	* @{ */
1649
1650	/**
1651	* For typedef'ing or declaring a C instruction implementation function taking
1652	* no extra arguments.
1653	*
1654	* @param a_Name The name of the type.
1655	*/
1656	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1657	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1658	/**
1659	* For defining a C instruction implementation function taking no extra
1660	* arguments.
1661	*
1662	* @param a_Name The name of the function
1663	*/
1664	# define IEM_CIMPL_DEF_0(a_Name) \
1665	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1666	/**
1667	* For calling a C instruction implementation function taking no extra
1668	* arguments.
1669	*
1670	* This special call macro adds default arguments to the call and allow us to
1671	* change these later.
1672	*
1673	* @param a_fn The name of the function.
1674	*/
1675	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1676
1677	/**
1678	* For typedef'ing or declaring a C instruction implementation function taking
1679	* one extra argument.
1680	*
1681	* @param a_Name The name of the type.
1682	* @param a_Type0 The argument type.
1683	* @param a_Arg0 The argument name.
1684	*/
1685	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1686	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1687	/**
1688	* For defining a C instruction implementation function taking one extra
1689	* argument.
1690	*
1691	* @param a_Name The name of the function
1692	* @param a_Type0 The argument type.
1693	* @param a_Arg0 The argument name.
1694	*/
1695	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1696	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1697	/**
1698	* For calling a C instruction implementation function taking one extra
1699	* argument.
1700	*
1701	* This special call macro adds default arguments to the call and allow us to
1702	* change these later.
1703	*
1704	* @param a_fn The name of the function.
1705	* @param a0 The name of the 1st argument.
1706	*/
1707	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1708
1709	/**
1710	* For typedef'ing or declaring a C instruction implementation function taking
1711	* two extra arguments.
1712	*
1713	* @param a_Name The name of the type.
1714	* @param a_Type0 The type of the 1st argument
1715	* @param a_Arg0 The name of the 1st argument.
1716	* @param a_Type1 The type of the 2nd argument.
1717	* @param a_Arg1 The name of the 2nd argument.
1718	*/
1719	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1720	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1721	/**
1722	* For defining a C instruction implementation function taking two extra
1723	* arguments.
1724	*
1725	* @param a_Name The name of the function.
1726	* @param a_Type0 The type of the 1st argument
1727	* @param a_Arg0 The name of the 1st argument.
1728	* @param a_Type1 The type of the 2nd argument.
1729	* @param a_Arg1 The name of the 2nd argument.
1730	*/
1731	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1732	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1733	/**
1734	* For calling a C instruction implementation function taking two extra
1735	* arguments.
1736	*
1737	* This special call macro adds default arguments to the call and allow us to
1738	* change these later.
1739	*
1740	* @param a_fn The name of the function.
1741	* @param a0 The name of the 1st argument.
1742	* @param a1 The name of the 2nd argument.
1743	*/
1744	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1745
1746	/**
1747	* For typedef'ing or declaring a C instruction implementation function taking
1748	* three extra arguments.
1749	*
1750	* @param a_Name The name of the type.
1751	* @param a_Type0 The type of the 1st argument
1752	* @param a_Arg0 The name of the 1st argument.
1753	* @param a_Type1 The type of the 2nd argument.
1754	* @param a_Arg1 The name of the 2nd argument.
1755	* @param a_Type2 The type of the 3rd argument.
1756	* @param a_Arg2 The name of the 3rd argument.
1757	*/
1758	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1759	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1760	/**
1761	* For defining a C instruction implementation function taking three extra
1762	* arguments.
1763	*
1764	* @param a_Name The name of the function.
1765	* @param a_Type0 The type of the 1st argument
1766	* @param a_Arg0 The name of the 1st argument.
1767	* @param a_Type1 The type of the 2nd argument.
1768	* @param a_Arg1 The name of the 2nd argument.
1769	* @param a_Type2 The type of the 3rd argument.
1770	* @param a_Arg2 The name of the 3rd argument.
1771	*/
1772	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1773	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1774	/**
1775	* For calling a C instruction implementation function taking three extra
1776	* arguments.
1777	*
1778	* This special call macro adds default arguments to the call and allow us to
1779	* change these later.
1780	*
1781	* @param a_fn The name of the function.
1782	* @param a0 The name of the 1st argument.
1783	* @param a1 The name of the 2nd argument.
1784	* @param a2 The name of the 3rd argument.
1785	*/
1786	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1787
1788
1789	/**
1790	* For typedef'ing or declaring a C instruction implementation function taking
1791	* four extra arguments.
1792	*
1793	* @param a_Name The name of the type.
1794	* @param a_Type0 The type of the 1st argument
1795	* @param a_Arg0 The name of the 1st argument.
1796	* @param a_Type1 The type of the 2nd argument.
1797	* @param a_Arg1 The name of the 2nd argument.
1798	* @param a_Type2 The type of the 3rd argument.
1799	* @param a_Arg2 The name of the 3rd argument.
1800	* @param a_Type3 The type of the 4th argument.
1801	* @param a_Arg3 The name of the 4th argument.
1802	*/
1803	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1804	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1805	/**
1806	* For defining a C instruction implementation function taking four extra
1807	* arguments.
1808	*
1809	* @param a_Name The name of the function.
1810	* @param a_Type0 The type of the 1st argument
1811	* @param a_Arg0 The name of the 1st argument.
1812	* @param a_Type1 The type of the 2nd argument.
1813	* @param a_Arg1 The name of the 2nd argument.
1814	* @param a_Type2 The type of the 3rd argument.
1815	* @param a_Arg2 The name of the 3rd argument.
1816	* @param a_Type3 The type of the 4th argument.
1817	* @param a_Arg3 The name of the 4th argument.
1818	*/
1819	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1820	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1821	a_Type2 a_Arg2, a_Type3 a_Arg3))
1822	/**
1823	* For calling a C instruction implementation function taking four extra
1824	* arguments.
1825	*
1826	* This special call macro adds default arguments to the call and allow us to
1827	* change these later.
1828	*
1829	* @param a_fn The name of the function.
1830	* @param a0 The name of the 1st argument.
1831	* @param a1 The name of the 2nd argument.
1832	* @param a2 The name of the 3rd argument.
1833	* @param a3 The name of the 4th argument.
1834	*/
1835	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1836
1837
1838	/**
1839	* For typedef'ing or declaring a C instruction implementation function taking
1840	* five extra arguments.
1841	*
1842	* @param a_Name The name of the type.
1843	* @param a_Type0 The type of the 1st argument
1844	* @param a_Arg0 The name of the 1st argument.
1845	* @param a_Type1 The type of the 2nd argument.
1846	* @param a_Arg1 The name of the 2nd argument.
1847	* @param a_Type2 The type of the 3rd argument.
1848	* @param a_Arg2 The name of the 3rd argument.
1849	* @param a_Type3 The type of the 4th argument.
1850	* @param a_Arg3 The name of the 4th argument.
1851	* @param a_Type4 The type of the 5th argument.
1852	* @param a_Arg4 The name of the 5th argument.
1853	*/
1854	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1855	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
1856	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1857	a_Type3 a_Arg3, a_Type4 a_Arg4))
1858	/**
1859	* For defining a C instruction implementation function taking five extra
1860	* arguments.
1861	*
1862	* @param a_Name The name of the function.
1863	* @param a_Type0 The type of the 1st argument
1864	* @param a_Arg0 The name of the 1st argument.
1865	* @param a_Type1 The type of the 2nd argument.
1866	* @param a_Arg1 The name of the 2nd argument.
1867	* @param a_Type2 The type of the 3rd argument.
1868	* @param a_Arg2 The name of the 3rd argument.
1869	* @param a_Type3 The type of the 4th argument.
1870	* @param a_Arg3 The name of the 4th argument.
1871	* @param a_Type4 The type of the 5th argument.
1872	* @param a_Arg4 The name of the 5th argument.
1873	*/
1874	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1875	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
1876	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1877	a_Type3 a_Arg3, a_Type4 a_Arg4))
1878	/**
1879	* For calling a C instruction implementation function taking five extra
1880	* arguments.
1881	*
1882	* This special call macro adds default arguments to the call and allow us to
1883	* change these later.
1884	*
1885	* @param a_fn The name of the function.
1886	* @param a0 The name of the 1st argument.
1887	* @param a1 The name of the 2nd argument.
1888	* @param a2 The name of the 3rd argument.
1889	* @param a3 The name of the 4th argument.
1890	* @param a4 The name of the 5th argument.
1891	*/
1892	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1893
1894	/** @} */
1895
1896
1897	/** @} */
1898
1899	RT_C_DECLS_END
1900
1901	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
1902

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 80651

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