VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMInternal-armv8.h@ 100140

Last change on this file since 100140 was 100072, checked in by vboxsync, 18 months ago

VMM/IEM: Reworked all the IEM_MC_CALL/DEFER_TO_CIMPL macros to include some clues about what they may end up doing. The IEM_MC_DEFER_TO_CIMPL_X macros now returns implictly and is renamed to IEM_MC_DEFER_TO_CIMPL_X_RET - this will ease adding more code/whatever to follow the return from the call when recompiling and such. Also fixed buggy POP CS in 8086 mode. bugref:10369
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 58.5 KB
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1/* $Id: IEMInternal-armv8.h 100072 2023-06-05 15:17:42Z vboxsync $ */
2/** @file
3 * IEM - Internal header file, ARMv8 variant.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMInternal_armv8_h
29#define VMM_INCLUDED_SRC_include_IEMInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/vmm/cpum.h>
35#include <VBox/vmm/iem.h>
36#include <VBox/vmm/pgm.h>
37#include <VBox/vmm/stam.h>
38#include <VBox/param.h>
39
40#include <iprt/setjmp-without-sigmask.h>
41
42
43RT_C_DECLS_BEGIN
44
45
46/** @defgroup grp_iem_int Internals
47 * @ingroup grp_iem
48 * @internal
49 * @{
50 */
51
52/** For expanding symbol in slickedit and other products tagging and
53 * crossreferencing IEM symbols. */
54#ifndef IEM_STATIC
55# define IEM_STATIC static
56#endif
57
58/** @def IEM_WITH_SETJMP
59 * Enables alternative status code handling using setjmps.
60 *
61 * This adds a bit of expense via the setjmp() call since it saves all the
62 * non-volatile registers. However, it eliminates return code checks and allows
63 * for more optimal return value passing (return regs instead of stack buffer).
64 */
65#if defined(DOXYGEN_RUNNING) || defined(RT_OS_WINDOWS) || 1
66# define IEM_WITH_SETJMP
67#endif
68
69/** @def IEM_WITH_THROW_CATCH
70 * Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71 * mode code when IEM_WITH_SETJMP is in effect.
72 *
73 * With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74 * setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
75 * result value improving by more than 1%. (Best out of three.)
76 *
77 * With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
78 * setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
79 * the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
80 * Linux, but it should be quite a bit faster for normal code.
81 */
82#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) || defined(_MSC_VER))) \
83 || defined(DOXYGEN_RUNNING)
84# define IEM_WITH_THROW_CATCH
85#endif
86
87/** @def IEM_DO_LONGJMP
88 *
89 * Wrapper around longjmp / throw.
90 *
91 * @param a_pVCpu The CPU handle.
92 * @param a_rc The status code jump back with / throw.
93 */
94#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
95# ifdef IEM_WITH_THROW_CATCH
96# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
97# else
98# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
99# endif
100#endif
101
102/** For use with IEM function that may do a longjmp (when enabled).
103 *
104 * Visual C++ has trouble longjmp'ing from/over functions with the noexcept
105 * attribute. So, we indicate that function that may be part of a longjmp may
106 * throw "exceptions" and that the compiler should definitely not generate and
107 * std::terminate calling unwind code.
108 *
109 * Here is one example of this ending in std::terminate:
110 * @code{.txt}
11100 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
11201 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
11302 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
11403 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
11504 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
11605 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
11706 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
11807 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
11908 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
12009 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
1210a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
1220b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
1230c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
1240d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
1250e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
1260f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
12710 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
128 @endcode
129 *
130 * @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
131 */
132#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) || defined(IEM_WITH_THROW_CATCH))
133# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
134#else
135# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
136#endif
137
138/** @def IEM_CFG_TARGET_CPU
139 * The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
140 *
141 * By default we allow this to be configured by the user via the
142 * CPUM/GuestCpuName config string, but this comes at a slight cost during
143 * decoding. So, for applications of this code where there is no need to
144 * be dynamic wrt target CPU, just modify this define.
145 */
146#if !defined(IEM_CFG_TARGET_CPU) || defined(DOXYGEN_RUNNING)
147# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
148#endif
149
150//#define IEM_WITH_CODE_TLB // - work in progress
151//#define IEM_WITH_DATA_TLB // - work in progress
152
153
154//#define IEM_LOG_MEMORY_WRITES
155
156#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
157/** Instruction statistics. */
158typedef struct IEMINSTRSTATS
159{
160# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
161/** @todo # include "IEMInstructionStatisticsTmpl.h" */
162 uint8_t bDummy;
163# undef IEM_DO_INSTR_STAT
164} IEMINSTRSTATS;
165#else
166struct IEMINSTRSTATS;
167typedef struct IEMINSTRSTATS IEMINSTRSTATS;
168#endif
169/** Pointer to IEM instruction statistics. */
170typedef IEMINSTRSTATS *PIEMINSTRSTATS;
171
172
173/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
174 * @{ */
175#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /**< Native result; Intel EFLAGS when on non-x86 hosts. */
176#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 1 /**< Reserved/dummy entry slot that's the same as 0. */
177#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 1 /**< For masking the index before use. */
178/** Selects the right variant from a_aArray.
179 * pVCpu is implicit in the caller context. */
180#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
181 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
182/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
183 * be used because the host CPU does not support the operation. */
184#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
185 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
186/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
187 * array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
188 * into the two.
189 * @sa IEM_SELECT_NATIVE_OR_FALLBACK */
190#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
191# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
192 (a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
193#else
194# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
195 (a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
196#endif
197/** @} */
198
199/**
200 * Branch types.
201 */
202typedef enum IEMBRANCH
203{
204 IEMBRANCH_JUMP = 1,
205 IEMBRANCH_CALL,
206 IEMBRANCH_TRAP,
207 IEMBRANCH_SOFTWARE_INT,
208 IEMBRANCH_HARDWARE_INT
209} IEMBRANCH;
210AssertCompileSize(IEMBRANCH, 4);
211
212
213/**
214 * INT instruction types.
215 */
216typedef enum IEMINT
217{
218 /** INT n instruction (opcode 0xcd imm). */
219 IEMINT_INTN = 0,
220 /** Single byte INT3 instruction (opcode 0xcc). */
221 IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
222 /** Single byte INTO instruction (opcode 0xce). */
223 IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
224 /** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
225 IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
226} IEMINT;
227AssertCompileSize(IEMINT, 4);
228
229
230typedef struct IEMTLBENTRY
231{
232 /** The TLB entry tag.
233 * Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
234 * is ASSUMING a virtual address width of 48 bits.
235 *
236 * Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
237 *
238 * The TLB lookup code uses the current TLB revision, which won't ever be zero,
239 * enabling an extremely cheap TLB invalidation most of the time. When the TLB
240 * revision wraps around though, the tags needs to be zeroed.
241 *
242 * @note Try use SHRD instruction? After seeing
243 * https://gmplib.org/~tege/x86-timing.pdf, maybe not.
244 *
245 * @todo This will need to be reorganized for 57-bit wide virtual address and
246 * PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
247 * have to move the TLB entry versioning entirely to the
248 * fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
249 * 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
250 * consumed by PCID and ASID (12 + 6 = 18).
251 */
252 uint64_t uTag;
253 /** Access flags and physical TLB revision.
254 *
255 * - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
256 * - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
257 * - Bit 2 - page tables - not user (complemented X86_PTE_US).
258 * - Bit 3 - pgm phys/virt - not directly writable.
259 * - Bit 4 - pgm phys page - not directly readable.
260 * - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
261 * - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
262 * - Bit 7 - tlb entry - pMappingR3 member not valid.
263 * - Bits 63 thru 8 are used for the physical TLB revision number.
264 *
265 * We're using complemented bit meanings here because it makes it easy to check
266 * whether special action is required. For instance a user mode write access
267 * would do a "TEST fFlags, (X86_PTE_RW | X86_PTE_US | X86_PTE_D)" and a
268 * non-zero result would mean special handling needed because either it wasn't
269 * writable, or it wasn't user, or the page wasn't dirty. A user mode read
270 * access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
271 * need to check any PTE flag.
272 */
273 uint64_t fFlagsAndPhysRev;
274 /** The guest physical page address. */
275 uint64_t GCPhys;
276 /** Pointer to the ring-3 mapping. */
277 R3PTRTYPE(uint8_t *) pbMappingR3;
278#if HC_ARCH_BITS == 32
279 uint32_t u32Padding1;
280#endif
281} IEMTLBENTRY;
282AssertCompileSize(IEMTLBENTRY, 32);
283/** Pointer to an IEM TLB entry. */
284typedef IEMTLBENTRY *PIEMTLBENTRY;
285
286/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
287 * @{ */
288#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /**< Page tables: Not executable. */
289#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /**< Page tables: Not writable. */
290#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /**< Page tables: Not user accessible (supervisor only). */
291#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /**< Phys page: Not writable (access handler, ROM, whatever). */
292#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /**< Phys page: Not readable (MMIO / access handler, ROM) */
293#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /**< Phys tables: Not accessed (need to be marked accessed). */
294#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /**< Page tables: Not dirty (needs to be made dirty on write). */
295#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /**< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. */
296#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /**< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
297#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
298/** @} */
299
300
301/**
302 * An IEM TLB.
303 *
304 * We've got two of these, one for data and one for instructions.
305 */
306typedef struct IEMTLB
307{
308 /** The TLB entries.
309 * We've choosen 256 because that way we can obtain the result directly from a
310 * 8-bit register without an additional AND instruction. */
311 IEMTLBENTRY aEntries[256];
312 /** The TLB revision.
313 * This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
314 * by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
315 * the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
316 * (The revision zero indicates an invalid TLB entry.)
317 *
318 * The initial value is choosen to cause an early wraparound. */
319 uint64_t uTlbRevision;
320 /** The TLB physical address revision - shadow of PGM variable.
321 *
322 * This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
323 * incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
324 * a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
325 * as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
326 *
327 * The initial value is choosen to cause an early wraparound. */
328 uint64_t volatile uTlbPhysRev;
329
330 /* Statistics: */
331
332 /** TLB hits (VBOX_WITH_STATISTICS only). */
333 uint64_t cTlbHits;
334 /** TLB misses. */
335 uint32_t cTlbMisses;
336 /** Slow read path. */
337 uint32_t cTlbSlowReadPath;
338#if 0
339 /** TLB misses because of tag mismatch. */
340 uint32_t cTlbMissesTag;
341 /** TLB misses because of virtual access violation. */
342 uint32_t cTlbMissesVirtAccess;
343 /** TLB misses because of dirty bit. */
344 uint32_t cTlbMissesDirty;
345 /** TLB misses because of MMIO */
346 uint32_t cTlbMissesMmio;
347 /** TLB misses because of write access handlers. */
348 uint32_t cTlbMissesWriteHandler;
349 /** TLB misses because no r3(/r0) mapping. */
350 uint32_t cTlbMissesMapping;
351#endif
352 /** Alignment padding. */
353 uint32_t au32Padding[3+5];
354} IEMTLB;
355AssertCompileSizeAlignment(IEMTLB, 64);
356/** IEMTLB::uTlbRevision increment. */
357#define IEMTLB_REVISION_INCR RT_BIT_64(36)
358/** IEMTLB::uTlbRevision mask. */
359#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
360/** IEMTLB::uTlbPhysRev increment.
361 * @sa IEMTLBE_F_PHYS_REV */
362#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
363/**
364 * Calculates the TLB tag for a virtual address.
365 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
366 * @param a_pTlb The TLB.
367 * @param a_GCPtr The virtual address.
368 */
369#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) | (a_pTlb)->uTlbRevision )
370/**
371 * Calculates the TLB tag for a virtual address but without TLB revision.
372 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
373 * @param a_GCPtr The virtual address.
374 */
375#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
376/**
377 * Converts a TLB tag value into a TLB index.
378 * @returns Index into IEMTLB::aEntries.
379 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
380 */
381#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
382/**
383 * Converts a TLB tag value into a TLB index.
384 * @returns Index into IEMTLB::aEntries.
385 * @param a_pTlb The TLB.
386 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
387 */
388#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
389
390
391/**
392 * The per-CPU IEM state.
393 *
394 * @todo This is just a STUB currently!
395 */
396typedef struct IEMCPU
397{
398 /** Info status code that needs to be propagated to the IEM caller.
399 * This cannot be passed internally, as it would complicate all success
400 * checks within the interpreter making the code larger and almost impossible
401 * to get right. Instead, we'll store status codes to pass on here. Each
402 * source of these codes will perform appropriate sanity checks. */
403 int32_t rcPassUp; /* 0x00 */
404
405 /** The current CPU execution mode (CS). */
406 IEMMODE enmCpuMode; /* 0x04 */
407 /** The Exception Level (EL). */
408 uint8_t uEl; /* 0x05 */
409
410 /** Whether to bypass access handlers or not. */
411 bool fBypassHandlers : 1; /* 0x06.0 */
412 /** Whether there are pending hardware instruction breakpoints. */
413 bool fPendingInstructionBreakpoints : 1; /* 0x06.2 */
414 /** Whether there are pending hardware data breakpoints. */
415 bool fPendingDataBreakpoints : 1; /* 0x06.3 */
416
417 /* Unused/padding */
418 bool fUnused; /* 0x07 */
419
420 /** @name Decoder state.
421 * @{ */
422#ifndef IEM_WITH_OPAQUE_DECODER_STATE
423 /** The current instruction being executed. */
424 uint32_t u32Insn;
425 uint8_t abOpaqueDecoder[0x48 - 0x4 - 0x8];
426#else /* IEM_WITH_OPAQUE_DECODER_STATE */
427 uint8_t abOpaqueDecoder[0x48 - 0x8];
428#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
429 /** @} */
430
431
432 /** The flags of the current exception / interrupt. */
433 uint32_t fCurXcpt; /* 0x48, 0x48 */
434 /** The current exception / interrupt. */
435 uint8_t uCurXcpt;
436 /** Exception / interrupt recursion depth. */
437 int8_t cXcptRecursions;
438
439 /** The number of active guest memory mappings. */
440 uint8_t cActiveMappings;
441 /** The next unused mapping index. */
442 uint8_t iNextMapping;
443 /** Records for tracking guest memory mappings. */
444 struct
445 {
446 /** The address of the mapped bytes. */
447 void *pv;
448 /** The access flags (IEM_ACCESS_XXX).
449 * IEM_ACCESS_INVALID if the entry is unused. */
450 uint32_t fAccess;
451#if HC_ARCH_BITS == 64
452 uint32_t u32Alignment4; /**< Alignment padding. */
453#endif
454 } aMemMappings[3];
455
456 /** Locking records for the mapped memory. */
457 union
458 {
459 PGMPAGEMAPLOCK Lock;
460 uint64_t au64Padding[2];
461 } aMemMappingLocks[3];
462
463 /** Bounce buffer info.
464 * This runs in parallel to aMemMappings. */
465 struct
466 {
467 /** The physical address of the first byte. */
468 RTGCPHYS GCPhysFirst;
469 /** The physical address of the second page. */
470 RTGCPHYS GCPhysSecond;
471 /** The number of bytes in the first page. */
472 uint16_t cbFirst;
473 /** The number of bytes in the second page. */
474 uint16_t cbSecond;
475 /** Whether it's unassigned memory. */
476 bool fUnassigned;
477 /** Explicit alignment padding. */
478 bool afAlignment5[3];
479 } aMemBbMappings[3];
480
481 /* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
482 uint64_t abAlignment7[1];
483
484 /** Bounce buffer storage.
485 * This runs in parallel to aMemMappings and aMemBbMappings. */
486 struct
487 {
488 uint8_t ab[512];
489 } aBounceBuffers[3];
490
491
492 /** Pointer set jump buffer - ring-3 context. */
493 R3PTRTYPE(jmp_buf *) pJmpBufR3;
494
495 /** The error code for the current exception / interrupt. */
496 uint32_t uCurXcptErr;
497
498 /** @name Statistics
499 * @{ */
500 /** The number of instructions we've executed. */
501 uint32_t cInstructions;
502 /** The number of potential exits. */
503 uint32_t cPotentialExits;
504 /** The number of bytes data or stack written (mostly for IEMExecOneEx).
505 * This may contain uncommitted writes. */
506 uint32_t cbWritten;
507 /** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
508 uint32_t cRetInstrNotImplemented;
509 /** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
510 uint32_t cRetAspectNotImplemented;
511 /** Counts informational statuses returned (other than VINF_SUCCESS). */
512 uint32_t cRetInfStatuses;
513 /** Counts other error statuses returned. */
514 uint32_t cRetErrStatuses;
515 /** Number of times rcPassUp has been used. */
516 uint32_t cRetPassUpStatus;
517 /** Number of times RZ left with instruction commit pending for ring-3. */
518 uint32_t cPendingCommit;
519 /** Number of long jumps. */
520 uint32_t cLongJumps;
521 /** @} */
522
523 /** @name Target CPU information.
524 * @{ */
525#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
526 /** The target CPU. */
527 uint8_t uTargetCpu;
528#else
529 uint8_t bTargetCpuPadding;
530#endif
531 /** For selecting assembly works matching the target CPU EFLAGS behaviour, see
532 * IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
533 * native host support and the 2nd for when there is.
534 *
535 * The two values are typically indexed by a g_CpumHostFeatures bit.
536 *
537 * This is for instance used for the BSF & BSR instructions where AMD and
538 * Intel CPUs produce different EFLAGS. */
539 uint8_t aidxTargetCpuEflFlavour[2];
540
541 uint8_t bPadding;
542
543 /** The CPU vendor. */
544 CPUMCPUVENDOR enmCpuVendor;
545 /** @} */
546
547 /** @name Host CPU information.
548 * @{ */
549 /** The CPU vendor. */
550 CPUMCPUVENDOR enmHostCpuVendor;
551 /** @} */
552
553 /** Data TLB.
554 * @remarks Must be 64-byte aligned. */
555 IEMTLB DataTlb;
556 /** Instruction TLB.
557 * @remarks Must be 64-byte aligned. */
558 IEMTLB CodeTlb;
559
560 /** Exception statistics. */
561 STAMCOUNTER aStatXcpts[32];
562 /** Interrupt statistics. */
563 uint32_t aStatInts[256];
564
565#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
566 /** Instruction statistics for ring-3. */
567 IEMINSTRSTATS StatsR3;
568#endif
569} IEMCPU;
570AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
571AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
572AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
573AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
574AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
575AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
576AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
577
578/** Pointer to the per-CPU IEM state. */
579typedef IEMCPU *PIEMCPU;
580/** Pointer to the const per-CPU IEM state. */
581typedef IEMCPU const *PCIEMCPU;
582
583
584/** @def IEM_GET_CTX
585 * Gets the guest CPU context for the calling EMT.
586 * @returns PCPUMCTX
587 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
588 */
589#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
590
591/** @def IEM_CTX_ASSERT
592 * Asserts that the @a a_fExtrnMbz is present in the CPU context.
593 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
594 * @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
595 */
596#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
597 ("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
598 (a_fExtrnMbz)))
599
600/** @def IEM_CTX_IMPORT_RET
601 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
602 *
603 * Will call the keep to import the bits as needed.
604 *
605 * Returns on import failure.
606 *
607 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
608 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
609 */
610#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
611 do { \
612 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
613 { /* likely */ } \
614 else \
615 { \
616 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
617 AssertRCReturn(rcCtxImport, rcCtxImport); \
618 } \
619 } while (0)
620
621/** @def IEM_CTX_IMPORT_NORET
622 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
623 *
624 * Will call the keep to import the bits as needed.
625 *
626 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
627 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
628 */
629#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
630 do { \
631 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
632 { /* likely */ } \
633 else \
634 { \
635 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
636 AssertLogRelRC(rcCtxImport); \
637 } \
638 } while (0)
639
640/** @def IEM_CTX_IMPORT_JMP
641 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
642 *
643 * Will call the keep to import the bits as needed.
644 *
645 * Jumps on import failure.
646 *
647 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
648 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
649 */
650#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
651 do { \
652 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
653 { /* likely */ } \
654 else \
655 { \
656 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
657 AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
658 } \
659 } while (0)
660
661
662
663/** @def IEM_GET_TARGET_CPU
664 * Gets the current IEMTARGETCPU value.
665 * @returns IEMTARGETCPU value.
666 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
667 */
668#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
669# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
670#else
671# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
672#endif
673
674/** @def IEM_GET_INSTR_LEN
675 * Gets the instruction length. */
676/** @todo Thumb mode. */
677#ifdef IEM_WITH_CODE_TLB
678# define IEM_GET_INSTR_LEN(a_pVCpu) (sizeof(uint32_t))
679#else
680# define IEM_GET_INSTR_LEN(a_pVCpu) (sizeof(uint32_t))
681#endif
682
683
684/**
685 * Shared per-VM IEM data.
686 */
687typedef struct IEM
688{
689 uint8_t bDummy;
690} IEM;
691
692
693
694/** @name IEM_ACCESS_XXX - Access details.
695 * @{ */
696#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
697#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
698#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
699#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
700#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
701#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
702#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
703#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
704#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
705#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
706/** The writes are partial, so if initialize the bounce buffer with the
707 * orignal RAM content. */
708#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
709/** Used in aMemMappings to indicate that the entry is bounce buffered. */
710#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
711/** Bounce buffer with ring-3 write pending, first page. */
712#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
713/** Bounce buffer with ring-3 write pending, second page. */
714#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
715/** Not locked, accessed via the TLB. */
716#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
717/** Valid bit mask. */
718#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
719/** Shift count for the TLB flags (upper word). */
720#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
721
722/** Read+write data alias. */
723#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
724/** Write data alias. */
725#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
726/** Read data alias. */
727#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA)
728/** Instruction fetch alias. */
729#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC | IEM_ACCESS_WHAT_CODE)
730/** Stack write alias. */
731#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
732/** Stack read alias. */
733#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_STACK)
734/** Stack read+write alias. */
735#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
736/** Read system table alias. */
737#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_SYS)
738/** Read+write system table alias. */
739#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_SYS)
740/** @} */
741
742/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
743#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
744
745/** @def IEM_DECL_IMPL_TYPE
746 * For typedef'ing an instruction implementation function.
747 *
748 * @param a_RetType The return type.
749 * @param a_Name The name of the type.
750 * @param a_ArgList The argument list enclosed in parentheses.
751 */
752
753/** @def IEM_DECL_IMPL_DEF
754 * For defining an instruction implementation function.
755 *
756 * @param a_RetType The return type.
757 * @param a_Name The name of the type.
758 * @param a_ArgList The argument list enclosed in parentheses.
759 */
760
761#if __cplusplus >= 201700 /* P0012R1 support */
762# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
763 a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
764# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
765 a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
766# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
767 a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
768
769#else
770# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
771 a_RetType (VBOXCALL a_Name) a_ArgList
772# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
773 a_RetType VBOXCALL a_Name a_ArgList
774# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
775 a_RetType VBOXCALL a_Name a_ArgList
776
777#endif
778
779/** @name C instruction implementations for anything slightly complicated.
780 * @{ */
781
782/**
783 * For typedef'ing or declaring a C instruction implementation function taking
784 * no extra arguments.
785 *
786 * @param a_Name The name of the type.
787 */
788# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
789 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
790/**
791 * For defining a C instruction implementation function taking no extra
792 * arguments.
793 *
794 * @param a_Name The name of the function
795 */
796# define IEM_CIMPL_DEF_0(a_Name) \
797 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
798/**
799 * Prototype version of IEM_CIMPL_DEF_0.
800 */
801# define IEM_CIMPL_PROTO_0(a_Name) \
802 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
803/**
804 * For calling a C instruction implementation function taking no extra
805 * arguments.
806 *
807 * This special call macro adds default arguments to the call and allow us to
808 * change these later.
809 *
810 * @param a_fn The name of the function.
811 */
812# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
813
814/**
815 * For typedef'ing or declaring a C instruction implementation function taking
816 * one extra argument.
817 *
818 * @param a_Name The name of the type.
819 * @param a_Type0 The argument type.
820 * @param a_Arg0 The argument name.
821 */
822# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
823 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
824/**
825 * For defining a C instruction implementation function taking one extra
826 * argument.
827 *
828 * @param a_Name The name of the function
829 * @param a_Type0 The argument type.
830 * @param a_Arg0 The argument name.
831 */
832# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
833 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
834/**
835 * Prototype version of IEM_CIMPL_DEF_1.
836 */
837# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
838 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
839/**
840 * For calling a C instruction implementation function taking one extra
841 * argument.
842 *
843 * This special call macro adds default arguments to the call and allow us to
844 * change these later.
845 *
846 * @param a_fn The name of the function.
847 * @param a0 The name of the 1st argument.
848 */
849# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
850
851/**
852 * For typedef'ing or declaring a C instruction implementation function taking
853 * two extra arguments.
854 *
855 * @param a_Name The name of the type.
856 * @param a_Type0 The type of the 1st argument
857 * @param a_Arg0 The name of the 1st argument.
858 * @param a_Type1 The type of the 2nd argument.
859 * @param a_Arg1 The name of the 2nd argument.
860 */
861# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
862 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
863/**
864 * For defining a C instruction implementation function taking two extra
865 * arguments.
866 *
867 * @param a_Name The name of the function.
868 * @param a_Type0 The type of the 1st argument
869 * @param a_Arg0 The name of the 1st argument.
870 * @param a_Type1 The type of the 2nd argument.
871 * @param a_Arg1 The name of the 2nd argument.
872 */
873# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
874 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
875/**
876 * Prototype version of IEM_CIMPL_DEF_2.
877 */
878# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
879 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
880/**
881 * For calling a C instruction implementation function taking two extra
882 * arguments.
883 *
884 * This special call macro adds default arguments to the call and allow us to
885 * change these later.
886 *
887 * @param a_fn The name of the function.
888 * @param a0 The name of the 1st argument.
889 * @param a1 The name of the 2nd argument.
890 */
891# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
892
893/**
894 * For typedef'ing or declaring a C instruction implementation function taking
895 * three extra arguments.
896 *
897 * @param a_Name The name of the type.
898 * @param a_Type0 The type of the 1st argument
899 * @param a_Arg0 The name of the 1st argument.
900 * @param a_Type1 The type of the 2nd argument.
901 * @param a_Arg1 The name of the 2nd argument.
902 * @param a_Type2 The type of the 3rd argument.
903 * @param a_Arg2 The name of the 3rd argument.
904 */
905# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
906 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
907/**
908 * For defining a C instruction implementation function taking three extra
909 * arguments.
910 *
911 * @param a_Name The name of the function.
912 * @param a_Type0 The type of the 1st argument
913 * @param a_Arg0 The name of the 1st argument.
914 * @param a_Type1 The type of the 2nd argument.
915 * @param a_Arg1 The name of the 2nd argument.
916 * @param a_Type2 The type of the 3rd argument.
917 * @param a_Arg2 The name of the 3rd argument.
918 */
919# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
920 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
921/**
922 * Prototype version of IEM_CIMPL_DEF_3.
923 */
924# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
925 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
926/**
927 * For calling a C instruction implementation function taking three extra
928 * arguments.
929 *
930 * This special call macro adds default arguments to the call and allow us to
931 * change these later.
932 *
933 * @param a_fn The name of the function.
934 * @param a0 The name of the 1st argument.
935 * @param a1 The name of the 2nd argument.
936 * @param a2 The name of the 3rd argument.
937 */
938# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
939
940
941/**
942 * For typedef'ing or declaring a C instruction implementation function taking
943 * four extra arguments.
944 *
945 * @param a_Name The name of the type.
946 * @param a_Type0 The type of the 1st argument
947 * @param a_Arg0 The name of the 1st argument.
948 * @param a_Type1 The type of the 2nd argument.
949 * @param a_Arg1 The name of the 2nd argument.
950 * @param a_Type2 The type of the 3rd argument.
951 * @param a_Arg2 The name of the 3rd argument.
952 * @param a_Type3 The type of the 4th argument.
953 * @param a_Arg3 The name of the 4th argument.
954 */
955# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
956 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
957/**
958 * For defining a C instruction implementation function taking four extra
959 * arguments.
960 *
961 * @param a_Name The name of the function.
962 * @param a_Type0 The type of the 1st argument
963 * @param a_Arg0 The name of the 1st argument.
964 * @param a_Type1 The type of the 2nd argument.
965 * @param a_Arg1 The name of the 2nd argument.
966 * @param a_Type2 The type of the 3rd argument.
967 * @param a_Arg2 The name of the 3rd argument.
968 * @param a_Type3 The type of the 4th argument.
969 * @param a_Arg3 The name of the 4th argument.
970 */
971# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
972 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
973 a_Type2 a_Arg2, a_Type3 a_Arg3))
974/**
975 * Prototype version of IEM_CIMPL_DEF_4.
976 */
977# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
978 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
979 a_Type2 a_Arg2, a_Type3 a_Arg3))
980/**
981 * For calling a C instruction implementation function taking four extra
982 * arguments.
983 *
984 * This special call macro adds default arguments to the call and allow us to
985 * change these later.
986 *
987 * @param a_fn The name of the function.
988 * @param a0 The name of the 1st argument.
989 * @param a1 The name of the 2nd argument.
990 * @param a2 The name of the 3rd argument.
991 * @param a3 The name of the 4th argument.
992 */
993# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
994
995
996/**
997 * For typedef'ing or declaring a C instruction implementation function taking
998 * five extra arguments.
999 *
1000 * @param a_Name The name of the type.
1001 * @param a_Type0 The type of the 1st argument
1002 * @param a_Arg0 The name of the 1st argument.
1003 * @param a_Type1 The type of the 2nd argument.
1004 * @param a_Arg1 The name of the 2nd argument.
1005 * @param a_Type2 The type of the 3rd argument.
1006 * @param a_Arg2 The name of the 3rd argument.
1007 * @param a_Type3 The type of the 4th argument.
1008 * @param a_Arg3 The name of the 4th argument.
1009 * @param a_Type4 The type of the 5th argument.
1010 * @param a_Arg4 The name of the 5th argument.
1011 */
1012# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1013 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
1014 a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1015 a_Type3 a_Arg3, a_Type4 a_Arg4))
1016/**
1017 * For defining a C instruction implementation function taking five extra
1018 * arguments.
1019 *
1020 * @param a_Name The name of the function.
1021 * @param a_Type0 The type of the 1st argument
1022 * @param a_Arg0 The name of the 1st argument.
1023 * @param a_Type1 The type of the 2nd argument.
1024 * @param a_Arg1 The name of the 2nd argument.
1025 * @param a_Type2 The type of the 3rd argument.
1026 * @param a_Arg2 The name of the 3rd argument.
1027 * @param a_Type3 The type of the 4th argument.
1028 * @param a_Arg3 The name of the 4th argument.
1029 * @param a_Type4 The type of the 5th argument.
1030 * @param a_Arg4 The name of the 5th argument.
1031 */
1032# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1033 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1034 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
1035/**
1036 * Prototype version of IEM_CIMPL_DEF_5.
1037 */
1038# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1039 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1040 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
1041/**
1042 * For calling a C instruction implementation function taking five extra
1043 * arguments.
1044 *
1045 * This special call macro adds default arguments to the call and allow us to
1046 * change these later.
1047 *
1048 * @param a_fn The name of the function.
1049 * @param a0 The name of the 1st argument.
1050 * @param a1 The name of the 2nd argument.
1051 * @param a2 The name of the 3rd argument.
1052 * @param a3 The name of the 4th argument.
1053 * @param a4 The name of the 5th argument.
1054 */
1055# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1056
1057/** @} */
1058
1059
1060/** @name Opcode Decoder Function Types.
1061 * @{ */
1062
1063# if 0 /** @todo r=bird: This upsets doxygen. Generally, these macros and types probably won't change with the target arch.
1064 * Nor will probably the TLB definitions. So, we need some better splitting of this code. */
1065/** @typedef PFNIEMOP
1066 * Pointer to an opcode decoder function.
1067 */
1068
1069/** @def FNIEMOP_DEF
1070 * Define an opcode decoder function.
1071 *
1072 * We're using macors for this so that adding and removing parameters as well as
1073 * tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
1074 *
1075 * @param a_Name The function name.
1076 */
1077#endif
1078
1079#if defined(__GNUC__) && defined(RT_ARCH_X86)
1080typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
1081# define FNIEMOP_DEF(a_Name) \
1082 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
1083# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
1084 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
1085# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
1086 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
1087
1088#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1089typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
1090# define FNIEMOP_DEF(a_Name) \
1091 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
1092# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
1093 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
1094# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
1095 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
1096
1097#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
1098typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
1099# define FNIEMOP_DEF(a_Name) \
1100 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
1101# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
1102 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
1103# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
1104 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
1105
1106#else
1107typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
1108# define FNIEMOP_DEF(a_Name) \
1109 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
1110# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
1111 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
1112# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
1113 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
1114
1115#endif
1116
1117/**
1118 * Call an opcode decoder function.
1119 *
1120 * We're using macors for this so that adding and removing parameters can be
1121 * done as we please. See FNIEMOP_DEF.
1122 */
1123#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
1124
1125/**
1126 * Call a common opcode decoder function taking one extra argument.
1127 *
1128 * We're using macors for this so that adding and removing parameters can be
1129 * done as we please. See FNIEMOP_DEF_1.
1130 */
1131#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
1132
1133/**
1134 * Call a common opcode decoder function taking one extra argument.
1135 *
1136 * We're using macors for this so that adding and removing parameters can be
1137 * done as we please. See FNIEMOP_DEF_1.
1138 */
1139#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
1140/** @} */
1141
1142
1143/** @name Misc Helpers
1144 * @{ */
1145
1146/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
1147 * due to GCC lacking knowledge about the value range of a switch. */
1148#if RT_CPLUSPLUS_PREREQ(202000)
1149# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
1150#else
1151# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
1152#endif
1153
1154/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
1155#if RT_CPLUSPLUS_PREREQ(202000)
1156# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
1157#else
1158# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
1159#endif
1160
1161/**
1162 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
1163 * occation.
1164 */
1165#ifdef LOG_ENABLED
1166# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
1167 do { \
1168 /*Log*/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
1169 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
1170 } while (0)
1171#else
1172# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
1173 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
1174#endif
1175
1176/**
1177 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
1178 * occation using the supplied logger statement.
1179 *
1180 * @param a_LoggerArgs What to log on failure.
1181 */
1182#ifdef LOG_ENABLED
1183# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
1184 do { \
1185 LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
1186 /*LogFunc(a_LoggerArgs);*/ \
1187 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
1188 } while (0)
1189#else
1190# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
1191 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
1192#endif
1193
1194/** @} */
1195
1196void iemInitPendingBreakpointsSlow(PVMCPUCC pVCpu);
1197
1198
1199/** @name Raising Exceptions.
1200 * @{ */
1201VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
1202 uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
1203#ifdef IEM_WITH_SETJMP
1204DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
1205 uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
1206#endif
1207VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
1208VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
1209VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
1210VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
1211#ifdef IEM_WITH_SETJMP
1212DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
1213#endif
1214VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
1215VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
1216#ifdef IEM_WITH_SETJMP
1217DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
1218#endif
1219VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
1220
1221IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
1222IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
1223
1224/**
1225 * Macro for calling iemCImplRaiseDivideError().
1226 *
1227 * This enables us to add/remove arguments and force different levels of
1228 * inlining as we wish.
1229 *
1230 * @return Strict VBox status code.
1231 */
1232#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(iemCImplRaiseDivideError)
1233
1234/**
1235 * Macro for calling iemCImplRaiseInvalidOpcode().
1236 *
1237 * This enables us to add/remove arguments and force different levels of
1238 * inlining as we wish.
1239 *
1240 * @return Strict VBox status code.
1241 */
1242#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(iemCImplRaiseInvalidOpcode)
1243/** @} */
1244
1245/** @name Memory access.
1246 * @{ */
1247
1248VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
1249 uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
1250VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
1251#ifndef IN_RING3
1252VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
1253#endif
1254void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
1255VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
1256VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
1257VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
1258
1259VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1260VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1261VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1262VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1263VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1264VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1265VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1266VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1267VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1268#ifdef IEM_WITH_SETJMP
1269uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1270uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1271uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1272uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1273void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1274void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1275void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1276void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1277#endif
1278
1279VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1280VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1281VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1282VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1283
1284VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
1285VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
1286VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
1287VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
1288VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
1289VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
1290#ifdef IEM_WITH_SETJMP
1291void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
1292void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
1293void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
1294void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
1295void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
1296void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
1297#endif
1298
1299VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
1300 void **ppvMem, uint64_t *puNewRsp) RT_NOEXCEPT;
1301VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
1302VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
1303VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
1304VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
1305VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1306VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1307VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1308VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
1309VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
1310 void const **ppvMem, uint64_t *puNewRsp) RT_NOEXCEPT;
1311VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
1312 void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
1313VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
1314VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
1315VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
1316VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
1317VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1318VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1319VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1320/** @} */
1321
1322/** @} */
1323
1324RT_C_DECLS_END
1325
1326#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_armv8_h */
1327
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