VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMInline.h@ 99208

Last change on this file since 99208 was 98969, checked in by vboxsync, 20 months ago

VMM/IEM: More work on processing MC blocks, mainly related to reworking common functions for binary operations into body macros. bugref:10369
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1/* $Id: IEMInline.h 98969 2023-03-15 00:24:47Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - Inlined Functions.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMInline_h
29#define VMM_INCLUDED_SRC_include_IEMInline_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35
36/**
37 * Makes status code addjustments (pass up from I/O and access handler)
38 * as well as maintaining statistics.
39 *
40 * @returns Strict VBox status code to pass up.
41 * @param pVCpu The cross context virtual CPU structure of the calling thread.
42 * @param rcStrict The status from executing an instruction.
43 */
44DECL_FORCE_INLINE(VBOXSTRICTRC) iemExecStatusCodeFiddling(PVMCPUCC pVCpu, VBOXSTRICTRC rcStrict) RT_NOEXCEPT
45{
46 if (rcStrict != VINF_SUCCESS)
47 {
48 if (RT_SUCCESS(rcStrict))
49 {
50 AssertMsg( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
51 || rcStrict == VINF_IOM_R3_IOPORT_READ
52 || rcStrict == VINF_IOM_R3_IOPORT_WRITE
53 || rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
54 || rcStrict == VINF_IOM_R3_MMIO_READ
55 || rcStrict == VINF_IOM_R3_MMIO_READ_WRITE
56 || rcStrict == VINF_IOM_R3_MMIO_WRITE
57 || rcStrict == VINF_IOM_R3_MMIO_COMMIT_WRITE
58 || rcStrict == VINF_CPUM_R3_MSR_READ
59 || rcStrict == VINF_CPUM_R3_MSR_WRITE
60 || rcStrict == VINF_EM_RAW_EMULATE_INSTR
61 || rcStrict == VINF_EM_RAW_TO_R3
62 || rcStrict == VINF_EM_TRIPLE_FAULT
63 || rcStrict == VINF_GIM_R3_HYPERCALL
64 /* raw-mode / virt handlers only: */
65 || rcStrict == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT
66 || rcStrict == VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT
67 || rcStrict == VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT
68 || rcStrict == VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT
69 || rcStrict == VINF_SELM_SYNC_GDT
70 || rcStrict == VINF_CSAM_PENDING_ACTION
71 || rcStrict == VINF_PATM_CHECK_PATCH_PAGE
72 /* nested hw.virt codes: */
73 || rcStrict == VINF_VMX_VMEXIT
74 || rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE
75 || rcStrict == VINF_VMX_MODIFIES_BEHAVIOR
76 || rcStrict == VINF_SVM_VMEXIT
77 , ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
78/** @todo adjust for VINF_EM_RAW_EMULATE_INSTR. */
79 int32_t const rcPassUp = pVCpu->iem.s.rcPassUp;
80#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
81 if ( rcStrict == VINF_VMX_VMEXIT
82 && rcPassUp == VINF_SUCCESS)
83 rcStrict = VINF_SUCCESS;
84 else
85#endif
86#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
87 if ( rcStrict == VINF_SVM_VMEXIT
88 && rcPassUp == VINF_SUCCESS)
89 rcStrict = VINF_SUCCESS;
90 else
91#endif
92 if (rcPassUp == VINF_SUCCESS)
93 pVCpu->iem.s.cRetInfStatuses++;
94 else if ( rcPassUp < VINF_EM_FIRST
95 || rcPassUp > VINF_EM_LAST
96 || rcPassUp < VBOXSTRICTRC_VAL(rcStrict))
97 {
98 Log(("IEM: rcPassUp=%Rrc! rcStrict=%Rrc\n", rcPassUp, VBOXSTRICTRC_VAL(rcStrict)));
99 pVCpu->iem.s.cRetPassUpStatus++;
100 rcStrict = rcPassUp;
101 }
102 else
103 {
104 Log(("IEM: rcPassUp=%Rrc rcStrict=%Rrc!\n", rcPassUp, VBOXSTRICTRC_VAL(rcStrict)));
105 pVCpu->iem.s.cRetInfStatuses++;
106 }
107 }
108 else if (rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
109 pVCpu->iem.s.cRetAspectNotImplemented++;
110 else if (rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED)
111 pVCpu->iem.s.cRetInstrNotImplemented++;
112 else
113 pVCpu->iem.s.cRetErrStatuses++;
114 }
115 else if (pVCpu->iem.s.rcPassUp != VINF_SUCCESS)
116 {
117 pVCpu->iem.s.cRetPassUpStatus++;
118 rcStrict = pVCpu->iem.s.rcPassUp;
119 }
120
121 return rcStrict;
122}
123
124
125/**
126 * Sets the pass up status.
127 *
128 * @returns VINF_SUCCESS.
129 * @param pVCpu The cross context virtual CPU structure of the
130 * calling thread.
131 * @param rcPassUp The pass up status. Must be informational.
132 * VINF_SUCCESS is not allowed.
133 */
134DECLINLINE(int) iemSetPassUpStatus(PVMCPUCC pVCpu, VBOXSTRICTRC rcPassUp) RT_NOEXCEPT
135{
136 AssertRC(VBOXSTRICTRC_VAL(rcPassUp)); Assert(rcPassUp != VINF_SUCCESS);
137
138 int32_t const rcOldPassUp = pVCpu->iem.s.rcPassUp;
139 if (rcOldPassUp == VINF_SUCCESS)
140 pVCpu->iem.s.rcPassUp = VBOXSTRICTRC_VAL(rcPassUp);
141 /* If both are EM scheduling codes, use EM priority rules. */
142 else if ( rcOldPassUp >= VINF_EM_FIRST && rcOldPassUp <= VINF_EM_LAST
143 && rcPassUp >= VINF_EM_FIRST && rcPassUp <= VINF_EM_LAST)
144 {
145 if (rcPassUp < rcOldPassUp)
146 {
147 Log(("IEM: rcPassUp=%Rrc! rcOldPassUp=%Rrc\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
148 pVCpu->iem.s.rcPassUp = VBOXSTRICTRC_VAL(rcPassUp);
149 }
150 else
151 Log(("IEM: rcPassUp=%Rrc rcOldPassUp=%Rrc!\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
152 }
153 /* Override EM scheduling with specific status code. */
154 else if (rcOldPassUp >= VINF_EM_FIRST && rcOldPassUp <= VINF_EM_LAST)
155 {
156 Log(("IEM: rcPassUp=%Rrc! rcOldPassUp=%Rrc\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
157 pVCpu->iem.s.rcPassUp = VBOXSTRICTRC_VAL(rcPassUp);
158 }
159 /* Don't override specific status code, first come first served. */
160 else
161 Log(("IEM: rcPassUp=%Rrc rcOldPassUp=%Rrc!\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
162 return VINF_SUCCESS;
163}
164
165
166/**
167 * Calculates the CPU mode.
168 *
169 * This is mainly for updating IEMCPU::enmCpuMode.
170 *
171 * @returns CPU mode.
172 * @param pVCpu The cross context virtual CPU structure of the
173 * calling thread.
174 */
175DECLINLINE(IEMMODE) iemCalcCpuMode(PVMCPUCC pVCpu) RT_NOEXCEPT
176{
177 if (CPUMIsGuestIn64BitCodeEx(&pVCpu->cpum.GstCtx))
178 return IEMMODE_64BIT;
179 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig) /** @todo check if this is correct... */
180 return IEMMODE_32BIT;
181 return IEMMODE_16BIT;
182}
183
184#ifndef IEM_WITH_OPAQUE_DECODER_STATE
185
186# if defined(VBOX_INCLUDED_vmm_dbgf_h) || defined(DOXYGEN_RUNNING) /* dbgf.ro.cEnabledHwBreakpoints */
187/**
188 * Initializes the execution state.
189 *
190 * @param pVCpu The cross context virtual CPU structure of the
191 * calling thread.
192 * @param fBypassHandlers Whether to bypass access handlers.
193 *
194 * @remarks Callers of this must call iemUninitExec() to undo potentially fatal
195 * side-effects in strict builds.
196 */
197DECLINLINE(void) iemInitExec(PVMCPUCC pVCpu, bool fBypassHandlers) RT_NOEXCEPT
198{
199 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
200 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_IEM));
201 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.cs));
202 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
203 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.es));
204 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ds));
205 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.fs));
206 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.gs));
207 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ldtr));
208 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.tr));
209
210 pVCpu->iem.s.uCpl = CPUMGetGuestCPL(pVCpu);
211 pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
212# ifdef VBOX_STRICT
213 pVCpu->iem.s.enmDefAddrMode = (IEMMODE)0xfe;
214 pVCpu->iem.s.enmEffAddrMode = (IEMMODE)0xfe;
215 pVCpu->iem.s.enmDefOpSize = (IEMMODE)0xfe;
216 pVCpu->iem.s.enmEffOpSize = (IEMMODE)0xfe;
217 pVCpu->iem.s.fPrefixes = 0xfeedbeef;
218 pVCpu->iem.s.uRexReg = 127;
219 pVCpu->iem.s.uRexB = 127;
220 pVCpu->iem.s.offModRm = 127;
221 pVCpu->iem.s.uRexIndex = 127;
222 pVCpu->iem.s.iEffSeg = 127;
223 pVCpu->iem.s.idxPrefix = 127;
224 pVCpu->iem.s.uVex3rdReg = 127;
225 pVCpu->iem.s.uVexLength = 127;
226 pVCpu->iem.s.fEvexStuff = 127;
227 pVCpu->iem.s.uFpuOpcode = UINT16_MAX;
228# ifdef IEM_WITH_CODE_TLB
229 pVCpu->iem.s.offInstrNextByte = UINT16_MAX;
230 pVCpu->iem.s.pbInstrBuf = NULL;
231 pVCpu->iem.s.cbInstrBuf = UINT16_MAX;
232 pVCpu->iem.s.cbInstrBufTotal = UINT16_MAX;
233 pVCpu->iem.s.offCurInstrStart = INT16_MAX;
234 pVCpu->iem.s.uInstrBufPc = UINT64_C(0xc0ffc0ffcff0c0ff);
235# else
236 pVCpu->iem.s.offOpcode = 127;
237 pVCpu->iem.s.cbOpcode = 127;
238# endif
239# endif /* VBOX_STRICT */
240
241 pVCpu->iem.s.cActiveMappings = 0;
242 pVCpu->iem.s.iNextMapping = 0;
243 pVCpu->iem.s.rcPassUp = VINF_SUCCESS;
244 pVCpu->iem.s.fBypassHandlers = fBypassHandlers;
245 pVCpu->iem.s.fDisregardLock = false;
246 pVCpu->iem.s.fPendingInstructionBreakpoints = false;
247 pVCpu->iem.s.fPendingDataBreakpoints = false;
248 pVCpu->iem.s.fPendingIoBreakpoints = false;
249 if (RT_LIKELY( !(pVCpu->cpum.GstCtx.dr[7] & X86_DR7_ENABLED_MASK)
250 && pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledHwBreakpoints == 0))
251 { /* likely */ }
252 else
253 iemInitPendingBreakpointsSlow(pVCpu);
254}
255# endif /* VBOX_INCLUDED_vmm_dbgf_h */
256
257
258# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
259/**
260 * Performs a minimal reinitialization of the execution state.
261 *
262 * This is intended to be used by VM-exits, SMM, LOADALL and other similar
263 * 'world-switch' types operations on the CPU. Currently only nested
264 * hardware-virtualization uses it.
265 *
266 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
267 */
268DECLINLINE(void) iemReInitExec(PVMCPUCC pVCpu) RT_NOEXCEPT
269{
270 IEMMODE const enmMode = iemCalcCpuMode(pVCpu);
271 uint8_t const uCpl = CPUMGetGuestCPL(pVCpu);
272
273 pVCpu->iem.s.uCpl = uCpl;
274 pVCpu->iem.s.enmCpuMode = enmMode;
275 pVCpu->iem.s.enmDefAddrMode = enmMode; /** @todo check if this is correct... */
276 pVCpu->iem.s.enmEffAddrMode = enmMode;
277 if (enmMode != IEMMODE_64BIT)
278 {
279 pVCpu->iem.s.enmDefOpSize = enmMode; /** @todo check if this is correct... */
280 pVCpu->iem.s.enmEffOpSize = enmMode;
281 }
282 else
283 {
284 pVCpu->iem.s.enmDefOpSize = IEMMODE_32BIT;
285 pVCpu->iem.s.enmEffOpSize = enmMode;
286 }
287 pVCpu->iem.s.iEffSeg = X86_SREG_DS;
288# ifndef IEM_WITH_CODE_TLB
289 /** @todo Shouldn't we be doing this in IEMTlbInvalidateAll()? */
290 pVCpu->iem.s.offOpcode = 0;
291 pVCpu->iem.s.cbOpcode = 0;
292# endif
293 pVCpu->iem.s.rcPassUp = VINF_SUCCESS;
294}
295# endif
296
297
298/**
299 * Counterpart to #iemInitExec that undoes evil strict-build stuff.
300 *
301 * @param pVCpu The cross context virtual CPU structure of the
302 * calling thread.
303 */
304DECLINLINE(void) iemUninitExec(PVMCPUCC pVCpu) RT_NOEXCEPT
305{
306 /* Note! do not touch fInPatchCode here! (see iemUninitExecAndFiddleStatusAndMaybeReenter) */
307# ifdef VBOX_STRICT
308# ifdef IEM_WITH_CODE_TLB
309 NOREF(pVCpu);
310# else
311 pVCpu->iem.s.cbOpcode = 0;
312# endif
313# else
314 NOREF(pVCpu);
315# endif
316}
317
318
319/**
320 * Calls iemUninitExec, iemExecStatusCodeFiddling and iemRCRawMaybeReenter.
321 *
322 * Only calling iemRCRawMaybeReenter in raw-mode, obviously.
323 *
324 * @returns Fiddled strict vbox status code, ready to return to non-IEM caller.
325 * @param pVCpu The cross context virtual CPU structure of the calling thread.
326 * @param rcStrict The status code to fiddle.
327 */
328DECLINLINE(VBOXSTRICTRC) iemUninitExecAndFiddleStatusAndMaybeReenter(PVMCPUCC pVCpu, VBOXSTRICTRC rcStrict) RT_NOEXCEPT
329{
330 iemUninitExec(pVCpu);
331 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
332}
333
334
335/**
336 * Macro used by the IEMExec* method to check the given instruction length.
337 *
338 * Will return on failure!
339 *
340 * @param a_cbInstr The given instruction length.
341 * @param a_cbMin The minimum length.
342 */
343# define IEMEXEC_ASSERT_INSTR_LEN_RETURN(a_cbInstr, a_cbMin) \
344 AssertMsgReturn((unsigned)(a_cbInstr) - (unsigned)(a_cbMin) <= (unsigned)15 - (unsigned)(a_cbMin), \
345 ("cbInstr=%u cbMin=%u\n", (a_cbInstr), (a_cbMin)), VERR_IEM_INVALID_INSTR_LENGTH)
346
347
348# ifndef IEM_WITH_SETJMP
349
350/**
351 * Fetches the first opcode byte.
352 *
353 * @returns Strict VBox status code.
354 * @param pVCpu The cross context virtual CPU structure of the
355 * calling thread.
356 * @param pu8 Where to return the opcode byte.
357 */
358DECLINLINE(VBOXSTRICTRC) iemOpcodeGetFirstU8(PVMCPUCC pVCpu, uint8_t *pu8) RT_NOEXCEPT
359{
360 /*
361 * Check for hardware instruction breakpoints.
362 */
363 if (RT_LIKELY(!pVCpu->iem.s.fPendingInstructionBreakpoints))
364 { /* likely */ }
365 else
366 {
367 VBOXSTRICTRC rcStrict = DBGFBpCheckInstruction(pVCpu->CTX_SUFF(pVM), pVCpu,
368 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
369 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
370 { /* likely */ }
371 else if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
372 return iemRaiseDebugException(pVCpu);
373 else
374 return rcStrict;
375 }
376
377 /*
378 * Fetch the first opcode byte.
379 */
380 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
381 if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
382 {
383 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
384 *pu8 = pVCpu->iem.s.abOpcode[offOpcode];
385 return VINF_SUCCESS;
386 }
387 return iemOpcodeGetNextU8Slow(pVCpu, pu8);
388}
389
390# else /* IEM_WITH_SETJMP */
391
392/**
393 * Fetches the first opcode byte, longjmp on error.
394 *
395 * @returns The opcode byte.
396 * @param pVCpu The cross context virtual CPU structure of the calling thread.
397 */
398DECL_INLINE_THROW(uint8_t) iemOpcodeGetFirstU8Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
399{
400 /*
401 * Check for hardware instruction breakpoints.
402 */
403 if (RT_LIKELY(!pVCpu->iem.s.fPendingInstructionBreakpoints))
404 { /* likely */ }
405 else
406 {
407 VBOXSTRICTRC rcStrict = DBGFBpCheckInstruction(pVCpu->CTX_SUFF(pVM), pVCpu,
408 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
409 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
410 { /* likely */ }
411 else
412 {
413 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
414 rcStrict = iemRaiseDebugException(pVCpu);
415 IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(rcStrict));
416 }
417 }
418
419 /*
420 * Fetch the first opcode byte.
421 */
422# ifdef IEM_WITH_CODE_TLB
423 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
424 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
425 if (RT_LIKELY( pbBuf != NULL
426 && offBuf < pVCpu->iem.s.cbInstrBuf))
427 {
428 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 1;
429 return pbBuf[offBuf];
430 }
431# else
432 uintptr_t offOpcode = pVCpu->iem.s.offOpcode;
433 if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
434 {
435 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
436 return pVCpu->iem.s.abOpcode[offOpcode];
437 }
438# endif
439 return iemOpcodeGetNextU8SlowJmp(pVCpu);
440}
441
442# endif /* IEM_WITH_SETJMP */
443
444/**
445 * Fetches the first opcode byte, returns/throws automatically on failure.
446 *
447 * @param a_pu8 Where to return the opcode byte.
448 * @remark Implicitly references pVCpu.
449 */
450# ifndef IEM_WITH_SETJMP
451# define IEM_OPCODE_GET_FIRST_U8(a_pu8) \
452 do \
453 { \
454 VBOXSTRICTRC rcStrict2 = iemOpcodeGetFirstU8(pVCpu, (a_pu8)); \
455 if (rcStrict2 == VINF_SUCCESS) \
456 { /* likely */ } \
457 else \
458 return rcStrict2; \
459 } while (0)
460# else
461# define IEM_OPCODE_GET_FIRST_U8(a_pu8) (*(a_pu8) = iemOpcodeGetFirstU8Jmp(pVCpu))
462# endif /* IEM_WITH_SETJMP */
463
464
465# ifndef IEM_WITH_SETJMP
466
467/**
468 * Fetches the next opcode byte.
469 *
470 * @returns Strict VBox status code.
471 * @param pVCpu The cross context virtual CPU structure of the
472 * calling thread.
473 * @param pu8 Where to return the opcode byte.
474 */
475DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU8(PVMCPUCC pVCpu, uint8_t *pu8) RT_NOEXCEPT
476{
477 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
478 if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
479 {
480 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
481 *pu8 = pVCpu->iem.s.abOpcode[offOpcode];
482 return VINF_SUCCESS;
483 }
484 return iemOpcodeGetNextU8Slow(pVCpu, pu8);
485}
486
487# else /* IEM_WITH_SETJMP */
488
489/**
490 * Fetches the next opcode byte, longjmp on error.
491 *
492 * @returns The opcode byte.
493 * @param pVCpu The cross context virtual CPU structure of the calling thread.
494 */
495DECL_INLINE_THROW(uint8_t) iemOpcodeGetNextU8Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
496{
497# ifdef IEM_WITH_CODE_TLB
498 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
499 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
500 if (RT_LIKELY( pbBuf != NULL
501 && offBuf < pVCpu->iem.s.cbInstrBuf))
502 {
503 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 1;
504 return pbBuf[offBuf];
505 }
506# else
507 uintptr_t offOpcode = pVCpu->iem.s.offOpcode;
508 if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
509 {
510 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
511 return pVCpu->iem.s.abOpcode[offOpcode];
512 }
513# endif
514 return iemOpcodeGetNextU8SlowJmp(pVCpu);
515}
516
517# endif /* IEM_WITH_SETJMP */
518
519/**
520 * Fetches the next opcode byte, returns automatically on failure.
521 *
522 * @param a_pu8 Where to return the opcode byte.
523 * @remark Implicitly references pVCpu.
524 */
525# ifndef IEM_WITH_SETJMP
526# define IEM_OPCODE_GET_NEXT_U8(a_pu8) \
527 do \
528 { \
529 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU8(pVCpu, (a_pu8)); \
530 if (rcStrict2 == VINF_SUCCESS) \
531 { /* likely */ } \
532 else \
533 return rcStrict2; \
534 } while (0)
535# else
536# define IEM_OPCODE_GET_NEXT_U8(a_pu8) (*(a_pu8) = iemOpcodeGetNextU8Jmp(pVCpu))
537# endif /* IEM_WITH_SETJMP */
538
539
540# ifndef IEM_WITH_SETJMP
541/**
542 * Fetches the next signed byte from the opcode stream.
543 *
544 * @returns Strict VBox status code.
545 * @param pVCpu The cross context virtual CPU structure of the calling thread.
546 * @param pi8 Where to return the signed byte.
547 */
548DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8(PVMCPUCC pVCpu, int8_t *pi8) RT_NOEXCEPT
549{
550 return iemOpcodeGetNextU8(pVCpu, (uint8_t *)pi8);
551}
552# endif /* !IEM_WITH_SETJMP */
553
554
555/**
556 * Fetches the next signed byte from the opcode stream, returning automatically
557 * on failure.
558 *
559 * @param a_pi8 Where to return the signed byte.
560 * @remark Implicitly references pVCpu.
561 */
562# ifndef IEM_WITH_SETJMP
563# define IEM_OPCODE_GET_NEXT_S8(a_pi8) \
564 do \
565 { \
566 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8(pVCpu, (a_pi8)); \
567 if (rcStrict2 != VINF_SUCCESS) \
568 return rcStrict2; \
569 } while (0)
570# else /* IEM_WITH_SETJMP */
571# define IEM_OPCODE_GET_NEXT_S8(a_pi8) (*(a_pi8) = (int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
572
573# endif /* IEM_WITH_SETJMP */
574
575
576# ifndef IEM_WITH_SETJMP
577/**
578 * Fetches the next signed byte from the opcode stream, extending it to
579 * unsigned 16-bit.
580 *
581 * @returns Strict VBox status code.
582 * @param pVCpu The cross context virtual CPU structure of the calling thread.
583 * @param pu16 Where to return the unsigned word.
584 */
585DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU16(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT
586{
587 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
588 if (RT_UNLIKELY(offOpcode >= pVCpu->iem.s.cbOpcode))
589 return iemOpcodeGetNextS8SxU16Slow(pVCpu, pu16);
590
591 *pu16 = (int8_t)pVCpu->iem.s.abOpcode[offOpcode];
592 pVCpu->iem.s.offOpcode = offOpcode + 1;
593 return VINF_SUCCESS;
594}
595# endif /* !IEM_WITH_SETJMP */
596
597/**
598 * Fetches the next signed byte from the opcode stream and sign-extending it to
599 * a word, returning automatically on failure.
600 *
601 * @param a_pu16 Where to return the word.
602 * @remark Implicitly references pVCpu.
603 */
604# ifndef IEM_WITH_SETJMP
605# define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) \
606 do \
607 { \
608 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU16(pVCpu, (a_pu16)); \
609 if (rcStrict2 != VINF_SUCCESS) \
610 return rcStrict2; \
611 } while (0)
612# else
613# define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) (*(a_pu16) = (int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
614# endif
615
616# ifndef IEM_WITH_SETJMP
617/**
618 * Fetches the next signed byte from the opcode stream, extending it to
619 * unsigned 32-bit.
620 *
621 * @returns Strict VBox status code.
622 * @param pVCpu The cross context virtual CPU structure of the calling thread.
623 * @param pu32 Where to return the unsigned dword.
624 */
625DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU32(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
626{
627 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
628 if (RT_UNLIKELY(offOpcode >= pVCpu->iem.s.cbOpcode))
629 return iemOpcodeGetNextS8SxU32Slow(pVCpu, pu32);
630
631 *pu32 = (int8_t)pVCpu->iem.s.abOpcode[offOpcode];
632 pVCpu->iem.s.offOpcode = offOpcode + 1;
633 return VINF_SUCCESS;
634}
635# endif /* !IEM_WITH_SETJMP */
636
637/**
638 * Fetches the next signed byte from the opcode stream and sign-extending it to
639 * a word, returning automatically on failure.
640 *
641 * @param a_pu32 Where to return the word.
642 * @remark Implicitly references pVCpu.
643 */
644# ifndef IEM_WITH_SETJMP
645# define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) \
646 do \
647 { \
648 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU32(pVCpu, (a_pu32)); \
649 if (rcStrict2 != VINF_SUCCESS) \
650 return rcStrict2; \
651 } while (0)
652# else
653# define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) (*(a_pu32) = (int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
654# endif
655
656
657# ifndef IEM_WITH_SETJMP
658/**
659 * Fetches the next signed byte from the opcode stream, extending it to
660 * unsigned 64-bit.
661 *
662 * @returns Strict VBox status code.
663 * @param pVCpu The cross context virtual CPU structure of the calling thread.
664 * @param pu64 Where to return the unsigned qword.
665 */
666DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
667{
668 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
669 if (RT_UNLIKELY(offOpcode >= pVCpu->iem.s.cbOpcode))
670 return iemOpcodeGetNextS8SxU64Slow(pVCpu, pu64);
671
672 *pu64 = (int8_t)pVCpu->iem.s.abOpcode[offOpcode];
673 pVCpu->iem.s.offOpcode = offOpcode + 1;
674 return VINF_SUCCESS;
675}
676# endif /* !IEM_WITH_SETJMP */
677
678/**
679 * Fetches the next signed byte from the opcode stream and sign-extending it to
680 * a word, returning automatically on failure.
681 *
682 * @param a_pu64 Where to return the word.
683 * @remark Implicitly references pVCpu.
684 */
685# ifndef IEM_WITH_SETJMP
686# define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) \
687 do \
688 { \
689 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU64(pVCpu, (a_pu64)); \
690 if (rcStrict2 != VINF_SUCCESS) \
691 return rcStrict2; \
692 } while (0)
693# else
694# define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) (*(a_pu64) = (int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
695# endif
696
697
698# ifndef IEM_WITH_SETJMP
699/**
700 * Fetches the next opcode byte.
701 *
702 * @returns Strict VBox status code.
703 * @param pVCpu The cross context virtual CPU structure of the
704 * calling thread.
705 * @param pu8 Where to return the opcode byte.
706 */
707DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextRm(PVMCPUCC pVCpu, uint8_t *pu8) RT_NOEXCEPT
708{
709 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
710 pVCpu->iem.s.offModRm = offOpcode;
711 if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
712 {
713 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
714 *pu8 = pVCpu->iem.s.abOpcode[offOpcode];
715 return VINF_SUCCESS;
716 }
717 return iemOpcodeGetNextU8Slow(pVCpu, pu8);
718}
719# else /* IEM_WITH_SETJMP */
720/**
721 * Fetches the next opcode byte, longjmp on error.
722 *
723 * @returns The opcode byte.
724 * @param pVCpu The cross context virtual CPU structure of the calling thread.
725 */
726DECL_INLINE_THROW(uint8_t) iemOpcodeGetNextRmJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
727{
728# ifdef IEM_WITH_CODE_TLB
729 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
730 pVCpu->iem.s.offModRm = offBuf;
731 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
732 if (RT_LIKELY( pbBuf != NULL
733 && offBuf < pVCpu->iem.s.cbInstrBuf))
734 {
735 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 1;
736 return pbBuf[offBuf];
737 }
738# else
739 uintptr_t offOpcode = pVCpu->iem.s.offOpcode;
740 pVCpu->iem.s.offModRm = offOpcode;
741 if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
742 {
743 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
744 return pVCpu->iem.s.abOpcode[offOpcode];
745 }
746# endif
747 return iemOpcodeGetNextU8SlowJmp(pVCpu);
748}
749# endif /* IEM_WITH_SETJMP */
750
751/**
752 * Fetches the next opcode byte, which is a ModR/M byte, returns automatically
753 * on failure.
754 *
755 * Will note down the position of the ModR/M byte for VT-x exits.
756 *
757 * @param a_pbRm Where to return the RM opcode byte.
758 * @remark Implicitly references pVCpu.
759 */
760# ifndef IEM_WITH_SETJMP
761# define IEM_OPCODE_GET_NEXT_RM(a_pbRm) \
762 do \
763 { \
764 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextRm(pVCpu, (a_pbRm)); \
765 if (rcStrict2 == VINF_SUCCESS) \
766 { /* likely */ } \
767 else \
768 return rcStrict2; \
769 } while (0)
770# else
771# define IEM_OPCODE_GET_NEXT_RM(a_pbRm) (*(a_pbRm) = iemOpcodeGetNextRmJmp(pVCpu))
772# endif /* IEM_WITH_SETJMP */
773
774
775# ifndef IEM_WITH_SETJMP
776
777/**
778 * Fetches the next opcode word.
779 *
780 * @returns Strict VBox status code.
781 * @param pVCpu The cross context virtual CPU structure of the calling thread.
782 * @param pu16 Where to return the opcode word.
783 */
784DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT
785{
786 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
787 if (RT_LIKELY((uint8_t)offOpcode + 2 <= pVCpu->iem.s.cbOpcode))
788 {
789 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 2;
790# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
791 *pu16 = *(uint16_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
792# else
793 *pu16 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
794# endif
795 return VINF_SUCCESS;
796 }
797 return iemOpcodeGetNextU16Slow(pVCpu, pu16);
798}
799
800# else /* IEM_WITH_SETJMP */
801
802/**
803 * Fetches the next opcode word, longjmp on error.
804 *
805 * @returns The opcode word.
806 * @param pVCpu The cross context virtual CPU structure of the calling thread.
807 */
808DECL_INLINE_THROW(uint16_t) iemOpcodeGetNextU16Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
809{
810# ifdef IEM_WITH_CODE_TLB
811 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
812 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
813 if (RT_LIKELY( pbBuf != NULL
814 && offBuf + 2 <= pVCpu->iem.s.cbInstrBuf))
815 {
816 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 2;
817# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
818 return *(uint16_t const *)&pbBuf[offBuf];
819# else
820 return RT_MAKE_U16(pbBuf[offBuf], pbBuf[offBuf + 1]);
821# endif
822 }
823# else /* !IEM_WITH_CODE_TLB */
824 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
825 if (RT_LIKELY((uint8_t)offOpcode + 2 <= pVCpu->iem.s.cbOpcode))
826 {
827 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 2;
828# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
829 return *(uint16_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
830# else
831 return RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
832# endif
833 }
834# endif /* !IEM_WITH_CODE_TLB */
835 return iemOpcodeGetNextU16SlowJmp(pVCpu);
836}
837
838# endif /* IEM_WITH_SETJMP */
839
840/**
841 * Fetches the next opcode word, returns automatically on failure.
842 *
843 * @param a_pu16 Where to return the opcode word.
844 * @remark Implicitly references pVCpu.
845 */
846# ifndef IEM_WITH_SETJMP
847# define IEM_OPCODE_GET_NEXT_U16(a_pu16) \
848 do \
849 { \
850 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16(pVCpu, (a_pu16)); \
851 if (rcStrict2 != VINF_SUCCESS) \
852 return rcStrict2; \
853 } while (0)
854# else
855# define IEM_OPCODE_GET_NEXT_U16(a_pu16) (*(a_pu16) = iemOpcodeGetNextU16Jmp(pVCpu))
856# endif
857
858# ifndef IEM_WITH_SETJMP
859/**
860 * Fetches the next opcode word, zero extending it to a double word.
861 *
862 * @returns Strict VBox status code.
863 * @param pVCpu The cross context virtual CPU structure of the calling thread.
864 * @param pu32 Where to return the opcode double word.
865 */
866DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16ZxU32(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
867{
868 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
869 if (RT_UNLIKELY(offOpcode + 2 > pVCpu->iem.s.cbOpcode))
870 return iemOpcodeGetNextU16ZxU32Slow(pVCpu, pu32);
871
872 *pu32 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
873 pVCpu->iem.s.offOpcode = offOpcode + 2;
874 return VINF_SUCCESS;
875}
876# endif /* !IEM_WITH_SETJMP */
877
878/**
879 * Fetches the next opcode word and zero extends it to a double word, returns
880 * automatically on failure.
881 *
882 * @param a_pu32 Where to return the opcode double word.
883 * @remark Implicitly references pVCpu.
884 */
885# ifndef IEM_WITH_SETJMP
886# define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) \
887 do \
888 { \
889 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16ZxU32(pVCpu, (a_pu32)); \
890 if (rcStrict2 != VINF_SUCCESS) \
891 return rcStrict2; \
892 } while (0)
893# else
894# define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) (*(a_pu32) = iemOpcodeGetNextU16Jmp(pVCpu))
895# endif
896
897# ifndef IEM_WITH_SETJMP
898/**
899 * Fetches the next opcode word, zero extending it to a quad word.
900 *
901 * @returns Strict VBox status code.
902 * @param pVCpu The cross context virtual CPU structure of the calling thread.
903 * @param pu64 Where to return the opcode quad word.
904 */
905DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16ZxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
906{
907 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
908 if (RT_UNLIKELY(offOpcode + 2 > pVCpu->iem.s.cbOpcode))
909 return iemOpcodeGetNextU16ZxU64Slow(pVCpu, pu64);
910
911 *pu64 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
912 pVCpu->iem.s.offOpcode = offOpcode + 2;
913 return VINF_SUCCESS;
914}
915# endif /* !IEM_WITH_SETJMP */
916
917/**
918 * Fetches the next opcode word and zero extends it to a quad word, returns
919 * automatically on failure.
920 *
921 * @param a_pu64 Where to return the opcode quad word.
922 * @remark Implicitly references pVCpu.
923 */
924# ifndef IEM_WITH_SETJMP
925# define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) \
926 do \
927 { \
928 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16ZxU64(pVCpu, (a_pu64)); \
929 if (rcStrict2 != VINF_SUCCESS) \
930 return rcStrict2; \
931 } while (0)
932# else
933# define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) (*(a_pu64) = iemOpcodeGetNextU16Jmp(pVCpu))
934# endif
935
936
937# ifndef IEM_WITH_SETJMP
938/**
939 * Fetches the next signed word from the opcode stream.
940 *
941 * @returns Strict VBox status code.
942 * @param pVCpu The cross context virtual CPU structure of the calling thread.
943 * @param pi16 Where to return the signed word.
944 */
945DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS16(PVMCPUCC pVCpu, int16_t *pi16) RT_NOEXCEPT
946{
947 return iemOpcodeGetNextU16(pVCpu, (uint16_t *)pi16);
948}
949# endif /* !IEM_WITH_SETJMP */
950
951
952/**
953 * Fetches the next signed word from the opcode stream, returning automatically
954 * on failure.
955 *
956 * @param a_pi16 Where to return the signed word.
957 * @remark Implicitly references pVCpu.
958 */
959# ifndef IEM_WITH_SETJMP
960# define IEM_OPCODE_GET_NEXT_S16(a_pi16) \
961 do \
962 { \
963 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS16(pVCpu, (a_pi16)); \
964 if (rcStrict2 != VINF_SUCCESS) \
965 return rcStrict2; \
966 } while (0)
967# else
968# define IEM_OPCODE_GET_NEXT_S16(a_pi16) (*(a_pi16) = (int16_t)iemOpcodeGetNextU16Jmp(pVCpu))
969# endif
970
971# ifndef IEM_WITH_SETJMP
972
973/**
974 * Fetches the next opcode dword.
975 *
976 * @returns Strict VBox status code.
977 * @param pVCpu The cross context virtual CPU structure of the calling thread.
978 * @param pu32 Where to return the opcode double word.
979 */
980DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU32(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
981{
982 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
983 if (RT_LIKELY((uint8_t)offOpcode + 4 <= pVCpu->iem.s.cbOpcode))
984 {
985 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 4;
986# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
987 *pu32 = *(uint32_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
988# else
989 *pu32 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
990 pVCpu->iem.s.abOpcode[offOpcode + 1],
991 pVCpu->iem.s.abOpcode[offOpcode + 2],
992 pVCpu->iem.s.abOpcode[offOpcode + 3]);
993# endif
994 return VINF_SUCCESS;
995 }
996 return iemOpcodeGetNextU32Slow(pVCpu, pu32);
997}
998
999# else /* IEM_WITH_SETJMP */
1000
1001/**
1002 * Fetches the next opcode dword, longjmp on error.
1003 *
1004 * @returns The opcode dword.
1005 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1006 */
1007DECL_INLINE_THROW(uint32_t) iemOpcodeGetNextU32Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
1008{
1009# ifdef IEM_WITH_CODE_TLB
1010 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
1011 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
1012 if (RT_LIKELY( pbBuf != NULL
1013 && offBuf + 4 <= pVCpu->iem.s.cbInstrBuf))
1014 {
1015 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 4;
1016# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1017 return *(uint32_t const *)&pbBuf[offBuf];
1018# else
1019 return RT_MAKE_U32_FROM_U8(pbBuf[offBuf],
1020 pbBuf[offBuf + 1],
1021 pbBuf[offBuf + 2],
1022 pbBuf[offBuf + 3]);
1023# endif
1024 }
1025# else
1026 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
1027 if (RT_LIKELY((uint8_t)offOpcode + 4 <= pVCpu->iem.s.cbOpcode))
1028 {
1029 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 4;
1030# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1031 return *(uint32_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
1032# else
1033 return RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1034 pVCpu->iem.s.abOpcode[offOpcode + 1],
1035 pVCpu->iem.s.abOpcode[offOpcode + 2],
1036 pVCpu->iem.s.abOpcode[offOpcode + 3]);
1037# endif
1038 }
1039# endif
1040 return iemOpcodeGetNextU32SlowJmp(pVCpu);
1041}
1042
1043# endif /* IEM_WITH_SETJMP */
1044
1045/**
1046 * Fetches the next opcode dword, returns automatically on failure.
1047 *
1048 * @param a_pu32 Where to return the opcode dword.
1049 * @remark Implicitly references pVCpu.
1050 */
1051# ifndef IEM_WITH_SETJMP
1052# define IEM_OPCODE_GET_NEXT_U32(a_pu32) \
1053 do \
1054 { \
1055 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU32(pVCpu, (a_pu32)); \
1056 if (rcStrict2 != VINF_SUCCESS) \
1057 return rcStrict2; \
1058 } while (0)
1059# else
1060# define IEM_OPCODE_GET_NEXT_U32(a_pu32) (*(a_pu32) = iemOpcodeGetNextU32Jmp(pVCpu))
1061# endif
1062
1063# ifndef IEM_WITH_SETJMP
1064/**
1065 * Fetches the next opcode dword, zero extending it to a quad word.
1066 *
1067 * @returns Strict VBox status code.
1068 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1069 * @param pu64 Where to return the opcode quad word.
1070 */
1071DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU32ZxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
1072{
1073 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
1074 if (RT_UNLIKELY(offOpcode + 4 > pVCpu->iem.s.cbOpcode))
1075 return iemOpcodeGetNextU32ZxU64Slow(pVCpu, pu64);
1076
1077 *pu64 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1078 pVCpu->iem.s.abOpcode[offOpcode + 1],
1079 pVCpu->iem.s.abOpcode[offOpcode + 2],
1080 pVCpu->iem.s.abOpcode[offOpcode + 3]);
1081 pVCpu->iem.s.offOpcode = offOpcode + 4;
1082 return VINF_SUCCESS;
1083}
1084# endif /* !IEM_WITH_SETJMP */
1085
1086/**
1087 * Fetches the next opcode dword and zero extends it to a quad word, returns
1088 * automatically on failure.
1089 *
1090 * @param a_pu64 Where to return the opcode quad word.
1091 * @remark Implicitly references pVCpu.
1092 */
1093# ifndef IEM_WITH_SETJMP
1094# define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) \
1095 do \
1096 { \
1097 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU32ZxU64(pVCpu, (a_pu64)); \
1098 if (rcStrict2 != VINF_SUCCESS) \
1099 return rcStrict2; \
1100 } while (0)
1101# else
1102# define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) (*(a_pu64) = iemOpcodeGetNextU32Jmp(pVCpu))
1103# endif
1104
1105
1106# ifndef IEM_WITH_SETJMP
1107/**
1108 * Fetches the next signed double word from the opcode stream.
1109 *
1110 * @returns Strict VBox status code.
1111 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1112 * @param pi32 Where to return the signed double word.
1113 */
1114DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS32(PVMCPUCC pVCpu, int32_t *pi32) RT_NOEXCEPT
1115{
1116 return iemOpcodeGetNextU32(pVCpu, (uint32_t *)pi32);
1117}
1118# endif
1119
1120/**
1121 * Fetches the next signed double word from the opcode stream, returning
1122 * automatically on failure.
1123 *
1124 * @param a_pi32 Where to return the signed double word.
1125 * @remark Implicitly references pVCpu.
1126 */
1127# ifndef IEM_WITH_SETJMP
1128# define IEM_OPCODE_GET_NEXT_S32(a_pi32) \
1129 do \
1130 { \
1131 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS32(pVCpu, (a_pi32)); \
1132 if (rcStrict2 != VINF_SUCCESS) \
1133 return rcStrict2; \
1134 } while (0)
1135# else
1136# define IEM_OPCODE_GET_NEXT_S32(a_pi32) (*(a_pi32) = (int32_t)iemOpcodeGetNextU32Jmp(pVCpu))
1137# endif
1138
1139# ifndef IEM_WITH_SETJMP
1140/**
1141 * Fetches the next opcode dword, sign extending it into a quad word.
1142 *
1143 * @returns Strict VBox status code.
1144 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1145 * @param pu64 Where to return the opcode quad word.
1146 */
1147DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS32SxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
1148{
1149 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
1150 if (RT_UNLIKELY(offOpcode + 4 > pVCpu->iem.s.cbOpcode))
1151 return iemOpcodeGetNextS32SxU64Slow(pVCpu, pu64);
1152
1153 int32_t i32 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1154 pVCpu->iem.s.abOpcode[offOpcode + 1],
1155 pVCpu->iem.s.abOpcode[offOpcode + 2],
1156 pVCpu->iem.s.abOpcode[offOpcode + 3]);
1157 *pu64 = i32;
1158 pVCpu->iem.s.offOpcode = offOpcode + 4;
1159 return VINF_SUCCESS;
1160}
1161# endif /* !IEM_WITH_SETJMP */
1162
1163/**
1164 * Fetches the next opcode double word and sign extends it to a quad word,
1165 * returns automatically on failure.
1166 *
1167 * @param a_pu64 Where to return the opcode quad word.
1168 * @remark Implicitly references pVCpu.
1169 */
1170# ifndef IEM_WITH_SETJMP
1171# define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) \
1172 do \
1173 { \
1174 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS32SxU64(pVCpu, (a_pu64)); \
1175 if (rcStrict2 != VINF_SUCCESS) \
1176 return rcStrict2; \
1177 } while (0)
1178# else
1179# define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) (*(a_pu64) = (int32_t)iemOpcodeGetNextU32Jmp(pVCpu))
1180# endif
1181
1182# ifndef IEM_WITH_SETJMP
1183
1184/**
1185 * Fetches the next opcode qword.
1186 *
1187 * @returns Strict VBox status code.
1188 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1189 * @param pu64 Where to return the opcode qword.
1190 */
1191DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
1192{
1193 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
1194 if (RT_LIKELY((uint8_t)offOpcode + 8 <= pVCpu->iem.s.cbOpcode))
1195 {
1196# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1197 *pu64 = *(uint64_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
1198# else
1199 *pu64 = RT_MAKE_U64_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1200 pVCpu->iem.s.abOpcode[offOpcode + 1],
1201 pVCpu->iem.s.abOpcode[offOpcode + 2],
1202 pVCpu->iem.s.abOpcode[offOpcode + 3],
1203 pVCpu->iem.s.abOpcode[offOpcode + 4],
1204 pVCpu->iem.s.abOpcode[offOpcode + 5],
1205 pVCpu->iem.s.abOpcode[offOpcode + 6],
1206 pVCpu->iem.s.abOpcode[offOpcode + 7]);
1207# endif
1208 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 8;
1209 return VINF_SUCCESS;
1210 }
1211 return iemOpcodeGetNextU64Slow(pVCpu, pu64);
1212}
1213
1214# else /* IEM_WITH_SETJMP */
1215
1216/**
1217 * Fetches the next opcode qword, longjmp on error.
1218 *
1219 * @returns The opcode qword.
1220 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1221 */
1222DECL_INLINE_THROW(uint64_t) iemOpcodeGetNextU64Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
1223{
1224# ifdef IEM_WITH_CODE_TLB
1225 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
1226 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
1227 if (RT_LIKELY( pbBuf != NULL
1228 && offBuf + 8 <= pVCpu->iem.s.cbInstrBuf))
1229 {
1230 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 8;
1231# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1232 return *(uint64_t const *)&pbBuf[offBuf];
1233# else
1234 return RT_MAKE_U64_FROM_U8(pbBuf[offBuf],
1235 pbBuf[offBuf + 1],
1236 pbBuf[offBuf + 2],
1237 pbBuf[offBuf + 3],
1238 pbBuf[offBuf + 4],
1239 pbBuf[offBuf + 5],
1240 pbBuf[offBuf + 6],
1241 pbBuf[offBuf + 7]);
1242# endif
1243 }
1244# else
1245 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
1246 if (RT_LIKELY((uint8_t)offOpcode + 8 <= pVCpu->iem.s.cbOpcode))
1247 {
1248 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 8;
1249# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1250 return *(uint64_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
1251# else
1252 return RT_MAKE_U64_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1253 pVCpu->iem.s.abOpcode[offOpcode + 1],
1254 pVCpu->iem.s.abOpcode[offOpcode + 2],
1255 pVCpu->iem.s.abOpcode[offOpcode + 3],
1256 pVCpu->iem.s.abOpcode[offOpcode + 4],
1257 pVCpu->iem.s.abOpcode[offOpcode + 5],
1258 pVCpu->iem.s.abOpcode[offOpcode + 6],
1259 pVCpu->iem.s.abOpcode[offOpcode + 7]);
1260# endif
1261 }
1262# endif
1263 return iemOpcodeGetNextU64SlowJmp(pVCpu);
1264}
1265
1266# endif /* IEM_WITH_SETJMP */
1267
1268/**
1269 * Fetches the next opcode quad word, returns automatically on failure.
1270 *
1271 * @param a_pu64 Where to return the opcode quad word.
1272 * @remark Implicitly references pVCpu.
1273 */
1274# ifndef IEM_WITH_SETJMP
1275# define IEM_OPCODE_GET_NEXT_U64(a_pu64) \
1276 do \
1277 { \
1278 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU64(pVCpu, (a_pu64)); \
1279 if (rcStrict2 != VINF_SUCCESS) \
1280 return rcStrict2; \
1281 } while (0)
1282# else
1283# define IEM_OPCODE_GET_NEXT_U64(a_pu64) ( *(a_pu64) = iemOpcodeGetNextU64Jmp(pVCpu) )
1284# endif
1285
1286#endif /* !IEM_WITH_OPAQUE_DECODER_STATE */
1287
1288
1289/** @name Misc Worker Functions.
1290 * @{
1291 */
1292
1293/**
1294 * Gets the correct EFLAGS regardless of whether PATM stores parts of them or
1295 * not (kind of obsolete now).
1296 *
1297 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1298 */
1299#define IEMMISC_GET_EFL(a_pVCpu) ( (a_pVCpu)->cpum.GstCtx.eflags.u )
1300
1301/**
1302 * Updates the EFLAGS in the correct manner wrt. PATM (kind of obsolete).
1303 *
1304 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1305 * @param a_fEfl The new EFLAGS.
1306 */
1307#define IEMMISC_SET_EFL(a_pVCpu, a_fEfl) do { (a_pVCpu)->cpum.GstCtx.eflags.u = (a_fEfl); } while (0)
1308
1309
1310/**
1311 * Loads a NULL data selector into a selector register, both the hidden and
1312 * visible parts, in protected mode.
1313 *
1314 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1315 * @param pSReg Pointer to the segment register.
1316 * @param uRpl The RPL.
1317 */
1318DECLINLINE(void) iemHlpLoadNullDataSelectorProt(PVMCPUCC pVCpu, PCPUMSELREG pSReg, RTSEL uRpl) RT_NOEXCEPT
1319{
1320 /** @todo Testcase: write a testcase checking what happends when loading a NULL
1321 * data selector in protected mode. */
1322 pSReg->Sel = uRpl;
1323 pSReg->ValidSel = uRpl;
1324 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
1325 if (IEM_IS_GUEST_CPU_INTEL(pVCpu))
1326 {
1327 /* VT-x (Intel 3960x) observed doing something like this. */
1328 pSReg->Attr.u = X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D | (pVCpu->iem.s.uCpl << X86DESCATTR_DPL_SHIFT);
1329 pSReg->u32Limit = UINT32_MAX;
1330 pSReg->u64Base = 0;
1331 }
1332 else
1333 {
1334 pSReg->Attr.u = X86DESCATTR_UNUSABLE;
1335 pSReg->u32Limit = 0;
1336 pSReg->u64Base = 0;
1337 }
1338}
1339
1340/** @} */
1341
1342
1343/*
1344 *
1345 * Helpers routines.
1346 * Helpers routines.
1347 * Helpers routines.
1348 *
1349 */
1350
1351#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1352
1353/**
1354 * Recalculates the effective operand size.
1355 *
1356 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1357 */
1358DECLINLINE(void) iemRecalEffOpSize(PVMCPUCC pVCpu) RT_NOEXCEPT
1359{
1360 switch (pVCpu->iem.s.enmCpuMode)
1361 {
1362 case IEMMODE_16BIT:
1363 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP ? IEMMODE_32BIT : IEMMODE_16BIT;
1364 break;
1365 case IEMMODE_32BIT:
1366 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP ? IEMMODE_16BIT : IEMMODE_32BIT;
1367 break;
1368 case IEMMODE_64BIT:
1369 switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_REX_W | IEM_OP_PRF_SIZE_OP))
1370 {
1371 case 0:
1372 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize;
1373 break;
1374 case IEM_OP_PRF_SIZE_OP:
1375 pVCpu->iem.s.enmEffOpSize = IEMMODE_16BIT;
1376 break;
1377 case IEM_OP_PRF_SIZE_REX_W:
1378 case IEM_OP_PRF_SIZE_REX_W | IEM_OP_PRF_SIZE_OP:
1379 pVCpu->iem.s.enmEffOpSize = IEMMODE_64BIT;
1380 break;
1381 }
1382 break;
1383 default:
1384 AssertFailed();
1385 }
1386}
1387
1388
1389/**
1390 * Sets the default operand size to 64-bit and recalculates the effective
1391 * operand size.
1392 *
1393 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1394 */
1395DECLINLINE(void) iemRecalEffOpSize64Default(PVMCPUCC pVCpu) RT_NOEXCEPT
1396{
1397 Assert(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
1398 pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
1399 if ((pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_REX_W | IEM_OP_PRF_SIZE_OP)) != IEM_OP_PRF_SIZE_OP)
1400 pVCpu->iem.s.enmEffOpSize = IEMMODE_64BIT;
1401 else
1402 pVCpu->iem.s.enmEffOpSize = IEMMODE_16BIT;
1403}
1404
1405
1406/**
1407 * Sets the default operand size to 64-bit and recalculates the effective
1408 * operand size, with intel ignoring any operand size prefix (AMD respects it).
1409 *
1410 * This is for the relative jumps.
1411 *
1412 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1413 */
1414DECLINLINE(void) iemRecalEffOpSize64DefaultAndIntelIgnoresOpSizePrefix(PVMCPUCC pVCpu) RT_NOEXCEPT
1415{
1416 Assert(pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT);
1417 pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
1418 if ( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_REX_W | IEM_OP_PRF_SIZE_OP)) != IEM_OP_PRF_SIZE_OP
1419 || pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1420 pVCpu->iem.s.enmEffOpSize = IEMMODE_64BIT;
1421 else
1422 pVCpu->iem.s.enmEffOpSize = IEMMODE_16BIT;
1423}
1424
1425#endif /* !IEM_WITH_OPAQUE_DECODER_STATE */
1426
1427
1428
1429/** @name Register Access.
1430 * @{
1431 */
1432
1433/**
1434 * Gets a reference (pointer) to the specified hidden segment register.
1435 *
1436 * @returns Hidden register reference.
1437 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1438 * @param iSegReg The segment register.
1439 */
1440DECLINLINE(PCPUMSELREG) iemSRegGetHid(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
1441{
1442 Assert(iSegReg < X86_SREG_COUNT);
1443 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
1444 PCPUMSELREG pSReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1445
1446 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
1447 return pSReg;
1448}
1449
1450
1451/**
1452 * Ensures that the given hidden segment register is up to date.
1453 *
1454 * @returns Hidden register reference.
1455 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1456 * @param pSReg The segment register.
1457 */
1458DECLINLINE(PCPUMSELREG) iemSRegUpdateHid(PVMCPUCC pVCpu, PCPUMSELREG pSReg) RT_NOEXCEPT
1459{
1460 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
1461 NOREF(pVCpu);
1462 return pSReg;
1463}
1464
1465
1466/**
1467 * Gets a reference (pointer) to the specified segment register (the selector
1468 * value).
1469 *
1470 * @returns Pointer to the selector variable.
1471 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1472 * @param iSegReg The segment register.
1473 */
1474DECLINLINE(uint16_t *) iemSRegRef(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
1475{
1476 Assert(iSegReg < X86_SREG_COUNT);
1477 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
1478 return &pVCpu->cpum.GstCtx.aSRegs[iSegReg].Sel;
1479}
1480
1481
1482/**
1483 * Fetches the selector value of a segment register.
1484 *
1485 * @returns The selector value.
1486 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1487 * @param iSegReg The segment register.
1488 */
1489DECLINLINE(uint16_t) iemSRegFetchU16(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
1490{
1491 Assert(iSegReg < X86_SREG_COUNT);
1492 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
1493 return pVCpu->cpum.GstCtx.aSRegs[iSegReg].Sel;
1494}
1495
1496
1497/**
1498 * Fetches the base address value of a segment register.
1499 *
1500 * @returns The selector value.
1501 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1502 * @param iSegReg The segment register.
1503 */
1504DECLINLINE(uint64_t) iemSRegBaseFetchU64(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
1505{
1506 Assert(iSegReg < X86_SREG_COUNT);
1507 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
1508 return pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base;
1509}
1510
1511
1512/**
1513 * Gets a reference (pointer) to the specified general purpose register.
1514 *
1515 * @returns Register reference.
1516 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1517 * @param iReg The general purpose register.
1518 */
1519DECLINLINE(void *) iemGRegRef(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1520{
1521 Assert(iReg < 16);
1522 return &pVCpu->cpum.GstCtx.aGRegs[iReg];
1523}
1524
1525
1526#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1527/**
1528 * Gets a reference (pointer) to the specified 8-bit general purpose register.
1529 *
1530 * Because of AH, CH, DH and BH we cannot use iemGRegRef directly here.
1531 *
1532 * @returns Register reference.
1533 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1534 * @param iReg The register.
1535 */
1536DECLINLINE(uint8_t *) iemGRegRefU8(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1537{
1538 if (iReg < 4 || (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX))
1539 {
1540 Assert(iReg < 16);
1541 return &pVCpu->cpum.GstCtx.aGRegs[iReg].u8;
1542 }
1543 /* high 8-bit register. */
1544 Assert(iReg < 8);
1545 return &pVCpu->cpum.GstCtx.aGRegs[iReg & 3].bHi;
1546}
1547#endif
1548
1549
1550/**
1551 * Gets a reference (pointer) to the specified 16-bit general purpose register.
1552 *
1553 * @returns Register reference.
1554 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1555 * @param iReg The register.
1556 */
1557DECLINLINE(uint16_t *) iemGRegRefU16(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1558{
1559 Assert(iReg < 16);
1560 return &pVCpu->cpum.GstCtx.aGRegs[iReg].u16;
1561}
1562
1563
1564/**
1565 * Gets a reference (pointer) to the specified 32-bit general purpose register.
1566 *
1567 * @returns Register reference.
1568 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1569 * @param iReg The register.
1570 */
1571DECLINLINE(uint32_t *) iemGRegRefU32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1572{
1573 Assert(iReg < 16);
1574 return &pVCpu->cpum.GstCtx.aGRegs[iReg].u32;
1575}
1576
1577
1578/**
1579 * Gets a reference (pointer) to the specified signed 32-bit general purpose register.
1580 *
1581 * @returns Register reference.
1582 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1583 * @param iReg The register.
1584 */
1585DECLINLINE(int32_t *) iemGRegRefI32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1586{
1587 Assert(iReg < 16);
1588 return (int32_t *)&pVCpu->cpum.GstCtx.aGRegs[iReg].u32;
1589}
1590
1591
1592/**
1593 * Gets a reference (pointer) to the specified 64-bit general purpose register.
1594 *
1595 * @returns Register reference.
1596 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1597 * @param iReg The register.
1598 */
1599DECLINLINE(uint64_t *) iemGRegRefU64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1600{
1601 Assert(iReg < 64);
1602 return &pVCpu->cpum.GstCtx.aGRegs[iReg].u64;
1603}
1604
1605
1606/**
1607 * Gets a reference (pointer) to the specified signed 64-bit general purpose register.
1608 *
1609 * @returns Register reference.
1610 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1611 * @param iReg The register.
1612 */
1613DECLINLINE(int64_t *) iemGRegRefI64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1614{
1615 Assert(iReg < 16);
1616 return (int64_t *)&pVCpu->cpum.GstCtx.aGRegs[iReg].u64;
1617}
1618
1619
1620/**
1621 * Gets a reference (pointer) to the specified segment register's base address.
1622 *
1623 * @returns Segment register base address reference.
1624 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1625 * @param iSegReg The segment selector.
1626 */
1627DECLINLINE(uint64_t *) iemSRegBaseRefU64(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
1628{
1629 Assert(iSegReg < X86_SREG_COUNT);
1630 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
1631 return &pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base;
1632}
1633
1634
1635#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1636/**
1637 * Fetches the value of a 8-bit general purpose register.
1638 *
1639 * @returns The register value.
1640 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1641 * @param iReg The register.
1642 */
1643DECLINLINE(uint8_t) iemGRegFetchU8(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1644{
1645 return *iemGRegRefU8(pVCpu, iReg);
1646}
1647#endif
1648
1649
1650/**
1651 * Fetches the value of a 16-bit general purpose register.
1652 *
1653 * @returns The register value.
1654 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1655 * @param iReg The register.
1656 */
1657DECLINLINE(uint16_t) iemGRegFetchU16(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1658{
1659 Assert(iReg < 16);
1660 return pVCpu->cpum.GstCtx.aGRegs[iReg].u16;
1661}
1662
1663
1664/**
1665 * Fetches the value of a 32-bit general purpose register.
1666 *
1667 * @returns The register value.
1668 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1669 * @param iReg The register.
1670 */
1671DECLINLINE(uint32_t) iemGRegFetchU32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1672{
1673 Assert(iReg < 16);
1674 return pVCpu->cpum.GstCtx.aGRegs[iReg].u32;
1675}
1676
1677
1678/**
1679 * Fetches the value of a 64-bit general purpose register.
1680 *
1681 * @returns The register value.
1682 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1683 * @param iReg The register.
1684 */
1685DECLINLINE(uint64_t) iemGRegFetchU64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1686{
1687 Assert(iReg < 16);
1688 return pVCpu->cpum.GstCtx.aGRegs[iReg].u64;
1689}
1690
1691
1692/**
1693 * Get the address of the top of the stack.
1694 *
1695 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1696 */
1697DECLINLINE(RTGCPTR) iemRegGetEffRsp(PCVMCPU pVCpu) RT_NOEXCEPT
1698{
1699 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
1700 return pVCpu->cpum.GstCtx.rsp;
1701 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
1702 return pVCpu->cpum.GstCtx.esp;
1703 return pVCpu->cpum.GstCtx.sp;
1704}
1705
1706
1707/**
1708 * Updates the RIP/EIP/IP to point to the next instruction.
1709 *
1710 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1711 * @param cbInstr The number of bytes to add.
1712 */
1713DECL_FORCE_INLINE(void) iemRegAddToRip(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
1714{
1715 /*
1716 * Advance RIP.
1717 *
1718 * When we're targetting 8086/8, 80186/8 or 80286 mode the updates are 16-bit,
1719 * while in all other modes except LM64 the updates are 32-bit. This means
1720 * we need to watch for both 32-bit and 16-bit "carry" situations, i.e.
1721 * 4GB and 64KB rollovers, and decide whether anything needs masking.
1722 *
1723 * See PC wrap around tests in bs3-cpu-weird-1.
1724 */
1725 uint64_t const uRipPrev = pVCpu->cpum.GstCtx.rip;
1726 uint64_t const uRipNext = uRipPrev + cbInstr;
1727 if (RT_LIKELY( !((uRipNext ^ uRipPrev) & (RT_BIT_64(32) | RT_BIT_64(16)))
1728 || pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT))
1729 pVCpu->cpum.GstCtx.rip = uRipNext;
1730 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
1731 pVCpu->cpum.GstCtx.rip = (uint32_t)uRipNext;
1732 else
1733 pVCpu->cpum.GstCtx.rip = (uint16_t)uRipNext;
1734}
1735
1736
1737/**
1738 * Called by iemRegAddToRipAndFinishingClearingRF and others when any of the
1739 * following EFLAGS bits are set:
1740 * - X86_EFL_RF - clear it.
1741 * - CPUMCTX_INHIBIT_SHADOW (_SS/_STI) - clear them.
1742 * - X86_EFL_TF - generate single step \#DB trap.
1743 * - CPUMCTX_DBG_HIT_DR0/1/2/3 - generate \#DB trap (data or I/O, not
1744 * instruction).
1745 *
1746 * According to @sdmv3{077,200,Table 6-2,Priority Among Concurrent Events},
1747 * a \#DB due to TF (single stepping) or a DRx non-instruction breakpoint
1748 * takes priority over both NMIs and hardware interrupts. So, neither is
1749 * considered here. (The RESET, \#MC, SMI, INIT, STOPCLK and FLUSH events are
1750 * either unsupported will be triggered on-top of any \#DB raised here.)
1751 *
1752 * The RF flag only needs to be cleared here as it only suppresses instruction
1753 * breakpoints which are not raised here (happens synchronously during
1754 * instruction fetching).
1755 *
1756 * The CPUMCTX_INHIBIT_SHADOW_SS flag will be cleared by this function, so its
1757 * status has no bearing on whether \#DB exceptions are raised.
1758 *
1759 * @note This must *NOT* be called by the two instructions setting the
1760 * CPUMCTX_INHIBIT_SHADOW_SS flag.
1761 *
1762 * @see @sdmv3{077,200,Table 6-2,Priority Among Concurrent Events}
1763 * @see @sdmv3{077,200,6.8.3,Masking Exceptions and Interrupts When Switching
1764 * Stacks}
1765 */
1766static VBOXSTRICTRC iemFinishInstructionWithFlagsSet(PVMCPUCC pVCpu) RT_NOEXCEPT
1767{
1768 /*
1769 * Normally we're just here to clear RF and/or interrupt shadow bits.
1770 */
1771 if (RT_LIKELY((pVCpu->cpum.GstCtx.eflags.uBoth & (X86_EFL_TF | CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK)) == 0))
1772 pVCpu->cpum.GstCtx.eflags.uBoth &= ~(X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW);
1773 else
1774 {
1775 /*
1776 * Raise a #DB or/and DBGF event.
1777 */
1778 VBOXSTRICTRC rcStrict;
1779 if (pVCpu->cpum.GstCtx.eflags.uBoth & (X86_EFL_TF | CPUMCTX_DBG_HIT_DRX_MASK))
1780 {
1781 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
1782 pVCpu->cpum.GstCtx.dr[6] &= ~X86_DR6_B_MASK;
1783 if (pVCpu->cpum.GstCtx.eflags.uBoth & X86_EFL_TF)
1784 pVCpu->cpum.GstCtx.dr[6] |= X86_DR6_BS;
1785 pVCpu->cpum.GstCtx.dr[6] |= (pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_HIT_DRX_MASK) >> CPUMCTX_DBG_HIT_DRX_SHIFT;
1786 LogFlowFunc(("Guest #DB fired at %04X:%016llX: DR6=%08X, RFLAGS=%16RX64\n",
1787 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, (unsigned)pVCpu->cpum.GstCtx.dr[6],
1788 pVCpu->cpum.GstCtx.rflags.uBoth));
1789
1790 pVCpu->cpum.GstCtx.eflags.uBoth &= ~(X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW | CPUMCTX_DBG_HIT_DRX_MASK);
1791 rcStrict = iemRaiseDebugException(pVCpu);
1792
1793 /* A DBGF event/breakpoint trumps the iemRaiseDebugException informational status code. */
1794 if ((pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_DBGF_MASK) && RT_FAILURE(rcStrict))
1795 {
1796 rcStrict = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_DBGF_BP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_EVENT;
1797 LogFlowFunc(("dbgf at %04X:%016llX: %Rrc\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, VBOXSTRICTRC_VAL(rcStrict)));
1798 }
1799 }
1800 else
1801 {
1802 Assert(pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_DBGF_MASK);
1803 rcStrict = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_DBGF_BP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_EVENT;
1804 LogFlowFunc(("dbgf at %04X:%016llX: %Rrc\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, VBOXSTRICTRC_VAL(rcStrict)));
1805 }
1806 pVCpu->cpum.GstCtx.eflags.uBoth &= ~CPUMCTX_DBG_DBGF_MASK;
1807 return rcStrict;
1808 }
1809 return VINF_SUCCESS;
1810}
1811
1812
1813/**
1814 * Clears the RF and CPUMCTX_INHIBIT_SHADOW, triggering \#DB if pending.
1815 *
1816 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1817 */
1818DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegFinishClearingRF(PVMCPUCC pVCpu) RT_NOEXCEPT
1819{
1820 /*
1821 * We assume that most of the time nothing actually needs doing here.
1822 */
1823 AssertCompile(CPUMCTX_INHIBIT_SHADOW < UINT32_MAX);
1824 if (RT_LIKELY(!( pVCpu->cpum.GstCtx.eflags.uBoth
1825 & (X86_EFL_TF | X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW | CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK)) ))
1826 return VINF_SUCCESS;
1827 return iemFinishInstructionWithFlagsSet(pVCpu);
1828}
1829
1830
1831/**
1832 * Updates the RIP/EIP/IP to point to the next instruction and clears EFLAGS.RF
1833 * and CPUMCTX_INHIBIT_SHADOW.
1834 *
1835 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1836 * @param cbInstr The number of bytes to add.
1837 */
1838DECLINLINE(VBOXSTRICTRC) iemRegAddToRipAndFinishingClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
1839{
1840 iemRegAddToRip(pVCpu, cbInstr);
1841 return iemRegFinishClearingRF(pVCpu);
1842}
1843
1844
1845/**
1846 * Extended version of iemFinishInstructionWithFlagsSet that goes with
1847 * iemRegAddToRipAndFinishingClearingRfEx.
1848 *
1849 * See iemFinishInstructionWithFlagsSet() for details.
1850 */
1851static VBOXSTRICTRC iemFinishInstructionWithTfSet(PVMCPUCC pVCpu) RT_NOEXCEPT
1852{
1853 /*
1854 * Raise a #DB.
1855 */
1856 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
1857 pVCpu->cpum.GstCtx.dr[6] &= ~X86_DR6_B_MASK;
1858 pVCpu->cpum.GstCtx.dr[6] |= X86_DR6_BS
1859 | (pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_HIT_DRX_MASK) >> CPUMCTX_DBG_HIT_DRX_SHIFT;
1860 /** @todo Do we set all pending \#DB events, or just one? */
1861 LogFlowFunc(("Guest #DB fired at %04X:%016llX: DR6=%08X, RFLAGS=%16RX64 (popf)\n",
1862 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, (unsigned)pVCpu->cpum.GstCtx.dr[6],
1863 pVCpu->cpum.GstCtx.rflags.uBoth));
1864 pVCpu->cpum.GstCtx.eflags.uBoth &= ~(X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW | CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK);
1865 return iemRaiseDebugException(pVCpu);
1866}
1867
1868
1869/**
1870 * Extended version of iemRegAddToRipAndFinishingClearingRF for use by POPF and
1871 * others potentially updating EFLAGS.TF.
1872 *
1873 * The single step event must be generated using the TF value at the start of
1874 * the instruction, not the new value set by it.
1875 *
1876 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1877 * @param cbInstr The number of bytes to add.
1878 * @param fEflOld The EFLAGS at the start of the instruction
1879 * execution.
1880 */
1881DECLINLINE(VBOXSTRICTRC) iemRegAddToRipAndFinishingClearingRfEx(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t fEflOld) RT_NOEXCEPT
1882{
1883 iemRegAddToRip(pVCpu, cbInstr);
1884 if (!(fEflOld & X86_EFL_TF))
1885 return iemRegFinishClearingRF(pVCpu);
1886 return iemFinishInstructionWithTfSet(pVCpu);
1887}
1888
1889
1890#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1891/**
1892 * Updates the RIP/EIP/IP to point to the next instruction and clears EFLAGS.RF.
1893 *
1894 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1895 */
1896DECLINLINE(VBOXSTRICTRC) iemRegUpdateRipAndFinishClearingRF(PVMCPUCC pVCpu) RT_NOEXCEPT
1897{
1898 return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu));
1899}
1900#endif
1901
1902
1903/**
1904 * Adds to the stack pointer.
1905 *
1906 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1907 * @param cbToAdd The number of bytes to add (8-bit!).
1908 */
1909DECLINLINE(void) iemRegAddToRsp(PVMCPUCC pVCpu, uint8_t cbToAdd) RT_NOEXCEPT
1910{
1911 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
1912 pVCpu->cpum.GstCtx.rsp += cbToAdd;
1913 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
1914 pVCpu->cpum.GstCtx.esp += cbToAdd;
1915 else
1916 pVCpu->cpum.GstCtx.sp += cbToAdd;
1917}
1918
1919
1920/**
1921 * Subtracts from the stack pointer.
1922 *
1923 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1924 * @param cbToSub The number of bytes to subtract (8-bit!).
1925 */
1926DECLINLINE(void) iemRegSubFromRsp(PVMCPUCC pVCpu, uint8_t cbToSub) RT_NOEXCEPT
1927{
1928 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
1929 pVCpu->cpum.GstCtx.rsp -= cbToSub;
1930 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
1931 pVCpu->cpum.GstCtx.esp -= cbToSub;
1932 else
1933 pVCpu->cpum.GstCtx.sp -= cbToSub;
1934}
1935
1936
1937/**
1938 * Adds to the temporary stack pointer.
1939 *
1940 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1941 * @param pTmpRsp The temporary SP/ESP/RSP to update.
1942 * @param cbToAdd The number of bytes to add (16-bit).
1943 */
1944DECLINLINE(void) iemRegAddToRspEx(PCVMCPU pVCpu, PRTUINT64U pTmpRsp, uint16_t cbToAdd) RT_NOEXCEPT
1945{
1946 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
1947 pTmpRsp->u += cbToAdd;
1948 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
1949 pTmpRsp->DWords.dw0 += cbToAdd;
1950 else
1951 pTmpRsp->Words.w0 += cbToAdd;
1952}
1953
1954
1955/**
1956 * Subtracts from the temporary stack pointer.
1957 *
1958 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1959 * @param pTmpRsp The temporary SP/ESP/RSP to update.
1960 * @param cbToSub The number of bytes to subtract.
1961 * @remarks The @a cbToSub argument *MUST* be 16-bit, iemCImpl_enter is
1962 * expecting that.
1963 */
1964DECLINLINE(void) iemRegSubFromRspEx(PCVMCPU pVCpu, PRTUINT64U pTmpRsp, uint16_t cbToSub) RT_NOEXCEPT
1965{
1966 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
1967 pTmpRsp->u -= cbToSub;
1968 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
1969 pTmpRsp->DWords.dw0 -= cbToSub;
1970 else
1971 pTmpRsp->Words.w0 -= cbToSub;
1972}
1973
1974
1975/**
1976 * Calculates the effective stack address for a push of the specified size as
1977 * well as the new RSP value (upper bits may be masked).
1978 *
1979 * @returns Effective stack addressf for the push.
1980 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1981 * @param cbItem The size of the stack item to pop.
1982 * @param puNewRsp Where to return the new RSP value.
1983 */
1984DECLINLINE(RTGCPTR) iemRegGetRspForPush(PCVMCPU pVCpu, uint8_t cbItem, uint64_t *puNewRsp) RT_NOEXCEPT
1985{
1986 RTUINT64U uTmpRsp;
1987 RTGCPTR GCPtrTop;
1988 uTmpRsp.u = pVCpu->cpum.GstCtx.rsp;
1989
1990 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
1991 GCPtrTop = uTmpRsp.u -= cbItem;
1992 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
1993 GCPtrTop = uTmpRsp.DWords.dw0 -= cbItem;
1994 else
1995 GCPtrTop = uTmpRsp.Words.w0 -= cbItem;
1996 *puNewRsp = uTmpRsp.u;
1997 return GCPtrTop;
1998}
1999
2000
2001/**
2002 * Gets the current stack pointer and calculates the value after a pop of the
2003 * specified size.
2004 *
2005 * @returns Current stack pointer.
2006 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2007 * @param cbItem The size of the stack item to pop.
2008 * @param puNewRsp Where to return the new RSP value.
2009 */
2010DECLINLINE(RTGCPTR) iemRegGetRspForPop(PCVMCPU pVCpu, uint8_t cbItem, uint64_t *puNewRsp) RT_NOEXCEPT
2011{
2012 RTUINT64U uTmpRsp;
2013 RTGCPTR GCPtrTop;
2014 uTmpRsp.u = pVCpu->cpum.GstCtx.rsp;
2015
2016 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2017 {
2018 GCPtrTop = uTmpRsp.u;
2019 uTmpRsp.u += cbItem;
2020 }
2021 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2022 {
2023 GCPtrTop = uTmpRsp.DWords.dw0;
2024 uTmpRsp.DWords.dw0 += cbItem;
2025 }
2026 else
2027 {
2028 GCPtrTop = uTmpRsp.Words.w0;
2029 uTmpRsp.Words.w0 += cbItem;
2030 }
2031 *puNewRsp = uTmpRsp.u;
2032 return GCPtrTop;
2033}
2034
2035
2036/**
2037 * Calculates the effective stack address for a push of the specified size as
2038 * well as the new temporary RSP value (upper bits may be masked).
2039 *
2040 * @returns Effective stack addressf for the push.
2041 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2042 * @param pTmpRsp The temporary stack pointer. This is updated.
2043 * @param cbItem The size of the stack item to pop.
2044 */
2045DECLINLINE(RTGCPTR) iemRegGetRspForPushEx(PCVMCPU pVCpu, PRTUINT64U pTmpRsp, uint8_t cbItem) RT_NOEXCEPT
2046{
2047 RTGCPTR GCPtrTop;
2048
2049 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2050 GCPtrTop = pTmpRsp->u -= cbItem;
2051 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2052 GCPtrTop = pTmpRsp->DWords.dw0 -= cbItem;
2053 else
2054 GCPtrTop = pTmpRsp->Words.w0 -= cbItem;
2055 return GCPtrTop;
2056}
2057
2058
2059/**
2060 * Gets the effective stack address for a pop of the specified size and
2061 * calculates and updates the temporary RSP.
2062 *
2063 * @returns Current stack pointer.
2064 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2065 * @param pTmpRsp The temporary stack pointer. This is updated.
2066 * @param cbItem The size of the stack item to pop.
2067 */
2068DECLINLINE(RTGCPTR) iemRegGetRspForPopEx(PCVMCPU pVCpu, PRTUINT64U pTmpRsp, uint8_t cbItem) RT_NOEXCEPT
2069{
2070 RTGCPTR GCPtrTop;
2071 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2072 {
2073 GCPtrTop = pTmpRsp->u;
2074 pTmpRsp->u += cbItem;
2075 }
2076 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2077 {
2078 GCPtrTop = pTmpRsp->DWords.dw0;
2079 pTmpRsp->DWords.dw0 += cbItem;
2080 }
2081 else
2082 {
2083 GCPtrTop = pTmpRsp->Words.w0;
2084 pTmpRsp->Words.w0 += cbItem;
2085 }
2086 return GCPtrTop;
2087}
2088
2089/** @} */
2090
2091
2092/** @name FPU access and helpers.
2093 *
2094 * @{
2095 */
2096
2097
2098/**
2099 * Hook for preparing to use the host FPU.
2100 *
2101 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2102 *
2103 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2104 */
2105DECLINLINE(void) iemFpuPrepareUsage(PVMCPUCC pVCpu) RT_NOEXCEPT
2106{
2107#ifdef IN_RING3
2108 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
2109#else
2110 CPUMRZFpuStatePrepareHostCpuForUse(pVCpu);
2111#endif
2112 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2113}
2114
2115
2116/**
2117 * Hook for preparing to use the host FPU for SSE.
2118 *
2119 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2120 *
2121 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2122 */
2123DECLINLINE(void) iemFpuPrepareUsageSse(PVMCPUCC pVCpu) RT_NOEXCEPT
2124{
2125 iemFpuPrepareUsage(pVCpu);
2126}
2127
2128
2129/**
2130 * Hook for preparing to use the host FPU for AVX.
2131 *
2132 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2133 *
2134 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2135 */
2136DECLINLINE(void) iemFpuPrepareUsageAvx(PVMCPUCC pVCpu) RT_NOEXCEPT
2137{
2138 iemFpuPrepareUsage(pVCpu);
2139}
2140
2141
2142/**
2143 * Hook for actualizing the guest FPU state before the interpreter reads it.
2144 *
2145 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2146 *
2147 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2148 */
2149DECLINLINE(void) iemFpuActualizeStateForRead(PVMCPUCC pVCpu) RT_NOEXCEPT
2150{
2151#ifdef IN_RING3
2152 NOREF(pVCpu);
2153#else
2154 CPUMRZFpuStateActualizeForRead(pVCpu);
2155#endif
2156 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2157}
2158
2159
2160/**
2161 * Hook for actualizing the guest FPU state before the interpreter changes it.
2162 *
2163 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2164 *
2165 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2166 */
2167DECLINLINE(void) iemFpuActualizeStateForChange(PVMCPUCC pVCpu) RT_NOEXCEPT
2168{
2169#ifdef IN_RING3
2170 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
2171#else
2172 CPUMRZFpuStateActualizeForChange(pVCpu);
2173#endif
2174 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2175}
2176
2177
2178/**
2179 * Hook for actualizing the guest XMM0..15 and MXCSR register state for read
2180 * only.
2181 *
2182 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2183 *
2184 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2185 */
2186DECLINLINE(void) iemFpuActualizeSseStateForRead(PVMCPUCC pVCpu) RT_NOEXCEPT
2187{
2188#if defined(IN_RING3) || defined(VBOX_WITH_KERNEL_USING_XMM)
2189 NOREF(pVCpu);
2190#else
2191 CPUMRZFpuStateActualizeSseForRead(pVCpu);
2192#endif
2193 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2194}
2195
2196
2197/**
2198 * Hook for actualizing the guest XMM0..15 and MXCSR register state for
2199 * read+write.
2200 *
2201 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2202 *
2203 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2204 */
2205DECLINLINE(void) iemFpuActualizeSseStateForChange(PVMCPUCC pVCpu) RT_NOEXCEPT
2206{
2207#if defined(IN_RING3) || defined(VBOX_WITH_KERNEL_USING_XMM)
2208 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
2209#else
2210 CPUMRZFpuStateActualizeForChange(pVCpu);
2211#endif
2212 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2213
2214 /* Make sure any changes are loaded the next time around. */
2215 pVCpu->cpum.GstCtx.XState.Hdr.bmXState |= XSAVE_C_SSE;
2216}
2217
2218
2219/**
2220 * Hook for actualizing the guest YMM0..15 and MXCSR register state for read
2221 * only.
2222 *
2223 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2224 *
2225 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2226 */
2227DECLINLINE(void) iemFpuActualizeAvxStateForRead(PVMCPUCC pVCpu) RT_NOEXCEPT
2228{
2229#ifdef IN_RING3
2230 NOREF(pVCpu);
2231#else
2232 CPUMRZFpuStateActualizeAvxForRead(pVCpu);
2233#endif
2234 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2235}
2236
2237
2238/**
2239 * Hook for actualizing the guest YMM0..15 and MXCSR register state for
2240 * read+write.
2241 *
2242 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2243 *
2244 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2245 */
2246DECLINLINE(void) iemFpuActualizeAvxStateForChange(PVMCPUCC pVCpu) RT_NOEXCEPT
2247{
2248#ifdef IN_RING3
2249 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
2250#else
2251 CPUMRZFpuStateActualizeForChange(pVCpu);
2252#endif
2253 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2254
2255 /* Just assume we're going to make changes to the SSE and YMM_HI parts. */
2256 pVCpu->cpum.GstCtx.XState.Hdr.bmXState |= XSAVE_C_YMM | XSAVE_C_SSE;
2257}
2258
2259
2260/**
2261 * Stores a QNaN value into a FPU register.
2262 *
2263 * @param pReg Pointer to the register.
2264 */
2265DECLINLINE(void) iemFpuStoreQNan(PRTFLOAT80U pReg) RT_NOEXCEPT
2266{
2267 pReg->au32[0] = UINT32_C(0x00000000);
2268 pReg->au32[1] = UINT32_C(0xc0000000);
2269 pReg->au16[4] = UINT16_C(0xffff);
2270}
2271
2272
2273#ifndef IEM_WITH_OPAQUE_DECODER_STATE
2274/**
2275 * Updates the FOP, FPU.CS and FPUIP registers.
2276 *
2277 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2278 * @param pFpuCtx The FPU context.
2279 */
2280DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorker(PVMCPUCC pVCpu, PX86FXSTATE pFpuCtx) RT_NOEXCEPT
2281{
2282 Assert(pVCpu->iem.s.uFpuOpcode != UINT16_MAX);
2283 pFpuCtx->FOP = pVCpu->iem.s.uFpuOpcode;
2284 /** @todo x87.CS and FPUIP needs to be kept seperately. */
2285 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
2286 {
2287 /** @todo Testcase: making assumptions about how FPUIP and FPUDP are handled
2288 * happens in real mode here based on the fnsave and fnstenv images. */
2289 pFpuCtx->CS = 0;
2290 pFpuCtx->FPUIP = pVCpu->cpum.GstCtx.eip | ((uint32_t)pVCpu->cpum.GstCtx.cs.Sel << 4);
2291 }
2292 else if (!IEM_IS_LONG_MODE(pVCpu))
2293 {
2294 pFpuCtx->CS = pVCpu->cpum.GstCtx.cs.Sel;
2295 pFpuCtx->FPUIP = pVCpu->cpum.GstCtx.rip;
2296 }
2297 else
2298 *(uint64_t *)&pFpuCtx->FPUIP = pVCpu->cpum.GstCtx.rip;
2299}
2300#endif /* !IEM_WITH_OPAQUE_DECODER_STATE */
2301
2302
2303
2304
2305/**
2306 * Marks the specified stack register as free (for FFREE).
2307 *
2308 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2309 * @param iStReg The register to free.
2310 */
2311DECLINLINE(void) iemFpuStackFree(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT
2312{
2313 Assert(iStReg < 8);
2314 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2315 uint8_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
2316 pFpuCtx->FTW &= ~RT_BIT(iReg);
2317}
2318
2319
2320/**
2321 * Increments FSW.TOP, i.e. pops an item off the stack without freeing it.
2322 *
2323 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2324 */
2325DECLINLINE(void) iemFpuStackIncTop(PVMCPUCC pVCpu) RT_NOEXCEPT
2326{
2327 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2328 uint16_t uFsw = pFpuCtx->FSW;
2329 uint16_t uTop = uFsw & X86_FSW_TOP_MASK;
2330 uTop = (uTop + (1 << X86_FSW_TOP_SHIFT)) & X86_FSW_TOP_MASK;
2331 uFsw &= ~X86_FSW_TOP_MASK;
2332 uFsw |= uTop;
2333 pFpuCtx->FSW = uFsw;
2334}
2335
2336
2337/**
2338 * Decrements FSW.TOP, i.e. push an item off the stack without storing anything.
2339 *
2340 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2341 */
2342DECLINLINE(void) iemFpuStackDecTop(PVMCPUCC pVCpu) RT_NOEXCEPT
2343{
2344 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2345 uint16_t uFsw = pFpuCtx->FSW;
2346 uint16_t uTop = uFsw & X86_FSW_TOP_MASK;
2347 uTop = (uTop + (7 << X86_FSW_TOP_SHIFT)) & X86_FSW_TOP_MASK;
2348 uFsw &= ~X86_FSW_TOP_MASK;
2349 uFsw |= uTop;
2350 pFpuCtx->FSW = uFsw;
2351}
2352
2353
2354
2355
2356DECLINLINE(int) iemFpuStRegNotEmpty(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT
2357{
2358 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2359 uint16_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
2360 if (pFpuCtx->FTW & RT_BIT(iReg))
2361 return VINF_SUCCESS;
2362 return VERR_NOT_FOUND;
2363}
2364
2365
2366DECLINLINE(int) iemFpuStRegNotEmptyRef(PVMCPUCC pVCpu, uint8_t iStReg, PCRTFLOAT80U *ppRef) RT_NOEXCEPT
2367{
2368 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2369 uint16_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
2370 if (pFpuCtx->FTW & RT_BIT(iReg))
2371 {
2372 *ppRef = &pFpuCtx->aRegs[iStReg].r80;
2373 return VINF_SUCCESS;
2374 }
2375 return VERR_NOT_FOUND;
2376}
2377
2378
2379DECLINLINE(int) iemFpu2StRegsNotEmptyRef(PVMCPUCC pVCpu, uint8_t iStReg0, PCRTFLOAT80U *ppRef0,
2380 uint8_t iStReg1, PCRTFLOAT80U *ppRef1) RT_NOEXCEPT
2381{
2382 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2383 uint16_t iTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
2384 uint16_t iReg0 = (iTop + iStReg0) & X86_FSW_TOP_SMASK;
2385 uint16_t iReg1 = (iTop + iStReg1) & X86_FSW_TOP_SMASK;
2386 if ((pFpuCtx->FTW & (RT_BIT(iReg0) | RT_BIT(iReg1))) == (RT_BIT(iReg0) | RT_BIT(iReg1)))
2387 {
2388 *ppRef0 = &pFpuCtx->aRegs[iStReg0].r80;
2389 *ppRef1 = &pFpuCtx->aRegs[iStReg1].r80;
2390 return VINF_SUCCESS;
2391 }
2392 return VERR_NOT_FOUND;
2393}
2394
2395
2396DECLINLINE(int) iemFpu2StRegsNotEmptyRefFirst(PVMCPUCC pVCpu, uint8_t iStReg0, PCRTFLOAT80U *ppRef0, uint8_t iStReg1) RT_NOEXCEPT
2397{
2398 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2399 uint16_t iTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
2400 uint16_t iReg0 = (iTop + iStReg0) & X86_FSW_TOP_SMASK;
2401 uint16_t iReg1 = (iTop + iStReg1) & X86_FSW_TOP_SMASK;
2402 if ((pFpuCtx->FTW & (RT_BIT(iReg0) | RT_BIT(iReg1))) == (RT_BIT(iReg0) | RT_BIT(iReg1)))
2403 {
2404 *ppRef0 = &pFpuCtx->aRegs[iStReg0].r80;
2405 return VINF_SUCCESS;
2406 }
2407 return VERR_NOT_FOUND;
2408}
2409
2410
2411/**
2412 * Rotates the stack registers when setting new TOS.
2413 *
2414 * @param pFpuCtx The FPU context.
2415 * @param iNewTop New TOS value.
2416 * @remarks We only do this to speed up fxsave/fxrstor which
2417 * arrange the FP registers in stack order.
2418 * MUST be done before writing the new TOS (FSW).
2419 */
2420DECLINLINE(void) iemFpuRotateStackSetTop(PX86FXSTATE pFpuCtx, uint16_t iNewTop) RT_NOEXCEPT
2421{
2422 uint16_t iOldTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
2423 RTFLOAT80U ar80Temp[8];
2424
2425 if (iOldTop == iNewTop)
2426 return;
2427
2428 /* Unscrew the stack and get it into 'native' order. */
2429 ar80Temp[0] = pFpuCtx->aRegs[(8 - iOldTop + 0) & X86_FSW_TOP_SMASK].r80;
2430 ar80Temp[1] = pFpuCtx->aRegs[(8 - iOldTop + 1) & X86_FSW_TOP_SMASK].r80;
2431 ar80Temp[2] = pFpuCtx->aRegs[(8 - iOldTop + 2) & X86_FSW_TOP_SMASK].r80;
2432 ar80Temp[3] = pFpuCtx->aRegs[(8 - iOldTop + 3) & X86_FSW_TOP_SMASK].r80;
2433 ar80Temp[4] = pFpuCtx->aRegs[(8 - iOldTop + 4) & X86_FSW_TOP_SMASK].r80;
2434 ar80Temp[5] = pFpuCtx->aRegs[(8 - iOldTop + 5) & X86_FSW_TOP_SMASK].r80;
2435 ar80Temp[6] = pFpuCtx->aRegs[(8 - iOldTop + 6) & X86_FSW_TOP_SMASK].r80;
2436 ar80Temp[7] = pFpuCtx->aRegs[(8 - iOldTop + 7) & X86_FSW_TOP_SMASK].r80;
2437
2438 /* Now rotate the stack to the new position. */
2439 pFpuCtx->aRegs[0].r80 = ar80Temp[(iNewTop + 0) & X86_FSW_TOP_SMASK];
2440 pFpuCtx->aRegs[1].r80 = ar80Temp[(iNewTop + 1) & X86_FSW_TOP_SMASK];
2441 pFpuCtx->aRegs[2].r80 = ar80Temp[(iNewTop + 2) & X86_FSW_TOP_SMASK];
2442 pFpuCtx->aRegs[3].r80 = ar80Temp[(iNewTop + 3) & X86_FSW_TOP_SMASK];
2443 pFpuCtx->aRegs[4].r80 = ar80Temp[(iNewTop + 4) & X86_FSW_TOP_SMASK];
2444 pFpuCtx->aRegs[5].r80 = ar80Temp[(iNewTop + 5) & X86_FSW_TOP_SMASK];
2445 pFpuCtx->aRegs[6].r80 = ar80Temp[(iNewTop + 6) & X86_FSW_TOP_SMASK];
2446 pFpuCtx->aRegs[7].r80 = ar80Temp[(iNewTop + 7) & X86_FSW_TOP_SMASK];
2447}
2448
2449
2450/**
2451 * Updates the FPU exception status after FCW is changed.
2452 *
2453 * @param pFpuCtx The FPU context.
2454 */
2455DECLINLINE(void) iemFpuRecalcExceptionStatus(PX86FXSTATE pFpuCtx) RT_NOEXCEPT
2456{
2457 uint16_t u16Fsw = pFpuCtx->FSW;
2458 if ((u16Fsw & X86_FSW_XCPT_MASK) & ~(pFpuCtx->FCW & X86_FCW_XCPT_MASK))
2459 u16Fsw |= X86_FSW_ES | X86_FSW_B;
2460 else
2461 u16Fsw &= ~(X86_FSW_ES | X86_FSW_B);
2462 pFpuCtx->FSW = u16Fsw;
2463}
2464
2465
2466/**
2467 * Calculates the full FTW (FPU tag word) for use in FNSTENV and FNSAVE.
2468 *
2469 * @returns The full FTW.
2470 * @param pFpuCtx The FPU context.
2471 */
2472DECLINLINE(uint16_t) iemFpuCalcFullFtw(PCX86FXSTATE pFpuCtx) RT_NOEXCEPT
2473{
2474 uint8_t const u8Ftw = (uint8_t)pFpuCtx->FTW;
2475 uint16_t u16Ftw = 0;
2476 unsigned const iTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
2477 for (unsigned iSt = 0; iSt < 8; iSt++)
2478 {
2479 unsigned const iReg = (iSt + iTop) & 7;
2480 if (!(u8Ftw & RT_BIT(iReg)))
2481 u16Ftw |= 3 << (iReg * 2); /* empty */
2482 else
2483 {
2484 uint16_t uTag;
2485 PCRTFLOAT80U const pr80Reg = &pFpuCtx->aRegs[iSt].r80;
2486 if (pr80Reg->s.uExponent == 0x7fff)
2487 uTag = 2; /* Exponent is all 1's => Special. */
2488 else if (pr80Reg->s.uExponent == 0x0000)
2489 {
2490 if (pr80Reg->s.uMantissa == 0x0000)
2491 uTag = 1; /* All bits are zero => Zero. */
2492 else
2493 uTag = 2; /* Must be special. */
2494 }
2495 else if (pr80Reg->s.uMantissa & RT_BIT_64(63)) /* The J bit. */
2496 uTag = 0; /* Valid. */
2497 else
2498 uTag = 2; /* Must be special. */
2499
2500 u16Ftw |= uTag << (iReg * 2);
2501 }
2502 }
2503
2504 return u16Ftw;
2505}
2506
2507
2508/**
2509 * Converts a full FTW to a compressed one (for use in FLDENV and FRSTOR).
2510 *
2511 * @returns The compressed FTW.
2512 * @param u16FullFtw The full FTW to convert.
2513 */
2514DECLINLINE(uint16_t) iemFpuCompressFtw(uint16_t u16FullFtw) RT_NOEXCEPT
2515{
2516 uint8_t u8Ftw = 0;
2517 for (unsigned i = 0; i < 8; i++)
2518 {
2519 if ((u16FullFtw & 3) != 3 /*empty*/)
2520 u8Ftw |= RT_BIT(i);
2521 u16FullFtw >>= 2;
2522 }
2523
2524 return u8Ftw;
2525}
2526
2527/** @} */
2528
2529
2530/** @name Memory access.
2531 *
2532 * @{
2533 */
2534
2535
2536/**
2537 * Checks whether alignment checks are enabled or not.
2538 *
2539 * @returns true if enabled, false if not.
2540 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2541 */
2542DECLINLINE(bool) iemMemAreAlignmentChecksEnabled(PVMCPUCC pVCpu) RT_NOEXCEPT
2543{
2544 AssertCompile(X86_CR0_AM == X86_EFL_AC);
2545 return pVCpu->iem.s.uCpl == 3
2546 && (((uint32_t)pVCpu->cpum.GstCtx.cr0 & pVCpu->cpum.GstCtx.eflags.u) & X86_CR0_AM);
2547}
2548
2549/**
2550 * Checks if the given segment can be written to, raise the appropriate
2551 * exception if not.
2552 *
2553 * @returns VBox strict status code.
2554 *
2555 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2556 * @param pHid Pointer to the hidden register.
2557 * @param iSegReg The register number.
2558 * @param pu64BaseAddr Where to return the base address to use for the
2559 * segment. (In 64-bit code it may differ from the
2560 * base in the hidden segment.)
2561 */
2562DECLINLINE(VBOXSTRICTRC) iemMemSegCheckWriteAccessEx(PVMCPUCC pVCpu, PCCPUMSELREGHID pHid,
2563 uint8_t iSegReg, uint64_t *pu64BaseAddr) RT_NOEXCEPT
2564{
2565 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
2566
2567 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2568 *pu64BaseAddr = iSegReg < X86_SREG_FS ? 0 : pHid->u64Base;
2569 else
2570 {
2571 if (!pHid->Attr.n.u1Present)
2572 {
2573 uint16_t uSel = iemSRegFetchU16(pVCpu, iSegReg);
2574 AssertRelease(uSel == 0);
2575 Log(("iemMemSegCheckWriteAccessEx: %#x (index %u) - bad selector -> #GP\n", uSel, iSegReg));
2576 return iemRaiseGeneralProtectionFault0(pVCpu);
2577 }
2578
2579 if ( ( (pHid->Attr.n.u4Type & X86_SEL_TYPE_CODE)
2580 || !(pHid->Attr.n.u4Type & X86_SEL_TYPE_WRITE) )
2581 && pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT )
2582 return iemRaiseSelectorInvalidAccess(pVCpu, iSegReg, IEM_ACCESS_DATA_W);
2583 *pu64BaseAddr = pHid->u64Base;
2584 }
2585 return VINF_SUCCESS;
2586}
2587
2588
2589/**
2590 * Checks if the given segment can be read from, raise the appropriate
2591 * exception if not.
2592 *
2593 * @returns VBox strict status code.
2594 *
2595 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2596 * @param pHid Pointer to the hidden register.
2597 * @param iSegReg The register number.
2598 * @param pu64BaseAddr Where to return the base address to use for the
2599 * segment. (In 64-bit code it may differ from the
2600 * base in the hidden segment.)
2601 */
2602DECLINLINE(VBOXSTRICTRC) iemMemSegCheckReadAccessEx(PVMCPUCC pVCpu, PCCPUMSELREGHID pHid,
2603 uint8_t iSegReg, uint64_t *pu64BaseAddr) RT_NOEXCEPT
2604{
2605 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
2606
2607 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2608 *pu64BaseAddr = iSegReg < X86_SREG_FS ? 0 : pHid->u64Base;
2609 else
2610 {
2611 if (!pHid->Attr.n.u1Present)
2612 {
2613 uint16_t uSel = iemSRegFetchU16(pVCpu, iSegReg);
2614 AssertRelease(uSel == 0);
2615 Log(("iemMemSegCheckReadAccessEx: %#x (index %u) - bad selector -> #GP\n", uSel, iSegReg));
2616 return iemRaiseGeneralProtectionFault0(pVCpu);
2617 }
2618
2619 if ((pHid->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
2620 return iemRaiseSelectorInvalidAccess(pVCpu, iSegReg, IEM_ACCESS_DATA_R);
2621 *pu64BaseAddr = pHid->u64Base;
2622 }
2623 return VINF_SUCCESS;
2624}
2625
2626
2627/**
2628 * Maps a physical page.
2629 *
2630 * @returns VBox status code (see PGMR3PhysTlbGCPhys2Ptr).
2631 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2632 * @param GCPhysMem The physical address.
2633 * @param fAccess The intended access.
2634 * @param ppvMem Where to return the mapping address.
2635 * @param pLock The PGM lock.
2636 */
2637DECLINLINE(int) iemMemPageMap(PVMCPUCC pVCpu, RTGCPHYS GCPhysMem, uint32_t fAccess,
2638 void **ppvMem, PPGMPAGEMAPLOCK pLock) RT_NOEXCEPT
2639{
2640#ifdef IEM_LOG_MEMORY_WRITES
2641 if (fAccess & IEM_ACCESS_TYPE_WRITE)
2642 return VERR_PGM_PHYS_TLB_CATCH_ALL;
2643#endif
2644
2645 /** @todo This API may require some improving later. A private deal with PGM
2646 * regarding locking and unlocking needs to be struct. A couple of TLBs
2647 * living in PGM, but with publicly accessible inlined access methods
2648 * could perhaps be an even better solution. */
2649 int rc = PGMPhysIemGCPhys2Ptr(pVCpu->CTX_SUFF(pVM), pVCpu,
2650 GCPhysMem,
2651 RT_BOOL(fAccess & IEM_ACCESS_TYPE_WRITE),
2652 pVCpu->iem.s.fBypassHandlers,
2653 ppvMem,
2654 pLock);
2655 /*Log(("PGMPhysIemGCPhys2Ptr %Rrc pLock=%.*Rhxs\n", rc, sizeof(*pLock), pLock));*/
2656 AssertMsg(rc == VINF_SUCCESS || RT_FAILURE_NP(rc), ("%Rrc\n", rc));
2657
2658 return rc;
2659}
2660
2661
2662/**
2663 * Unmap a page previously mapped by iemMemPageMap.
2664 *
2665 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2666 * @param GCPhysMem The physical address.
2667 * @param fAccess The intended access.
2668 * @param pvMem What iemMemPageMap returned.
2669 * @param pLock The PGM lock.
2670 */
2671DECLINLINE(void) iemMemPageUnmap(PVMCPUCC pVCpu, RTGCPHYS GCPhysMem, uint32_t fAccess,
2672 const void *pvMem, PPGMPAGEMAPLOCK pLock) RT_NOEXCEPT
2673{
2674 NOREF(pVCpu);
2675 NOREF(GCPhysMem);
2676 NOREF(fAccess);
2677 NOREF(pvMem);
2678 PGMPhysReleasePageMappingLock(pVCpu->CTX_SUFF(pVM), pLock);
2679}
2680
2681#ifdef IEM_WITH_SETJMP
2682
2683/** @todo slim this down */
2684DECL_INLINE_THROW(RTGCPTR) iemMemApplySegmentToReadJmp(PVMCPUCC pVCpu, uint8_t iSegReg,
2685 size_t cbMem, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
2686{
2687 Assert(cbMem >= 1);
2688 Assert(iSegReg < X86_SREG_COUNT);
2689
2690 /*
2691 * 64-bit mode is simpler.
2692 */
2693 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2694 {
2695 if (iSegReg >= X86_SREG_FS && iSegReg != UINT8_MAX)
2696 {
2697 IEM_CTX_IMPORT_JMP(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
2698 PCPUMSELREGHID const pSel = iemSRegGetHid(pVCpu, iSegReg);
2699 GCPtrMem += pSel->u64Base;
2700 }
2701
2702 if (RT_LIKELY(X86_IS_CANONICAL(GCPtrMem) && X86_IS_CANONICAL(GCPtrMem + cbMem - 1)))
2703 return GCPtrMem;
2704 iemRaiseGeneralProtectionFault0Jmp(pVCpu);
2705 }
2706 /*
2707 * 16-bit and 32-bit segmentation.
2708 */
2709 else if (iSegReg != UINT8_MAX)
2710 {
2711 /** @todo Does this apply to segments with 4G-1 limit? */
2712 uint32_t const GCPtrLast32 = (uint32_t)GCPtrMem + (uint32_t)cbMem - 1;
2713 if (RT_LIKELY(GCPtrLast32 >= (uint32_t)GCPtrMem))
2714 {
2715 IEM_CTX_IMPORT_JMP(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
2716 PCPUMSELREGHID const pSel = iemSRegGetHid(pVCpu, iSegReg);
2717 switch (pSel->Attr.u & ( X86DESCATTR_P | X86DESCATTR_UNUSABLE
2718 | X86_SEL_TYPE_READ | X86_SEL_TYPE_WRITE /* same as read */
2719 | X86_SEL_TYPE_DOWN | X86_SEL_TYPE_CONF /* same as down */
2720 | X86_SEL_TYPE_CODE))
2721 {
2722 case X86DESCATTR_P: /* readonly data, expand up */
2723 case X86DESCATTR_P | X86_SEL_TYPE_WRITE: /* writable data, expand up */
2724 case X86DESCATTR_P | X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ: /* code, read-only */
2725 case X86DESCATTR_P | X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_CONF: /* conforming code, read-only */
2726 /* expand up */
2727 if (RT_LIKELY(GCPtrLast32 <= pSel->u32Limit))
2728 return (uint32_t)GCPtrMem + (uint32_t)pSel->u64Base;
2729 Log10(("iemMemApplySegmentToReadJmp: out of bounds %#x..%#x vs %#x\n",
2730 (uint32_t)GCPtrMem, GCPtrLast32, pSel->u32Limit));
2731 break;
2732
2733 case X86DESCATTR_P | X86_SEL_TYPE_DOWN: /* readonly data, expand down */
2734 case X86DESCATTR_P | X86_SEL_TYPE_DOWN | X86_SEL_TYPE_WRITE: /* writable data, expand down */
2735 /* expand down */
2736 if (RT_LIKELY( (uint32_t)GCPtrMem > pSel->u32Limit
2737 && ( pSel->Attr.n.u1DefBig
2738 || GCPtrLast32 <= UINT32_C(0xffff)) ))
2739 return (uint32_t)GCPtrMem + (uint32_t)pSel->u64Base;
2740 Log10(("iemMemApplySegmentToReadJmp: expand down out of bounds %#x..%#x vs %#x..%#x\n",
2741 (uint32_t)GCPtrMem, GCPtrLast32, pSel->u32Limit, pSel->Attr.n.u1DefBig ? UINT32_MAX : UINT16_MAX));
2742 break;
2743
2744 default:
2745 Log10(("iemMemApplySegmentToReadJmp: bad selector %#x\n", pSel->Attr.u));
2746 iemRaiseSelectorInvalidAccessJmp(pVCpu, iSegReg, IEM_ACCESS_DATA_R);
2747 break;
2748 }
2749 }
2750 Log10(("iemMemApplySegmentToReadJmp: out of bounds %#x..%#x\n",(uint32_t)GCPtrMem, GCPtrLast32));
2751 iemRaiseSelectorBoundsJmp(pVCpu, iSegReg, IEM_ACCESS_DATA_R);
2752 }
2753 /*
2754 * 32-bit flat address.
2755 */
2756 else
2757 return GCPtrMem;
2758}
2759
2760
2761/** @todo slim this down */
2762DECL_INLINE_THROW(RTGCPTR) iemMemApplySegmentToWriteJmp(PVMCPUCC pVCpu, uint8_t iSegReg, size_t cbMem,
2763 RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
2764{
2765 Assert(cbMem >= 1);
2766 Assert(iSegReg < X86_SREG_COUNT);
2767
2768 /*
2769 * 64-bit mode is simpler.
2770 */
2771 if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
2772 {
2773 if (iSegReg >= X86_SREG_FS)
2774 {
2775 IEM_CTX_IMPORT_JMP(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
2776 PCPUMSELREGHID pSel = iemSRegGetHid(pVCpu, iSegReg);
2777 GCPtrMem += pSel->u64Base;
2778 }
2779
2780 if (RT_LIKELY(X86_IS_CANONICAL(GCPtrMem) && X86_IS_CANONICAL(GCPtrMem + cbMem - 1)))
2781 return GCPtrMem;
2782 }
2783 /*
2784 * 16-bit and 32-bit segmentation.
2785 */
2786 else
2787 {
2788 IEM_CTX_IMPORT_JMP(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
2789 PCPUMSELREGHID pSel = iemSRegGetHid(pVCpu, iSegReg);
2790 uint32_t const fRelevantAttrs = pSel->Attr.u & ( X86DESCATTR_P | X86DESCATTR_UNUSABLE
2791 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE | X86_SEL_TYPE_DOWN);
2792 if (fRelevantAttrs == (X86DESCATTR_P | X86_SEL_TYPE_WRITE)) /* data, expand up */
2793 {
2794 /* expand up */
2795 uint32_t GCPtrLast32 = (uint32_t)GCPtrMem + (uint32_t)cbMem;
2796 if (RT_LIKELY( GCPtrLast32 > pSel->u32Limit
2797 && GCPtrLast32 > (uint32_t)GCPtrMem))
2798 return (uint32_t)GCPtrMem + (uint32_t)pSel->u64Base;
2799 }
2800 else if (fRelevantAttrs == (X86DESCATTR_P | X86_SEL_TYPE_WRITE | X86_SEL_TYPE_DOWN)) /* data, expand up */
2801 {
2802 /* expand down */
2803 uint32_t GCPtrLast32 = (uint32_t)GCPtrMem + (uint32_t)cbMem;
2804 if (RT_LIKELY( (uint32_t)GCPtrMem > pSel->u32Limit
2805 && GCPtrLast32 <= (pSel->Attr.n.u1DefBig ? UINT32_MAX : UINT32_C(0xffff))
2806 && GCPtrLast32 > (uint32_t)GCPtrMem))
2807 return (uint32_t)GCPtrMem + (uint32_t)pSel->u64Base;
2808 }
2809 else
2810 iemRaiseSelectorInvalidAccessJmp(pVCpu, iSegReg, IEM_ACCESS_DATA_W);
2811 iemRaiseSelectorBoundsJmp(pVCpu, iSegReg, IEM_ACCESS_DATA_W);
2812 }
2813 iemRaiseGeneralProtectionFault0Jmp(pVCpu);
2814}
2815
2816#endif /* IEM_WITH_SETJMP */
2817
2818/**
2819 * Fakes a long mode stack selector for SS = 0.
2820 *
2821 * @param pDescSs Where to return the fake stack descriptor.
2822 * @param uDpl The DPL we want.
2823 */
2824DECLINLINE(void) iemMemFakeStackSelDesc(PIEMSELDESC pDescSs, uint32_t uDpl) RT_NOEXCEPT
2825{
2826 pDescSs->Long.au64[0] = 0;
2827 pDescSs->Long.au64[1] = 0;
2828 pDescSs->Long.Gen.u4Type = X86_SEL_TYPE_RW_ACC;
2829 pDescSs->Long.Gen.u1DescType = 1; /* 1 = code / data, 0 = system. */
2830 pDescSs->Long.Gen.u2Dpl = uDpl;
2831 pDescSs->Long.Gen.u1Present = 1;
2832 pDescSs->Long.Gen.u1Long = 1;
2833}
2834
2835/** @} */
2836
2837
2838#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2839
2840/**
2841 * Gets CR0 fixed-0 bits in VMX operation.
2842 *
2843 * We do this rather than fetching what we report to the guest (in
2844 * IA32_VMX_CR0_FIXED0 MSR) because real hardware (and so do we) report the same
2845 * values regardless of whether unrestricted-guest feature is available on the CPU.
2846 *
2847 * @returns CR0 fixed-0 bits.
2848 * @param pVCpu The cross context virtual CPU structure.
2849 * @param fVmxNonRootMode Whether the CR0 fixed-0 bits for VMX non-root mode
2850 * must be returned. When @c false, the CR0 fixed-0
2851 * bits for VMX root mode is returned.
2852 *
2853 */
2854DECLINLINE(uint64_t) iemVmxGetCr0Fixed0(PCVMCPUCC pVCpu, bool fVmxNonRootMode) RT_NOEXCEPT
2855{
2856 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
2857
2858 PCVMXMSRS pMsrs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs;
2859 if ( fVmxNonRootMode
2860 && (pMsrs->ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST))
2861 return VMX_V_CR0_FIXED0_UX;
2862 return VMX_V_CR0_FIXED0;
2863}
2864
2865
2866/**
2867 * Sets virtual-APIC write emulation as pending.
2868 *
2869 * @param pVCpu The cross context virtual CPU structure.
2870 * @param offApic The offset in the virtual-APIC page that was written.
2871 */
2872DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
2873{
2874 Assert(offApic < XAPIC_OFF_END + 4);
2875
2876 /*
2877 * Record the currently updated APIC offset, as we need this later for figuring
2878 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
2879 * as for supplying the exit qualification when causing an APIC-write VM-exit.
2880 */
2881 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
2882
2883 /*
2884 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
2885 * virtualization or APIC-write emulation).
2886 */
2887 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
2888 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
2889}
2890
2891#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
2892
2893#endif /* !VMM_INCLUDED_SRC_include_IEMInline_h */
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