VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMInline.h@ 100725

Last change on this file since 100725 was 100591, checked in by vboxsync, 17 months ago

VMM/IEM: Must pass the FPU opcode word to the various MCs updating FOP as IEMCPU::uFpuOpcode isn't available during recompiled code execution. bugref:10369
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 119.1 KB
Line 
1/* $Id: IEMInline.h 100591 2023-07-15 01:20:13Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - Inlined Functions.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMInline_h
29#define VMM_INCLUDED_SRC_include_IEMInline_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35
36/**
37 * Makes status code addjustments (pass up from I/O and access handler)
38 * as well as maintaining statistics.
39 *
40 * @returns Strict VBox status code to pass up.
41 * @param pVCpu The cross context virtual CPU structure of the calling thread.
42 * @param rcStrict The status from executing an instruction.
43 */
44DECL_FORCE_INLINE(VBOXSTRICTRC) iemExecStatusCodeFiddling(PVMCPUCC pVCpu, VBOXSTRICTRC rcStrict) RT_NOEXCEPT
45{
46 if (rcStrict != VINF_SUCCESS)
47 {
48 if (RT_SUCCESS(rcStrict))
49 {
50 AssertMsg( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
51 || rcStrict == VINF_IOM_R3_IOPORT_READ
52 || rcStrict == VINF_IOM_R3_IOPORT_WRITE
53 || rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
54 || rcStrict == VINF_IOM_R3_MMIO_READ
55 || rcStrict == VINF_IOM_R3_MMIO_READ_WRITE
56 || rcStrict == VINF_IOM_R3_MMIO_WRITE
57 || rcStrict == VINF_IOM_R3_MMIO_COMMIT_WRITE
58 || rcStrict == VINF_CPUM_R3_MSR_READ
59 || rcStrict == VINF_CPUM_R3_MSR_WRITE
60 || rcStrict == VINF_EM_RAW_EMULATE_INSTR
61 || rcStrict == VINF_EM_RAW_TO_R3
62 || rcStrict == VINF_EM_TRIPLE_FAULT
63 || rcStrict == VINF_GIM_R3_HYPERCALL
64 /* raw-mode / virt handlers only: */
65 || rcStrict == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT
66 || rcStrict == VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT
67 || rcStrict == VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT
68 || rcStrict == VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT
69 || rcStrict == VINF_SELM_SYNC_GDT
70 || rcStrict == VINF_CSAM_PENDING_ACTION
71 || rcStrict == VINF_PATM_CHECK_PATCH_PAGE
72 /* nested hw.virt codes: */
73 || rcStrict == VINF_VMX_VMEXIT
74 || rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE
75 || rcStrict == VINF_VMX_MODIFIES_BEHAVIOR
76 || rcStrict == VINF_SVM_VMEXIT
77 , ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
78/** @todo adjust for VINF_EM_RAW_EMULATE_INSTR. */
79 int32_t const rcPassUp = pVCpu->iem.s.rcPassUp;
80#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
81 if ( rcStrict == VINF_VMX_VMEXIT
82 && rcPassUp == VINF_SUCCESS)
83 rcStrict = VINF_SUCCESS;
84 else
85#endif
86#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
87 if ( rcStrict == VINF_SVM_VMEXIT
88 && rcPassUp == VINF_SUCCESS)
89 rcStrict = VINF_SUCCESS;
90 else
91#endif
92 if (rcPassUp == VINF_SUCCESS)
93 pVCpu->iem.s.cRetInfStatuses++;
94 else if ( rcPassUp < VINF_EM_FIRST
95 || rcPassUp > VINF_EM_LAST
96 || rcPassUp < VBOXSTRICTRC_VAL(rcStrict))
97 {
98 Log(("IEM: rcPassUp=%Rrc! rcStrict=%Rrc\n", rcPassUp, VBOXSTRICTRC_VAL(rcStrict)));
99 pVCpu->iem.s.cRetPassUpStatus++;
100 rcStrict = rcPassUp;
101 }
102 else
103 {
104 Log(("IEM: rcPassUp=%Rrc rcStrict=%Rrc!\n", rcPassUp, VBOXSTRICTRC_VAL(rcStrict)));
105 pVCpu->iem.s.cRetInfStatuses++;
106 }
107 }
108 else if (rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
109 pVCpu->iem.s.cRetAspectNotImplemented++;
110 else if (rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED)
111 pVCpu->iem.s.cRetInstrNotImplemented++;
112 else
113 pVCpu->iem.s.cRetErrStatuses++;
114 }
115 else if (pVCpu->iem.s.rcPassUp != VINF_SUCCESS)
116 {
117 pVCpu->iem.s.cRetPassUpStatus++;
118 rcStrict = pVCpu->iem.s.rcPassUp;
119 }
120
121 return rcStrict;
122}
123
124
125/**
126 * Sets the pass up status.
127 *
128 * @returns VINF_SUCCESS.
129 * @param pVCpu The cross context virtual CPU structure of the
130 * calling thread.
131 * @param rcPassUp The pass up status. Must be informational.
132 * VINF_SUCCESS is not allowed.
133 */
134DECLINLINE(int) iemSetPassUpStatus(PVMCPUCC pVCpu, VBOXSTRICTRC rcPassUp) RT_NOEXCEPT
135{
136 AssertRC(VBOXSTRICTRC_VAL(rcPassUp)); Assert(rcPassUp != VINF_SUCCESS);
137
138 int32_t const rcOldPassUp = pVCpu->iem.s.rcPassUp;
139 if (rcOldPassUp == VINF_SUCCESS)
140 pVCpu->iem.s.rcPassUp = VBOXSTRICTRC_VAL(rcPassUp);
141 /* If both are EM scheduling codes, use EM priority rules. */
142 else if ( rcOldPassUp >= VINF_EM_FIRST && rcOldPassUp <= VINF_EM_LAST
143 && rcPassUp >= VINF_EM_FIRST && rcPassUp <= VINF_EM_LAST)
144 {
145 if (rcPassUp < rcOldPassUp)
146 {
147 Log(("IEM: rcPassUp=%Rrc! rcOldPassUp=%Rrc\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
148 pVCpu->iem.s.rcPassUp = VBOXSTRICTRC_VAL(rcPassUp);
149 }
150 else
151 Log(("IEM: rcPassUp=%Rrc rcOldPassUp=%Rrc!\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
152 }
153 /* Override EM scheduling with specific status code. */
154 else if (rcOldPassUp >= VINF_EM_FIRST && rcOldPassUp <= VINF_EM_LAST)
155 {
156 Log(("IEM: rcPassUp=%Rrc! rcOldPassUp=%Rrc\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
157 pVCpu->iem.s.rcPassUp = VBOXSTRICTRC_VAL(rcPassUp);
158 }
159 /* Don't override specific status code, first come first served. */
160 else
161 Log(("IEM: rcPassUp=%Rrc rcOldPassUp=%Rrc!\n", VBOXSTRICTRC_VAL(rcPassUp), rcOldPassUp));
162 return VINF_SUCCESS;
163}
164
165
166/**
167 * Calculates the IEM_F_MODE_X86_32BIT_FLAT flag.
168 *
169 * Checks if CS, SS, DS and SS are all wide open flat 32-bit segments. This will
170 * reject expand down data segments and conforming code segments.
171 *
172 * ASSUMES that the CPU is in 32-bit mode.
173 *
174 * @returns IEM_F_MODE_X86_32BIT_FLAT or zero.
175 * @param pVCpu The cross context virtual CPU structure of the
176 * calling thread.
177 * @sa iemCalc32BitFlatIndicatorEsDs
178 */
179DECL_FORCE_INLINE(uint32_t) iemCalc32BitFlatIndicator(PVMCPUCC pVCpu) RT_NOEXCEPT
180{
181 AssertCompile(X86_SEL_TYPE_DOWN == X86_SEL_TYPE_CONF);
182 return ( ( pVCpu->cpum.GstCtx.es.Attr.u
183 | pVCpu->cpum.GstCtx.cs.Attr.u
184 | pVCpu->cpum.GstCtx.ss.Attr.u
185 | pVCpu->cpum.GstCtx.ds.Attr.u)
186 & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_DOWN | X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_P))
187 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_DOWN | X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_P)
188 && ( (pVCpu->cpum.GstCtx.es.u32Limit + 1)
189 | (pVCpu->cpum.GstCtx.cs.u32Limit + 1)
190 | (pVCpu->cpum.GstCtx.ss.u32Limit + 1)
191 | (pVCpu->cpum.GstCtx.ds.u32Limit + 1))
192 == 0
193 && ( pVCpu->cpum.GstCtx.es.u64Base
194 | pVCpu->cpum.GstCtx.cs.u64Base
195 | pVCpu->cpum.GstCtx.ss.u64Base
196 | pVCpu->cpum.GstCtx.ds.u64Base)
197 == 0
198 && !(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ES | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_ES))
199 ? IEM_F_MODE_X86_32BIT_FLAT : 0;
200}
201
202
203/**
204 * Calculates the IEM_F_MODE_X86_32BIT_FLAT flag, ASSUMING the CS and SS are
205 * flat already.
206 *
207 * This is used by sysenter.
208 *
209 * @returns IEM_F_MODE_X86_32BIT_FLAT or zero.
210 * @param pVCpu The cross context virtual CPU structure of the
211 * calling thread.
212 * @sa iemCalc32BitFlatIndicator
213 */
214DECL_FORCE_INLINE(uint32_t) iemCalc32BitFlatIndicatorEsDs(PVMCPUCC pVCpu) RT_NOEXCEPT
215{
216 AssertCompile(X86_SEL_TYPE_DOWN == X86_SEL_TYPE_CONF);
217 return ( ( pVCpu->cpum.GstCtx.es.Attr.u
218 | pVCpu->cpum.GstCtx.ds.Attr.u)
219 & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_DOWN | X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_P))
220 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_DOWN | X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_P)
221 && ( (pVCpu->cpum.GstCtx.es.u32Limit + 1)
222 | (pVCpu->cpum.GstCtx.ds.u32Limit + 1))
223 == 0
224 && ( pVCpu->cpum.GstCtx.es.u64Base
225 | pVCpu->cpum.GstCtx.ds.u64Base)
226 == 0
227 && !(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ES | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_ES))
228 ? IEM_F_MODE_X86_32BIT_FLAT : 0;
229}
230
231
232/**
233 * Calculates the IEM_F_MODE_XXX and CPL flags.
234 *
235 * @returns IEM_F_MODE_XXX
236 * @param pVCpu The cross context virtual CPU structure of the
237 * calling thread.
238 */
239DECL_FORCE_INLINE(uint32_t) iemCalcExecModeAndCplFlags(PVMCPUCC pVCpu) RT_NOEXCEPT
240{
241 /*
242 * We're duplicates code from CPUMGetGuestCPL and CPUMIsGuestIn64BitCodeEx
243 * here to try get this done as efficiently as possible.
244 */
245 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_CS);
246
247 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE)
248 {
249 if (!pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
250 {
251 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
252 uint32_t fExec = ((uint32_t)pVCpu->cpum.GstCtx.ss.Attr.n.u2Dpl << IEM_F_X86_CPL_SHIFT);
253 if (pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig)
254 {
255 Assert(!pVCpu->cpum.GstCtx.cs.Attr.n.u1Long || !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA));
256 fExec |= IEM_F_MODE_X86_32BIT_PROT | iemCalc32BitFlatIndicator(pVCpu);
257 }
258 else if ( pVCpu->cpum.GstCtx.cs.Attr.n.u1Long
259 && (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LMA))
260 fExec |= IEM_F_MODE_X86_64BIT;
261 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
262 fExec |= IEM_F_MODE_X86_16BIT_PROT;
263 else
264 fExec |= IEM_F_MODE_X86_16BIT_PROT_PRE_386;
265 return fExec;
266 }
267 return IEM_F_MODE_X86_16BIT_PROT_V86 | (UINT32_C(3) << IEM_F_X86_CPL_SHIFT);
268 }
269
270 /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
271 if (RT_LIKELY(!pVCpu->cpum.GstCtx.cs.Attr.n.u1DefBig))
272 {
273 if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
274 return IEM_F_MODE_X86_16BIT;
275 return IEM_F_MODE_X86_16BIT_PRE_386;
276 }
277
278 /* 32-bit unreal mode. */
279 return IEM_F_MODE_X86_32BIT | iemCalc32BitFlatIndicator(pVCpu);
280}
281
282
283/**
284 * Calculates the AMD-V and VT-x related context flags.
285 *
286 * @returns 0 or a combination of IEM_F_X86_CTX_IN_GUEST, IEM_F_X86_CTX_SVM and
287 * IEM_F_X86_CTX_VMX.
288 * @param pVCpu The cross context virtual CPU structure of the
289 * calling thread.
290 */
291DECL_FORCE_INLINE(uint32_t) iemCalcExecHwVirtFlags(PVMCPUCC pVCpu) RT_NOEXCEPT
292{
293 /*
294 * This duplicates code from CPUMIsGuestVmxEnabled, CPUMIsGuestSvmEnabled
295 * and CPUMIsGuestInNestedHwvirtMode to some extent.
296 */
297 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
298
299 AssertCompile(X86_CR4_VMXE != MSR_K6_EFER_SVME);
300 uint64_t const fTmp = (pVCpu->cpum.GstCtx.cr4 & X86_CR4_VMXE)
301 | (pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_SVME);
302 if (RT_LIKELY(!fTmp))
303 return 0; /* likely */
304
305 if (fTmp & X86_CR4_VMXE)
306 {
307 Assert(pVCpu->cpum.GstCtx.hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
308 if (pVCpu->cpum.GstCtx.hwvirt.vmx.fInVmxNonRootMode)
309 return IEM_F_X86_CTX_VMX | IEM_F_X86_CTX_IN_GUEST;
310 return IEM_F_X86_CTX_VMX;
311 }
312
313 Assert(pVCpu->cpum.GstCtx.hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
314 if (pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb.ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN)
315 return IEM_F_X86_CTX_SVM | IEM_F_X86_CTX_IN_GUEST;
316 return IEM_F_X86_CTX_SVM;
317}
318
319
320/**
321 * Calculates IEM_F_BRK_PENDING_XXX (IEM_F_PENDING_BRK_MASK) flags.
322 *
323 * @returns IEM_F_BRK_PENDING_XXX or zero.
324 * @param pVCpu The cross context virtual CPU structure of the
325 * calling thread.
326 */
327DECL_FORCE_INLINE(uint32_t) iemCalcExecDbgFlags(PVMCPUCC pVCpu) RT_NOEXCEPT
328{
329 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7);
330
331 if (RT_LIKELY( !(pVCpu->cpum.GstCtx.dr[7] & X86_DR7_ENABLED_MASK)
332 && pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledHwBreakpoints == 0))
333 return 0;
334 return iemCalcExecDbgFlagsSlow(pVCpu);
335}
336
337/**
338 * Calculates the the IEM_F_XXX flags.
339 *
340 * @returns IEM_F_XXX combination match the current CPU state.
341 * @param pVCpu The cross context virtual CPU structure of the
342 * calling thread.
343 */
344DECL_FORCE_INLINE(uint32_t) iemCalcExecFlags(PVMCPUCC pVCpu) RT_NOEXCEPT
345{
346 return iemCalcExecModeAndCplFlags(pVCpu)
347 | iemCalcExecHwVirtFlags(pVCpu)
348 /* SMM is not yet implemented */
349 | iemCalcExecDbgFlags(pVCpu)
350 ;
351}
352
353
354/**
355 * Re-calculates the MODE and CPL parts of IEMCPU::fExec.
356 *
357 * @param pVCpu The cross context virtual CPU structure of the
358 * calling thread.
359 */
360DECL_FORCE_INLINE(void) iemRecalcExecModeAndCplFlags(PVMCPUCC pVCpu)
361{
362 pVCpu->iem.s.fExec = (pVCpu->iem.s.fExec & ~(IEM_F_MODE_MASK | IEM_F_X86_CPL_MASK))
363 | iemCalcExecModeAndCplFlags(pVCpu);
364}
365
366
367/**
368 * Re-calculates the IEM_F_PENDING_BRK_MASK part of IEMCPU::fExec.
369 *
370 * @param pVCpu The cross context virtual CPU structure of the
371 * calling thread.
372 */
373DECL_FORCE_INLINE(void) iemRecalcExecDbgFlags(PVMCPUCC pVCpu)
374{
375 pVCpu->iem.s.fExec = (pVCpu->iem.s.fExec & ~IEM_F_PENDING_BRK_MASK)
376 | iemCalcExecDbgFlags(pVCpu);
377}
378
379
380#ifndef IEM_WITH_OPAQUE_DECODER_STATE
381
382# if defined(VBOX_INCLUDED_vmm_dbgf_h) || defined(DOXYGEN_RUNNING) /* dbgf.ro.cEnabledHwBreakpoints */
383/**
384 * Initializes the execution state.
385 *
386 * @param pVCpu The cross context virtual CPU structure of the
387 * calling thread.
388 * @param fExecOpts Optional execution flags:
389 * - IEM_F_BYPASS_HANDLERS
390 * - IEM_F_X86_DISREGARD_LOCK
391 *
392 * @remarks Callers of this must call iemUninitExec() to undo potentially fatal
393 * side-effects in strict builds.
394 */
395DECLINLINE(void) iemInitExec(PVMCPUCC pVCpu, uint32_t fExecOpts) RT_NOEXCEPT
396{
397 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
398 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_IEM));
399 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.cs));
400 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ss));
401 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.es));
402 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ds));
403 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.fs));
404 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.gs));
405 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.ldtr));
406 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.GstCtx.tr));
407
408 pVCpu->iem.s.rcPassUp = VINF_SUCCESS;
409 pVCpu->iem.s.fExec = iemCalcExecFlags(pVCpu) | fExecOpts;
410 pVCpu->iem.s.cActiveMappings = 0;
411 pVCpu->iem.s.iNextMapping = 0;
412
413# ifdef VBOX_STRICT
414 pVCpu->iem.s.enmDefAddrMode = (IEMMODE)0xfe;
415 pVCpu->iem.s.enmEffAddrMode = (IEMMODE)0xfe;
416 pVCpu->iem.s.enmDefOpSize = (IEMMODE)0xfe;
417 pVCpu->iem.s.enmEffOpSize = (IEMMODE)0xfe;
418 pVCpu->iem.s.fPrefixes = 0xfeedbeef;
419 pVCpu->iem.s.uRexReg = 127;
420 pVCpu->iem.s.uRexB = 127;
421 pVCpu->iem.s.offModRm = 127;
422 pVCpu->iem.s.uRexIndex = 127;
423 pVCpu->iem.s.iEffSeg = 127;
424 pVCpu->iem.s.idxPrefix = 127;
425 pVCpu->iem.s.uVex3rdReg = 127;
426 pVCpu->iem.s.uVexLength = 127;
427 pVCpu->iem.s.fEvexStuff = 127;
428 pVCpu->iem.s.uFpuOpcode = UINT16_MAX;
429# ifdef IEM_WITH_CODE_TLB
430 pVCpu->iem.s.offInstrNextByte = UINT16_MAX;
431 pVCpu->iem.s.pbInstrBuf = NULL;
432 pVCpu->iem.s.cbInstrBuf = UINT16_MAX;
433 pVCpu->iem.s.cbInstrBufTotal = UINT16_MAX;
434 pVCpu->iem.s.offCurInstrStart = INT16_MAX;
435 pVCpu->iem.s.uInstrBufPc = UINT64_C(0xc0ffc0ffcff0c0ff);
436# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
437 pVCpu->iem.s.offOpcode = 127;
438# endif
439# else
440 pVCpu->iem.s.offOpcode = 127;
441 pVCpu->iem.s.cbOpcode = 127;
442# endif
443# endif /* VBOX_STRICT */
444}
445# endif /* VBOX_INCLUDED_vmm_dbgf_h */
446
447
448# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
449/**
450 * Performs a minimal reinitialization of the execution state.
451 *
452 * This is intended to be used by VM-exits, SMM, LOADALL and other similar
453 * 'world-switch' types operations on the CPU. Currently only nested
454 * hardware-virtualization uses it.
455 *
456 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
457 * @param cbInstr The instruction length (for flushing).
458 */
459DECLINLINE(void) iemReInitExec(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
460{
461 pVCpu->iem.s.fExec = iemCalcExecFlags(pVCpu) | (pVCpu->iem.s.fExec & IEM_F_USER_OPTS);
462 iemOpcodeFlushHeavy(pVCpu, cbInstr);
463}
464# endif
465
466
467/**
468 * Counterpart to #iemInitExec that undoes evil strict-build stuff.
469 *
470 * @param pVCpu The cross context virtual CPU structure of the
471 * calling thread.
472 */
473DECLINLINE(void) iemUninitExec(PVMCPUCC pVCpu) RT_NOEXCEPT
474{
475 /* Note! do not touch fInPatchCode here! (see iemUninitExecAndFiddleStatusAndMaybeReenter) */
476# ifdef VBOX_STRICT
477# ifdef IEM_WITH_CODE_TLB
478 NOREF(pVCpu);
479# else
480 pVCpu->iem.s.cbOpcode = 0;
481# endif
482# else
483 NOREF(pVCpu);
484# endif
485}
486
487
488/**
489 * Calls iemUninitExec, iemExecStatusCodeFiddling and iemRCRawMaybeReenter.
490 *
491 * Only calling iemRCRawMaybeReenter in raw-mode, obviously.
492 *
493 * @returns Fiddled strict vbox status code, ready to return to non-IEM caller.
494 * @param pVCpu The cross context virtual CPU structure of the calling thread.
495 * @param rcStrict The status code to fiddle.
496 */
497DECLINLINE(VBOXSTRICTRC) iemUninitExecAndFiddleStatusAndMaybeReenter(PVMCPUCC pVCpu, VBOXSTRICTRC rcStrict) RT_NOEXCEPT
498{
499 iemUninitExec(pVCpu);
500 return iemExecStatusCodeFiddling(pVCpu, rcStrict);
501}
502
503
504/**
505 * Macro used by the IEMExec* method to check the given instruction length.
506 *
507 * Will return on failure!
508 *
509 * @param a_cbInstr The given instruction length.
510 * @param a_cbMin The minimum length.
511 */
512# define IEMEXEC_ASSERT_INSTR_LEN_RETURN(a_cbInstr, a_cbMin) \
513 AssertMsgReturn((unsigned)(a_cbInstr) - (unsigned)(a_cbMin) <= (unsigned)15 - (unsigned)(a_cbMin), \
514 ("cbInstr=%u cbMin=%u\n", (a_cbInstr), (a_cbMin)), VERR_IEM_INVALID_INSTR_LENGTH)
515
516
517# ifndef IEM_WITH_SETJMP
518
519/**
520 * Fetches the first opcode byte.
521 *
522 * @returns Strict VBox status code.
523 * @param pVCpu The cross context virtual CPU structure of the
524 * calling thread.
525 * @param pu8 Where to return the opcode byte.
526 */
527DECLINLINE(VBOXSTRICTRC) iemOpcodeGetFirstU8(PVMCPUCC pVCpu, uint8_t *pu8) RT_NOEXCEPT
528{
529 /*
530 * Check for hardware instruction breakpoints.
531 */
532 if (RT_LIKELY(!(pVCpu->iem.s.fExec & IEM_F_PENDING_BRK_INSTR)))
533 { /* likely */ }
534 else
535 {
536 VBOXSTRICTRC rcStrict = DBGFBpCheckInstruction(pVCpu->CTX_SUFF(pVM), pVCpu,
537 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
538 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
539 { /* likely */ }
540 else if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
541 return iemRaiseDebugException(pVCpu);
542 else
543 return rcStrict;
544 }
545
546 /*
547 * Fetch the first opcode byte.
548 */
549 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
550 if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
551 {
552 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
553 *pu8 = pVCpu->iem.s.abOpcode[offOpcode];
554 return VINF_SUCCESS;
555 }
556 return iemOpcodeGetNextU8Slow(pVCpu, pu8);
557}
558
559# else /* IEM_WITH_SETJMP */
560
561/**
562 * Fetches the first opcode byte, longjmp on error.
563 *
564 * @returns The opcode byte.
565 * @param pVCpu The cross context virtual CPU structure of the calling thread.
566 */
567DECL_INLINE_THROW(uint8_t) iemOpcodeGetFirstU8Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
568{
569 /*
570 * Check for hardware instruction breakpoints.
571 */
572 if (RT_LIKELY(!(pVCpu->iem.s.fExec & IEM_F_PENDING_BRK_INSTR)))
573 { /* likely */ }
574 else
575 {
576 VBOXSTRICTRC rcStrict = DBGFBpCheckInstruction(pVCpu->CTX_SUFF(pVM), pVCpu,
577 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
578 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
579 { /* likely */ }
580 else
581 {
582 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
583 rcStrict = iemRaiseDebugException(pVCpu);
584 IEM_DO_LONGJMP(pVCpu, VBOXSTRICTRC_VAL(rcStrict));
585 }
586 }
587
588 /*
589 * Fetch the first opcode byte.
590 */
591# ifdef IEM_WITH_CODE_TLB
592 uint8_t bRet;
593 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
594 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
595 if (RT_LIKELY( pbBuf != NULL
596 && offBuf < pVCpu->iem.s.cbInstrBuf))
597 {
598 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 1;
599 bRet = pbBuf[offBuf];
600 }
601 else
602 bRet = iemOpcodeGetNextU8SlowJmp(pVCpu);
603# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
604 Assert(pVCpu->iem.s.offOpcode == 0);
605 pVCpu->iem.s.abOpcode[pVCpu->iem.s.offOpcode++] = bRet;
606# endif
607 return bRet;
608
609# else /* !IEM_WITH_CODE_TLB */
610 uintptr_t offOpcode = pVCpu->iem.s.offOpcode;
611 if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
612 {
613 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
614 return pVCpu->iem.s.abOpcode[offOpcode];
615 }
616 return iemOpcodeGetNextU8SlowJmp(pVCpu);
617# endif
618}
619
620# endif /* IEM_WITH_SETJMP */
621
622/**
623 * Fetches the first opcode byte, returns/throws automatically on failure.
624 *
625 * @param a_pu8 Where to return the opcode byte.
626 * @remark Implicitly references pVCpu.
627 */
628# ifndef IEM_WITH_SETJMP
629# define IEM_OPCODE_GET_FIRST_U8(a_pu8) \
630 do \
631 { \
632 VBOXSTRICTRC rcStrict2 = iemOpcodeGetFirstU8(pVCpu, (a_pu8)); \
633 if (rcStrict2 == VINF_SUCCESS) \
634 { /* likely */ } \
635 else \
636 return rcStrict2; \
637 } while (0)
638# else
639# define IEM_OPCODE_GET_FIRST_U8(a_pu8) (*(a_pu8) = iemOpcodeGetFirstU8Jmp(pVCpu))
640# endif /* IEM_WITH_SETJMP */
641
642
643# ifndef IEM_WITH_SETJMP
644
645/**
646 * Fetches the next opcode byte.
647 *
648 * @returns Strict VBox status code.
649 * @param pVCpu The cross context virtual CPU structure of the
650 * calling thread.
651 * @param pu8 Where to return the opcode byte.
652 */
653DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU8(PVMCPUCC pVCpu, uint8_t *pu8) RT_NOEXCEPT
654{
655 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
656 if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
657 {
658 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
659 *pu8 = pVCpu->iem.s.abOpcode[offOpcode];
660 return VINF_SUCCESS;
661 }
662 return iemOpcodeGetNextU8Slow(pVCpu, pu8);
663}
664
665# else /* IEM_WITH_SETJMP */
666
667/**
668 * Fetches the next opcode byte, longjmp on error.
669 *
670 * @returns The opcode byte.
671 * @param pVCpu The cross context virtual CPU structure of the calling thread.
672 */
673DECL_INLINE_THROW(uint8_t) iemOpcodeGetNextU8Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
674{
675# ifdef IEM_WITH_CODE_TLB
676 uint8_t bRet;
677 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
678 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
679 if (RT_LIKELY( pbBuf != NULL
680 && offBuf < pVCpu->iem.s.cbInstrBuf))
681 {
682 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 1;
683 bRet = pbBuf[offBuf];
684 }
685 else
686 bRet = iemOpcodeGetNextU8SlowJmp(pVCpu);
687# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
688 Assert(pVCpu->iem.s.offOpcode < sizeof(pVCpu->iem.s.abOpcode));
689 pVCpu->iem.s.abOpcode[pVCpu->iem.s.offOpcode++] = bRet;
690# endif
691 return bRet;
692
693# else /* !IEM_WITH_CODE_TLB */
694 uintptr_t offOpcode = pVCpu->iem.s.offOpcode;
695 if (RT_LIKELY((uint8_t)offOpcode < pVCpu->iem.s.cbOpcode))
696 {
697 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 1;
698 return pVCpu->iem.s.abOpcode[offOpcode];
699 }
700 return iemOpcodeGetNextU8SlowJmp(pVCpu);
701# endif
702}
703
704# endif /* IEM_WITH_SETJMP */
705
706/**
707 * Fetches the next opcode byte, returns automatically on failure.
708 *
709 * @param a_pu8 Where to return the opcode byte.
710 * @remark Implicitly references pVCpu.
711 */
712# ifndef IEM_WITH_SETJMP
713# define IEM_OPCODE_GET_NEXT_U8(a_pu8) \
714 do \
715 { \
716 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU8(pVCpu, (a_pu8)); \
717 if (rcStrict2 == VINF_SUCCESS) \
718 { /* likely */ } \
719 else \
720 return rcStrict2; \
721 } while (0)
722# else
723# define IEM_OPCODE_GET_NEXT_U8(a_pu8) (*(a_pu8) = iemOpcodeGetNextU8Jmp(pVCpu))
724# endif /* IEM_WITH_SETJMP */
725
726
727# ifndef IEM_WITH_SETJMP
728/**
729 * Fetches the next signed byte from the opcode stream.
730 *
731 * @returns Strict VBox status code.
732 * @param pVCpu The cross context virtual CPU structure of the calling thread.
733 * @param pi8 Where to return the signed byte.
734 */
735DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8(PVMCPUCC pVCpu, int8_t *pi8) RT_NOEXCEPT
736{
737 return iemOpcodeGetNextU8(pVCpu, (uint8_t *)pi8);
738}
739# endif /* !IEM_WITH_SETJMP */
740
741
742/**
743 * Fetches the next signed byte from the opcode stream, returning automatically
744 * on failure.
745 *
746 * @param a_pi8 Where to return the signed byte.
747 * @remark Implicitly references pVCpu.
748 */
749# ifndef IEM_WITH_SETJMP
750# define IEM_OPCODE_GET_NEXT_S8(a_pi8) \
751 do \
752 { \
753 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8(pVCpu, (a_pi8)); \
754 if (rcStrict2 != VINF_SUCCESS) \
755 return rcStrict2; \
756 } while (0)
757# else /* IEM_WITH_SETJMP */
758# define IEM_OPCODE_GET_NEXT_S8(a_pi8) (*(a_pi8) = (int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
759
760# endif /* IEM_WITH_SETJMP */
761
762
763# ifndef IEM_WITH_SETJMP
764/**
765 * Fetches the next signed byte from the opcode stream, extending it to
766 * unsigned 16-bit.
767 *
768 * @returns Strict VBox status code.
769 * @param pVCpu The cross context virtual CPU structure of the calling thread.
770 * @param pu16 Where to return the unsigned word.
771 */
772DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU16(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT
773{
774 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
775 if (RT_UNLIKELY(offOpcode >= pVCpu->iem.s.cbOpcode))
776 return iemOpcodeGetNextS8SxU16Slow(pVCpu, pu16);
777
778 *pu16 = (uint16_t)(int16_t)(int8_t)pVCpu->iem.s.abOpcode[offOpcode];
779 pVCpu->iem.s.offOpcode = offOpcode + 1;
780 return VINF_SUCCESS;
781}
782# endif /* !IEM_WITH_SETJMP */
783
784/**
785 * Fetches the next signed byte from the opcode stream and sign-extending it to
786 * a word, returning automatically on failure.
787 *
788 * @param a_pu16 Where to return the word.
789 * @remark Implicitly references pVCpu.
790 */
791# ifndef IEM_WITH_SETJMP
792# define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) \
793 do \
794 { \
795 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU16(pVCpu, (a_pu16)); \
796 if (rcStrict2 != VINF_SUCCESS) \
797 return rcStrict2; \
798 } while (0)
799# else
800# define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) (*(a_pu16) = (uint16_t)(int16_t)(int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
801# endif
802
803# ifndef IEM_WITH_SETJMP
804/**
805 * Fetches the next signed byte from the opcode stream, extending it to
806 * unsigned 32-bit.
807 *
808 * @returns Strict VBox status code.
809 * @param pVCpu The cross context virtual CPU structure of the calling thread.
810 * @param pu32 Where to return the unsigned dword.
811 */
812DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU32(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
813{
814 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
815 if (RT_UNLIKELY(offOpcode >= pVCpu->iem.s.cbOpcode))
816 return iemOpcodeGetNextS8SxU32Slow(pVCpu, pu32);
817
818 *pu32 = (uint32_t)(int32_t)(int8_t)pVCpu->iem.s.abOpcode[offOpcode];
819 pVCpu->iem.s.offOpcode = offOpcode + 1;
820 return VINF_SUCCESS;
821}
822# endif /* !IEM_WITH_SETJMP */
823
824/**
825 * Fetches the next signed byte from the opcode stream and sign-extending it to
826 * a word, returning automatically on failure.
827 *
828 * @param a_pu32 Where to return the word.
829 * @remark Implicitly references pVCpu.
830 */
831# ifndef IEM_WITH_SETJMP
832# define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) \
833 do \
834 { \
835 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU32(pVCpu, (a_pu32)); \
836 if (rcStrict2 != VINF_SUCCESS) \
837 return rcStrict2; \
838 } while (0)
839# else
840# define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) (*(a_pu32) = (uint32_t)(int32_t)(int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
841# endif
842
843
844# ifndef IEM_WITH_SETJMP
845/**
846 * Fetches the next signed byte from the opcode stream, extending it to
847 * unsigned 64-bit.
848 *
849 * @returns Strict VBox status code.
850 * @param pVCpu The cross context virtual CPU structure of the calling thread.
851 * @param pu64 Where to return the unsigned qword.
852 */
853DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS8SxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
854{
855 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
856 if (RT_UNLIKELY(offOpcode >= pVCpu->iem.s.cbOpcode))
857 return iemOpcodeGetNextS8SxU64Slow(pVCpu, pu64);
858
859 *pu64 = (uint64_t)(int64_t)(int8_t)pVCpu->iem.s.abOpcode[offOpcode];
860 pVCpu->iem.s.offOpcode = offOpcode + 1;
861 return VINF_SUCCESS;
862}
863# endif /* !IEM_WITH_SETJMP */
864
865/**
866 * Fetches the next signed byte from the opcode stream and sign-extending it to
867 * a word, returning automatically on failure.
868 *
869 * @param a_pu64 Where to return the word.
870 * @remark Implicitly references pVCpu.
871 */
872# ifndef IEM_WITH_SETJMP
873# define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) \
874 do \
875 { \
876 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS8SxU64(pVCpu, (a_pu64)); \
877 if (rcStrict2 != VINF_SUCCESS) \
878 return rcStrict2; \
879 } while (0)
880# else
881# define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) (*(a_pu64) = (uint64_t)(int64_t)(int8_t)iemOpcodeGetNextU8Jmp(pVCpu))
882# endif
883
884
885# ifndef IEM_WITH_SETJMP
886
887/**
888 * Fetches the next opcode word.
889 *
890 * @returns Strict VBox status code.
891 * @param pVCpu The cross context virtual CPU structure of the calling thread.
892 * @param pu16 Where to return the opcode word.
893 */
894DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT
895{
896 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
897 if (RT_LIKELY((uint8_t)offOpcode + 2 <= pVCpu->iem.s.cbOpcode))
898 {
899 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 2;
900# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
901 *pu16 = *(uint16_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
902# else
903 *pu16 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
904# endif
905 return VINF_SUCCESS;
906 }
907 return iemOpcodeGetNextU16Slow(pVCpu, pu16);
908}
909
910# else /* IEM_WITH_SETJMP */
911
912/**
913 * Fetches the next opcode word, longjmp on error.
914 *
915 * @returns The opcode word.
916 * @param pVCpu The cross context virtual CPU structure of the calling thread.
917 */
918DECL_INLINE_THROW(uint16_t) iemOpcodeGetNextU16Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
919{
920# ifdef IEM_WITH_CODE_TLB
921 uint16_t u16Ret;
922 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
923 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
924 if (RT_LIKELY( pbBuf != NULL
925 && offBuf + 2 <= pVCpu->iem.s.cbInstrBuf))
926 {
927 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 2;
928# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
929 u16Ret = *(uint16_t const *)&pbBuf[offBuf];
930# else
931 u16Ret = RT_MAKE_U16(pbBuf[offBuf], pbBuf[offBuf + 1]);
932# endif
933 }
934 else
935 u16Ret = iemOpcodeGetNextU16SlowJmp(pVCpu);
936
937# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
938 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
939 Assert(offOpcode + 1 < sizeof(pVCpu->iem.s.abOpcode));
940# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
941 *(uint16_t *)&pVCpu->iem.s.abOpcode[offOpcode] = u16Ret;
942# else
943 pVCpu->iem.s.abOpcode[offOpcode] = RT_LO_U8(u16Ret);
944 pVCpu->iem.s.abOpcode[offOpcode + 1] = RT_HI_U8(u16Ret);
945# endif
946 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + (uint8_t)2;
947# endif
948
949 return u16Ret;
950
951# else /* !IEM_WITH_CODE_TLB */
952 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
953 if (RT_LIKELY((uint8_t)offOpcode + 2 <= pVCpu->iem.s.cbOpcode))
954 {
955 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 2;
956# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
957 return *(uint16_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
958# else
959 return RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
960# endif
961 }
962 return iemOpcodeGetNextU16SlowJmp(pVCpu);
963# endif /* !IEM_WITH_CODE_TLB */
964}
965
966# endif /* IEM_WITH_SETJMP */
967
968/**
969 * Fetches the next opcode word, returns automatically on failure.
970 *
971 * @param a_pu16 Where to return the opcode word.
972 * @remark Implicitly references pVCpu.
973 */
974# ifndef IEM_WITH_SETJMP
975# define IEM_OPCODE_GET_NEXT_U16(a_pu16) \
976 do \
977 { \
978 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16(pVCpu, (a_pu16)); \
979 if (rcStrict2 != VINF_SUCCESS) \
980 return rcStrict2; \
981 } while (0)
982# else
983# define IEM_OPCODE_GET_NEXT_U16(a_pu16) (*(a_pu16) = iemOpcodeGetNextU16Jmp(pVCpu))
984# endif
985
986# ifndef IEM_WITH_SETJMP
987/**
988 * Fetches the next opcode word, zero extending it to a double word.
989 *
990 * @returns Strict VBox status code.
991 * @param pVCpu The cross context virtual CPU structure of the calling thread.
992 * @param pu32 Where to return the opcode double word.
993 */
994DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16ZxU32(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
995{
996 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
997 if (RT_UNLIKELY(offOpcode + 2 > pVCpu->iem.s.cbOpcode))
998 return iemOpcodeGetNextU16ZxU32Slow(pVCpu, pu32);
999
1000 *pu32 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
1001 pVCpu->iem.s.offOpcode = offOpcode + 2;
1002 return VINF_SUCCESS;
1003}
1004# endif /* !IEM_WITH_SETJMP */
1005
1006/**
1007 * Fetches the next opcode word and zero extends it to a double word, returns
1008 * automatically on failure.
1009 *
1010 * @param a_pu32 Where to return the opcode double word.
1011 * @remark Implicitly references pVCpu.
1012 */
1013# ifndef IEM_WITH_SETJMP
1014# define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) \
1015 do \
1016 { \
1017 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16ZxU32(pVCpu, (a_pu32)); \
1018 if (rcStrict2 != VINF_SUCCESS) \
1019 return rcStrict2; \
1020 } while (0)
1021# else
1022# define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) (*(a_pu32) = iemOpcodeGetNextU16Jmp(pVCpu))
1023# endif
1024
1025# ifndef IEM_WITH_SETJMP
1026/**
1027 * Fetches the next opcode word, zero extending it to a quad word.
1028 *
1029 * @returns Strict VBox status code.
1030 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1031 * @param pu64 Where to return the opcode quad word.
1032 */
1033DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU16ZxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
1034{
1035 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
1036 if (RT_UNLIKELY(offOpcode + 2 > pVCpu->iem.s.cbOpcode))
1037 return iemOpcodeGetNextU16ZxU64Slow(pVCpu, pu64);
1038
1039 *pu64 = RT_MAKE_U16(pVCpu->iem.s.abOpcode[offOpcode], pVCpu->iem.s.abOpcode[offOpcode + 1]);
1040 pVCpu->iem.s.offOpcode = offOpcode + 2;
1041 return VINF_SUCCESS;
1042}
1043# endif /* !IEM_WITH_SETJMP */
1044
1045/**
1046 * Fetches the next opcode word and zero extends it to a quad word, returns
1047 * automatically on failure.
1048 *
1049 * @param a_pu64 Where to return the opcode quad word.
1050 * @remark Implicitly references pVCpu.
1051 */
1052# ifndef IEM_WITH_SETJMP
1053# define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) \
1054 do \
1055 { \
1056 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU16ZxU64(pVCpu, (a_pu64)); \
1057 if (rcStrict2 != VINF_SUCCESS) \
1058 return rcStrict2; \
1059 } while (0)
1060# else
1061# define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) (*(a_pu64) = iemOpcodeGetNextU16Jmp(pVCpu))
1062# endif
1063
1064
1065# ifndef IEM_WITH_SETJMP
1066/**
1067 * Fetches the next signed word from the opcode stream.
1068 *
1069 * @returns Strict VBox status code.
1070 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1071 * @param pi16 Where to return the signed word.
1072 */
1073DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS16(PVMCPUCC pVCpu, int16_t *pi16) RT_NOEXCEPT
1074{
1075 return iemOpcodeGetNextU16(pVCpu, (uint16_t *)pi16);
1076}
1077# endif /* !IEM_WITH_SETJMP */
1078
1079
1080/**
1081 * Fetches the next signed word from the opcode stream, returning automatically
1082 * on failure.
1083 *
1084 * @param a_pi16 Where to return the signed word.
1085 * @remark Implicitly references pVCpu.
1086 */
1087# ifndef IEM_WITH_SETJMP
1088# define IEM_OPCODE_GET_NEXT_S16(a_pi16) \
1089 do \
1090 { \
1091 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS16(pVCpu, (a_pi16)); \
1092 if (rcStrict2 != VINF_SUCCESS) \
1093 return rcStrict2; \
1094 } while (0)
1095# else
1096# define IEM_OPCODE_GET_NEXT_S16(a_pi16) (*(a_pi16) = (int16_t)iemOpcodeGetNextU16Jmp(pVCpu))
1097# endif
1098
1099# ifndef IEM_WITH_SETJMP
1100
1101/**
1102 * Fetches the next opcode dword.
1103 *
1104 * @returns Strict VBox status code.
1105 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1106 * @param pu32 Where to return the opcode double word.
1107 */
1108DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU32(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT
1109{
1110 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
1111 if (RT_LIKELY((uint8_t)offOpcode + 4 <= pVCpu->iem.s.cbOpcode))
1112 {
1113 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 4;
1114# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1115 *pu32 = *(uint32_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
1116# else
1117 *pu32 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1118 pVCpu->iem.s.abOpcode[offOpcode + 1],
1119 pVCpu->iem.s.abOpcode[offOpcode + 2],
1120 pVCpu->iem.s.abOpcode[offOpcode + 3]);
1121# endif
1122 return VINF_SUCCESS;
1123 }
1124 return iemOpcodeGetNextU32Slow(pVCpu, pu32);
1125}
1126
1127# else /* IEM_WITH_SETJMP */
1128
1129/**
1130 * Fetches the next opcode dword, longjmp on error.
1131 *
1132 * @returns The opcode dword.
1133 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1134 */
1135DECL_INLINE_THROW(uint32_t) iemOpcodeGetNextU32Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
1136{
1137# ifdef IEM_WITH_CODE_TLB
1138 uint32_t u32Ret;
1139 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
1140 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
1141 if (RT_LIKELY( pbBuf != NULL
1142 && offBuf + 4 <= pVCpu->iem.s.cbInstrBuf))
1143 {
1144 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 4;
1145# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1146 u32Ret = *(uint32_t const *)&pbBuf[offBuf];
1147# else
1148 u32Ret = RT_MAKE_U32_FROM_U8(pbBuf[offBuf],
1149 pbBuf[offBuf + 1],
1150 pbBuf[offBuf + 2],
1151 pbBuf[offBuf + 3]);
1152# endif
1153 }
1154 else
1155 u32Ret = iemOpcodeGetNextU32SlowJmp(pVCpu);
1156
1157# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1158 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
1159 Assert(offOpcode + 3 < sizeof(pVCpu->iem.s.abOpcode));
1160# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1161 *(uint32_t *)&pVCpu->iem.s.abOpcode[offOpcode] = u32Ret;
1162# else
1163 pVCpu->iem.s.abOpcode[offOpcode] = RT_BYTE1(u32Ret);
1164 pVCpu->iem.s.abOpcode[offOpcode + 1] = RT_BYTE2(u32Ret);
1165 pVCpu->iem.s.abOpcode[offOpcode + 2] = RT_BYTE3(u32Ret);
1166 pVCpu->iem.s.abOpcode[offOpcode + 3] = RT_BYTE4(u32Ret);
1167# endif
1168 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + (uint8_t)4;
1169# endif /* IEM_WITH_CODE_TLB_AND_OPCODE_BUF */
1170
1171 return u32Ret;
1172
1173# else /* !IEM_WITH_CODE_TLB */
1174 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
1175 if (RT_LIKELY((uint8_t)offOpcode + 4 <= pVCpu->iem.s.cbOpcode))
1176 {
1177 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 4;
1178# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1179 return *(uint32_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
1180# else
1181 return RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1182 pVCpu->iem.s.abOpcode[offOpcode + 1],
1183 pVCpu->iem.s.abOpcode[offOpcode + 2],
1184 pVCpu->iem.s.abOpcode[offOpcode + 3]);
1185# endif
1186 }
1187 return iemOpcodeGetNextU32SlowJmp(pVCpu);
1188# endif
1189}
1190
1191# endif /* IEM_WITH_SETJMP */
1192
1193/**
1194 * Fetches the next opcode dword, returns automatically on failure.
1195 *
1196 * @param a_pu32 Where to return the opcode dword.
1197 * @remark Implicitly references pVCpu.
1198 */
1199# ifndef IEM_WITH_SETJMP
1200# define IEM_OPCODE_GET_NEXT_U32(a_pu32) \
1201 do \
1202 { \
1203 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU32(pVCpu, (a_pu32)); \
1204 if (rcStrict2 != VINF_SUCCESS) \
1205 return rcStrict2; \
1206 } while (0)
1207# else
1208# define IEM_OPCODE_GET_NEXT_U32(a_pu32) (*(a_pu32) = iemOpcodeGetNextU32Jmp(pVCpu))
1209# endif
1210
1211# ifndef IEM_WITH_SETJMP
1212/**
1213 * Fetches the next opcode dword, zero extending it to a quad word.
1214 *
1215 * @returns Strict VBox status code.
1216 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1217 * @param pu64 Where to return the opcode quad word.
1218 */
1219DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU32ZxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
1220{
1221 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
1222 if (RT_UNLIKELY(offOpcode + 4 > pVCpu->iem.s.cbOpcode))
1223 return iemOpcodeGetNextU32ZxU64Slow(pVCpu, pu64);
1224
1225 *pu64 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1226 pVCpu->iem.s.abOpcode[offOpcode + 1],
1227 pVCpu->iem.s.abOpcode[offOpcode + 2],
1228 pVCpu->iem.s.abOpcode[offOpcode + 3]);
1229 pVCpu->iem.s.offOpcode = offOpcode + 4;
1230 return VINF_SUCCESS;
1231}
1232# endif /* !IEM_WITH_SETJMP */
1233
1234/**
1235 * Fetches the next opcode dword and zero extends it to a quad word, returns
1236 * automatically on failure.
1237 *
1238 * @param a_pu64 Where to return the opcode quad word.
1239 * @remark Implicitly references pVCpu.
1240 */
1241# ifndef IEM_WITH_SETJMP
1242# define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) \
1243 do \
1244 { \
1245 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU32ZxU64(pVCpu, (a_pu64)); \
1246 if (rcStrict2 != VINF_SUCCESS) \
1247 return rcStrict2; \
1248 } while (0)
1249# else
1250# define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) (*(a_pu64) = iemOpcodeGetNextU32Jmp(pVCpu))
1251# endif
1252
1253
1254# ifndef IEM_WITH_SETJMP
1255/**
1256 * Fetches the next signed double word from the opcode stream.
1257 *
1258 * @returns Strict VBox status code.
1259 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1260 * @param pi32 Where to return the signed double word.
1261 */
1262DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS32(PVMCPUCC pVCpu, int32_t *pi32) RT_NOEXCEPT
1263{
1264 return iemOpcodeGetNextU32(pVCpu, (uint32_t *)pi32);
1265}
1266# endif
1267
1268/**
1269 * Fetches the next signed double word from the opcode stream, returning
1270 * automatically on failure.
1271 *
1272 * @param a_pi32 Where to return the signed double word.
1273 * @remark Implicitly references pVCpu.
1274 */
1275# ifndef IEM_WITH_SETJMP
1276# define IEM_OPCODE_GET_NEXT_S32(a_pi32) \
1277 do \
1278 { \
1279 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS32(pVCpu, (a_pi32)); \
1280 if (rcStrict2 != VINF_SUCCESS) \
1281 return rcStrict2; \
1282 } while (0)
1283# else
1284# define IEM_OPCODE_GET_NEXT_S32(a_pi32) (*(a_pi32) = (int32_t)iemOpcodeGetNextU32Jmp(pVCpu))
1285# endif
1286
1287# ifndef IEM_WITH_SETJMP
1288/**
1289 * Fetches the next opcode dword, sign extending it into a quad word.
1290 *
1291 * @returns Strict VBox status code.
1292 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1293 * @param pu64 Where to return the opcode quad word.
1294 */
1295DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextS32SxU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
1296{
1297 uint8_t const offOpcode = pVCpu->iem.s.offOpcode;
1298 if (RT_UNLIKELY(offOpcode + 4 > pVCpu->iem.s.cbOpcode))
1299 return iemOpcodeGetNextS32SxU64Slow(pVCpu, pu64);
1300
1301 int32_t i32 = RT_MAKE_U32_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1302 pVCpu->iem.s.abOpcode[offOpcode + 1],
1303 pVCpu->iem.s.abOpcode[offOpcode + 2],
1304 pVCpu->iem.s.abOpcode[offOpcode + 3]);
1305 *pu64 = (uint64_t)(int64_t)i32;
1306 pVCpu->iem.s.offOpcode = offOpcode + 4;
1307 return VINF_SUCCESS;
1308}
1309# endif /* !IEM_WITH_SETJMP */
1310
1311/**
1312 * Fetches the next opcode double word and sign extends it to a quad word,
1313 * returns automatically on failure.
1314 *
1315 * @param a_pu64 Where to return the opcode quad word.
1316 * @remark Implicitly references pVCpu.
1317 */
1318# ifndef IEM_WITH_SETJMP
1319# define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) \
1320 do \
1321 { \
1322 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextS32SxU64(pVCpu, (a_pu64)); \
1323 if (rcStrict2 != VINF_SUCCESS) \
1324 return rcStrict2; \
1325 } while (0)
1326# else
1327# define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) (*(a_pu64) = (uint64_t)(int64_t)(int32_t)iemOpcodeGetNextU32Jmp(pVCpu))
1328# endif
1329
1330# ifndef IEM_WITH_SETJMP
1331
1332/**
1333 * Fetches the next opcode qword.
1334 *
1335 * @returns Strict VBox status code.
1336 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1337 * @param pu64 Where to return the opcode qword.
1338 */
1339DECLINLINE(VBOXSTRICTRC) iemOpcodeGetNextU64(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT
1340{
1341 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
1342 if (RT_LIKELY((uint8_t)offOpcode + 8 <= pVCpu->iem.s.cbOpcode))
1343 {
1344# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1345 *pu64 = *(uint64_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
1346# else
1347 *pu64 = RT_MAKE_U64_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1348 pVCpu->iem.s.abOpcode[offOpcode + 1],
1349 pVCpu->iem.s.abOpcode[offOpcode + 2],
1350 pVCpu->iem.s.abOpcode[offOpcode + 3],
1351 pVCpu->iem.s.abOpcode[offOpcode + 4],
1352 pVCpu->iem.s.abOpcode[offOpcode + 5],
1353 pVCpu->iem.s.abOpcode[offOpcode + 6],
1354 pVCpu->iem.s.abOpcode[offOpcode + 7]);
1355# endif
1356 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 8;
1357 return VINF_SUCCESS;
1358 }
1359 return iemOpcodeGetNextU64Slow(pVCpu, pu64);
1360}
1361
1362# else /* IEM_WITH_SETJMP */
1363
1364/**
1365 * Fetches the next opcode qword, longjmp on error.
1366 *
1367 * @returns The opcode qword.
1368 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1369 */
1370DECL_INLINE_THROW(uint64_t) iemOpcodeGetNextU64Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
1371{
1372# ifdef IEM_WITH_CODE_TLB
1373 uint64_t u64Ret;
1374 uintptr_t offBuf = pVCpu->iem.s.offInstrNextByte;
1375 uint8_t const *pbBuf = pVCpu->iem.s.pbInstrBuf;
1376 if (RT_LIKELY( pbBuf != NULL
1377 && offBuf + 8 <= pVCpu->iem.s.cbInstrBuf))
1378 {
1379 pVCpu->iem.s.offInstrNextByte = (uint32_t)offBuf + 8;
1380# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1381 u64Ret = *(uint64_t const *)&pbBuf[offBuf];
1382# else
1383 u64Ret = RT_MAKE_U64_FROM_U8(pbBuf[offBuf],
1384 pbBuf[offBuf + 1],
1385 pbBuf[offBuf + 2],
1386 pbBuf[offBuf + 3],
1387 pbBuf[offBuf + 4],
1388 pbBuf[offBuf + 5],
1389 pbBuf[offBuf + 6],
1390 pbBuf[offBuf + 7]);
1391# endif
1392 }
1393 else
1394 u64Ret = iemOpcodeGetNextU64SlowJmp(pVCpu);
1395
1396# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1397 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
1398 Assert(offOpcode + 7 < sizeof(pVCpu->iem.s.abOpcode));
1399# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1400 *(uint64_t *)&pVCpu->iem.s.abOpcode[offOpcode] = u64Ret;
1401# else
1402 pVCpu->iem.s.abOpcode[offOpcode] = RT_BYTE1(u64Ret);
1403 pVCpu->iem.s.abOpcode[offOpcode + 1] = RT_BYTE2(u64Ret);
1404 pVCpu->iem.s.abOpcode[offOpcode + 2] = RT_BYTE3(u64Ret);
1405 pVCpu->iem.s.abOpcode[offOpcode + 3] = RT_BYTE4(u64Ret);
1406 pVCpu->iem.s.abOpcode[offOpcode + 4] = RT_BYTE5(u64Ret);
1407 pVCpu->iem.s.abOpcode[offOpcode + 5] = RT_BYTE6(u64Ret);
1408 pVCpu->iem.s.abOpcode[offOpcode + 6] = RT_BYTE7(u64Ret);
1409 pVCpu->iem.s.abOpcode[offOpcode + 7] = RT_BYTE8(u64Ret);
1410# endif
1411 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + (uint8_t)8;
1412# endif /* IEM_WITH_CODE_TLB_AND_OPCODE_BUF */
1413
1414 return u64Ret;
1415
1416# else /* !IEM_WITH_CODE_TLB */
1417 uintptr_t const offOpcode = pVCpu->iem.s.offOpcode;
1418 if (RT_LIKELY((uint8_t)offOpcode + 8 <= pVCpu->iem.s.cbOpcode))
1419 {
1420 pVCpu->iem.s.offOpcode = (uint8_t)offOpcode + 8;
1421# ifdef IEM_USE_UNALIGNED_DATA_ACCESS
1422 return *(uint64_t const *)&pVCpu->iem.s.abOpcode[offOpcode];
1423# else
1424 return RT_MAKE_U64_FROM_U8(pVCpu->iem.s.abOpcode[offOpcode],
1425 pVCpu->iem.s.abOpcode[offOpcode + 1],
1426 pVCpu->iem.s.abOpcode[offOpcode + 2],
1427 pVCpu->iem.s.abOpcode[offOpcode + 3],
1428 pVCpu->iem.s.abOpcode[offOpcode + 4],
1429 pVCpu->iem.s.abOpcode[offOpcode + 5],
1430 pVCpu->iem.s.abOpcode[offOpcode + 6],
1431 pVCpu->iem.s.abOpcode[offOpcode + 7]);
1432# endif
1433 }
1434 return iemOpcodeGetNextU64SlowJmp(pVCpu);
1435# endif /* !IEM_WITH_CODE_TLB */
1436}
1437
1438# endif /* IEM_WITH_SETJMP */
1439
1440/**
1441 * Fetches the next opcode quad word, returns automatically on failure.
1442 *
1443 * @param a_pu64 Where to return the opcode quad word.
1444 * @remark Implicitly references pVCpu.
1445 */
1446# ifndef IEM_WITH_SETJMP
1447# define IEM_OPCODE_GET_NEXT_U64(a_pu64) \
1448 do \
1449 { \
1450 VBOXSTRICTRC rcStrict2 = iemOpcodeGetNextU64(pVCpu, (a_pu64)); \
1451 if (rcStrict2 != VINF_SUCCESS) \
1452 return rcStrict2; \
1453 } while (0)
1454# else
1455# define IEM_OPCODE_GET_NEXT_U64(a_pu64) ( *(a_pu64) = iemOpcodeGetNextU64Jmp(pVCpu) )
1456# endif
1457
1458#endif /* !IEM_WITH_OPAQUE_DECODER_STATE */
1459
1460
1461/** @name Misc Worker Functions.
1462 * @{
1463 */
1464
1465/**
1466 * Gets the correct EFLAGS regardless of whether PATM stores parts of them or
1467 * not (kind of obsolete now).
1468 *
1469 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1470 */
1471#define IEMMISC_GET_EFL(a_pVCpu) ( (a_pVCpu)->cpum.GstCtx.eflags.u )
1472
1473/**
1474 * Updates the EFLAGS in the correct manner wrt. PATM (kind of obsolete).
1475 *
1476 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1477 * @param a_fEfl The new EFLAGS.
1478 */
1479#define IEMMISC_SET_EFL(a_pVCpu, a_fEfl) do { (a_pVCpu)->cpum.GstCtx.eflags.u = (a_fEfl); } while (0)
1480
1481
1482/**
1483 * Loads a NULL data selector into a selector register, both the hidden and
1484 * visible parts, in protected mode.
1485 *
1486 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1487 * @param pSReg Pointer to the segment register.
1488 * @param uRpl The RPL.
1489 */
1490DECLINLINE(void) iemHlpLoadNullDataSelectorProt(PVMCPUCC pVCpu, PCPUMSELREG pSReg, RTSEL uRpl) RT_NOEXCEPT
1491{
1492 /** @todo Testcase: write a testcase checking what happends when loading a NULL
1493 * data selector in protected mode. */
1494 pSReg->Sel = uRpl;
1495 pSReg->ValidSel = uRpl;
1496 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
1497 if (IEM_IS_GUEST_CPU_INTEL(pVCpu))
1498 {
1499 /* VT-x (Intel 3960x) observed doing something like this. */
1500 pSReg->Attr.u = X86DESCATTR_UNUSABLE | X86DESCATTR_G | X86DESCATTR_D | (IEM_GET_CPL(pVCpu) << X86DESCATTR_DPL_SHIFT);
1501 pSReg->u32Limit = UINT32_MAX;
1502 pSReg->u64Base = 0;
1503 }
1504 else
1505 {
1506 pSReg->Attr.u = X86DESCATTR_UNUSABLE;
1507 pSReg->u32Limit = 0;
1508 pSReg->u64Base = 0;
1509 }
1510}
1511
1512/** @} */
1513
1514
1515/*
1516 *
1517 * Helpers routines.
1518 * Helpers routines.
1519 * Helpers routines.
1520 *
1521 */
1522
1523#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1524
1525/**
1526 * Recalculates the effective operand size.
1527 *
1528 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1529 */
1530DECLINLINE(void) iemRecalEffOpSize(PVMCPUCC pVCpu) RT_NOEXCEPT
1531{
1532 switch (IEM_GET_CPU_MODE(pVCpu))
1533 {
1534 case IEMMODE_16BIT:
1535 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP ? IEMMODE_32BIT : IEMMODE_16BIT;
1536 break;
1537 case IEMMODE_32BIT:
1538 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_OP ? IEMMODE_16BIT : IEMMODE_32BIT;
1539 break;
1540 case IEMMODE_64BIT:
1541 switch (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_REX_W | IEM_OP_PRF_SIZE_OP))
1542 {
1543 case 0:
1544 pVCpu->iem.s.enmEffOpSize = pVCpu->iem.s.enmDefOpSize;
1545 break;
1546 case IEM_OP_PRF_SIZE_OP:
1547 pVCpu->iem.s.enmEffOpSize = IEMMODE_16BIT;
1548 break;
1549 case IEM_OP_PRF_SIZE_REX_W:
1550 case IEM_OP_PRF_SIZE_REX_W | IEM_OP_PRF_SIZE_OP:
1551 pVCpu->iem.s.enmEffOpSize = IEMMODE_64BIT;
1552 break;
1553 }
1554 break;
1555 default:
1556 AssertFailed();
1557 }
1558}
1559
1560
1561/**
1562 * Sets the default operand size to 64-bit and recalculates the effective
1563 * operand size.
1564 *
1565 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1566 */
1567DECLINLINE(void) iemRecalEffOpSize64Default(PVMCPUCC pVCpu) RT_NOEXCEPT
1568{
1569 Assert(IEM_IS_64BIT_CODE(pVCpu));
1570 pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
1571 if ((pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_REX_W | IEM_OP_PRF_SIZE_OP)) != IEM_OP_PRF_SIZE_OP)
1572 pVCpu->iem.s.enmEffOpSize = IEMMODE_64BIT;
1573 else
1574 pVCpu->iem.s.enmEffOpSize = IEMMODE_16BIT;
1575}
1576
1577
1578/**
1579 * Sets the default operand size to 64-bit and recalculates the effective
1580 * operand size, with intel ignoring any operand size prefix (AMD respects it).
1581 *
1582 * This is for the relative jumps.
1583 *
1584 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1585 */
1586DECLINLINE(void) iemRecalEffOpSize64DefaultAndIntelIgnoresOpSizePrefix(PVMCPUCC pVCpu) RT_NOEXCEPT
1587{
1588 Assert(IEM_IS_64BIT_CODE(pVCpu));
1589 pVCpu->iem.s.enmDefOpSize = IEMMODE_64BIT;
1590 if ( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_SIZE_REX_W | IEM_OP_PRF_SIZE_OP)) != IEM_OP_PRF_SIZE_OP
1591 || pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1592 pVCpu->iem.s.enmEffOpSize = IEMMODE_64BIT;
1593 else
1594 pVCpu->iem.s.enmEffOpSize = IEMMODE_16BIT;
1595}
1596
1597#endif /* !IEM_WITH_OPAQUE_DECODER_STATE */
1598
1599
1600
1601/** @name Register Access.
1602 * @{
1603 */
1604
1605/**
1606 * Gets a reference (pointer) to the specified hidden segment register.
1607 *
1608 * @returns Hidden register reference.
1609 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1610 * @param iSegReg The segment register.
1611 */
1612DECL_FORCE_INLINE(PCPUMSELREG) iemSRegGetHid(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
1613{
1614 Assert(iSegReg < X86_SREG_COUNT);
1615 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
1616 PCPUMSELREG pSReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
1617
1618 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
1619 return pSReg;
1620}
1621
1622
1623/**
1624 * Ensures that the given hidden segment register is up to date.
1625 *
1626 * @returns Hidden register reference.
1627 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1628 * @param pSReg The segment register.
1629 */
1630DECL_FORCE_INLINE(PCPUMSELREG) iemSRegUpdateHid(PVMCPUCC pVCpu, PCPUMSELREG pSReg) RT_NOEXCEPT
1631{
1632 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
1633 NOREF(pVCpu);
1634 return pSReg;
1635}
1636
1637
1638/**
1639 * Gets a reference (pointer) to the specified segment register (the selector
1640 * value).
1641 *
1642 * @returns Pointer to the selector variable.
1643 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1644 * @param iSegReg The segment register.
1645 */
1646DECL_FORCE_INLINE(uint16_t *) iemSRegRef(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
1647{
1648 Assert(iSegReg < X86_SREG_COUNT);
1649 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
1650 return &pVCpu->cpum.GstCtx.aSRegs[iSegReg].Sel;
1651}
1652
1653
1654/**
1655 * Fetches the selector value of a segment register.
1656 *
1657 * @returns The selector value.
1658 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1659 * @param iSegReg The segment register.
1660 */
1661DECL_FORCE_INLINE(uint16_t) iemSRegFetchU16(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
1662{
1663 Assert(iSegReg < X86_SREG_COUNT);
1664 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
1665 return pVCpu->cpum.GstCtx.aSRegs[iSegReg].Sel;
1666}
1667
1668
1669/**
1670 * Fetches the base address value of a segment register.
1671 *
1672 * @returns The selector value.
1673 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1674 * @param iSegReg The segment register.
1675 */
1676DECL_FORCE_INLINE(uint64_t) iemSRegBaseFetchU64(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
1677{
1678 Assert(iSegReg < X86_SREG_COUNT);
1679 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
1680 return pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base;
1681}
1682
1683
1684/**
1685 * Gets a reference (pointer) to the specified general purpose register.
1686 *
1687 * @returns Register reference.
1688 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1689 * @param iReg The general purpose register.
1690 */
1691DECL_FORCE_INLINE(void *) iemGRegRef(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1692{
1693 Assert(iReg < 16);
1694 return &pVCpu->cpum.GstCtx.aGRegs[iReg];
1695}
1696
1697
1698#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1699/**
1700 * Gets a reference (pointer) to the specified 8-bit general purpose register.
1701 *
1702 * Because of AH, CH, DH and BH we cannot use iemGRegRef directly here.
1703 *
1704 * @returns Register reference.
1705 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1706 * @param iReg The register.
1707 */
1708DECL_FORCE_INLINE(uint8_t *) iemGRegRefU8(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1709{
1710 if (iReg < 4 || (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX))
1711 {
1712 Assert(iReg < 16);
1713 return &pVCpu->cpum.GstCtx.aGRegs[iReg].u8;
1714 }
1715 /* high 8-bit register. */
1716 Assert(iReg < 8);
1717 return &pVCpu->cpum.GstCtx.aGRegs[iReg & 3].bHi;
1718}
1719#endif
1720
1721
1722/**
1723 * Gets a reference (pointer) to the specified 8-bit general purpose register,
1724 * alternative version with extended (20) register index.
1725 *
1726 * @returns Register reference.
1727 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1728 * @param iRegEx The register. The 16 first are regular ones,
1729 * whereas 16 thru 19 maps to AH, CH, DH and BH.
1730 */
1731DECL_FORCE_INLINE(uint8_t *) iemGRegRefU8Ex(PVMCPUCC pVCpu, uint8_t iRegEx) RT_NOEXCEPT
1732{
1733 /** @todo This could be done by double indexing on little endian hosts:
1734 * return &pVCpu->cpum.GstCtx.aGRegs[iRegEx & 15].ab[iRegEx >> 4]; */
1735 if (iRegEx < 16)
1736 return &pVCpu->cpum.GstCtx.aGRegs[iRegEx].u8;
1737
1738 /* high 8-bit register. */
1739 Assert(iRegEx < 20);
1740 return &pVCpu->cpum.GstCtx.aGRegs[iRegEx & 3].bHi;
1741}
1742
1743
1744/**
1745 * Gets a reference (pointer) to the specified 16-bit general purpose register.
1746 *
1747 * @returns Register reference.
1748 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1749 * @param iReg The register.
1750 */
1751DECL_FORCE_INLINE(uint16_t *) iemGRegRefU16(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1752{
1753 Assert(iReg < 16);
1754 return &pVCpu->cpum.GstCtx.aGRegs[iReg].u16;
1755}
1756
1757
1758/**
1759 * Gets a reference (pointer) to the specified 32-bit general purpose register.
1760 *
1761 * @returns Register reference.
1762 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1763 * @param iReg The register.
1764 */
1765DECL_FORCE_INLINE(uint32_t *) iemGRegRefU32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1766{
1767 Assert(iReg < 16);
1768 return &pVCpu->cpum.GstCtx.aGRegs[iReg].u32;
1769}
1770
1771
1772/**
1773 * Gets a reference (pointer) to the specified signed 32-bit general purpose register.
1774 *
1775 * @returns Register reference.
1776 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1777 * @param iReg The register.
1778 */
1779DECL_FORCE_INLINE(int32_t *) iemGRegRefI32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1780{
1781 Assert(iReg < 16);
1782 return (int32_t *)&pVCpu->cpum.GstCtx.aGRegs[iReg].u32;
1783}
1784
1785
1786/**
1787 * Gets a reference (pointer) to the specified 64-bit general purpose register.
1788 *
1789 * @returns Register reference.
1790 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1791 * @param iReg The register.
1792 */
1793DECL_FORCE_INLINE(uint64_t *) iemGRegRefU64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1794{
1795 Assert(iReg < 64);
1796 return &pVCpu->cpum.GstCtx.aGRegs[iReg].u64;
1797}
1798
1799
1800/**
1801 * Gets a reference (pointer) to the specified signed 64-bit general purpose register.
1802 *
1803 * @returns Register reference.
1804 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1805 * @param iReg The register.
1806 */
1807DECL_FORCE_INLINE(int64_t *) iemGRegRefI64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1808{
1809 Assert(iReg < 16);
1810 return (int64_t *)&pVCpu->cpum.GstCtx.aGRegs[iReg].u64;
1811}
1812
1813
1814/**
1815 * Gets a reference (pointer) to the specified segment register's base address.
1816 *
1817 * @returns Segment register base address reference.
1818 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1819 * @param iSegReg The segment selector.
1820 */
1821DECL_FORCE_INLINE(uint64_t *) iemSRegBaseRefU64(PVMCPUCC pVCpu, uint8_t iSegReg) RT_NOEXCEPT
1822{
1823 Assert(iSegReg < X86_SREG_COUNT);
1824 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
1825 return &pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base;
1826}
1827
1828
1829#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1830/**
1831 * Fetches the value of a 8-bit general purpose register.
1832 *
1833 * @returns The register value.
1834 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1835 * @param iReg The register.
1836 */
1837DECL_FORCE_INLINE(uint8_t) iemGRegFetchU8(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1838{
1839 return *iemGRegRefU8(pVCpu, iReg);
1840}
1841#endif
1842
1843
1844/**
1845 * Fetches the value of a 8-bit general purpose register, alternative version
1846 * with extended (20) register index.
1847
1848 * @returns The register value.
1849 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1850 * @param iRegEx The register. The 16 first are regular ones,
1851 * whereas 16 thru 19 maps to AH, CH, DH and BH.
1852 */
1853DECL_FORCE_INLINE(uint8_t) iemGRegFetchU8Ex(PVMCPUCC pVCpu, uint8_t iRegEx) RT_NOEXCEPT
1854{
1855 return *iemGRegRefU8Ex(pVCpu, iRegEx);
1856}
1857
1858
1859/**
1860 * Fetches the value of a 16-bit general purpose register.
1861 *
1862 * @returns The register value.
1863 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1864 * @param iReg The register.
1865 */
1866DECL_FORCE_INLINE(uint16_t) iemGRegFetchU16(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1867{
1868 Assert(iReg < 16);
1869 return pVCpu->cpum.GstCtx.aGRegs[iReg].u16;
1870}
1871
1872
1873/**
1874 * Fetches the value of a 32-bit general purpose register.
1875 *
1876 * @returns The register value.
1877 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1878 * @param iReg The register.
1879 */
1880DECL_FORCE_INLINE(uint32_t) iemGRegFetchU32(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1881{
1882 Assert(iReg < 16);
1883 return pVCpu->cpum.GstCtx.aGRegs[iReg].u32;
1884}
1885
1886
1887/**
1888 * Fetches the value of a 64-bit general purpose register.
1889 *
1890 * @returns The register value.
1891 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1892 * @param iReg The register.
1893 */
1894DECL_FORCE_INLINE(uint64_t) iemGRegFetchU64(PVMCPUCC pVCpu, uint8_t iReg) RT_NOEXCEPT
1895{
1896 Assert(iReg < 16);
1897 return pVCpu->cpum.GstCtx.aGRegs[iReg].u64;
1898}
1899
1900
1901/**
1902 * Stores a 16-bit value to a general purpose register.
1903 *
1904 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1905 * @param iReg The register.
1906 * @param uValue The value to store.
1907 */
1908DECL_FORCE_INLINE(void) iemGRegStoreU16(PVMCPUCC pVCpu, uint8_t iReg, uint16_t uValue) RT_NOEXCEPT
1909{
1910 Assert(iReg < 16);
1911 pVCpu->cpum.GstCtx.aGRegs[iReg].u16 = uValue;
1912}
1913
1914
1915/**
1916 * Stores a 32-bit value to a general purpose register, implicitly clearing high
1917 * values.
1918 *
1919 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1920 * @param iReg The register.
1921 * @param uValue The value to store.
1922 */
1923DECL_FORCE_INLINE(void) iemGRegStoreU32(PVMCPUCC pVCpu, uint8_t iReg, uint32_t uValue) RT_NOEXCEPT
1924{
1925 Assert(iReg < 16);
1926 pVCpu->cpum.GstCtx.aGRegs[iReg].u64 = uValue;
1927}
1928
1929
1930/**
1931 * Stores a 64-bit value to a general purpose register.
1932 *
1933 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1934 * @param iReg The register.
1935 * @param uValue The value to store.
1936 */
1937DECL_FORCE_INLINE(void) iemGRegStoreU64(PVMCPUCC pVCpu, uint8_t iReg, uint64_t uValue) RT_NOEXCEPT
1938{
1939 Assert(iReg < 16);
1940 pVCpu->cpum.GstCtx.aGRegs[iReg].u64 = uValue;
1941}
1942
1943
1944/**
1945 * Get the address of the top of the stack.
1946 *
1947 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1948 */
1949DECL_FORCE_INLINE(RTGCPTR) iemRegGetEffRsp(PCVMCPU pVCpu) RT_NOEXCEPT
1950{
1951 if (IEM_IS_64BIT_CODE(pVCpu))
1952 return pVCpu->cpum.GstCtx.rsp;
1953 if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
1954 return pVCpu->cpum.GstCtx.esp;
1955 return pVCpu->cpum.GstCtx.sp;
1956}
1957
1958
1959/**
1960 * Updates the RIP/EIP/IP to point to the next instruction.
1961 *
1962 * @param pVCpu The cross context virtual CPU structure of the calling thread.
1963 * @param cbInstr The number of bytes to add.
1964 */
1965DECL_FORCE_INLINE(void) iemRegAddToRip(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
1966{
1967 /*
1968 * Advance RIP.
1969 *
1970 * When we're targetting 8086/8, 80186/8 or 80286 mode the updates are 16-bit,
1971 * while in all other modes except LM64 the updates are 32-bit. This means
1972 * we need to watch for both 32-bit and 16-bit "carry" situations, i.e.
1973 * 4GB and 64KB rollovers, and decide whether anything needs masking.
1974 *
1975 * See PC wrap around tests in bs3-cpu-weird-1.
1976 */
1977 uint64_t const uRipPrev = pVCpu->cpum.GstCtx.rip;
1978 uint64_t const uRipNext = uRipPrev + cbInstr;
1979 if (RT_LIKELY( !((uRipNext ^ uRipPrev) & (RT_BIT_64(32) | RT_BIT_64(16)))
1980 || IEM_IS_64BIT_CODE(pVCpu)))
1981 pVCpu->cpum.GstCtx.rip = uRipNext;
1982 else if (IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_386)
1983 pVCpu->cpum.GstCtx.rip = (uint32_t)uRipNext;
1984 else
1985 pVCpu->cpum.GstCtx.rip = (uint16_t)uRipNext;
1986}
1987
1988
1989/**
1990 * Called by iemRegAddToRipAndFinishingClearingRF and others when any of the
1991 * following EFLAGS bits are set:
1992 * - X86_EFL_RF - clear it.
1993 * - CPUMCTX_INHIBIT_SHADOW (_SS/_STI) - clear them.
1994 * - X86_EFL_TF - generate single step \#DB trap.
1995 * - CPUMCTX_DBG_HIT_DR0/1/2/3 - generate \#DB trap (data or I/O, not
1996 * instruction).
1997 *
1998 * According to @sdmv3{077,200,Table 6-2,Priority Among Concurrent Events},
1999 * a \#DB due to TF (single stepping) or a DRx non-instruction breakpoint
2000 * takes priority over both NMIs and hardware interrupts. So, neither is
2001 * considered here. (The RESET, \#MC, SMI, INIT, STOPCLK and FLUSH events are
2002 * either unsupported will be triggered on-top of any \#DB raised here.)
2003 *
2004 * The RF flag only needs to be cleared here as it only suppresses instruction
2005 * breakpoints which are not raised here (happens synchronously during
2006 * instruction fetching).
2007 *
2008 * The CPUMCTX_INHIBIT_SHADOW_SS flag will be cleared by this function, so its
2009 * status has no bearing on whether \#DB exceptions are raised.
2010 *
2011 * @note This must *NOT* be called by the two instructions setting the
2012 * CPUMCTX_INHIBIT_SHADOW_SS flag.
2013 *
2014 * @see @sdmv3{077,200,Table 6-2,Priority Among Concurrent Events}
2015 * @see @sdmv3{077,200,6.8.3,Masking Exceptions and Interrupts When Switching
2016 * Stacks}
2017 */
2018static VBOXSTRICTRC iemFinishInstructionWithFlagsSet(PVMCPUCC pVCpu) RT_NOEXCEPT
2019{
2020 /*
2021 * Normally we're just here to clear RF and/or interrupt shadow bits.
2022 */
2023 if (RT_LIKELY((pVCpu->cpum.GstCtx.eflags.uBoth & (X86_EFL_TF | CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK)) == 0))
2024 pVCpu->cpum.GstCtx.eflags.uBoth &= ~(X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW);
2025 else
2026 {
2027 /*
2028 * Raise a #DB or/and DBGF event.
2029 */
2030 VBOXSTRICTRC rcStrict;
2031 if (pVCpu->cpum.GstCtx.eflags.uBoth & (X86_EFL_TF | CPUMCTX_DBG_HIT_DRX_MASK))
2032 {
2033 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
2034 pVCpu->cpum.GstCtx.dr[6] &= ~X86_DR6_B_MASK;
2035 if (pVCpu->cpum.GstCtx.eflags.uBoth & X86_EFL_TF)
2036 pVCpu->cpum.GstCtx.dr[6] |= X86_DR6_BS;
2037 pVCpu->cpum.GstCtx.dr[6] |= (pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_HIT_DRX_MASK) >> CPUMCTX_DBG_HIT_DRX_SHIFT;
2038 LogFlowFunc(("Guest #DB fired at %04X:%016llX: DR6=%08X, RFLAGS=%16RX64\n",
2039 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, (unsigned)pVCpu->cpum.GstCtx.dr[6],
2040 pVCpu->cpum.GstCtx.rflags.uBoth));
2041
2042 pVCpu->cpum.GstCtx.eflags.uBoth &= ~(X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW | CPUMCTX_DBG_HIT_DRX_MASK);
2043 rcStrict = iemRaiseDebugException(pVCpu);
2044
2045 /* A DBGF event/breakpoint trumps the iemRaiseDebugException informational status code. */
2046 if ((pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_DBGF_MASK) && RT_FAILURE(rcStrict))
2047 {
2048 rcStrict = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_DBGF_BP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_EVENT;
2049 LogFlowFunc(("dbgf at %04X:%016llX: %Rrc\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, VBOXSTRICTRC_VAL(rcStrict)));
2050 }
2051 }
2052 else
2053 {
2054 Assert(pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_DBGF_MASK);
2055 rcStrict = pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_DBGF_BP ? VINF_EM_DBG_BREAKPOINT : VINF_EM_DBG_EVENT;
2056 LogFlowFunc(("dbgf at %04X:%016llX: %Rrc\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, VBOXSTRICTRC_VAL(rcStrict)));
2057 }
2058 pVCpu->cpum.GstCtx.eflags.uBoth &= ~CPUMCTX_DBG_DBGF_MASK;
2059 return rcStrict;
2060 }
2061 return VINF_SUCCESS;
2062}
2063
2064
2065/**
2066 * Clears the RF and CPUMCTX_INHIBIT_SHADOW, triggering \#DB if pending.
2067 *
2068 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2069 */
2070DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegFinishClearingRF(PVMCPUCC pVCpu) RT_NOEXCEPT
2071{
2072 /*
2073 * We assume that most of the time nothing actually needs doing here.
2074 */
2075 AssertCompile(CPUMCTX_INHIBIT_SHADOW < UINT32_MAX);
2076 if (RT_LIKELY(!( pVCpu->cpum.GstCtx.eflags.uBoth
2077 & (X86_EFL_TF | X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW | CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK)) ))
2078 return VINF_SUCCESS;
2079 return iemFinishInstructionWithFlagsSet(pVCpu);
2080}
2081
2082
2083/**
2084 * Updates the RIP/EIP/IP to point to the next instruction and clears EFLAGS.RF
2085 * and CPUMCTX_INHIBIT_SHADOW.
2086 *
2087 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2088 * @param cbInstr The number of bytes to add.
2089 */
2090DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegAddToRipAndFinishingClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2091{
2092 iemRegAddToRip(pVCpu, cbInstr);
2093 return iemRegFinishClearingRF(pVCpu);
2094}
2095
2096
2097/**
2098 * Updates the RIP to point to the next instruction and clears EFLAGS.RF
2099 * and CPUMCTX_INHIBIT_SHADOW.
2100 *
2101 * Only called from 64-bit code.
2102 *
2103 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2104 * @param cbInstr The number of bytes to add.
2105 */
2106DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegAddToRip64AndFinishingClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2107{
2108 pVCpu->cpum.GstCtx.rip = pVCpu->cpum.GstCtx.rip + cbInstr;
2109 return iemRegFinishClearingRF(pVCpu);
2110}
2111
2112
2113/**
2114 * Updates the EIP to point to the next instruction and clears EFLAGS.RF and
2115 * CPUMCTX_INHIBIT_SHADOW.
2116 *
2117 * This is never from 64-bit code.
2118 *
2119 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2120 * @param cbInstr The number of bytes to add.
2121 */
2122DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegAddToEip32AndFinishingClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2123{
2124 pVCpu->cpum.GstCtx.rip = (uint32_t)(pVCpu->cpum.GstCtx.eip + cbInstr);
2125 return iemRegFinishClearingRF(pVCpu);
2126}
2127
2128
2129/**
2130 * Updates the IP to point to the next instruction and clears EFLAGS.RF and
2131 * CPUMCTX_INHIBIT_SHADOW.
2132 *
2133 * This is only ever used from 16-bit code on a pre-386 CPU.
2134 *
2135 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2136 * @param cbInstr The number of bytes to add.
2137 */
2138DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegAddToIp16AndFinishingClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT
2139{
2140 pVCpu->cpum.GstCtx.rip = (uint16_t)(pVCpu->cpum.GstCtx.ip + cbInstr);
2141 return iemRegFinishClearingRF(pVCpu);
2142}
2143
2144
2145/**
2146 * Adds a 8-bit signed jump offset to RIP from 64-bit code.
2147 *
2148 * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
2149 * segment limit.
2150 *
2151 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2152 * @param cbInstr Instruction size.
2153 * @param offNextInstr The offset of the next instruction.
2154 * @param enmEffOpSize Effective operand size.
2155 */
2156DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegRip64RelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
2157 IEMMODE enmEffOpSize) RT_NOEXCEPT
2158{
2159 Assert(IEM_IS_64BIT_CODE(pVCpu));
2160 Assert(enmEffOpSize == IEMMODE_64BIT || enmEffOpSize == IEMMODE_16BIT);
2161
2162 uint64_t uNewRip = pVCpu->cpum.GstCtx.rip + cbInstr + (int64_t)offNextInstr;
2163 if (enmEffOpSize == IEMMODE_16BIT)
2164 uNewRip &= UINT16_MAX;
2165
2166 if (RT_LIKELY(IEM_IS_CANONICAL(uNewRip)))
2167 pVCpu->cpum.GstCtx.rip = uNewRip;
2168 else
2169 return iemRaiseGeneralProtectionFault0(pVCpu);
2170
2171#ifndef IEM_WITH_CODE_TLB
2172 iemOpcodeFlushLight(pVCpu, cbInstr);
2173#endif
2174
2175 /*
2176 * Clear RF and finish the instruction (maybe raise #DB).
2177 */
2178 return iemRegFinishClearingRF(pVCpu);
2179}
2180
2181
2182/**
2183 * Adds a 8-bit signed jump offset to EIP, on 386 or later from 16-bit or 32-bit
2184 * code (never 64-bit).
2185 *
2186 * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
2187 * segment limit.
2188 *
2189 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2190 * @param cbInstr Instruction size.
2191 * @param offNextInstr The offset of the next instruction.
2192 * @param enmEffOpSize Effective operand size.
2193 */
2194DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegEip32RelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
2195 IEMMODE enmEffOpSize) RT_NOEXCEPT
2196{
2197 Assert(!IEM_IS_64BIT_CODE(pVCpu));
2198 Assert(enmEffOpSize == IEMMODE_32BIT || enmEffOpSize == IEMMODE_16BIT);
2199
2200 uint32_t uNewEip = pVCpu->cpum.GstCtx.eip + cbInstr + (int32_t)offNextInstr;
2201 if (enmEffOpSize == IEMMODE_16BIT)
2202 uNewEip &= UINT16_MAX;
2203 if (RT_LIKELY(uNewEip <= pVCpu->cpum.GstCtx.cs.u32Limit))
2204 pVCpu->cpum.GstCtx.rip = uNewEip;
2205 else
2206 return iemRaiseGeneralProtectionFault0(pVCpu);
2207
2208#ifndef IEM_WITH_CODE_TLB
2209 iemOpcodeFlushLight(pVCpu, cbInstr);
2210#endif
2211
2212 /*
2213 * Clear RF and finish the instruction (maybe raise #DB).
2214 */
2215 return iemRegFinishClearingRF(pVCpu);
2216}
2217
2218
2219/**
2220 * Adds a 8-bit signed jump offset to IP, on a pre-386 CPU.
2221 *
2222 * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
2223 * segment limit.
2224 *
2225 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2226 * @param cbInstr Instruction size.
2227 * @param offNextInstr The offset of the next instruction.
2228 */
2229DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegIp16RelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr,
2230 int8_t offNextInstr) RT_NOEXCEPT
2231{
2232 Assert(!IEM_IS_64BIT_CODE(pVCpu));
2233
2234 uint16_t const uNewIp = pVCpu->cpum.GstCtx.ip + cbInstr + (int16_t)offNextInstr;
2235 if (RT_LIKELY(uNewIp <= pVCpu->cpum.GstCtx.cs.u32Limit))
2236 pVCpu->cpum.GstCtx.rip = uNewIp;
2237 else
2238 return iemRaiseGeneralProtectionFault0(pVCpu);
2239
2240#ifndef IEM_WITH_CODE_TLB
2241 iemOpcodeFlushLight(pVCpu, cbInstr);
2242#endif
2243
2244 /*
2245 * Clear RF and finish the instruction (maybe raise #DB).
2246 */
2247 return iemRegFinishClearingRF(pVCpu);
2248}
2249
2250
2251/**
2252 * Adds a 16-bit signed jump offset to RIP from 64-bit code.
2253 *
2254 * @returns Strict VBox status code.
2255 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2256 * @param cbInstr Instruction size.
2257 * @param offNextInstr The offset of the next instruction.
2258 */
2259DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegRip64RelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr,
2260 int16_t offNextInstr) RT_NOEXCEPT
2261{
2262 Assert(IEM_IS_64BIT_CODE(pVCpu));
2263
2264 pVCpu->cpum.GstCtx.rip = (uint16_t)(pVCpu->cpum.GstCtx.ip + cbInstr + offNextInstr);
2265
2266#ifndef IEM_WITH_CODE_TLB
2267 iemOpcodeFlushLight(pVCpu, cbInstr);
2268#endif
2269
2270 /*
2271 * Clear RF and finish the instruction (maybe raise #DB).
2272 */
2273 return iemRegFinishClearingRF(pVCpu);
2274}
2275
2276
2277/**
2278 * Adds a 16-bit signed jump offset to EIP from 16-bit or 32-bit code.
2279 *
2280 * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
2281 * segment limit.
2282 *
2283 * @returns Strict VBox status code.
2284 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2285 * @param cbInstr Instruction size.
2286 * @param offNextInstr The offset of the next instruction.
2287 *
2288 * @note This is also used by 16-bit code in pre-386 mode, as the code is
2289 * identical.
2290 */
2291DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegEip32RelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr,
2292 int16_t offNextInstr) RT_NOEXCEPT
2293{
2294 Assert(!IEM_IS_64BIT_CODE(pVCpu));
2295
2296 uint16_t const uNewIp = pVCpu->cpum.GstCtx.ip + cbInstr + offNextInstr;
2297 if (RT_LIKELY(uNewIp <= pVCpu->cpum.GstCtx.cs.u32Limit))
2298 pVCpu->cpum.GstCtx.rip = uNewIp;
2299 else
2300 return iemRaiseGeneralProtectionFault0(pVCpu);
2301
2302#ifndef IEM_WITH_CODE_TLB
2303 iemOpcodeFlushLight(pVCpu, cbInstr);
2304#endif
2305
2306 /*
2307 * Clear RF and finish the instruction (maybe raise #DB).
2308 */
2309 return iemRegFinishClearingRF(pVCpu);
2310}
2311
2312
2313/**
2314 * Adds a 32-bit signed jump offset to RIP from 64-bit code.
2315 *
2316 * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
2317 * segment limit.
2318 *
2319 * We ASSUME that the effective operand size is 64-bit here, as 16-bit is the
2320 * only alternative for relative jumps in 64-bit code and that is already
2321 * handled in the decoder stage.
2322 *
2323 * @returns Strict VBox status code.
2324 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2325 * @param cbInstr Instruction size.
2326 * @param offNextInstr The offset of the next instruction.
2327 */
2328DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegRip64RelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr,
2329 int32_t offNextInstr) RT_NOEXCEPT
2330{
2331 Assert(IEM_IS_64BIT_CODE(pVCpu));
2332
2333 uint64_t const uNewRip = pVCpu->cpum.GstCtx.rip + cbInstr + (int64_t)offNextInstr;
2334 if (RT_LIKELY(IEM_IS_CANONICAL(uNewRip)))
2335 pVCpu->cpum.GstCtx.rip = uNewRip;
2336 else
2337 return iemRaiseGeneralProtectionFault0(pVCpu);
2338
2339#ifndef IEM_WITH_CODE_TLB
2340 iemOpcodeFlushLight(pVCpu, cbInstr);
2341#endif
2342
2343 /*
2344 * Clear RF and finish the instruction (maybe raise #DB).
2345 */
2346 return iemRegFinishClearingRF(pVCpu);
2347}
2348
2349
2350/**
2351 * Adds a 32-bit signed jump offset to RIP from 64-bit code.
2352 *
2353 * May raise a \#GP(0) if the new RIP is non-canonical or outside the code
2354 * segment limit.
2355 *
2356 * We ASSUME that the effective operand size is 32-bit here, as 16-bit is the
2357 * only alternative for relative jumps in 32-bit code and that is already
2358 * handled in the decoder stage.
2359 *
2360 * @returns Strict VBox status code.
2361 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2362 * @param cbInstr Instruction size.
2363 * @param offNextInstr The offset of the next instruction.
2364 */
2365DECL_FORCE_INLINE(VBOXSTRICTRC) iemRegEip32RelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr,
2366 int32_t offNextInstr) RT_NOEXCEPT
2367{
2368 Assert(!IEM_IS_64BIT_CODE(pVCpu));
2369 Assert(pVCpu->cpum.GstCtx.rip <= UINT32_MAX);
2370
2371 uint32_t const uNewEip = pVCpu->cpum.GstCtx.eip + cbInstr + offNextInstr;
2372 if (RT_LIKELY(uNewEip <= pVCpu->cpum.GstCtx.cs.u32Limit))
2373 pVCpu->cpum.GstCtx.rip = uNewEip;
2374 else
2375 return iemRaiseGeneralProtectionFault0(pVCpu);
2376
2377#ifndef IEM_WITH_CODE_TLB
2378 iemOpcodeFlushLight(pVCpu, cbInstr);
2379#endif
2380
2381 /*
2382 * Clear RF and finish the instruction (maybe raise #DB).
2383 */
2384 return iemRegFinishClearingRF(pVCpu);
2385}
2386
2387
2388/**
2389 * Extended version of iemFinishInstructionWithFlagsSet that goes with
2390 * iemRegAddToRipAndFinishingClearingRfEx.
2391 *
2392 * See iemFinishInstructionWithFlagsSet() for details.
2393 */
2394static VBOXSTRICTRC iemFinishInstructionWithTfSet(PVMCPUCC pVCpu) RT_NOEXCEPT
2395{
2396 /*
2397 * Raise a #DB.
2398 */
2399 IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
2400 pVCpu->cpum.GstCtx.dr[6] &= ~X86_DR6_B_MASK;
2401 pVCpu->cpum.GstCtx.dr[6] |= X86_DR6_BS
2402 | (pVCpu->cpum.GstCtx.eflags.uBoth & CPUMCTX_DBG_HIT_DRX_MASK) >> CPUMCTX_DBG_HIT_DRX_SHIFT;
2403 /** @todo Do we set all pending \#DB events, or just one? */
2404 LogFlowFunc(("Guest #DB fired at %04X:%016llX: DR6=%08X, RFLAGS=%16RX64 (popf)\n",
2405 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, (unsigned)pVCpu->cpum.GstCtx.dr[6],
2406 pVCpu->cpum.GstCtx.rflags.uBoth));
2407 pVCpu->cpum.GstCtx.eflags.uBoth &= ~(X86_EFL_RF | CPUMCTX_INHIBIT_SHADOW | CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK);
2408 return iemRaiseDebugException(pVCpu);
2409}
2410
2411
2412/**
2413 * Extended version of iemRegAddToRipAndFinishingClearingRF for use by POPF and
2414 * others potentially updating EFLAGS.TF.
2415 *
2416 * The single step event must be generated using the TF value at the start of
2417 * the instruction, not the new value set by it.
2418 *
2419 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2420 * @param cbInstr The number of bytes to add.
2421 * @param fEflOld The EFLAGS at the start of the instruction
2422 * execution.
2423 */
2424DECLINLINE(VBOXSTRICTRC) iemRegAddToRipAndFinishingClearingRfEx(PVMCPUCC pVCpu, uint8_t cbInstr, uint32_t fEflOld) RT_NOEXCEPT
2425{
2426 iemRegAddToRip(pVCpu, cbInstr);
2427 if (!(fEflOld & X86_EFL_TF))
2428 return iemRegFinishClearingRF(pVCpu);
2429 return iemFinishInstructionWithTfSet(pVCpu);
2430}
2431
2432
2433#ifndef IEM_WITH_OPAQUE_DECODER_STATE
2434/**
2435 * Updates the RIP/EIP/IP to point to the next instruction and clears EFLAGS.RF.
2436 *
2437 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2438 */
2439DECLINLINE(VBOXSTRICTRC) iemRegUpdateRipAndFinishClearingRF(PVMCPUCC pVCpu) RT_NOEXCEPT
2440{
2441 return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu));
2442}
2443#endif
2444
2445
2446/**
2447 * Adds to the stack pointer.
2448 *
2449 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2450 * @param cbToAdd The number of bytes to add (8-bit!).
2451 */
2452DECLINLINE(void) iemRegAddToRsp(PVMCPUCC pVCpu, uint8_t cbToAdd) RT_NOEXCEPT
2453{
2454 if (IEM_IS_64BIT_CODE(pVCpu))
2455 pVCpu->cpum.GstCtx.rsp += cbToAdd;
2456 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2457 pVCpu->cpum.GstCtx.esp += cbToAdd;
2458 else
2459 pVCpu->cpum.GstCtx.sp += cbToAdd;
2460}
2461
2462
2463/**
2464 * Subtracts from the stack pointer.
2465 *
2466 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2467 * @param cbToSub The number of bytes to subtract (8-bit!).
2468 */
2469DECLINLINE(void) iemRegSubFromRsp(PVMCPUCC pVCpu, uint8_t cbToSub) RT_NOEXCEPT
2470{
2471 if (IEM_IS_64BIT_CODE(pVCpu))
2472 pVCpu->cpum.GstCtx.rsp -= cbToSub;
2473 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2474 pVCpu->cpum.GstCtx.esp -= cbToSub;
2475 else
2476 pVCpu->cpum.GstCtx.sp -= cbToSub;
2477}
2478
2479
2480/**
2481 * Adds to the temporary stack pointer.
2482 *
2483 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2484 * @param pTmpRsp The temporary SP/ESP/RSP to update.
2485 * @param cbToAdd The number of bytes to add (16-bit).
2486 */
2487DECLINLINE(void) iemRegAddToRspEx(PCVMCPU pVCpu, PRTUINT64U pTmpRsp, uint16_t cbToAdd) RT_NOEXCEPT
2488{
2489 if (IEM_IS_64BIT_CODE(pVCpu))
2490 pTmpRsp->u += cbToAdd;
2491 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2492 pTmpRsp->DWords.dw0 += cbToAdd;
2493 else
2494 pTmpRsp->Words.w0 += cbToAdd;
2495}
2496
2497
2498/**
2499 * Subtracts from the temporary stack pointer.
2500 *
2501 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2502 * @param pTmpRsp The temporary SP/ESP/RSP to update.
2503 * @param cbToSub The number of bytes to subtract.
2504 * @remarks The @a cbToSub argument *MUST* be 16-bit, iemCImpl_enter is
2505 * expecting that.
2506 */
2507DECLINLINE(void) iemRegSubFromRspEx(PCVMCPU pVCpu, PRTUINT64U pTmpRsp, uint16_t cbToSub) RT_NOEXCEPT
2508{
2509 if (IEM_IS_64BIT_CODE(pVCpu))
2510 pTmpRsp->u -= cbToSub;
2511 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2512 pTmpRsp->DWords.dw0 -= cbToSub;
2513 else
2514 pTmpRsp->Words.w0 -= cbToSub;
2515}
2516
2517
2518/**
2519 * Calculates the effective stack address for a push of the specified size as
2520 * well as the new RSP value (upper bits may be masked).
2521 *
2522 * @returns Effective stack addressf for the push.
2523 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2524 * @param cbItem The size of the stack item to pop.
2525 * @param puNewRsp Where to return the new RSP value.
2526 */
2527DECLINLINE(RTGCPTR) iemRegGetRspForPush(PCVMCPU pVCpu, uint8_t cbItem, uint64_t *puNewRsp) RT_NOEXCEPT
2528{
2529 RTUINT64U uTmpRsp;
2530 RTGCPTR GCPtrTop;
2531 uTmpRsp.u = pVCpu->cpum.GstCtx.rsp;
2532
2533 if (IEM_IS_64BIT_CODE(pVCpu))
2534 GCPtrTop = uTmpRsp.u -= cbItem;
2535 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2536 GCPtrTop = uTmpRsp.DWords.dw0 -= cbItem;
2537 else
2538 GCPtrTop = uTmpRsp.Words.w0 -= cbItem;
2539 *puNewRsp = uTmpRsp.u;
2540 return GCPtrTop;
2541}
2542
2543
2544/**
2545 * Gets the current stack pointer and calculates the value after a pop of the
2546 * specified size.
2547 *
2548 * @returns Current stack pointer.
2549 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2550 * @param cbItem The size of the stack item to pop.
2551 * @param puNewRsp Where to return the new RSP value.
2552 */
2553DECLINLINE(RTGCPTR) iemRegGetRspForPop(PCVMCPU pVCpu, uint8_t cbItem, uint64_t *puNewRsp) RT_NOEXCEPT
2554{
2555 RTUINT64U uTmpRsp;
2556 RTGCPTR GCPtrTop;
2557 uTmpRsp.u = pVCpu->cpum.GstCtx.rsp;
2558
2559 if (IEM_IS_64BIT_CODE(pVCpu))
2560 {
2561 GCPtrTop = uTmpRsp.u;
2562 uTmpRsp.u += cbItem;
2563 }
2564 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2565 {
2566 GCPtrTop = uTmpRsp.DWords.dw0;
2567 uTmpRsp.DWords.dw0 += cbItem;
2568 }
2569 else
2570 {
2571 GCPtrTop = uTmpRsp.Words.w0;
2572 uTmpRsp.Words.w0 += cbItem;
2573 }
2574 *puNewRsp = uTmpRsp.u;
2575 return GCPtrTop;
2576}
2577
2578
2579/**
2580 * Calculates the effective stack address for a push of the specified size as
2581 * well as the new temporary RSP value (upper bits may be masked).
2582 *
2583 * @returns Effective stack addressf for the push.
2584 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2585 * @param pTmpRsp The temporary stack pointer. This is updated.
2586 * @param cbItem The size of the stack item to pop.
2587 */
2588DECLINLINE(RTGCPTR) iemRegGetRspForPushEx(PCVMCPU pVCpu, PRTUINT64U pTmpRsp, uint8_t cbItem) RT_NOEXCEPT
2589{
2590 RTGCPTR GCPtrTop;
2591
2592 if (IEM_IS_64BIT_CODE(pVCpu))
2593 GCPtrTop = pTmpRsp->u -= cbItem;
2594 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2595 GCPtrTop = pTmpRsp->DWords.dw0 -= cbItem;
2596 else
2597 GCPtrTop = pTmpRsp->Words.w0 -= cbItem;
2598 return GCPtrTop;
2599}
2600
2601
2602/**
2603 * Gets the effective stack address for a pop of the specified size and
2604 * calculates and updates the temporary RSP.
2605 *
2606 * @returns Current stack pointer.
2607 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2608 * @param pTmpRsp The temporary stack pointer. This is updated.
2609 * @param cbItem The size of the stack item to pop.
2610 */
2611DECLINLINE(RTGCPTR) iemRegGetRspForPopEx(PCVMCPU pVCpu, PRTUINT64U pTmpRsp, uint8_t cbItem) RT_NOEXCEPT
2612{
2613 RTGCPTR GCPtrTop;
2614 if (IEM_IS_64BIT_CODE(pVCpu))
2615 {
2616 GCPtrTop = pTmpRsp->u;
2617 pTmpRsp->u += cbItem;
2618 }
2619 else if (pVCpu->cpum.GstCtx.ss.Attr.n.u1DefBig)
2620 {
2621 GCPtrTop = pTmpRsp->DWords.dw0;
2622 pTmpRsp->DWords.dw0 += cbItem;
2623 }
2624 else
2625 {
2626 GCPtrTop = pTmpRsp->Words.w0;
2627 pTmpRsp->Words.w0 += cbItem;
2628 }
2629 return GCPtrTop;
2630}
2631
2632/** @} */
2633
2634
2635/** @name FPU access and helpers.
2636 *
2637 * @{
2638 */
2639
2640
2641/**
2642 * Hook for preparing to use the host FPU.
2643 *
2644 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2645 *
2646 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2647 */
2648DECLINLINE(void) iemFpuPrepareUsage(PVMCPUCC pVCpu) RT_NOEXCEPT
2649{
2650#ifdef IN_RING3
2651 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
2652#else
2653 CPUMRZFpuStatePrepareHostCpuForUse(pVCpu);
2654#endif
2655 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2656}
2657
2658
2659/**
2660 * Hook for preparing to use the host FPU for SSE.
2661 *
2662 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2663 *
2664 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2665 */
2666DECLINLINE(void) iemFpuPrepareUsageSse(PVMCPUCC pVCpu) RT_NOEXCEPT
2667{
2668 iemFpuPrepareUsage(pVCpu);
2669}
2670
2671
2672/**
2673 * Hook for preparing to use the host FPU for AVX.
2674 *
2675 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2676 *
2677 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2678 */
2679DECLINLINE(void) iemFpuPrepareUsageAvx(PVMCPUCC pVCpu) RT_NOEXCEPT
2680{
2681 iemFpuPrepareUsage(pVCpu);
2682}
2683
2684
2685/**
2686 * Hook for actualizing the guest FPU state before the interpreter reads it.
2687 *
2688 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2689 *
2690 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2691 */
2692DECLINLINE(void) iemFpuActualizeStateForRead(PVMCPUCC pVCpu) RT_NOEXCEPT
2693{
2694#ifdef IN_RING3
2695 NOREF(pVCpu);
2696#else
2697 CPUMRZFpuStateActualizeForRead(pVCpu);
2698#endif
2699 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2700}
2701
2702
2703/**
2704 * Hook for actualizing the guest FPU state before the interpreter changes it.
2705 *
2706 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2707 *
2708 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2709 */
2710DECLINLINE(void) iemFpuActualizeStateForChange(PVMCPUCC pVCpu) RT_NOEXCEPT
2711{
2712#ifdef IN_RING3
2713 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
2714#else
2715 CPUMRZFpuStateActualizeForChange(pVCpu);
2716#endif
2717 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2718}
2719
2720
2721/**
2722 * Hook for actualizing the guest XMM0..15 and MXCSR register state for read
2723 * only.
2724 *
2725 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2726 *
2727 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2728 */
2729DECLINLINE(void) iemFpuActualizeSseStateForRead(PVMCPUCC pVCpu) RT_NOEXCEPT
2730{
2731#if defined(IN_RING3) || defined(VBOX_WITH_KERNEL_USING_XMM)
2732 NOREF(pVCpu);
2733#else
2734 CPUMRZFpuStateActualizeSseForRead(pVCpu);
2735#endif
2736 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2737}
2738
2739
2740/**
2741 * Hook for actualizing the guest XMM0..15 and MXCSR register state for
2742 * read+write.
2743 *
2744 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2745 *
2746 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2747 */
2748DECLINLINE(void) iemFpuActualizeSseStateForChange(PVMCPUCC pVCpu) RT_NOEXCEPT
2749{
2750#if defined(IN_RING3) || defined(VBOX_WITH_KERNEL_USING_XMM)
2751 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
2752#else
2753 CPUMRZFpuStateActualizeForChange(pVCpu);
2754#endif
2755 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2756
2757 /* Make sure any changes are loaded the next time around. */
2758 pVCpu->cpum.GstCtx.XState.Hdr.bmXState |= XSAVE_C_SSE;
2759}
2760
2761
2762/**
2763 * Hook for actualizing the guest YMM0..15 and MXCSR register state for read
2764 * only.
2765 *
2766 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2767 *
2768 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2769 */
2770DECLINLINE(void) iemFpuActualizeAvxStateForRead(PVMCPUCC pVCpu) RT_NOEXCEPT
2771{
2772#ifdef IN_RING3
2773 NOREF(pVCpu);
2774#else
2775 CPUMRZFpuStateActualizeAvxForRead(pVCpu);
2776#endif
2777 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2778}
2779
2780
2781/**
2782 * Hook for actualizing the guest YMM0..15 and MXCSR register state for
2783 * read+write.
2784 *
2785 * This is necessary in ring-0 and raw-mode context (nop in ring-3).
2786 *
2787 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2788 */
2789DECLINLINE(void) iemFpuActualizeAvxStateForChange(PVMCPUCC pVCpu) RT_NOEXCEPT
2790{
2791#ifdef IN_RING3
2792 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_FPU_REM);
2793#else
2794 CPUMRZFpuStateActualizeForChange(pVCpu);
2795#endif
2796 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx);
2797
2798 /* Just assume we're going to make changes to the SSE and YMM_HI parts. */
2799 pVCpu->cpum.GstCtx.XState.Hdr.bmXState |= XSAVE_C_YMM | XSAVE_C_SSE;
2800}
2801
2802
2803/**
2804 * Stores a QNaN value into a FPU register.
2805 *
2806 * @param pReg Pointer to the register.
2807 */
2808DECLINLINE(void) iemFpuStoreQNan(PRTFLOAT80U pReg) RT_NOEXCEPT
2809{
2810 pReg->au32[0] = UINT32_C(0x00000000);
2811 pReg->au32[1] = UINT32_C(0xc0000000);
2812 pReg->au16[4] = UINT16_C(0xffff);
2813}
2814
2815
2816/**
2817 * Updates the FOP, FPU.CS and FPUIP registers, extended version.
2818 *
2819 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2820 * @param pFpuCtx The FPU context.
2821 * @param uFpuOpcode The FPU opcode value (see IEMCPU::uFpuOpcode).
2822 */
2823DECLINLINE(void) iemFpuUpdateOpcodeAndIpWorkerEx(PVMCPUCC pVCpu, PX86FXSTATE pFpuCtx, uint16_t uFpuOpcode) RT_NOEXCEPT
2824{
2825 Assert(uFpuOpcode != UINT16_MAX);
2826 pFpuCtx->FOP = uFpuOpcode;
2827 /** @todo x87.CS and FPUIP needs to be kept seperately. */
2828 if (IEM_IS_REAL_OR_V86_MODE(pVCpu))
2829 {
2830 /** @todo Testcase: making assumptions about how FPUIP and FPUDP are handled
2831 * happens in real mode here based on the fnsave and fnstenv images. */
2832 pFpuCtx->CS = 0;
2833 pFpuCtx->FPUIP = pVCpu->cpum.GstCtx.eip | ((uint32_t)pVCpu->cpum.GstCtx.cs.Sel << 4);
2834 }
2835 else if (!IEM_IS_LONG_MODE(pVCpu))
2836 {
2837 pFpuCtx->CS = pVCpu->cpum.GstCtx.cs.Sel;
2838 pFpuCtx->FPUIP = pVCpu->cpum.GstCtx.rip;
2839 }
2840 else
2841 *(uint64_t *)&pFpuCtx->FPUIP = pVCpu->cpum.GstCtx.rip;
2842}
2843
2844
2845/**
2846 * Marks the specified stack register as free (for FFREE).
2847 *
2848 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2849 * @param iStReg The register to free.
2850 */
2851DECLINLINE(void) iemFpuStackFree(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT
2852{
2853 Assert(iStReg < 8);
2854 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2855 uint8_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
2856 pFpuCtx->FTW &= ~RT_BIT(iReg);
2857}
2858
2859
2860/**
2861 * Increments FSW.TOP, i.e. pops an item off the stack without freeing it.
2862 *
2863 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2864 */
2865DECLINLINE(void) iemFpuStackIncTop(PVMCPUCC pVCpu) RT_NOEXCEPT
2866{
2867 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2868 uint16_t uFsw = pFpuCtx->FSW;
2869 uint16_t uTop = uFsw & X86_FSW_TOP_MASK;
2870 uTop = (uTop + (1 << X86_FSW_TOP_SHIFT)) & X86_FSW_TOP_MASK;
2871 uFsw &= ~X86_FSW_TOP_MASK;
2872 uFsw |= uTop;
2873 pFpuCtx->FSW = uFsw;
2874}
2875
2876
2877/**
2878 * Decrements FSW.TOP, i.e. push an item off the stack without storing anything.
2879 *
2880 * @param pVCpu The cross context virtual CPU structure of the calling thread.
2881 */
2882DECLINLINE(void) iemFpuStackDecTop(PVMCPUCC pVCpu) RT_NOEXCEPT
2883{
2884 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2885 uint16_t uFsw = pFpuCtx->FSW;
2886 uint16_t uTop = uFsw & X86_FSW_TOP_MASK;
2887 uTop = (uTop + (7 << X86_FSW_TOP_SHIFT)) & X86_FSW_TOP_MASK;
2888 uFsw &= ~X86_FSW_TOP_MASK;
2889 uFsw |= uTop;
2890 pFpuCtx->FSW = uFsw;
2891}
2892
2893
2894
2895
2896DECLINLINE(int) iemFpuStRegNotEmpty(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT
2897{
2898 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2899 uint16_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
2900 if (pFpuCtx->FTW & RT_BIT(iReg))
2901 return VINF_SUCCESS;
2902 return VERR_NOT_FOUND;
2903}
2904
2905
2906DECLINLINE(int) iemFpuStRegNotEmptyRef(PVMCPUCC pVCpu, uint8_t iStReg, PCRTFLOAT80U *ppRef) RT_NOEXCEPT
2907{
2908 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2909 uint16_t iReg = (X86_FSW_TOP_GET(pFpuCtx->FSW) + iStReg) & X86_FSW_TOP_SMASK;
2910 if (pFpuCtx->FTW & RT_BIT(iReg))
2911 {
2912 *ppRef = &pFpuCtx->aRegs[iStReg].r80;
2913 return VINF_SUCCESS;
2914 }
2915 return VERR_NOT_FOUND;
2916}
2917
2918
2919DECLINLINE(int) iemFpu2StRegsNotEmptyRef(PVMCPUCC pVCpu, uint8_t iStReg0, PCRTFLOAT80U *ppRef0,
2920 uint8_t iStReg1, PCRTFLOAT80U *ppRef1) RT_NOEXCEPT
2921{
2922 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2923 uint16_t iTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
2924 uint16_t iReg0 = (iTop + iStReg0) & X86_FSW_TOP_SMASK;
2925 uint16_t iReg1 = (iTop + iStReg1) & X86_FSW_TOP_SMASK;
2926 if ((pFpuCtx->FTW & (RT_BIT(iReg0) | RT_BIT(iReg1))) == (RT_BIT(iReg0) | RT_BIT(iReg1)))
2927 {
2928 *ppRef0 = &pFpuCtx->aRegs[iStReg0].r80;
2929 *ppRef1 = &pFpuCtx->aRegs[iStReg1].r80;
2930 return VINF_SUCCESS;
2931 }
2932 return VERR_NOT_FOUND;
2933}
2934
2935
2936DECLINLINE(int) iemFpu2StRegsNotEmptyRefFirst(PVMCPUCC pVCpu, uint8_t iStReg0, PCRTFLOAT80U *ppRef0, uint8_t iStReg1) RT_NOEXCEPT
2937{
2938 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
2939 uint16_t iTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
2940 uint16_t iReg0 = (iTop + iStReg0) & X86_FSW_TOP_SMASK;
2941 uint16_t iReg1 = (iTop + iStReg1) & X86_FSW_TOP_SMASK;
2942 if ((pFpuCtx->FTW & (RT_BIT(iReg0) | RT_BIT(iReg1))) == (RT_BIT(iReg0) | RT_BIT(iReg1)))
2943 {
2944 *ppRef0 = &pFpuCtx->aRegs[iStReg0].r80;
2945 return VINF_SUCCESS;
2946 }
2947 return VERR_NOT_FOUND;
2948}
2949
2950
2951/**
2952 * Rotates the stack registers when setting new TOS.
2953 *
2954 * @param pFpuCtx The FPU context.
2955 * @param iNewTop New TOS value.
2956 * @remarks We only do this to speed up fxsave/fxrstor which
2957 * arrange the FP registers in stack order.
2958 * MUST be done before writing the new TOS (FSW).
2959 */
2960DECLINLINE(void) iemFpuRotateStackSetTop(PX86FXSTATE pFpuCtx, uint16_t iNewTop) RT_NOEXCEPT
2961{
2962 uint16_t iOldTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
2963 RTFLOAT80U ar80Temp[8];
2964
2965 if (iOldTop == iNewTop)
2966 return;
2967
2968 /* Unscrew the stack and get it into 'native' order. */
2969 ar80Temp[0] = pFpuCtx->aRegs[(8 - iOldTop + 0) & X86_FSW_TOP_SMASK].r80;
2970 ar80Temp[1] = pFpuCtx->aRegs[(8 - iOldTop + 1) & X86_FSW_TOP_SMASK].r80;
2971 ar80Temp[2] = pFpuCtx->aRegs[(8 - iOldTop + 2) & X86_FSW_TOP_SMASK].r80;
2972 ar80Temp[3] = pFpuCtx->aRegs[(8 - iOldTop + 3) & X86_FSW_TOP_SMASK].r80;
2973 ar80Temp[4] = pFpuCtx->aRegs[(8 - iOldTop + 4) & X86_FSW_TOP_SMASK].r80;
2974 ar80Temp[5] = pFpuCtx->aRegs[(8 - iOldTop + 5) & X86_FSW_TOP_SMASK].r80;
2975 ar80Temp[6] = pFpuCtx->aRegs[(8 - iOldTop + 6) & X86_FSW_TOP_SMASK].r80;
2976 ar80Temp[7] = pFpuCtx->aRegs[(8 - iOldTop + 7) & X86_FSW_TOP_SMASK].r80;
2977
2978 /* Now rotate the stack to the new position. */
2979 pFpuCtx->aRegs[0].r80 = ar80Temp[(iNewTop + 0) & X86_FSW_TOP_SMASK];
2980 pFpuCtx->aRegs[1].r80 = ar80Temp[(iNewTop + 1) & X86_FSW_TOP_SMASK];
2981 pFpuCtx->aRegs[2].r80 = ar80Temp[(iNewTop + 2) & X86_FSW_TOP_SMASK];
2982 pFpuCtx->aRegs[3].r80 = ar80Temp[(iNewTop + 3) & X86_FSW_TOP_SMASK];
2983 pFpuCtx->aRegs[4].r80 = ar80Temp[(iNewTop + 4) & X86_FSW_TOP_SMASK];
2984 pFpuCtx->aRegs[5].r80 = ar80Temp[(iNewTop + 5) & X86_FSW_TOP_SMASK];
2985 pFpuCtx->aRegs[6].r80 = ar80Temp[(iNewTop + 6) & X86_FSW_TOP_SMASK];
2986 pFpuCtx->aRegs[7].r80 = ar80Temp[(iNewTop + 7) & X86_FSW_TOP_SMASK];
2987}
2988
2989
2990/**
2991 * Updates the FPU exception status after FCW is changed.
2992 *
2993 * @param pFpuCtx The FPU context.
2994 */
2995DECLINLINE(void) iemFpuRecalcExceptionStatus(PX86FXSTATE pFpuCtx) RT_NOEXCEPT
2996{
2997 uint16_t u16Fsw = pFpuCtx->FSW;
2998 if ((u16Fsw & X86_FSW_XCPT_MASK) & ~(pFpuCtx->FCW & X86_FCW_XCPT_MASK))
2999 u16Fsw |= X86_FSW_ES | X86_FSW_B;
3000 else
3001 u16Fsw &= ~(X86_FSW_ES | X86_FSW_B);
3002 pFpuCtx->FSW = u16Fsw;
3003}
3004
3005
3006/**
3007 * Calculates the full FTW (FPU tag word) for use in FNSTENV and FNSAVE.
3008 *
3009 * @returns The full FTW.
3010 * @param pFpuCtx The FPU context.
3011 */
3012DECLINLINE(uint16_t) iemFpuCalcFullFtw(PCX86FXSTATE pFpuCtx) RT_NOEXCEPT
3013{
3014 uint8_t const u8Ftw = (uint8_t)pFpuCtx->FTW;
3015 uint16_t u16Ftw = 0;
3016 unsigned const iTop = X86_FSW_TOP_GET(pFpuCtx->FSW);
3017 for (unsigned iSt = 0; iSt < 8; iSt++)
3018 {
3019 unsigned const iReg = (iSt + iTop) & 7;
3020 if (!(u8Ftw & RT_BIT(iReg)))
3021 u16Ftw |= 3 << (iReg * 2); /* empty */
3022 else
3023 {
3024 uint16_t uTag;
3025 PCRTFLOAT80U const pr80Reg = &pFpuCtx->aRegs[iSt].r80;
3026 if (pr80Reg->s.uExponent == 0x7fff)
3027 uTag = 2; /* Exponent is all 1's => Special. */
3028 else if (pr80Reg->s.uExponent == 0x0000)
3029 {
3030 if (pr80Reg->s.uMantissa == 0x0000)
3031 uTag = 1; /* All bits are zero => Zero. */
3032 else
3033 uTag = 2; /* Must be special. */
3034 }
3035 else if (pr80Reg->s.uMantissa & RT_BIT_64(63)) /* The J bit. */
3036 uTag = 0; /* Valid. */
3037 else
3038 uTag = 2; /* Must be special. */
3039
3040 u16Ftw |= uTag << (iReg * 2);
3041 }
3042 }
3043
3044 return u16Ftw;
3045}
3046
3047
3048/**
3049 * Converts a full FTW to a compressed one (for use in FLDENV and FRSTOR).
3050 *
3051 * @returns The compressed FTW.
3052 * @param u16FullFtw The full FTW to convert.
3053 */
3054DECLINLINE(uint16_t) iemFpuCompressFtw(uint16_t u16FullFtw) RT_NOEXCEPT
3055{
3056 uint8_t u8Ftw = 0;
3057 for (unsigned i = 0; i < 8; i++)
3058 {
3059 if ((u16FullFtw & 3) != 3 /*empty*/)
3060 u8Ftw |= RT_BIT(i);
3061 u16FullFtw >>= 2;
3062 }
3063
3064 return u8Ftw;
3065}
3066
3067/** @} */
3068
3069
3070/** @name Memory access.
3071 *
3072 * @{
3073 */
3074
3075
3076/**
3077 * Checks whether alignment checks are enabled or not.
3078 *
3079 * @returns true if enabled, false if not.
3080 * @param pVCpu The cross context virtual CPU structure of the calling thread.
3081 */
3082DECLINLINE(bool) iemMemAreAlignmentChecksEnabled(PVMCPUCC pVCpu) RT_NOEXCEPT
3083{
3084 AssertCompile(X86_CR0_AM == X86_EFL_AC);
3085 return IEM_GET_CPL(pVCpu) == 3
3086 && (((uint32_t)pVCpu->cpum.GstCtx.cr0 & pVCpu->cpum.GstCtx.eflags.u) & X86_CR0_AM);
3087}
3088
3089/**
3090 * Checks if the given segment can be written to, raise the appropriate
3091 * exception if not.
3092 *
3093 * @returns VBox strict status code.
3094 *
3095 * @param pVCpu The cross context virtual CPU structure of the calling thread.
3096 * @param pHid Pointer to the hidden register.
3097 * @param iSegReg The register number.
3098 * @param pu64BaseAddr Where to return the base address to use for the
3099 * segment. (In 64-bit code it may differ from the
3100 * base in the hidden segment.)
3101 */
3102DECLINLINE(VBOXSTRICTRC) iemMemSegCheckWriteAccessEx(PVMCPUCC pVCpu, PCCPUMSELREGHID pHid,
3103 uint8_t iSegReg, uint64_t *pu64BaseAddr) RT_NOEXCEPT
3104{
3105 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
3106
3107 if (IEM_IS_64BIT_CODE(pVCpu))
3108 *pu64BaseAddr = iSegReg < X86_SREG_FS ? 0 : pHid->u64Base;
3109 else
3110 {
3111 if (!pHid->Attr.n.u1Present)
3112 {
3113 uint16_t uSel = iemSRegFetchU16(pVCpu, iSegReg);
3114 AssertRelease(uSel == 0);
3115 Log(("iemMemSegCheckWriteAccessEx: %#x (index %u) - bad selector -> #GP\n", uSel, iSegReg));
3116 return iemRaiseGeneralProtectionFault0(pVCpu);
3117 }
3118
3119 if ( ( (pHid->Attr.n.u4Type & X86_SEL_TYPE_CODE)
3120 || !(pHid->Attr.n.u4Type & X86_SEL_TYPE_WRITE) )
3121 && !IEM_IS_64BIT_CODE(pVCpu) )
3122 return iemRaiseSelectorInvalidAccess(pVCpu, iSegReg, IEM_ACCESS_DATA_W);
3123 *pu64BaseAddr = pHid->u64Base;
3124 }
3125 return VINF_SUCCESS;
3126}
3127
3128
3129/**
3130 * Checks if the given segment can be read from, raise the appropriate
3131 * exception if not.
3132 *
3133 * @returns VBox strict status code.
3134 *
3135 * @param pVCpu The cross context virtual CPU structure of the calling thread.
3136 * @param pHid Pointer to the hidden register.
3137 * @param iSegReg The register number.
3138 * @param pu64BaseAddr Where to return the base address to use for the
3139 * segment. (In 64-bit code it may differ from the
3140 * base in the hidden segment.)
3141 */
3142DECLINLINE(VBOXSTRICTRC) iemMemSegCheckReadAccessEx(PVMCPUCC pVCpu, PCCPUMSELREGHID pHid,
3143 uint8_t iSegReg, uint64_t *pu64BaseAddr) RT_NOEXCEPT
3144{
3145 IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
3146
3147 if (IEM_IS_64BIT_CODE(pVCpu))
3148 *pu64BaseAddr = iSegReg < X86_SREG_FS ? 0 : pHid->u64Base;
3149 else
3150 {
3151 if (!pHid->Attr.n.u1Present)
3152 {
3153 uint16_t uSel = iemSRegFetchU16(pVCpu, iSegReg);
3154 AssertRelease(uSel == 0);
3155 Log(("iemMemSegCheckReadAccessEx: %#x (index %u) - bad selector -> #GP\n", uSel, iSegReg));
3156 return iemRaiseGeneralProtectionFault0(pVCpu);
3157 }
3158
3159 if ((pHid->Attr.n.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ)) == X86_SEL_TYPE_CODE)
3160 return iemRaiseSelectorInvalidAccess(pVCpu, iSegReg, IEM_ACCESS_DATA_R);
3161 *pu64BaseAddr = pHid->u64Base;
3162 }
3163 return VINF_SUCCESS;
3164}
3165
3166
3167/**
3168 * Maps a physical page.
3169 *
3170 * @returns VBox status code (see PGMR3PhysTlbGCPhys2Ptr).
3171 * @param pVCpu The cross context virtual CPU structure of the calling thread.
3172 * @param GCPhysMem The physical address.
3173 * @param fAccess The intended access.
3174 * @param ppvMem Where to return the mapping address.
3175 * @param pLock The PGM lock.
3176 */
3177DECLINLINE(int) iemMemPageMap(PVMCPUCC pVCpu, RTGCPHYS GCPhysMem, uint32_t fAccess,
3178 void **ppvMem, PPGMPAGEMAPLOCK pLock) RT_NOEXCEPT
3179{
3180#ifdef IEM_LOG_MEMORY_WRITES
3181 if (fAccess & IEM_ACCESS_TYPE_WRITE)
3182 return VERR_PGM_PHYS_TLB_CATCH_ALL;
3183#endif
3184
3185 /** @todo This API may require some improving later. A private deal with PGM
3186 * regarding locking and unlocking needs to be struct. A couple of TLBs
3187 * living in PGM, but with publicly accessible inlined access methods
3188 * could perhaps be an even better solution. */
3189 int rc = PGMPhysIemGCPhys2Ptr(pVCpu->CTX_SUFF(pVM), pVCpu,
3190 GCPhysMem,
3191 RT_BOOL(fAccess & IEM_ACCESS_TYPE_WRITE),
3192 RT_BOOL(pVCpu->iem.s.fExec & IEM_F_BYPASS_HANDLERS),
3193 ppvMem,
3194 pLock);
3195 /*Log(("PGMPhysIemGCPhys2Ptr %Rrc pLock=%.*Rhxs\n", rc, sizeof(*pLock), pLock));*/
3196 AssertMsg(rc == VINF_SUCCESS || RT_FAILURE_NP(rc), ("%Rrc\n", rc));
3197
3198 return rc;
3199}
3200
3201
3202/**
3203 * Unmap a page previously mapped by iemMemPageMap.
3204 *
3205 * @param pVCpu The cross context virtual CPU structure of the calling thread.
3206 * @param GCPhysMem The physical address.
3207 * @param fAccess The intended access.
3208 * @param pvMem What iemMemPageMap returned.
3209 * @param pLock The PGM lock.
3210 */
3211DECLINLINE(void) iemMemPageUnmap(PVMCPUCC pVCpu, RTGCPHYS GCPhysMem, uint32_t fAccess,
3212 const void *pvMem, PPGMPAGEMAPLOCK pLock) RT_NOEXCEPT
3213{
3214 NOREF(pVCpu);
3215 NOREF(GCPhysMem);
3216 NOREF(fAccess);
3217 NOREF(pvMem);
3218 PGMPhysReleasePageMappingLock(pVCpu->CTX_SUFF(pVM), pLock);
3219}
3220
3221#ifdef IEM_WITH_SETJMP
3222
3223/** @todo slim this down */
3224DECL_INLINE_THROW(RTGCPTR) iemMemApplySegmentToReadJmp(PVMCPUCC pVCpu, uint8_t iSegReg,
3225 size_t cbMem, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
3226{
3227 Assert(cbMem >= 1);
3228 Assert(iSegReg < X86_SREG_COUNT);
3229
3230 /*
3231 * 64-bit mode is simpler.
3232 */
3233 if (IEM_IS_64BIT_CODE(pVCpu))
3234 {
3235 if (iSegReg >= X86_SREG_FS && iSegReg != UINT8_MAX)
3236 {
3237 IEM_CTX_IMPORT_JMP(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
3238 PCPUMSELREGHID const pSel = iemSRegGetHid(pVCpu, iSegReg);
3239 GCPtrMem += pSel->u64Base;
3240 }
3241
3242 if (RT_LIKELY(X86_IS_CANONICAL(GCPtrMem) && X86_IS_CANONICAL(GCPtrMem + cbMem - 1)))
3243 return GCPtrMem;
3244 iemRaiseGeneralProtectionFault0Jmp(pVCpu);
3245 }
3246 /*
3247 * 16-bit and 32-bit segmentation.
3248 */
3249 else if (iSegReg != UINT8_MAX)
3250 {
3251 /** @todo Does this apply to segments with 4G-1 limit? */
3252 uint32_t const GCPtrLast32 = (uint32_t)GCPtrMem + (uint32_t)cbMem - 1;
3253 if (RT_LIKELY(GCPtrLast32 >= (uint32_t)GCPtrMem))
3254 {
3255 IEM_CTX_IMPORT_JMP(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
3256 PCPUMSELREGHID const pSel = iemSRegGetHid(pVCpu, iSegReg);
3257 switch (pSel->Attr.u & ( X86DESCATTR_P | X86DESCATTR_UNUSABLE
3258 | X86_SEL_TYPE_READ | X86_SEL_TYPE_WRITE /* same as read */
3259 | X86_SEL_TYPE_DOWN | X86_SEL_TYPE_CONF /* same as down */
3260 | X86_SEL_TYPE_CODE))
3261 {
3262 case X86DESCATTR_P: /* readonly data, expand up */
3263 case X86DESCATTR_P | X86_SEL_TYPE_WRITE: /* writable data, expand up */
3264 case X86DESCATTR_P | X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ: /* code, read-only */
3265 case X86DESCATTR_P | X86_SEL_TYPE_CODE | X86_SEL_TYPE_READ | X86_SEL_TYPE_CONF: /* conforming code, read-only */
3266 /* expand up */
3267 if (RT_LIKELY(GCPtrLast32 <= pSel->u32Limit))
3268 return (uint32_t)GCPtrMem + (uint32_t)pSel->u64Base;
3269 Log10(("iemMemApplySegmentToReadJmp: out of bounds %#x..%#x vs %#x\n",
3270 (uint32_t)GCPtrMem, GCPtrLast32, pSel->u32Limit));
3271 break;
3272
3273 case X86DESCATTR_P | X86_SEL_TYPE_DOWN: /* readonly data, expand down */
3274 case X86DESCATTR_P | X86_SEL_TYPE_DOWN | X86_SEL_TYPE_WRITE: /* writable data, expand down */
3275 /* expand down */
3276 if (RT_LIKELY( (uint32_t)GCPtrMem > pSel->u32Limit
3277 && ( pSel->Attr.n.u1DefBig
3278 || GCPtrLast32 <= UINT32_C(0xffff)) ))
3279 return (uint32_t)GCPtrMem + (uint32_t)pSel->u64Base;
3280 Log10(("iemMemApplySegmentToReadJmp: expand down out of bounds %#x..%#x vs %#x..%#x\n",
3281 (uint32_t)GCPtrMem, GCPtrLast32, pSel->u32Limit, pSel->Attr.n.u1DefBig ? UINT32_MAX : UINT16_MAX));
3282 break;
3283
3284 default:
3285 Log10(("iemMemApplySegmentToReadJmp: bad selector %#x\n", pSel->Attr.u));
3286 iemRaiseSelectorInvalidAccessJmp(pVCpu, iSegReg, IEM_ACCESS_DATA_R);
3287 break;
3288 }
3289 }
3290 Log10(("iemMemApplySegmentToReadJmp: out of bounds %#x..%#x\n",(uint32_t)GCPtrMem, GCPtrLast32));
3291 iemRaiseSelectorBoundsJmp(pVCpu, iSegReg, IEM_ACCESS_DATA_R);
3292 }
3293 /*
3294 * 32-bit flat address.
3295 */
3296 else
3297 return GCPtrMem;
3298}
3299
3300
3301/** @todo slim this down */
3302DECL_INLINE_THROW(RTGCPTR) iemMemApplySegmentToWriteJmp(PVMCPUCC pVCpu, uint8_t iSegReg, size_t cbMem,
3303 RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP
3304{
3305 Assert(cbMem >= 1);
3306 Assert(iSegReg < X86_SREG_COUNT);
3307
3308 /*
3309 * 64-bit mode is simpler.
3310 */
3311 if (IEM_IS_64BIT_CODE(pVCpu))
3312 {
3313 if (iSegReg >= X86_SREG_FS)
3314 {
3315 IEM_CTX_IMPORT_JMP(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
3316 PCPUMSELREGHID pSel = iemSRegGetHid(pVCpu, iSegReg);
3317 GCPtrMem += pSel->u64Base;
3318 }
3319
3320 if (RT_LIKELY(X86_IS_CANONICAL(GCPtrMem) && X86_IS_CANONICAL(GCPtrMem + cbMem - 1)))
3321 return GCPtrMem;
3322 }
3323 /*
3324 * 16-bit and 32-bit segmentation.
3325 */
3326 else
3327 {
3328 IEM_CTX_IMPORT_JMP(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(iSegReg));
3329 PCPUMSELREGHID pSel = iemSRegGetHid(pVCpu, iSegReg);
3330 uint32_t const fRelevantAttrs = pSel->Attr.u & ( X86DESCATTR_P | X86DESCATTR_UNUSABLE
3331 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_WRITE | X86_SEL_TYPE_DOWN);
3332 if (fRelevantAttrs == (X86DESCATTR_P | X86_SEL_TYPE_WRITE)) /* data, expand up */
3333 {
3334 /* expand up */
3335 uint32_t GCPtrLast32 = (uint32_t)GCPtrMem + (uint32_t)cbMem;
3336 if (RT_LIKELY( GCPtrLast32 > pSel->u32Limit
3337 && GCPtrLast32 > (uint32_t)GCPtrMem))
3338 return (uint32_t)GCPtrMem + (uint32_t)pSel->u64Base;
3339 }
3340 else if (fRelevantAttrs == (X86DESCATTR_P | X86_SEL_TYPE_WRITE | X86_SEL_TYPE_DOWN)) /* data, expand up */
3341 {
3342 /* expand down */
3343 uint32_t GCPtrLast32 = (uint32_t)GCPtrMem + (uint32_t)cbMem;
3344 if (RT_LIKELY( (uint32_t)GCPtrMem > pSel->u32Limit
3345 && GCPtrLast32 <= (pSel->Attr.n.u1DefBig ? UINT32_MAX : UINT32_C(0xffff))
3346 && GCPtrLast32 > (uint32_t)GCPtrMem))
3347 return (uint32_t)GCPtrMem + (uint32_t)pSel->u64Base;
3348 }
3349 else
3350 iemRaiseSelectorInvalidAccessJmp(pVCpu, iSegReg, IEM_ACCESS_DATA_W);
3351 iemRaiseSelectorBoundsJmp(pVCpu, iSegReg, IEM_ACCESS_DATA_W);
3352 }
3353 iemRaiseGeneralProtectionFault0Jmp(pVCpu);
3354}
3355
3356#endif /* IEM_WITH_SETJMP */
3357
3358/**
3359 * Fakes a long mode stack selector for SS = 0.
3360 *
3361 * @param pDescSs Where to return the fake stack descriptor.
3362 * @param uDpl The DPL we want.
3363 */
3364DECLINLINE(void) iemMemFakeStackSelDesc(PIEMSELDESC pDescSs, uint32_t uDpl) RT_NOEXCEPT
3365{
3366 pDescSs->Long.au64[0] = 0;
3367 pDescSs->Long.au64[1] = 0;
3368 pDescSs->Long.Gen.u4Type = X86_SEL_TYPE_RW_ACC;
3369 pDescSs->Long.Gen.u1DescType = 1; /* 1 = code / data, 0 = system. */
3370 pDescSs->Long.Gen.u2Dpl = uDpl;
3371 pDescSs->Long.Gen.u1Present = 1;
3372 pDescSs->Long.Gen.u1Long = 1;
3373}
3374
3375/** @} */
3376
3377
3378#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3379
3380/**
3381 * Gets CR0 fixed-0 bits in VMX operation.
3382 *
3383 * We do this rather than fetching what we report to the guest (in
3384 * IA32_VMX_CR0_FIXED0 MSR) because real hardware (and so do we) report the same
3385 * values regardless of whether unrestricted-guest feature is available on the CPU.
3386 *
3387 * @returns CR0 fixed-0 bits.
3388 * @param pVCpu The cross context virtual CPU structure.
3389 * @param fVmxNonRootMode Whether the CR0 fixed-0 bits for VMX non-root mode
3390 * must be returned. When @c false, the CR0 fixed-0
3391 * bits for VMX root mode is returned.
3392 *
3393 */
3394DECLINLINE(uint64_t) iemVmxGetCr0Fixed0(PCVMCPUCC pVCpu, bool fVmxNonRootMode) RT_NOEXCEPT
3395{
3396 Assert(IEM_VMX_IS_ROOT_MODE(pVCpu));
3397
3398 PCVMXMSRS pMsrs = &pVCpu->cpum.GstCtx.hwvirt.vmx.Msrs;
3399 if ( fVmxNonRootMode
3400 && (pMsrs->ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST))
3401 return VMX_V_CR0_FIXED0_UX;
3402 return VMX_V_CR0_FIXED0;
3403}
3404
3405
3406/**
3407 * Sets virtual-APIC write emulation as pending.
3408 *
3409 * @param pVCpu The cross context virtual CPU structure.
3410 * @param offApic The offset in the virtual-APIC page that was written.
3411 */
3412DECLINLINE(void) iemVmxVirtApicSetPendingWrite(PVMCPUCC pVCpu, uint16_t offApic) RT_NOEXCEPT
3413{
3414 Assert(offApic < XAPIC_OFF_END + 4);
3415
3416 /*
3417 * Record the currently updated APIC offset, as we need this later for figuring
3418 * out whether to perform TPR, EOI or self-IPI virtualization as well as well
3419 * as for supplying the exit qualification when causing an APIC-write VM-exit.
3420 */
3421 pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = offApic;
3422
3423 /*
3424 * Flag that we need to perform virtual-APIC write emulation (TPR/PPR/EOI/Self-IPI
3425 * virtualization or APIC-write emulation).
3426 */
3427 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
3428 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE);
3429}
3430
3431#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
3432
3433#endif /* !VMM_INCLUDED_SRC_include_IEMInline_h */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette