HMInternal.mac@ 94156

Last change on this file since 94156 was 93963, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Add HM ring-0 API for querying transient VMX/SVM info.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 9.3 KB

Line
1	;$Id: HMInternal.mac 93963 2022-02-28 08:39:08Z vboxsync $
2	;; @file
3	; HM - Internal header file.
4	;
5
6	;
7	; Copyright (C) 2006-2022 Oracle Corporation
8	;
9	; This file is part of VirtualBox Open Source Edition (OSE), as
10	; available from http://www.virtualbox.org. This file is free software;
11	; you can redistribute it and/or modify it under the terms of the GNU
12	; General Public License (GPL) as published by the Free Software
13	; Foundation, in version 2 as it comes in the "COPYING" file of the
14	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	;
17
18	%ifndef VMX_VMCS_GUEST_FIELD_ES
19	%include "VBox/vmm/hm_vmx.mac" ; For VMXRESTOREHOST
20	%endif
21
22	struc VMXVMCSINFOSHARED
23	.fWasInRealMode resb 1
24	alignb 8
25	.RealMode.AttrCS resd 1
26	.RealMode.AttrDS resd 1
27	.RealMode.AttrES resd 1
28	.RealMode.AttrFS resd 1
29	.RealMode.AttrGS resd 1
30	.RealMode.AttrSS resd 1
31	.RealMode.Eflags resd 1 ; should be EFlags?
32	.RealMode.fRealOnV86Active resb 1
33
34	alignb 8
35	.au64LbrFromIpMsr resq 32
36	.au64LbrToIpMsr resq 32
37	.au64LbrInfoMsr resq 32
38	.u64LbrTosMsr resq 1
39	.u64LerFromIpMsr resq 1
40	.u64LerToIpMsr resq 1
41	endstruc
42
43
44	struc VMXVMCSINFO
45	.pShared RTR0PTR_RES 1
46
47	.HCPhysEPTP RTHCPHYS_RES 1
48	.fVmcsState resd 1
49	.fShadowVmcsState resd 1
50	.idHostCpuState resd 1
51	.idHostCpuExec resd 1
52	.cEntryMsrLoad resd 1
53	.cExitMsrStore resd 1
54	.cExitMsrLoad resd 1
55
56	.u32PinCtls resd 1
57	.u32ProcCtls resd 1
58	.u32ProcCtls2 resd 1
59	.u64ProcCtls3 resq 1
60	.u32EntryCtls resd 1
61	.u32ExitCtls resd 1
62	.u32XcptBitmap resd 1
63	.u32XcptPFMask resd 1
64	.u32XcptPFMatch resd 1
65
66	alignb 8
67	.u64TscOffset resq 1
68	.u64VmcsLinkPtr resq 1
69	.u64Cr0Mask resq 1
70	.u64Cr4Mask resq 1
71	.uHostRip resq 1
72	.uHostRsp resq 1
73
74	.pvVmcs RTR0PTR_RES 1
75	.pvShadowVmcs RTR0PTR_RES 1
76	.pbVirtApic RTR0PTR_RES 1
77	.pvMsrBitmap RTR0PTR_RES 1
78	.pvGuestMsrLoad RTR0PTR_RES 1
79	.pvGuestMsrStore RTR0PTR_RES 1
80	.pvHostMsrLoad RTR0PTR_RES 1
81
82	alignb 8
83	.HCPhysVmcs RTHCPHYS_RES 1
84	.HCPhysShadowVmcs RTHCPHYS_RES 1
85	.HCPhysVirtApic RTHCPHYS_RES 1
86	.HCPhysMsrBitmap RTHCPHYS_RES 1
87	.HCPhysGuestMsrLoad RTHCPHYS_RES 1
88	.HCPhysGuestMsrStore RTHCPHYS_RES 1
89	.HCPhysHostMsrLoad RTHCPHYS_RES 1
90
91	.hMemObj RTR0PTR_RES 1
92	endstruc
93
94	%define VMX_RESTORE_HOST_SEL_DS 0001h ;RT_BIT(0)
95	%define VMX_RESTORE_HOST_SEL_ES 0002h ;RT_BIT(1)
96	%define VMX_RESTORE_HOST_SEL_FS 0004h ;RT_BIT(2)
97	%define VMX_RESTORE_HOST_SEL_GS 0008h ;RT_BIT(3)
98	%define VMX_RESTORE_HOST_SEL_TR 0010h ;RT_BIT(4)
99	%define VMX_RESTORE_HOST_GDTR 0020h ;RT_BIT(5)
100	%define VMX_RESTORE_HOST_IDTR 0040h ;RT_BIT(6)
101	%define VMX_RESTORE_HOST_GDT_READ_ONLY 0080h ;RT_BIT(7)
102	%define VMX_RESTORE_HOST_GDT_NEED_WRITABLE 0100h ;RT_BIT(8)
103	%define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE 0200h ;RT_BIT(9)
104	%define VMX_RESTORE_HOST_REQUIRED 0400h ;RT_BIT(10) - must be the highest bit!
105	struc VMXRESTOREHOST
106	.uHostSelDS resw 1
107	.uHostSelES resw 1
108	.uHostSelFS resw 1
109	.HostGdtr resb 10
110	.uHostSelGS resw 1
111	.uHostSelTR resw 1
112	.uHostSelSS resw 1
113	.HostGdtrRw resb 10
114	.uHostSelCS resw 1
115	.abPadding1 resb 4
116	.HostIdtr resb 10
117	alignb 8
118	.uHostFSBase resq 1
119	.uHostGSBase resq 1
120	endstruc
121
122	struc HMCPUVMX
123	.VmcsInfo resb VMXVMCSINFOSHARED_size
124	.VmcsInfoNstGst resb VMXVMCSINFOSHARED_size
125	.fSwitchedToNstGstVmcsCopyForRing3 resb 1
126	.fMergedNstGstCtls resb 1
127	.fCopiedNstGstToShadowVmcs resb 1
128	.fSwitchedNstGstFlushTlb resb 1
129
130	alignb 8
131	.u64GstMsrApicBase resq 1
132
133	.LastError.idCurrentCpu resd 1
134	.LastError.idEnteredCpu resd 1
135	.LastError.HCPhysCurrentVmcs resq 1
136	.LastError.u32VmcsRev resd 1
137	.LastError.u32InstrError resd 1
138	.LastError.u32ExitReason resd 1
139	.LastError.u32GuestIntrState resd 1
140	endstruc
141
142	struc HMCPUSVM
143	.fEmulateLongModeSysEnterExit resb 1
144
145	alignb 8
146	.NstGstVmcbCache resb 40
147	endstruc
148
149	struc HMCPU
150	.fCheckedTLBFlush resb 1
151	.fActive resb 1
152	.fUseDebugLoop resb 1
153
154	.fGIMTrapXcptUD resb 1
155	.fTrapXcptGpForLovelyMesaDrv resb 1
156	.fSingleInstruction resb 1
157	alignb 8
158
159	.u32HMError resd 1
160	.rcLastExitToR3 resd 1
161	alignb 8
162	.fCtxChanged resq 1
163
164	alignb 8
165	.vmx resb HMCPUVMX_size
166	alignb 8
167	.svm resb HMCPUSVM_size
168
169	.Event.fPending resd 1
170	.Event.u32ErrCode resd 1
171	.Event.cbInstr resd 1
172	alignb 8
173	.Event.u64IntInfo resq 1
174	.Event.GCPtrFaultAddress RTGCPTR_RES 1
175
176	.enmShadowMode resd 1
177	alignb 8
178	.aPdpes resq 4
179
180	.StatVmxWriteHostRip resq 1
181	.StatVmxWriteHostRsp resq 1
182
183	; The remainer is disassembly state and statistics.
184	endstruc
185
186	struc HMR0CPUVMX
187	.pfnStartVm RTR0PTR_RES 1
188	.uTscDeadline resq 1
189	.uTscDeadlineVersion resq 1
190
191
192	.VmcsInfo resb VMXVMCSINFO_size
193	.VmcsInfoNstGst resb VMXVMCSINFO_size
194	.fSwitchedToNstGstVmcs resb 1
195	alignb 8
196	.pVmxTransient RTR0PTR_RES 1
197
198	.u64HostMsrLStar resq 1
199	.u64HostMsrStar resq 1
200	.u64HostMsrSfMask resq 1
201	.u64HostMsrKernelGsBase resq 1
202	.fLazyMsrs resd 1
203	.fUpdatedHostAutoMsrs resb 1
204	alignb 4
205	.fRestoreHostFlags resd 1
206	alignb 8
207	.RestoreHost resb VMXRESTOREHOST_size
208	endstruc
209
210	struc HMR0CPUSVM
211	.pfnVMRun RTR0PTR_RES 1
212
213	alignb 8
214	.HCPhysVmcbHost RTHCPHYS_RES 1
215
216	alignb 8
217	.hMemObjVmcbHost RTR0PTR_RES 1
218
219	alignb 8
220	.HCPhysVmcb RTHCPHYS_RES 1
221	.hMemObjVmcb RTR0PTR_RES 1
222	.pVmcb RTR0PTR_RES 1
223
224	alignb 8
225	.HCPhysMsrBitmap RTHCPHYS_RES 1
226	.hMemObjMsrBitmap RTR0PTR_RES 1
227	.pvMsrBitmap RTR0PTR_RES 1
228
229	.fSyncVTpr resb 1
230
231	alignb 8
232	.pSvmTransient RTR0PTR_RES 1
233	.u64HostTscAux resq 1
234
235	alignb 8
236	.DisState resb 0d8h
237	endstruc
238
239	struc HMR0PERVCPU
240	.cWorldSwitchExits resd 1
241	.cTlbFlushes resd 1
242	.idLastCpu resd 1
243	.idEnteredCpu resd 1
244	.uCurrentAsid resd 1
245
246	.fForceTLBFlush resb 1
247	.fLeaveDone resb 1
248	.fUsingHyperDR7 resb 1
249	.fUsingDebugLoop resb 1
250	.fDebugWantRdTscExit resb 1
251	.fLoadSaveGuestXcr0 resb 1
252	.fClearTrapFlag resb 1
253
254	alignb 4
255	.fWorldSwitcher resd 1
256	.uTscExit resq 1
257
258	alignb 8
259	.vmx resb HMR0CPUVMX_size
260	alignb 8
261	.svm resb HMR0CPUSVM_size
262	endstruc
263
264	%define HM_WSF_IBPB_EXIT RT_BIT_32(0)
265	%define HM_WSF_IBPB_ENTRY RT_BIT_32(1)
266	%define HM_WSF_L1D_ENTRY RT_BIT_32(2)
267	%define HM_WSF_MDS_ENTRY RT_BIT_32(3)
268

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