| 1 | ;$Id: HMInternal.mac 87754 2021-02-13 17:44:31Z vboxsync $
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| 2 | ;; @file
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| 3 | ; HM - Internal header file.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2006-2020 Oracle Corporation
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 |
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| 18 | %ifndef VMX_VMCS_GUEST_FIELD_ES
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| 19 | %include "VBox/vmm/hm_vmx.mac" ; For VMXRESTOREHOST
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| 20 | %endif
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| 21 |
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| 22 | struc VMXVMCSINFOSHARED
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| 23 | .fWasInRealMode resb 1
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| 24 | alignb 8
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| 25 | .RealMode.AttrCS resd 1
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| 26 | .RealMode.AttrDS resd 1
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| 27 | .RealMode.AttrES resd 1
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| 28 | .RealMode.AttrFS resd 1
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| 29 | .RealMode.AttrGS resd 1
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| 30 | .RealMode.AttrSS resd 1
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| 31 | .RealMode.Eflags resd 1 ; should be EFlags?
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| 32 | .RealMode.fRealOnV86Active resb 1
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| 33 |
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| 34 | alignb 8
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| 35 | .au64LbrFromIpMsr resq 32
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| 36 | .au64LbrToIpMsr resq 32
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| 37 | .u64LbrTosMsr resq 1
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| 38 | endstruc
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| 39 |
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| 40 |
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| 41 | struc VMXVMCSINFO
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| 42 | .pShared RTR0PTR_RES 1
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| 43 |
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| 44 | .HCPhysEPTP RTHCPHYS_RES 1
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| 45 | .fVmcsState resd 1
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| 46 | .fShadowVmcsState resd 1
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| 47 | .idHostCpuState resd 1
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| 48 | .idHostCpuExec resd 1
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| 49 | .cEntryMsrLoad resd 1
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| 50 | .cExitMsrStore resd 1
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| 51 | .cExitMsrLoad resd 1
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| 52 |
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| 53 | .u32PinCtls resd 1
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| 54 | .u32ProcCtls resd 1
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| 55 | .u32ProcCtls2 resd 1
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| 56 | .u32EntryCtls resd 1
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| 57 | .u32ExitCtls resd 1
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| 58 | .u32XcptBitmap resd 1
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| 59 | .u32XcptPFMask resd 1
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| 60 | .u32XcptPFMatch resd 1
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| 61 |
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| 62 | alignb 8
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| 63 | .u64TscOffset resq 1
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| 64 | .u64VmcsLinkPtr resq 1
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| 65 | .u64Cr0Mask resq 1
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| 66 | .u64Cr4Mask resq 1
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| 67 | .uHostRip resq 1
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| 68 | .uHostRsp resq 1
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| 69 |
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| 70 | .pvVmcs RTR0PTR_RES 1
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| 71 | .pvShadowVmcs RTR0PTR_RES 1
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| 72 | .pbVirtApic RTR0PTR_RES 1
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| 73 | .pvMsrBitmap RTR0PTR_RES 1
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| 74 | .pvGuestMsrLoad RTR0PTR_RES 1
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| 75 | .pvGuestMsrStore RTR0PTR_RES 1
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| 76 | .pvHostMsrLoad RTR0PTR_RES 1
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| 77 |
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| 78 | alignb 8
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| 79 | .HCPhysVmcs RTHCPHYS_RES 1
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| 80 | .HCPhysShadowVmcs RTHCPHYS_RES 1
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| 81 | .HCPhysVirtApic RTHCPHYS_RES 1
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| 82 | .HCPhysMsrBitmap RTHCPHYS_RES 1
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| 83 | .HCPhysGuestMsrLoad RTHCPHYS_RES 1
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| 84 | .HCPhysGuestMsrStore RTHCPHYS_RES 1
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| 85 | .HCPhysHostMsrLoad RTHCPHYS_RES 1
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| 86 |
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| 87 | .hMemObj RTR0PTR_RES 1
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| 88 | endstruc
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| 89 |
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| 90 | %define VMX_RESTORE_HOST_SEL_DS 0001h ;RT_BIT(0)
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| 91 | %define VMX_RESTORE_HOST_SEL_ES 0002h ;RT_BIT(1)
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| 92 | %define VMX_RESTORE_HOST_SEL_FS 0004h ;RT_BIT(2)
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| 93 | %define VMX_RESTORE_HOST_SEL_GS 0008h ;RT_BIT(3)
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| 94 | %define VMX_RESTORE_HOST_SEL_TR 0010h ;RT_BIT(4)
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| 95 | %define VMX_RESTORE_HOST_GDTR 0020h ;RT_BIT(5)
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| 96 | %define VMX_RESTORE_HOST_IDTR 0040h ;RT_BIT(6)
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| 97 | %define VMX_RESTORE_HOST_GDT_READ_ONLY 0080h ;RT_BIT(7)
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| 98 | %define VMX_RESTORE_HOST_GDT_NEED_WRITABLE 0100h ;RT_BIT(8)
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| 99 | %define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE 0200h ;RT_BIT(9)
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| 100 | %define VMX_RESTORE_HOST_REQUIRED 0400h ;RT_BIT(10) - must be the highest bit!
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| 101 | struc VMXRESTOREHOST
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| 102 | .uHostSelDS resw 1
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| 103 | .uHostSelES resw 1
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| 104 | .uHostSelFS resw 1
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| 105 | .HostGdtr resb 10
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| 106 | .uHostSelGS resw 1
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| 107 | .uHostSelTR resw 1
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| 108 | .uHostSelSS resw 1
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| 109 | .HostGdtrRw resb 10
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| 110 | .uHostSelCS resw 1
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| 111 | .abPadding1 resb 4
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| 112 | .HostIdtr resb 10
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| 113 | alignb 8
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| 114 | .uHostFSBase resq 1
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| 115 | .uHostGSBase resq 1
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| 116 | endstruc
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| 117 |
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| 118 | struc HMCPUVMX
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| 119 | .VmcsInfo resb VMXVMCSINFOSHARED_size
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| 120 | .VmcsInfoNstGst resb VMXVMCSINFOSHARED_size
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| 121 | .fSwitchedToNstGstVmcsCopyForRing3 resb 1
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| 122 | .fMergedNstGstCtls resb 1
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| 123 | .fCopiedNstGstToShadowVmcs resb 1
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| 124 | .fSwitchedNstGstFlushTlb resb 1
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| 125 |
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| 126 | alignb 8
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| 127 | .u64GstMsrApicBase resq 1
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| 128 |
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| 129 | .LastError.idCurrentCpu resd 1
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| 130 | .LastError.idEnteredCpu resd 1
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| 131 | .LastError.HCPhysCurrentVmcs resq 1
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| 132 | .LastError.u32VmcsRev resd 1
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| 133 | .LastError.u32InstrError resd 1
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| 134 | .LastError.u32ExitReason resd 1
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| 135 | .LastError.u32GuestIntrState resd 1
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| 136 | endstruc
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| 137 |
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| 138 | struc HMCPUSVM
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| 139 | .fEmulateLongModeSysEnterExit resb 1
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| 140 |
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| 141 | alignb 8
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| 142 | .NstGstVmcbCache resb 40
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| 143 | endstruc
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| 144 |
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| 145 | struc HMCPU
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| 146 | .fCheckedTLBFlush resb 1
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| 147 | .fActive resb 1
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| 148 | .fUseDebugLoop resb 1
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| 149 |
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| 150 | .fGIMTrapXcptUD resb 1
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| 151 | .fTrapXcptGpForLovelyMesaDrv resb 1
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| 152 | .fSingleInstruction resb 1
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| 153 | alignb 8
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| 154 |
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| 155 | .u32HMError resd 1
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| 156 | .rcLastExitToR3 resd 1
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| 157 | alignb 8
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| 158 | .fCtxChanged resq 1
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| 159 |
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| 160 | alignb 8
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| 161 | .vmx resb HMCPUVMX_size
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| 162 | alignb 8
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| 163 | .svm resb HMCPUSVM_size
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| 164 |
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| 165 | .Event.fPending resd 1
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| 166 | .Event.u32ErrCode resd 1
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| 167 | .Event.cbInstr resd 1
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| 168 | alignb 8
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| 169 | .Event.u64IntInfo resq 1
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| 170 | .Event.GCPtrFaultAddress RTGCPTR_RES 1
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| 171 |
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| 172 | .enmShadowMode resd 1
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| 173 | alignb 8
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| 174 | .aPdpes resq 4
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| 175 |
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| 176 | .StatVmxWriteHostRip resq 1
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| 177 | .StatVmxWriteHostRsp resq 1
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| 178 |
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| 179 | ; The remainer is disassembly state and statistics.
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| 180 | endstruc
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| 181 |
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| 182 | struc HMR0CPUVMX
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| 183 | .pfnStartVm RTR0PTR_RES 1
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| 184 | .uTscDeadline resq 1
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| 185 | .uTscDeadlineVersion resq 1
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| 186 |
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| 187 |
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| 188 | .VmcsInfo resb VMXVMCSINFO_size
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| 189 | .VmcsInfoNstGst resb VMXVMCSINFO_size
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| 190 | .fSwitchedToNstGstVmcs resb 1
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| 191 |
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| 192 | alignb 8
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| 193 | .u64HostMsrLStar resq 1
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| 194 | .u64HostMsrStar resq 1
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| 195 | .u64HostMsrSfMask resq 1
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| 196 | .u64HostMsrKernelGsBase resq 1
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| 197 | .fLazyMsrs resd 1
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| 198 | .fUpdatedHostAutoMsrs resb 1
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| 199 | alignb 4
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| 200 | .fRestoreHostFlags resd 1
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| 201 | alignb 8
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| 202 | .RestoreHost resb VMXRESTOREHOST_size
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| 203 | endstruc
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| 204 |
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| 205 | struc HMR0CPUSVM
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| 206 | .pfnVMRun RTR0PTR_RES 1
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| 207 |
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| 208 | alignb 8
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| 209 | .HCPhysVmcbHost RTHCPHYS_RES 1
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| 210 |
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| 211 | alignb 8
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| 212 | .hMemObjVmcbHost RTR0PTR_RES 1
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| 213 |
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| 214 | alignb 8
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| 215 | .HCPhysVmcb RTHCPHYS_RES 1
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| 216 | .hMemObjVmcb RTR0PTR_RES 1
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| 217 | .pVmcb RTR0PTR_RES 1
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| 218 |
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| 219 | alignb 8
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| 220 | .HCPhysMsrBitmap RTHCPHYS_RES 1
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| 221 | .hMemObjMsrBitmap RTR0PTR_RES 1
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| 222 | .pvMsrBitmap RTR0PTR_RES 1
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| 223 |
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| 224 | .fSyncVTpr resb 1
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| 225 |
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| 226 | alignb 8
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| 227 | .u64HostTscAux resq 1
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| 228 |
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| 229 | alignb 8
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| 230 | .DisState resb 0d8h
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| 231 | endstruc
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| 232 |
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| 233 | struc HMR0PERVCPU
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| 234 | .cWorldSwitchExits resd 1
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| 235 | .cTlbFlushes resd 1
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| 236 | .idLastCpu resd 1
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| 237 | .idEnteredCpu resd 1
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| 238 | .uCurrentAsid resd 1
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| 239 |
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| 240 | .fForceTLBFlush resb 1
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| 241 | .fLeaveDone resb 1
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| 242 | .fUsingHyperDR7 resb 1
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| 243 | .fUsingDebugLoop resb 1
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| 244 | .fDebugWantRdTscExit resb 1
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| 245 | .fLoadSaveGuestXcr0 resb 1
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| 246 | .fClearTrapFlag resb 1
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| 247 |
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| 248 | alignb 4
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| 249 | .fWorldSwitcher resd 1
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| 250 | .uTscExit resq 1
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| 251 |
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| 252 | alignb 8
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| 253 | .vmx resb HMR0CPUVMX_size
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| 254 | alignb 8
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| 255 | .svm resb HMR0CPUSVM_size
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| 256 | endstruc
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| 257 |
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| 258 | %define HM_WSF_IBPB_EXIT RT_BIT_32(0)
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| 259 | %define HM_WSF_IBPB_ENTRY RT_BIT_32(1)
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| 260 | %define HM_WSF_L1D_ENTRY RT_BIT_32(2)
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| 261 | %define HM_WSF_MDS_ENTRY RT_BIT_32(3)
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| 262 |
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