VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 77379

Last change on this file since 77379 was 77325, checked in by vboxsync, 6 years ago

VMM/HM: Added V8086 mode checks to HMCanExecuteVmxGuest.
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File size: 47.0 KB
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1/* $Id: HMInternal.h 77325 2019-02-15 07:55:09Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32 && defined(RT_OS_DARWIN)
41# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
42#endif
43
44#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_64_BITS_GUESTS)
45/* Enable 64 bits guest support. */
46# define VBOX_ENABLE_64_BITS_GUESTS
47#endif
48
49#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
50# define VMX_USE_CACHED_VMCS_ACCESSES
51#endif
52
53/** @def HM_PROFILE_EXIT_DISPATCH
54 * Enables profiling of the VM exit handler dispatching. */
55#if 0 || defined(DOXYGEN_RUNNING)
56# define HM_PROFILE_EXIT_DISPATCH
57#endif
58
59RT_C_DECLS_BEGIN
60
61
62/** @defgroup grp_hm_int Internal
63 * @ingroup grp_hm
64 * @internal
65 * @{
66 */
67
68/** @name HM_CHANGED_XXX
69 * HM CPU-context changed flags.
70 *
71 * These flags are used to keep track of which registers and state has been
72 * modified since they were imported back into the guest-CPU context.
73 *
74 * @{
75 */
76#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
77#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
78#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
79
80#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
81#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
82#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
83#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
84#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
85#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
86#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
87#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
88#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
89#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
90
91#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
92#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
93#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
94#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
95#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
96#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
97#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
98
99#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
100#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
101#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
102#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
103#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
104
105#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
106#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
107#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
108#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
109#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
110
111#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
112#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
113
114#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
115#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
116#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
117#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
118
119#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
120#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
121#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
122#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
123
124#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
125#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
126#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
127#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
128#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
129#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
130#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
131#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
132#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
133 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
134 | HM_CHANGED_GUEST_SYSCALL_MSRS \
135 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
136 | HM_CHANGED_GUEST_TSC_AUX \
137 | HM_CHANGED_GUEST_OTHER_MSRS)
138
139#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
140#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
141
142#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
143
144#define HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
145#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
146#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
147#define HM_CHANGED_VMX_ENTRY_CTLS UINT64_C(0x0008000000000000)
148#define HM_CHANGED_VMX_EXIT_CTLS UINT64_C(0x0010000000000000)
149#define HM_CHANGED_VMX_MASK UINT64_C(0x001f000000000000)
150#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
151 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
152
153#define HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
154#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
155#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
156
157#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
158 | HM_CHANGED_KEEPER_STATE_MASK)
159
160/** Mask of what state might have changed when IEM raised an exception.
161 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
162#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
163 | HM_CHANGED_GUEST_RIP \
164 | HM_CHANGED_GUEST_RFLAGS \
165 | HM_CHANGED_GUEST_SS \
166 | HM_CHANGED_GUEST_CS \
167 | HM_CHANGED_GUEST_CR0 \
168 | HM_CHANGED_GUEST_CR3 \
169 | HM_CHANGED_GUEST_CR4 \
170 | HM_CHANGED_GUEST_APIC_TPR \
171 | HM_CHANGED_GUEST_EFER_MSR \
172 | HM_CHANGED_GUEST_DR7 \
173 | HM_CHANGED_GUEST_CR2 \
174 | HM_CHANGED_GUEST_SREG_MASK \
175 | HM_CHANGED_GUEST_TABLE_MASK)
176
177#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
178/** Mask of what state might have changed when \#VMEXIT is emulated. */
179# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
180 | HM_CHANGED_GUEST_RAX \
181 | HM_CHANGED_GUEST_RIP \
182 | HM_CHANGED_GUEST_RFLAGS \
183 | HM_CHANGED_GUEST_CS \
184 | HM_CHANGED_GUEST_SS \
185 | HM_CHANGED_GUEST_DS \
186 | HM_CHANGED_GUEST_ES \
187 | HM_CHANGED_GUEST_GDTR \
188 | HM_CHANGED_GUEST_IDTR \
189 | HM_CHANGED_GUEST_CR_MASK \
190 | HM_CHANGED_GUEST_EFER_MSR \
191 | HM_CHANGED_GUEST_DR6 \
192 | HM_CHANGED_GUEST_DR7 \
193 | HM_CHANGED_GUEST_OTHER_MSRS \
194 | HM_CHANGED_GUEST_HWVIRT \
195 | HM_CHANGED_SVM_MASK \
196 | HM_CHANGED_GUEST_APIC_TPR)
197
198/** Mask of what state might have changed when \#VMEXIT is emulated. */
199# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
200#endif
201/** @} */
202
203/** Maximum number of exit reason statistics counters. */
204#define MAX_EXITREASON_STAT 0x100
205#define MASK_EXITREASON_STAT 0xff
206#define MASK_INJECT_IRQ_STAT 0xff
207
208/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
209#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
210/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
211#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
212/** Total guest mapped memory needed. */
213#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
214
215
216/** @name Macros for enabling and disabling preemption.
217 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
218 * preemption has already been disabled when there is no context hook.
219 * @{ */
220#ifdef VBOX_STRICT
221# define HM_DISABLE_PREEMPT(a_pVCpu) \
222 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
223 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
224 RTThreadPreemptDisable(&PreemptStateInternal)
225#else
226# define HM_DISABLE_PREEMPT(a_pVCpu) \
227 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
228 RTThreadPreemptDisable(&PreemptStateInternal)
229#endif /* VBOX_STRICT */
230#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
231/** @} */
232
233
234/** @name HM saved state versions.
235 * @{
236 */
237#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
238#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
239#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
240#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
241#define HM_SAVED_STATE_VERSION_2_0_X 3
242/** @} */
243
244
245/**
246 * HM physical (host) CPU information.
247 */
248typedef struct HMPHYSCPU
249{
250 /** The CPU ID. */
251 RTCPUID idCpu;
252 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
253 RTR0MEMOBJ hMemObj;
254 /** The physical address of the first page in hMemObj (it's a
255 * physcially contigous allocation if it spans multiple pages). */
256 RTHCPHYS HCPhysMemObj;
257 /** The address of the memory (for pfnEnable). */
258 void *pvMemObj;
259 /** Current ASID (AMD-V) / VPID (Intel). */
260 uint32_t uCurrentAsid;
261 /** TLB flush count. */
262 uint32_t cTlbFlushes;
263 /** Whether to flush each new ASID/VPID before use. */
264 bool fFlushAsidBeforeUse;
265 /** Configured for VT-x or AMD-V. */
266 bool fConfigured;
267 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
268 bool fIgnoreAMDVInUseError;
269 /** In use by our code. (for power suspend) */
270 bool volatile fInUse;
271#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
272 /** Nested-guest union (put data common to SVM/VMX outside the union). */
273 union
274 {
275 /** Nested-guest SVM data. */
276 struct
277 {
278 /** The active nested-guest MSR permission bitmap memory backing. */
279 RTR0MEMOBJ hNstGstMsrpm;
280 /** The physical address of the first page in hNstGstMsrpm (physcially
281 * contiguous allocation). */
282 RTHCPHYS HCPhysNstGstMsrpm;
283 /** The address of the active nested-guest MSRPM. */
284 void *pvNstGstMsrpm;
285 } svm;
286 /** @todo Nested-VMX. */
287 } n;
288#endif
289} HMPHYSCPU;
290/** Pointer to HMPHYSCPU struct. */
291typedef HMPHYSCPU *PHMPHYSCPU;
292/** Pointer to a const HMPHYSCPU struct. */
293typedef const HMPHYSCPU *PCHMPHYSCPU;
294
295/**
296 * TPR-instruction type.
297 */
298typedef enum
299{
300 HMTPRINSTR_INVALID,
301 HMTPRINSTR_READ,
302 HMTPRINSTR_READ_SHR4,
303 HMTPRINSTR_WRITE_REG,
304 HMTPRINSTR_WRITE_IMM,
305 HMTPRINSTR_JUMP_REPLACEMENT,
306 /** The usual 32-bit paranoia. */
307 HMTPRINSTR_32BIT_HACK = 0x7fffffff
308} HMTPRINSTR;
309
310/**
311 * TPR patch information.
312 */
313typedef struct
314{
315 /** The key is the address of patched instruction. (32 bits GC ptr) */
316 AVLOU32NODECORE Core;
317 /** Original opcode. */
318 uint8_t aOpcode[16];
319 /** Instruction size. */
320 uint32_t cbOp;
321 /** Replacement opcode. */
322 uint8_t aNewOpcode[16];
323 /** Replacement instruction size. */
324 uint32_t cbNewOp;
325 /** Instruction type. */
326 HMTPRINSTR enmType;
327 /** Source operand. */
328 uint32_t uSrcOperand;
329 /** Destination operand. */
330 uint32_t uDstOperand;
331 /** Number of times the instruction caused a fault. */
332 uint32_t cFaults;
333 /** Patch address of the jump replacement. */
334 RTGCPTR32 pJumpTarget;
335} HMTPRPATCH;
336/** Pointer to HMTPRPATCH. */
337typedef HMTPRPATCH *PHMTPRPATCH;
338/** Pointer to a const HMTPRPATCH. */
339typedef const HMTPRPATCH *PCHMTPRPATCH;
340
341
342/**
343 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
344 *
345 * @returns 64-bit key
346 * @param a_uPC The RIP + CS.BASE value of the exit.
347 * @param a_uExit The exit code.
348 * @todo Add CPL?
349 */
350#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
351
352typedef struct HMEXITINFO
353{
354 /** See HMEXITSTAT_MAKE_KEY(). */
355 uint64_t uKey;
356 /** Number of recent hits (depreciates with time). */
357 uint32_t volatile cHits;
358 /** The age + lock. */
359 uint16_t volatile uAge;
360 /** Action or action table index. */
361 uint16_t iAction;
362} HMEXITINFO;
363AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
364
365typedef struct HMEXITHISTORY
366{
367 /** The exit timestamp. */
368 uint64_t uTscExit;
369 /** The index of the corresponding HMEXITINFO entry.
370 * UINT32_MAX if none (too many collisions, race, whatever). */
371 uint32_t iExitInfo;
372 /** Figure out later, needed for padding now. */
373 uint32_t uSomeClueOrSomething;
374} HMEXITHISTORY;
375
376/**
377 * Switcher function, HC to the special 64-bit RC.
378 *
379 * @param pVM The cross context VM structure.
380 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
381 * @returns Return code indicating the action to take.
382 */
383typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
384/** Pointer to switcher function. */
385typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
386
387/** @def HM_UNION_NM
388 * For compilers (like DTrace) that does not grok nameless unions, we have a
389 * little hack to make them palatable.
390 */
391/** @def HM_STRUCT_NM
392 * For compilers (like DTrace) that does not grok nameless structs (it is
393 * non-standard C++), we have a little hack to make them palatable.
394 */
395#ifdef VBOX_FOR_DTRACE_LIB
396# define HM_UNION_NM(a_Nm) a_Nm
397# define HM_STRUCT_NM(a_Nm) a_Nm
398#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
399# define HM_UNION_NM(a_Nm) a_Nm
400# define HM_STRUCT_NM(a_Nm) a_Nm
401#else
402# define HM_UNION_NM(a_Nm)
403# define HM_STRUCT_NM(a_Nm)
404#endif
405
406/**
407 * HM VM Instance data.
408 * Changes to this must checked against the padding of the hm union in VM!
409 */
410typedef struct HM
411{
412 /** Set when we've initialized VMX or SVM. */
413 bool fInitialized;
414 /** Set if nested paging is enabled. */
415 bool fNestedPaging;
416 /** Set if nested paging is allowed. */
417 bool fAllowNestedPaging;
418 /** Set if large pages are enabled (requires nested paging). */
419 bool fLargePages;
420 /** Set if we can support 64-bit guests or not. */
421 bool fAllow64BitGuests;
422 /** Set when TPR patching is allowed. */
423 bool fTprPatchingAllowed;
424 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
425 bool fGlobalInit;
426 /** Set when TPR patching is active. */
427 bool fTPRPatchingActive;
428 /** Set when the debug facility has breakpoints/events enabled that requires
429 * us to use the debug execution loop in ring-0. */
430 bool fUseDebugLoop;
431 /** Set if hardware APIC virtualization is enabled. */
432 bool fVirtApicRegs;
433 /** Set if posted interrupt processing is enabled. */
434 bool fPostedIntrs;
435 /** Set if indirect branch prediction barrier on VM exit. */
436 bool fIbpbOnVmExit;
437 /** Set if indirect branch prediction barrier on VM entry. */
438 bool fIbpbOnVmEntry;
439 /** Set if level 1 data cache should be flushed on VM entry. */
440 bool fL1dFlushOnVmEntry;
441 /** Set if level 1 data cache should be flushed on EMT scheduling. */
442 bool fL1dFlushOnSched;
443 /** Set if host manages speculation control settings. */
444 bool fSpecCtrlByHost;
445
446 /** Maximum ASID allowed. */
447 uint32_t uMaxAsid;
448 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
449 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
450 uint32_t cMaxResumeLoops;
451
452 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
453 uint32_t fHostKernelFeatures;
454
455 /** Size of the guest patch memory block. */
456 uint32_t cbGuestPatchMem;
457 /** Guest allocated memory for patching purposes. */
458 RTGCPTR pGuestPatchMem;
459 /** Current free pointer inside the patch block. */
460 RTGCPTR pFreeGuestPatchMem;
461
462#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
463 /** 32 to 64 bits switcher entrypoint. */
464 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
465 RTR0PTR pvR0Alignment0;
466#endif
467
468 struct
469 {
470 /** Set by the ring-0 side of HM to indicate VMX is supported by the
471 * CPU. */
472 bool fSupported;
473 /** Set when we've enabled VMX. */
474 bool fEnabled;
475 /** Set if VPID is supported. */
476 bool fVpid;
477 /** Set if VT-x VPID is allowed. */
478 bool fAllowVpid;
479 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
480 bool fUnrestrictedGuest;
481 /** Set if unrestricted guest execution is allowed to be used. */
482 bool fAllowUnrestricted;
483 /** Set if the preemption timer is in use or not. */
484 bool fUsePreemptTimer;
485 /** The shift mask employed by the VMX-Preemption timer. */
486 uint8_t cPreemptTimerShift;
487
488 /** Virtual address of the TSS page used for real mode emulation. */
489 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
490 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
491 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
492
493 /** Physical address of the APIC-access page. */
494 RTHCPHYS HCPhysApicAccess;
495 /** R0 memory object for the APIC-access page. */
496 RTR0MEMOBJ hMemObjApicAccess;
497 /** Virtual address of the APIC-access page. */
498 R0PTRTYPE(uint8_t *) pbApicAccess;
499
500#ifdef VBOX_WITH_CRASHDUMP_MAGIC
501 RTHCPHYS HCPhysScratch;
502 RTR0MEMOBJ hMemObjScratch;
503 R0PTRTYPE(uint8_t *) pbScratch;
504#endif
505
506 /** Tagged-TLB flush type. */
507 VMXTLBFLUSHTYPE enmTlbFlushType;
508 /** Flush type to use for INVEPT. */
509 VMXTLBFLUSHEPT enmTlbFlushEpt;
510 /** Flush type to use for INVVPID. */
511 VMXTLBFLUSHVPID enmTlbFlushVpid;
512
513 /** Pause-loop exiting (PLE) gap in ticks. */
514 uint32_t cPleGapTicks;
515 /** Pause-loop exiting (PLE) window in ticks. */
516 uint32_t cPleWindowTicks;
517 uint32_t u32Alignment0;
518
519 /** Host CR4 value (set by ring-0 VMX init) */
520 uint64_t u64HostCr4;
521 /** Host SMM monitor control (set by ring-0 VMX init) */
522 uint64_t u64HostSmmMonitorCtl;
523 /** Host EFER value (set by ring-0 VMX init) */
524 uint64_t u64HostEfer;
525 /** Whether the CPU supports VMCS fields for swapping EFER. */
526 bool fSupportsVmcsEfer;
527 uint8_t u8Alignment2[7];
528
529 /** VMX MSR values. */
530 VMXMSRS Msrs;
531
532 /** Host-physical address for a failing VMXON instruction. */
533 RTHCPHYS HCPhysVmxEnableError;
534 } vmx;
535
536 struct
537 {
538 /** Set by the ring-0 side of HM to indicate SVM is supported by the
539 * CPU. */
540 bool fSupported;
541 /** Set when we've enabled SVM. */
542 bool fEnabled;
543 /** Set if erratum 170 affects the AMD cpu. */
544 bool fAlwaysFlushTLB;
545 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
546 bool fIgnoreInUseError;
547 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
548 bool fVirtVmsaveVmload;
549 /** Whether to use virtual GIF feature. */
550 bool fVGif;
551 uint8_t u8Alignment0[2];
552
553 /** Physical address of the IO bitmap (12kb). */
554 RTHCPHYS HCPhysIOBitmap;
555 /** R0 memory object for the IO bitmap (12kb). */
556 RTR0MEMOBJ hMemObjIOBitmap;
557 /** Virtual address of the IO bitmap. */
558 R0PTRTYPE(void *) pvIOBitmap;
559
560 /* HWCR MSR (for diagnostics) */
561 uint64_t u64MsrHwcr;
562
563 /** SVM revision. */
564 uint32_t u32Rev;
565 /** SVM feature bits from cpuid 0x8000000a */
566 uint32_t u32Features;
567
568 /** Pause filter counter. */
569 uint16_t cPauseFilter;
570 /** Pause filter treshold in ticks. */
571 uint16_t cPauseFilterThresholdTicks;
572 uint32_t u32Alignment0;
573 } svm;
574
575 /**
576 * AVL tree with all patches (active or disabled) sorted by guest instruction
577 * address.
578 */
579 AVLOU32TREE PatchTree;
580 uint32_t cPatches;
581 HMTPRPATCH aPatches[64];
582
583 /** Last recorded error code during HM ring-0 init. */
584 int32_t rcInit;
585
586 /** HMR0Init was run */
587 bool fHMR0Init;
588 bool u8Alignment1[3];
589
590 STAMCOUNTER StatTprPatchSuccess;
591 STAMCOUNTER StatTprPatchFailure;
592 STAMCOUNTER StatTprReplaceSuccessCr8;
593 STAMCOUNTER StatTprReplaceSuccessVmc;
594 STAMCOUNTER StatTprReplaceFailure;
595} HM;
596/** Pointer to HM VM instance data. */
597typedef HM *PHM;
598
599AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
600
601/* Maximum number of cached entries. */
602#define VMCSCACHE_MAX_ENTRY 128
603
604/**
605 * Structure for storing read and write VMCS actions.
606 */
607typedef struct VMCSCACHE
608{
609#ifdef VBOX_WITH_CRASHDUMP_MAGIC
610 /* Magic marker for searching in crash dumps. */
611 uint8_t aMagic[16];
612 uint64_t uMagic;
613 uint64_t u64TimeEntry;
614 uint64_t u64TimeSwitch;
615 uint64_t cResume;
616 uint64_t interPD;
617 uint64_t pSwitcher;
618 uint32_t uPos;
619 uint32_t idCpu;
620#endif
621 /* CR2 is saved here for EPT syncing. */
622 uint64_t cr2;
623 struct
624 {
625 uint32_t cValidEntries;
626 uint32_t uAlignment;
627 uint32_t aField[VMCSCACHE_MAX_ENTRY];
628 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
629 } Write;
630 struct
631 {
632 uint32_t cValidEntries;
633 uint32_t uAlignment;
634 uint32_t aField[VMCSCACHE_MAX_ENTRY];
635 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
636 } Read;
637#ifdef VBOX_STRICT
638 struct
639 {
640 RTHCPHYS HCPhysCpuPage;
641 RTHCPHYS HCPhysVmcs;
642 RTGCPTR pCache;
643 RTGCPTR pCtx;
644 } TestIn;
645 struct
646 {
647 RTHCPHYS HCPhysVmcs;
648 RTGCPTR pCache;
649 RTGCPTR pCtx;
650 uint64_t eflags;
651 uint64_t cr8;
652 } TestOut;
653 struct
654 {
655 uint64_t param1;
656 uint64_t param2;
657 uint64_t param3;
658 uint64_t param4;
659 } ScratchPad;
660#endif
661} VMCSCACHE;
662/** Pointer to VMCSCACHE. */
663typedef VMCSCACHE *PVMCSCACHE;
664AssertCompileSizeAlignment(VMCSCACHE, 8);
665
666/**
667 * VMX StartVM function.
668 *
669 * @returns VBox status code (no informational stuff).
670 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
671 * @param pCtx The CPU register context.
672 * @param pCache The VMCS cache.
673 * @param pVM Pointer to the cross context VM structure.
674 * @param pVCpu Pointer to the cross context per-CPU structure.
675 */
676typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
677/** Pointer to a VMX StartVM function. */
678typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
679
680/** SVM VMRun function. */
681typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
682/** Pointer to a SVM VMRun function. */
683typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
684
685/**
686 * HM VMCPU Instance data.
687 *
688 * Note! If you change members of this struct, make sure to check if the
689 * assembly counterpart in HMInternal.mac needs to be updated as well.
690 */
691typedef struct HMCPU
692{
693 /** Set when the TLB has been checked until we return from the world switch. */
694 bool volatile fCheckedTLBFlush;
695 /** Set if we need to flush the TLB during the world switch. */
696 bool fForceTLBFlush;
697 /** Set when we're using VT-x or AMD-V at that moment. */
698 bool fActive;
699 /** Whether we've completed the inner HM leave function. */
700 bool fLeaveDone;
701 /** Whether we're using the hyper DR7 or guest DR7. */
702 bool fUsingHyperDR7;
703 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
704 * execution. */
705 bool fLoadSaveGuestXcr0;
706
707 /** Whether we should use the debug loop because of single stepping or special
708 * debug breakpoints / events are armed. */
709 bool fUseDebugLoop;
710 /** Whether we are currently executing in the debug loop.
711 * Mainly for assertions. */
712 bool fUsingDebugLoop;
713 /** Set if we using the debug loop and wish to intercept RDTSC. */
714 bool fDebugWantRdTscExit;
715 /** Whether we're executing a single instruction. */
716 bool fSingleInstruction;
717 /** Set if we need to clear the trap flag because of single stepping. */
718 bool fClearTrapFlag;
719
720 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
721 bool fGIMTrapXcptUD;
722 /** Whether \#GP needs to be intercept for mesa driver workaround. */
723 bool fTrapXcptGpForLovelyMesaDrv;
724 uint8_t u8Alignment0[3];
725
726 /** World switch exit counter. */
727 uint32_t volatile cWorldSwitchExits;
728 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
729 RTCPUID idLastCpu;
730 /** TLB flush count. */
731 uint32_t cTlbFlushes;
732 /** Current ASID in use by the VM. */
733 uint32_t uCurrentAsid;
734 /** An additional error code used for some gurus. */
735 uint32_t u32HMError;
736 /** The last exit-to-ring-3 reason. */
737 int32_t rcLastExitToR3;
738 /** CPU-context changed flags (see HM_CHANGED_xxx). */
739 uint64_t fCtxChanged;
740 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
741 uint64_t u64HostTscAux;
742
743 union /* no tag! */
744 {
745 /** VT-x data. */
746 struct
747 {
748 /** Ring 0 handlers for VT-x. */
749 PFNHMVMXSTARTVM pfnStartVM;
750#if HC_ARCH_BITS == 32
751 uint32_t u32Alignment0;
752#endif
753
754 /** Current pin-based VM-execution controls. */
755 uint32_t u32PinCtls;
756 /** Current processor-based VM-execution controls. */
757 uint32_t u32ProcCtls;
758 /** Current secondary processor-based VM-execution controls. */
759 uint32_t u32ProcCtls2;
760 /** Current VM-entry controls. */
761 uint32_t u32EntryCtls;
762 /** Current VM-exit controls. */
763 uint32_t u32ExitCtls;
764 /** Current CR0 mask. */
765 uint32_t u32Cr0Mask;
766 /** Current CR4 mask. */
767 uint32_t u32Cr4Mask;
768 /** Current exception bitmap. */
769 uint32_t u32XcptBitmap;
770 /** Padding. */
771 uint32_t au32Alignment0[2];
772
773 /** Physical address of the VM control structure (VMCS). */
774 RTHCPHYS HCPhysVmcs;
775 /** R0 memory object for the VM control structure (VMCS). */
776 RTR0MEMOBJ hMemObjVmcs;
777 /** Virtual address of the VM control structure (VMCS). */
778 R0PTRTYPE(void *) pvVmcs;
779
780 /** Physical address of the virtual APIC page for TPR caching. */
781 RTHCPHYS HCPhysVirtApic;
782 /** Padding. */
783 R0PTRTYPE(void *) pvAlignment0;
784 /** Virtual address of the virtual APIC page for TPR caching. */
785 R0PTRTYPE(uint8_t *) pbVirtApic;
786
787 /** Physical address of the MSR bitmap. */
788 RTHCPHYS HCPhysMsrBitmap;
789 /** R0 memory object for the MSR bitmap. */
790 RTR0MEMOBJ hMemObjMsrBitmap;
791 /** Virtual address of the MSR bitmap. */
792 R0PTRTYPE(void *) pvMsrBitmap;
793
794 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
795 * for guest MSRs). */
796 RTHCPHYS HCPhysGuestMsr;
797 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
798 * (used for guest MSRs). */
799 RTR0MEMOBJ hMemObjGuestMsr;
800 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
801 * for guest MSRs). */
802 R0PTRTYPE(void *) pvGuestMsr;
803
804 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
805 RTHCPHYS HCPhysHostMsr;
806 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
807 RTR0MEMOBJ hMemObjHostMsr;
808 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
809 R0PTRTYPE(void *) pvHostMsr;
810
811 /** Physical address of the current EPTP. */
812 RTHCPHYS HCPhysEPTP;
813
814 /** Number of guest/host MSR pairs in the auto-load/store area. */
815 uint32_t cMsrs;
816 /** Whether the host MSR values are up-to-date in the auto-load/store area. */
817 bool fUpdatedHostMsrs;
818 uint8_t au8Alignment0[3];
819
820 /** Host LSTAR MSR value to restore lazily while leaving VT-x. */
821 uint64_t u64HostLStarMsr;
822 /** Host STAR MSR value to restore lazily while leaving VT-x. */
823 uint64_t u64HostStarMsr;
824 /** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
825 uint64_t u64HostSFMaskMsr;
826 /** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
827 uint64_t u64HostKernelGSBaseMsr;
828 /** A mask of which MSRs have been swapped and need restoration. */
829 uint32_t fLazyMsrs;
830 uint32_t u32Alignment1;
831
832 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
833 uint64_t u64MsrApicBase;
834 /** Last use TSC offset value. (cached) */
835 uint64_t u64TscOffset;
836
837 /** VMCS cache. */
838 VMCSCACHE VMCSCache;
839
840 /** Real-mode emulation state. */
841 struct
842 {
843 X86DESCATTR AttrCS;
844 X86DESCATTR AttrDS;
845 X86DESCATTR AttrES;
846 X86DESCATTR AttrFS;
847 X86DESCATTR AttrGS;
848 X86DESCATTR AttrSS;
849 X86EFLAGS Eflags;
850 bool fRealOnV86Active;
851 } RealMode;
852
853 /** VT-x error-reporting (mainly for ring-3 propagation). */
854 struct
855 {
856 uint64_t u64VmcsPhys;
857 uint32_t u32VmcsRev;
858 uint32_t u32InstrError;
859 uint32_t u32ExitReason;
860 uint32_t u32Alignment0;
861 RTCPUID idEnteredCpu;
862 RTCPUID idCurrentCpu;
863 } LastError;
864
865 /** Current state of the VMCS. */
866 uint32_t fVmcsState;
867 /** Which host-state bits to restore before being preempted. */
868 uint32_t fRestoreHostFlags;
869 /** The host-state restoration structure. */
870 VMXRESTOREHOST RestoreHost;
871
872 /** Set if guest was executing in real mode (extra checks). */
873 bool fWasInRealMode;
874 /** Set if guest switched to 64-bit mode on a 32-bit host. */
875 bool fSwitchedTo64on32;
876 /** Padding. */
877 uint8_t au8Alignment1[6];
878 } vmx;
879
880 /** SVM data. */
881 struct
882 {
883 /** Ring 0 handlers for VT-x. */
884 PFNHMSVMVMRUN pfnVMRun;
885#if HC_ARCH_BITS == 32
886 uint32_t u32Alignment0;
887#endif
888
889 /** Physical address of the host VMCB which holds additional host-state. */
890 RTHCPHYS HCPhysVmcbHost;
891 /** R0 memory object for the host VMCB which holds additional host-state. */
892 RTR0MEMOBJ hMemObjVmcbHost;
893 /** Padding. */
894 R0PTRTYPE(void *) pvPadding;
895
896 /** Physical address of the guest VMCB. */
897 RTHCPHYS HCPhysVmcb;
898 /** R0 memory object for the guest VMCB. */
899 RTR0MEMOBJ hMemObjVmcb;
900 /** Pointer to the guest VMCB. */
901 R0PTRTYPE(PSVMVMCB) pVmcb;
902
903 /** Physical address of the MSR bitmap (8 KB). */
904 RTHCPHYS HCPhysMsrBitmap;
905 /** R0 memory object for the MSR bitmap (8 KB). */
906 RTR0MEMOBJ hMemObjMsrBitmap;
907 /** Pointer to the MSR bitmap. */
908 R0PTRTYPE(void *) pvMsrBitmap;
909
910 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
911 * we should check if the VTPR changed on every VM-exit. */
912 bool fSyncVTpr;
913 uint8_t au8Alignment0[7];
914
915 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
916 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
917 SVMNESTEDVMCBCACHE NstGstVmcbCache;
918 } svm;
919 } HM_UNION_NM(u);
920
921 /** Event injection state. */
922 struct
923 {
924 uint32_t fPending;
925 uint32_t u32ErrCode;
926 uint32_t cbInstr;
927 uint32_t u32Padding; /**< Explicit alignment padding. */
928 uint64_t u64IntInfo;
929 RTGCUINTPTR GCPtrFaultAddress;
930 } Event;
931
932 /** The PAE PDPEs used with Nested Paging (only valid when
933 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
934 X86PDPE aPdpes[4];
935
936 /** Current shadow paging mode for updating CR4. */
937 PGMMODE enmShadowMode;
938
939 /** The CPU ID of the CPU currently owning the VMCS. Set in
940 * HMR0Enter and cleared in HMR0Leave. */
941 RTCPUID idEnteredCpu;
942
943 /** For saving stack space, the disassembler state is allocated here instead of
944 * on the stack. */
945 DISCPUSTATE DisState;
946
947 STAMPROFILEADV StatEntry;
948 STAMPROFILEADV StatPreExit;
949 STAMPROFILEADV StatExitHandling;
950 STAMPROFILEADV StatExitIO;
951 STAMPROFILEADV StatExitMovCRx;
952 STAMPROFILEADV StatExitXcptNmi;
953 STAMPROFILEADV StatImportGuestState;
954 STAMPROFILEADV StatExportGuestState;
955 STAMPROFILEADV StatLoadGuestFpuState;
956 STAMPROFILEADV StatInGC;
957#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
958 STAMPROFILEADV StatWorldSwitch3264;
959#endif
960 STAMPROFILEADV StatPoke;
961 STAMPROFILEADV StatSpinPoke;
962 STAMPROFILEADV StatSpinPokeFailed;
963
964 STAMCOUNTER StatInjectInterrupt;
965 STAMCOUNTER StatInjectXcpt;
966 STAMCOUNTER StatInjectPendingReflect;
967 STAMCOUNTER StatInjectPendingInterpret;
968
969 STAMCOUNTER StatExitAll;
970 STAMCOUNTER StatExitShadowNM;
971 STAMCOUNTER StatExitGuestNM;
972 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
973 STAMCOUNTER StatExitShadowPFEM;
974 STAMCOUNTER StatExitGuestPF;
975 STAMCOUNTER StatExitGuestUD;
976 STAMCOUNTER StatExitGuestSS;
977 STAMCOUNTER StatExitGuestNP;
978 STAMCOUNTER StatExitGuestTS;
979 STAMCOUNTER StatExitGuestGP;
980 STAMCOUNTER StatExitGuestDE;
981 STAMCOUNTER StatExitGuestDB;
982 STAMCOUNTER StatExitGuestMF;
983 STAMCOUNTER StatExitGuestBP;
984 STAMCOUNTER StatExitGuestXF;
985 STAMCOUNTER StatExitGuestXcpUnk;
986 STAMCOUNTER StatExitCli;
987 STAMCOUNTER StatExitSti;
988 STAMCOUNTER StatExitPushf;
989 STAMCOUNTER StatExitPopf;
990 STAMCOUNTER StatExitIret;
991 STAMCOUNTER StatExitInt;
992 STAMCOUNTER StatExitHlt;
993 STAMCOUNTER StatExitDRxWrite;
994 STAMCOUNTER StatExitDRxRead;
995 STAMCOUNTER StatExitCR0Read;
996 STAMCOUNTER StatExitCR2Read;
997 STAMCOUNTER StatExitCR3Read;
998 STAMCOUNTER StatExitCR4Read;
999 STAMCOUNTER StatExitCR8Read;
1000 STAMCOUNTER StatExitCR0Write;
1001 STAMCOUNTER StatExitCR2Write;
1002 STAMCOUNTER StatExitCR3Write;
1003 STAMCOUNTER StatExitCR4Write;
1004 STAMCOUNTER StatExitCR8Write;
1005 STAMCOUNTER StatExitRdmsr;
1006 STAMCOUNTER StatExitWrmsr;
1007 STAMCOUNTER StatExitClts;
1008 STAMCOUNTER StatExitXdtrAccess;
1009 STAMCOUNTER StatExitMwait;
1010 STAMCOUNTER StatExitMonitor;
1011 STAMCOUNTER StatExitLmsw;
1012 STAMCOUNTER StatExitIOWrite;
1013 STAMCOUNTER StatExitIORead;
1014 STAMCOUNTER StatExitIOStringWrite;
1015 STAMCOUNTER StatExitIOStringRead;
1016 STAMCOUNTER StatExitIntWindow;
1017 STAMCOUNTER StatExitExtInt;
1018 STAMCOUNTER StatExitHostNmiInGC;
1019 STAMCOUNTER StatExitPreemptTimer;
1020 STAMCOUNTER StatExitTprBelowThreshold;
1021 STAMCOUNTER StatExitTaskSwitch;
1022 STAMCOUNTER StatExitMtf;
1023 STAMCOUNTER StatExitApicAccess;
1024 STAMCOUNTER StatExitReasonNpf;
1025
1026 STAMCOUNTER StatNestedExitReasonNpf;
1027
1028 STAMCOUNTER StatFlushPage;
1029 STAMCOUNTER StatFlushPageManual;
1030 STAMCOUNTER StatFlushPhysPageManual;
1031 STAMCOUNTER StatFlushTlb;
1032 STAMCOUNTER StatFlushTlbManual;
1033 STAMCOUNTER StatFlushTlbWorldSwitch;
1034 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1035 STAMCOUNTER StatFlushEntire;
1036 STAMCOUNTER StatFlushAsid;
1037 STAMCOUNTER StatFlushNestedPaging;
1038 STAMCOUNTER StatFlushTlbInvlpgVirt;
1039 STAMCOUNTER StatFlushTlbInvlpgPhys;
1040 STAMCOUNTER StatTlbShootdown;
1041 STAMCOUNTER StatTlbShootdownFlush;
1042
1043 STAMCOUNTER StatSwitchPendingHostIrq;
1044 STAMCOUNTER StatSwitchTprMaskedIrq;
1045 STAMCOUNTER StatSwitchGuestIrq;
1046 STAMCOUNTER StatSwitchHmToR3FF;
1047 STAMCOUNTER StatSwitchExitToR3;
1048 STAMCOUNTER StatSwitchLongJmpToR3;
1049 STAMCOUNTER StatSwitchMaxResumeLoops;
1050 STAMCOUNTER StatSwitchHltToR3;
1051 STAMCOUNTER StatSwitchApicAccessToR3;
1052 STAMCOUNTER StatSwitchPreempt;
1053 STAMCOUNTER StatSwitchPreemptExportHostState;
1054
1055 STAMCOUNTER StatTscParavirt;
1056 STAMCOUNTER StatTscOffset;
1057 STAMCOUNTER StatTscIntercept;
1058
1059 STAMCOUNTER StatDRxArmed;
1060 STAMCOUNTER StatDRxContextSwitch;
1061 STAMCOUNTER StatDRxIoCheck;
1062
1063 STAMCOUNTER StatExportMinimal;
1064 STAMCOUNTER StatExportFull;
1065 STAMCOUNTER StatLoadGuestFpu;
1066
1067 STAMCOUNTER StatVmxCheckBadRmSelBase;
1068 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1069 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1070 STAMCOUNTER StatVmxCheckBadV86SelBase;
1071 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1072 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1073 STAMCOUNTER StatVmxCheckRmOk;
1074 STAMCOUNTER StatVmxCheckBadSel;
1075 STAMCOUNTER StatVmxCheckBadRpl;
1076 STAMCOUNTER StatVmxCheckPmOk;
1077
1078#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1079 STAMCOUNTER StatFpu64SwitchBack;
1080 STAMCOUNTER StatDebug64SwitchBack;
1081#endif
1082#ifdef VBOX_WITH_STATISTICS
1083 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1084 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1085 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1086 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1087 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1088 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1089#endif
1090#ifdef HM_PROFILE_EXIT_DISPATCH
1091 STAMPROFILEADV StatExitDispatch;
1092#endif
1093} HMCPU;
1094/** Pointer to HM VMCPU instance data. */
1095typedef HMCPU *PHMCPU;
1096AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1097AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1098AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx, 8);
1099AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) svm, 8);
1100AssertCompileMemberAlignment(HMCPU, Event, 8);
1101
1102#ifdef IN_RING0
1103VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1104VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu);
1105
1106# ifdef VBOX_STRICT
1107VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu);
1108VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1109# endif
1110
1111# ifdef VBOX_WITH_KERNEL_USING_XMM
1112DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu,
1113 PFNHMVMXSTARTVM pfnStartVM);
1114DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu,
1115 PFNHMSVMVMRUN pfnVMRun);
1116# endif
1117#endif /* IN_RING0 */
1118
1119int hmEmulateSvmMovTpr(PVMCPU pVCpu);
1120
1121/** @} */
1122
1123RT_C_DECLS_END
1124
1125#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1126
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