VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 76550

Last change on this file since 76550 was 76543, checked in by vboxsync, 6 years ago

VMM: scm --fix-header-guards. bugref:9344
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1/* $Id: HMInternal.h 76543 2018-12-30 06:38:55Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32 && defined(RT_OS_DARWIN)
41# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
42#endif
43
44#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_64_BITS_GUESTS)
45/* Enable 64 bits guest support. */
46# define VBOX_ENABLE_64_BITS_GUESTS
47#endif
48
49#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
50# define VMX_USE_CACHED_VMCS_ACCESSES
51#endif
52
53/** @def HM_PROFILE_EXIT_DISPATCH
54 * Enables profiling of the VM exit handler dispatching. */
55#if 0 || defined(DOXYGEN_RUNNING)
56# define HM_PROFILE_EXIT_DISPATCH
57#endif
58
59RT_C_DECLS_BEGIN
60
61
62/** @defgroup grp_hm_int Internal
63 * @ingroup grp_hm
64 * @internal
65 * @{
66 */
67
68/** @name HM_CHANGED_XXX
69 * HM CPU-context changed flags.
70 *
71 * These flags are used to keep track of which registers and state has been
72 * modified since they were imported back into the guest-CPU context.
73 *
74 * @{
75 */
76#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
77#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
78#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
79
80#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
81#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
82#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
83#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
84#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
85#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
86#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
87#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
88#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
89#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
90
91#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
92#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
93#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
94#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
95#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
96#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
97#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
98
99#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
100#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
101#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
102#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
103#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
104
105#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
106#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
107#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
108#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
109#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
110
111#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
112#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
113
114#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
115#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
116#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
117#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
118
119#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
120#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
121#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
122#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
123
124#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
125#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
126#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
127#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
128#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
129#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
130#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
131#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
132#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
133 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
134 | HM_CHANGED_GUEST_SYSCALL_MSRS \
135 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
136 | HM_CHANGED_GUEST_TSC_AUX \
137 | HM_CHANGED_GUEST_OTHER_MSRS)
138
139#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
140#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
141
142#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
143
144#define HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
145#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
146#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
147#define HM_CHANGED_VMX_ENTRY_CTLS UINT64_C(0x0008000000000000)
148#define HM_CHANGED_VMX_EXIT_CTLS UINT64_C(0x0010000000000000)
149#define HM_CHANGED_VMX_MASK UINT64_C(0x001f000000000000)
150#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
151 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
152
153#define HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
154#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
155#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
156
157#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
158 | HM_CHANGED_KEEPER_STATE_MASK)
159
160/** Mask of what state might have changed when IEM raised an exception.
161 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
162#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
163 | HM_CHANGED_GUEST_RIP \
164 | HM_CHANGED_GUEST_RFLAGS \
165 | HM_CHANGED_GUEST_SS \
166 | HM_CHANGED_GUEST_CS \
167 | HM_CHANGED_GUEST_CR0 \
168 | HM_CHANGED_GUEST_CR3 \
169 | HM_CHANGED_GUEST_CR4 \
170 | HM_CHANGED_GUEST_APIC_TPR \
171 | HM_CHANGED_GUEST_EFER_MSR \
172 | HM_CHANGED_GUEST_DR7 \
173 | HM_CHANGED_GUEST_CR2 \
174 | HM_CHANGED_GUEST_SREG_MASK \
175 | HM_CHANGED_GUEST_TABLE_MASK)
176
177#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
178/** Mask of what state might have changed when \#VMEXIT is emulated. */
179# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
180 | HM_CHANGED_GUEST_RAX \
181 | HM_CHANGED_GUEST_RIP \
182 | HM_CHANGED_GUEST_RFLAGS \
183 | HM_CHANGED_GUEST_CS \
184 | HM_CHANGED_GUEST_SS \
185 | HM_CHANGED_GUEST_DS \
186 | HM_CHANGED_GUEST_ES \
187 | HM_CHANGED_GUEST_GDTR \
188 | HM_CHANGED_GUEST_IDTR \
189 | HM_CHANGED_GUEST_CR_MASK \
190 | HM_CHANGED_GUEST_EFER_MSR \
191 | HM_CHANGED_GUEST_DR6 \
192 | HM_CHANGED_GUEST_DR7 \
193 | HM_CHANGED_GUEST_OTHER_MSRS \
194 | HM_CHANGED_GUEST_HWVIRT \
195 | HM_CHANGED_SVM_MASK \
196 | HM_CHANGED_GUEST_APIC_TPR)
197
198/** Mask of what state might have changed when \#VMEXIT is emulated. */
199# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
200#endif
201/** @} */
202
203/** Maximum number of exit reason statistics counters. */
204#define MAX_EXITREASON_STAT 0x100
205#define MASK_EXITREASON_STAT 0xff
206#define MASK_INJECT_IRQ_STAT 0xff
207
208/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
209#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
210/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
211#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
212/** Total guest mapped memory needed. */
213#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
214
215
216/** @name Macros for enabling and disabling preemption.
217 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
218 * preemption has already been disabled when there is no context hook.
219 * @{ */
220#ifdef VBOX_STRICT
221# define HM_DISABLE_PREEMPT(a_pVCpu) \
222 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
223 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
224 RTThreadPreemptDisable(&PreemptStateInternal)
225#else
226# define HM_DISABLE_PREEMPT(a_pVCpu) \
227 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
228 RTThreadPreemptDisable(&PreemptStateInternal)
229#endif /* VBOX_STRICT */
230#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
231/** @} */
232
233
234/** @name HM saved state versions.
235 * @{
236 */
237#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
238#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
239#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
240#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
241#define HM_SAVED_STATE_VERSION_2_0_X 3
242/** @} */
243
244
245/**
246 * HM physical (host) CPU information.
247 */
248typedef struct HMPHYSCPU
249{
250 /** The CPU ID. */
251 RTCPUID idCpu;
252 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
253 RTR0MEMOBJ hMemObj;
254 /** The physical address of the first page in hMemObj (it's a
255 * physcially contigous allocation if it spans multiple pages). */
256 RTHCPHYS HCPhysMemObj;
257 /** The address of the memory (for pfnEnable). */
258 void *pvMemObj;
259 /** Current ASID (AMD-V) / VPID (Intel). */
260 uint32_t uCurrentAsid;
261 /** TLB flush count. */
262 uint32_t cTlbFlushes;
263 /** Whether to flush each new ASID/VPID before use. */
264 bool fFlushAsidBeforeUse;
265 /** Configured for VT-x or AMD-V. */
266 bool fConfigured;
267 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
268 bool fIgnoreAMDVInUseError;
269 /** In use by our code. (for power suspend) */
270 bool volatile fInUse;
271#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
272 /** Nested-guest union (put data common to SVM/VMX outside the union). */
273 union
274 {
275 /** Nested-guest SVM data. */
276 struct
277 {
278 /** The active nested-guest MSR permission bitmap memory backing. */
279 RTR0MEMOBJ hNstGstMsrpm;
280 /** The physical address of the first page in hNstGstMsrpm (physcially
281 * contiguous allocation). */
282 RTHCPHYS HCPhysNstGstMsrpm;
283 /** The address of the active nested-guest MSRPM. */
284 void *pvNstGstMsrpm;
285 } svm;
286 /** @todo Nested-VMX. */
287 } n;
288#endif
289} HMPHYSCPU;
290/** Pointer to HMPHYSCPU struct. */
291typedef HMPHYSCPU *PHMPHYSCPU;
292/** Pointer to a const HMPHYSCPU struct. */
293typedef const HMPHYSCPU *PCHMPHYSCPU;
294
295/**
296 * TPR-instruction type.
297 */
298typedef enum
299{
300 HMTPRINSTR_INVALID,
301 HMTPRINSTR_READ,
302 HMTPRINSTR_READ_SHR4,
303 HMTPRINSTR_WRITE_REG,
304 HMTPRINSTR_WRITE_IMM,
305 HMTPRINSTR_JUMP_REPLACEMENT,
306 /** The usual 32-bit paranoia. */
307 HMTPRINSTR_32BIT_HACK = 0x7fffffff
308} HMTPRINSTR;
309
310/**
311 * TPR patch information.
312 */
313typedef struct
314{
315 /** The key is the address of patched instruction. (32 bits GC ptr) */
316 AVLOU32NODECORE Core;
317 /** Original opcode. */
318 uint8_t aOpcode[16];
319 /** Instruction size. */
320 uint32_t cbOp;
321 /** Replacement opcode. */
322 uint8_t aNewOpcode[16];
323 /** Replacement instruction size. */
324 uint32_t cbNewOp;
325 /** Instruction type. */
326 HMTPRINSTR enmType;
327 /** Source operand. */
328 uint32_t uSrcOperand;
329 /** Destination operand. */
330 uint32_t uDstOperand;
331 /** Number of times the instruction caused a fault. */
332 uint32_t cFaults;
333 /** Patch address of the jump replacement. */
334 RTGCPTR32 pJumpTarget;
335} HMTPRPATCH;
336/** Pointer to HMTPRPATCH. */
337typedef HMTPRPATCH *PHMTPRPATCH;
338/** Pointer to a const HMTPRPATCH. */
339typedef const HMTPRPATCH *PCHMTPRPATCH;
340
341
342/**
343 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
344 *
345 * @returns 64-bit key
346 * @param a_uPC The RIP + CS.BASE value of the exit.
347 * @param a_uExit The exit code.
348 * @todo Add CPL?
349 */
350#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
351
352typedef struct HMEXITINFO
353{
354 /** See HMEXITSTAT_MAKE_KEY(). */
355 uint64_t uKey;
356 /** Number of recent hits (depreciates with time). */
357 uint32_t volatile cHits;
358 /** The age + lock. */
359 uint16_t volatile uAge;
360 /** Action or action table index. */
361 uint16_t iAction;
362} HMEXITINFO;
363AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
364
365typedef struct HMEXITHISTORY
366{
367 /** The exit timestamp. */
368 uint64_t uTscExit;
369 /** The index of the corresponding HMEXITINFO entry.
370 * UINT32_MAX if none (too many collisions, race, whatever). */
371 uint32_t iExitInfo;
372 /** Figure out later, needed for padding now. */
373 uint32_t uSomeClueOrSomething;
374} HMEXITHISTORY;
375
376/**
377 * Switcher function, HC to the special 64-bit RC.
378 *
379 * @param pVM The cross context VM structure.
380 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
381 * @returns Return code indicating the action to take.
382 */
383typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
384/** Pointer to switcher function. */
385typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
386
387/** @def HM_UNION_NM
388 * For compilers (like DTrace) that does not grok nameless unions, we have a
389 * little hack to make them palatable.
390 */
391/** @def HM_STRUCT_NM
392 * For compilers (like DTrace) that does not grok nameless structs (it is
393 * non-standard C++), we have a little hack to make them palatable.
394 */
395#ifdef VBOX_FOR_DTRACE_LIB
396# define HM_UNION_NM(a_Nm) a_Nm
397# define HM_STRUCT_NM(a_Nm) a_Nm
398#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
399# define HM_UNION_NM(a_Nm) a_Nm
400# define HM_STRUCT_NM(a_Nm) a_Nm
401#else
402# define HM_UNION_NM(a_Nm)
403# define HM_STRUCT_NM(a_Nm)
404#endif
405
406/**
407 * HM VM Instance data.
408 * Changes to this must checked against the padding of the hm union in VM!
409 */
410typedef struct HM
411{
412 /** Set when we've initialized VMX or SVM. */
413 bool fInitialized;
414 /** Set if nested paging is enabled. */
415 bool fNestedPaging;
416 /** Set if nested paging is allowed. */
417 bool fAllowNestedPaging;
418 /** Set if large pages are enabled (requires nested paging). */
419 bool fLargePages;
420 /** Set if we can support 64-bit guests or not. */
421 bool fAllow64BitGuests;
422 /** Set when TPR patching is allowed. */
423 bool fTprPatchingAllowed;
424 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
425 bool fGlobalInit;
426 /** Set when TPR patching is active. */
427 bool fTPRPatchingActive;
428 /** Set when the debug facility has breakpoints/events enabled that requires
429 * us to use the debug execution loop in ring-0. */
430 bool fUseDebugLoop;
431 /** Set if hardware APIC virtualization is enabled. */
432 bool fVirtApicRegs;
433 /** Set if posted interrupt processing is enabled. */
434 bool fPostedIntrs;
435 /** Set if indirect branch prediction barrier on VM exit. */
436 bool fIbpbOnVmExit;
437 /** Set if indirect branch prediction barrier on VM entry. */
438 bool fIbpbOnVmEntry;
439 /** Set if host manages speculation control settings. */
440 bool fSpecCtrlByHost;
441 /** Explicit padding. */
442 bool afPadding[2];
443
444 /** Maximum ASID allowed. */
445 uint32_t uMaxAsid;
446 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
447 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
448 uint32_t cMaxResumeLoops;
449
450 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
451 uint32_t fHostKernelFeatures;
452
453 /** Size of the guest patch memory block. */
454 uint32_t cbGuestPatchMem;
455 /** Guest allocated memory for patching purposes. */
456 RTGCPTR pGuestPatchMem;
457 /** Current free pointer inside the patch block. */
458 RTGCPTR pFreeGuestPatchMem;
459
460#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
461 /** 32 to 64 bits switcher entrypoint. */
462 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
463 RTR0PTR pvR0Alignment0;
464#endif
465
466 struct
467 {
468 /** Set by the ring-0 side of HM to indicate VMX is supported by the
469 * CPU. */
470 bool fSupported;
471 /** Set when we've enabled VMX. */
472 bool fEnabled;
473 /** Set if VPID is supported. */
474 bool fVpid;
475 /** Set if VT-x VPID is allowed. */
476 bool fAllowVpid;
477 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
478 bool fUnrestrictedGuest;
479 /** Set if unrestricted guest execution is allowed to be used. */
480 bool fAllowUnrestricted;
481 /** Set if the preemption timer is in use or not. */
482 bool fUsePreemptTimer;
483 /** The shift mask employed by the VMX-Preemption timer. */
484 uint8_t cPreemptTimerShift;
485
486 /** Virtual address of the TSS page used for real mode emulation. */
487 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
488 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
489 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
490
491 /** Physical address of the APIC-access page. */
492 RTHCPHYS HCPhysApicAccess;
493 /** R0 memory object for the APIC-access page. */
494 RTR0MEMOBJ hMemObjApicAccess;
495 /** Virtual address of the APIC-access page. */
496 R0PTRTYPE(uint8_t *) pbApicAccess;
497
498#ifdef VBOX_WITH_CRASHDUMP_MAGIC
499 RTHCPHYS HCPhysScratch;
500 RTR0MEMOBJ hMemObjScratch;
501 R0PTRTYPE(uint8_t *) pbScratch;
502#endif
503
504 /** Tagged-TLB flush type. */
505 VMXTLBFLUSHTYPE enmTlbFlushType;
506 /** Flush type to use for INVEPT. */
507 VMXTLBFLUSHEPT enmTlbFlushEpt;
508 /** Flush type to use for INVVPID. */
509 VMXTLBFLUSHVPID enmTlbFlushVpid;
510
511 /** Pause-loop exiting (PLE) gap in ticks. */
512 uint32_t cPleGapTicks;
513 /** Pause-loop exiting (PLE) window in ticks. */
514 uint32_t cPleWindowTicks;
515 uint32_t u32Alignment0;
516
517 /** Host CR4 value (set by ring-0 VMX init) */
518 uint64_t u64HostCr4;
519 /** Host SMM monitor control (set by ring-0 VMX init) */
520 uint64_t u64HostSmmMonitorCtl;
521 /** Host EFER value (set by ring-0 VMX init) */
522 uint64_t u64HostEfer;
523 /** Whether the CPU supports VMCS fields for swapping EFER. */
524 bool fSupportsVmcsEfer;
525 uint8_t u8Alignment2[7];
526
527 /** VMX MSR values. */
528 VMXMSRS Msrs;
529
530 /** Host-physical address for a failing VMXON instruction. */
531 RTHCPHYS HCPhysVmxEnableError;
532 } vmx;
533
534 struct
535 {
536 /** Set by the ring-0 side of HM to indicate SVM is supported by the
537 * CPU. */
538 bool fSupported;
539 /** Set when we've enabled SVM. */
540 bool fEnabled;
541 /** Set if erratum 170 affects the AMD cpu. */
542 bool fAlwaysFlushTLB;
543 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
544 bool fIgnoreInUseError;
545 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
546 bool fVirtVmsaveVmload;
547 /** Whether to use virtual GIF feature. */
548 bool fVGif;
549 uint8_t u8Alignment0[2];
550
551 /** Physical address of the IO bitmap (12kb). */
552 RTHCPHYS HCPhysIOBitmap;
553 /** R0 memory object for the IO bitmap (12kb). */
554 RTR0MEMOBJ hMemObjIOBitmap;
555 /** Virtual address of the IO bitmap. */
556 R0PTRTYPE(void *) pvIOBitmap;
557
558 /* HWCR MSR (for diagnostics) */
559 uint64_t u64MsrHwcr;
560
561 /** SVM revision. */
562 uint32_t u32Rev;
563 /** SVM feature bits from cpuid 0x8000000a */
564 uint32_t u32Features;
565
566 /** Pause filter counter. */
567 uint16_t cPauseFilter;
568 /** Pause filter treshold in ticks. */
569 uint16_t cPauseFilterThresholdTicks;
570 uint32_t u32Alignment0;
571 } svm;
572
573 /**
574 * AVL tree with all patches (active or disabled) sorted by guest instruction
575 * address.
576 */
577 AVLOU32TREE PatchTree;
578 uint32_t cPatches;
579 HMTPRPATCH aPatches[64];
580
581 /** Last recorded error code during HM ring-0 init. */
582 int32_t rcInit;
583
584 /** HMR0Init was run */
585 bool fHMR0Init;
586 bool u8Alignment1[3];
587
588 STAMCOUNTER StatTprPatchSuccess;
589 STAMCOUNTER StatTprPatchFailure;
590 STAMCOUNTER StatTprReplaceSuccessCr8;
591 STAMCOUNTER StatTprReplaceSuccessVmc;
592 STAMCOUNTER StatTprReplaceFailure;
593} HM;
594/** Pointer to HM VM instance data. */
595typedef HM *PHM;
596
597AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
598
599/* Maximum number of cached entries. */
600#define VMCSCACHE_MAX_ENTRY 128
601
602/**
603 * Structure for storing read and write VMCS actions.
604 */
605typedef struct VMCSCACHE
606{
607#ifdef VBOX_WITH_CRASHDUMP_MAGIC
608 /* Magic marker for searching in crash dumps. */
609 uint8_t aMagic[16];
610 uint64_t uMagic;
611 uint64_t u64TimeEntry;
612 uint64_t u64TimeSwitch;
613 uint64_t cResume;
614 uint64_t interPD;
615 uint64_t pSwitcher;
616 uint32_t uPos;
617 uint32_t idCpu;
618#endif
619 /* CR2 is saved here for EPT syncing. */
620 uint64_t cr2;
621 struct
622 {
623 uint32_t cValidEntries;
624 uint32_t uAlignment;
625 uint32_t aField[VMCSCACHE_MAX_ENTRY];
626 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
627 } Write;
628 struct
629 {
630 uint32_t cValidEntries;
631 uint32_t uAlignment;
632 uint32_t aField[VMCSCACHE_MAX_ENTRY];
633 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
634 } Read;
635#ifdef VBOX_STRICT
636 struct
637 {
638 RTHCPHYS HCPhysCpuPage;
639 RTHCPHYS HCPhysVmcs;
640 RTGCPTR pCache;
641 RTGCPTR pCtx;
642 } TestIn;
643 struct
644 {
645 RTHCPHYS HCPhysVmcs;
646 RTGCPTR pCache;
647 RTGCPTR pCtx;
648 uint64_t eflags;
649 uint64_t cr8;
650 } TestOut;
651 struct
652 {
653 uint64_t param1;
654 uint64_t param2;
655 uint64_t param3;
656 uint64_t param4;
657 } ScratchPad;
658#endif
659} VMCSCACHE;
660/** Pointer to VMCSCACHE. */
661typedef VMCSCACHE *PVMCSCACHE;
662AssertCompileSizeAlignment(VMCSCACHE, 8);
663
664/**
665 * VMX StartVM function.
666 *
667 * @returns VBox status code (no informational stuff).
668 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
669 * @param pCtx The CPU register context.
670 * @param pCache The VMCS cache.
671 * @param pVM Pointer to the cross context VM structure.
672 * @param pVCpu Pointer to the cross context per-CPU structure.
673 */
674typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
675/** Pointer to a VMX StartVM function. */
676typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
677
678/** SVM VMRun function. */
679typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
680/** Pointer to a SVM VMRun function. */
681typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
682
683/**
684 * HM VMCPU Instance data.
685 *
686 * Note! If you change members of this struct, make sure to check if the
687 * assembly counterpart in HMInternal.mac needs to be updated as well.
688 */
689typedef struct HMCPU
690{
691 /** Set when the TLB has been checked until we return from the world switch. */
692 bool volatile fCheckedTLBFlush;
693 /** Set if we need to flush the TLB during the world switch. */
694 bool fForceTLBFlush;
695 /** Set when we're using VT-x or AMD-V at that moment. */
696 bool fActive;
697 /** Whether we've completed the inner HM leave function. */
698 bool fLeaveDone;
699 /** Whether we're using the hyper DR7 or guest DR7. */
700 bool fUsingHyperDR7;
701 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
702 * execution. */
703 bool fLoadSaveGuestXcr0;
704
705 /** Whether we should use the debug loop because of single stepping or special
706 * debug breakpoints / events are armed. */
707 bool fUseDebugLoop;
708 /** Whether we are currently executing in the debug loop.
709 * Mainly for assertions. */
710 bool fUsingDebugLoop;
711 /** Set if we using the debug loop and wish to intercept RDTSC. */
712 bool fDebugWantRdTscExit;
713 /** Whether we're executing a single instruction. */
714 bool fSingleInstruction;
715 /** Set if we need to clear the trap flag because of single stepping. */
716 bool fClearTrapFlag;
717
718 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
719 bool fGIMTrapXcptUD;
720 /** Whether \#GP needs to be intercept for mesa driver workaround. */
721 bool fTrapXcptGpForLovelyMesaDrv;
722 uint8_t u8Alignment0[3];
723
724 /** World switch exit counter. */
725 uint32_t volatile cWorldSwitchExits;
726 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
727 RTCPUID idLastCpu;
728 /** TLB flush count. */
729 uint32_t cTlbFlushes;
730 /** Current ASID in use by the VM. */
731 uint32_t uCurrentAsid;
732 /** An additional error code used for some gurus. */
733 uint32_t u32HMError;
734 /** The last exit-to-ring-3 reason. */
735 int32_t rcLastExitToR3;
736 /** CPU-context changed flags (see HM_CHANGED_xxx). */
737 uint64_t fCtxChanged;
738 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
739 uint64_t u64HostTscAux;
740
741 union /* no tag! */
742 {
743 /** VT-x data. */
744 struct
745 {
746 /** Ring 0 handlers for VT-x. */
747 PFNHMVMXSTARTVM pfnStartVM;
748#if HC_ARCH_BITS == 32
749 uint32_t u32Alignment0;
750#endif
751
752 /** Current pin-based VM-execution controls. */
753 uint32_t u32PinCtls;
754 /** Current processor-based VM-execution controls. */
755 uint32_t u32ProcCtls;
756 /** Current secondary processor-based VM-execution controls. */
757 uint32_t u32ProcCtls2;
758 /** Current VM-entry controls. */
759 uint32_t u32EntryCtls;
760 /** Current VM-exit controls. */
761 uint32_t u32ExitCtls;
762 /** Current CR0 mask. */
763 uint32_t u32Cr0Mask;
764 /** Current CR4 mask. */
765 uint32_t u32Cr4Mask;
766 /** Current exception bitmap. */
767 uint32_t u32XcptBitmap;
768 /** Padding. */
769 uint32_t au32Alignment0[2];
770
771 /** Physical address of the VM control structure (VMCS). */
772 RTHCPHYS HCPhysVmcs;
773 /** R0 memory object for the VM control structure (VMCS). */
774 RTR0MEMOBJ hMemObjVmcs;
775 /** Virtual address of the VM control structure (VMCS). */
776 R0PTRTYPE(void *) pvVmcs;
777
778 /** Physical address of the virtual APIC page for TPR caching. */
779 RTHCPHYS HCPhysVirtApic;
780 /** Padding. */
781 R0PTRTYPE(void *) pvAlignment0;
782 /** Virtual address of the virtual APIC page for TPR caching. */
783 R0PTRTYPE(uint8_t *) pbVirtApic;
784
785 /** Physical address of the MSR bitmap. */
786 RTHCPHYS HCPhysMsrBitmap;
787 /** R0 memory object for the MSR bitmap. */
788 RTR0MEMOBJ hMemObjMsrBitmap;
789 /** Virtual address of the MSR bitmap. */
790 R0PTRTYPE(void *) pvMsrBitmap;
791
792 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
793 * for guest MSRs). */
794 RTHCPHYS HCPhysGuestMsr;
795 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
796 * (used for guest MSRs). */
797 RTR0MEMOBJ hMemObjGuestMsr;
798 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
799 * for guest MSRs). */
800 R0PTRTYPE(void *) pvGuestMsr;
801
802 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
803 RTHCPHYS HCPhysHostMsr;
804 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
805 RTR0MEMOBJ hMemObjHostMsr;
806 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
807 R0PTRTYPE(void *) pvHostMsr;
808
809 /** Physical address of the current EPTP. */
810 RTHCPHYS HCPhysEPTP;
811
812 /** Number of guest/host MSR pairs in the auto-load/store area. */
813 uint32_t cMsrs;
814 /** Whether the host MSR values are up-to-date in the auto-load/store area. */
815 bool fUpdatedHostMsrs;
816 uint8_t au8Alignment0[3];
817
818 /** Host LSTAR MSR value to restore lazily while leaving VT-x. */
819 uint64_t u64HostLStarMsr;
820 /** Host STAR MSR value to restore lazily while leaving VT-x. */
821 uint64_t u64HostStarMsr;
822 /** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
823 uint64_t u64HostSFMaskMsr;
824 /** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
825 uint64_t u64HostKernelGSBaseMsr;
826 /** A mask of which MSRs have been swapped and need restoration. */
827 uint32_t fLazyMsrs;
828 uint32_t u32Alignment1;
829
830 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
831 uint64_t u64MsrApicBase;
832 /** Last use TSC offset value. (cached) */
833 uint64_t u64TscOffset;
834
835 /** VMCS cache. */
836 VMCSCACHE VMCSCache;
837
838 /** Real-mode emulation state. */
839 struct
840 {
841 X86DESCATTR AttrCS;
842 X86DESCATTR AttrDS;
843 X86DESCATTR AttrES;
844 X86DESCATTR AttrFS;
845 X86DESCATTR AttrGS;
846 X86DESCATTR AttrSS;
847 X86EFLAGS Eflags;
848 bool fRealOnV86Active;
849 } RealMode;
850
851 /** VT-x error-reporting (mainly for ring-3 propagation). */
852 struct
853 {
854 uint64_t u64VmcsPhys;
855 uint32_t u32VmcsRev;
856 uint32_t u32InstrError;
857 uint32_t u32ExitReason;
858 uint32_t u32Alignment0;
859 RTCPUID idEnteredCpu;
860 RTCPUID idCurrentCpu;
861 } LastError;
862
863 /** Current state of the VMCS. */
864 uint32_t fVmcsState;
865 /** Which host-state bits to restore before being preempted. */
866 uint32_t fRestoreHostFlags;
867 /** The host-state restoration structure. */
868 VMXRESTOREHOST RestoreHost;
869
870 /** Set if guest was executing in real mode (extra checks). */
871 bool fWasInRealMode;
872 /** Set if guest switched to 64-bit mode on a 32-bit host. */
873 bool fSwitchedTo64on32;
874 /** Padding. */
875 uint8_t au8Alignment1[6];
876 } vmx;
877
878 /** SVM data. */
879 struct
880 {
881 /** Ring 0 handlers for VT-x. */
882 PFNHMSVMVMRUN pfnVMRun;
883#if HC_ARCH_BITS == 32
884 uint32_t u32Alignment0;
885#endif
886
887 /** Physical address of the host VMCB which holds additional host-state. */
888 RTHCPHYS HCPhysVmcbHost;
889 /** R0 memory object for the host VMCB which holds additional host-state. */
890 RTR0MEMOBJ hMemObjVmcbHost;
891 /** Padding. */
892 R0PTRTYPE(void *) pvPadding;
893
894 /** Physical address of the guest VMCB. */
895 RTHCPHYS HCPhysVmcb;
896 /** R0 memory object for the guest VMCB. */
897 RTR0MEMOBJ hMemObjVmcb;
898 /** Pointer to the guest VMCB. */
899 R0PTRTYPE(PSVMVMCB) pVmcb;
900
901 /** Physical address of the MSR bitmap (8 KB). */
902 RTHCPHYS HCPhysMsrBitmap;
903 /** R0 memory object for the MSR bitmap (8 KB). */
904 RTR0MEMOBJ hMemObjMsrBitmap;
905 /** Pointer to the MSR bitmap. */
906 R0PTRTYPE(void *) pvMsrBitmap;
907
908 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
909 * we should check if the VTPR changed on every VM-exit. */
910 bool fSyncVTpr;
911 uint8_t au8Alignment0[7];
912
913 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
914 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
915 SVMNESTEDVMCBCACHE NstGstVmcbCache;
916 } svm;
917 } HM_UNION_NM(u);
918
919 /** Event injection state. */
920 struct
921 {
922 uint32_t fPending;
923 uint32_t u32ErrCode;
924 uint32_t cbInstr;
925 uint32_t u32Padding; /**< Explicit alignment padding. */
926 uint64_t u64IntInfo;
927 RTGCUINTPTR GCPtrFaultAddress;
928 } Event;
929
930 /** The PAE PDPEs used with Nested Paging (only valid when
931 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
932 X86PDPE aPdpes[4];
933
934 /** Current shadow paging mode for updating CR4. */
935 PGMMODE enmShadowMode;
936
937 /** The CPU ID of the CPU currently owning the VMCS. Set in
938 * HMR0Enter and cleared in HMR0Leave. */
939 RTCPUID idEnteredCpu;
940
941 /** For saving stack space, the disassembler state is allocated here instead of
942 * on the stack. */
943 DISCPUSTATE DisState;
944
945 STAMPROFILEADV StatEntry;
946 STAMPROFILEADV StatPreExit;
947 STAMPROFILEADV StatExitHandling;
948 STAMPROFILEADV StatExitIO;
949 STAMPROFILEADV StatExitMovCRx;
950 STAMPROFILEADV StatExitXcptNmi;
951 STAMPROFILEADV StatImportGuestState;
952 STAMPROFILEADV StatExportGuestState;
953 STAMPROFILEADV StatLoadGuestFpuState;
954 STAMPROFILEADV StatInGC;
955#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
956 STAMPROFILEADV StatWorldSwitch3264;
957#endif
958 STAMPROFILEADV StatPoke;
959 STAMPROFILEADV StatSpinPoke;
960 STAMPROFILEADV StatSpinPokeFailed;
961
962 STAMCOUNTER StatInjectInterrupt;
963 STAMCOUNTER StatInjectXcpt;
964 STAMCOUNTER StatInjectPendingReflect;
965 STAMCOUNTER StatInjectPendingInterpret;
966
967 STAMCOUNTER StatExitAll;
968 STAMCOUNTER StatExitShadowNM;
969 STAMCOUNTER StatExitGuestNM;
970 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
971 STAMCOUNTER StatExitShadowPFEM;
972 STAMCOUNTER StatExitGuestPF;
973 STAMCOUNTER StatExitGuestUD;
974 STAMCOUNTER StatExitGuestSS;
975 STAMCOUNTER StatExitGuestNP;
976 STAMCOUNTER StatExitGuestTS;
977 STAMCOUNTER StatExitGuestGP;
978 STAMCOUNTER StatExitGuestDE;
979 STAMCOUNTER StatExitGuestDB;
980 STAMCOUNTER StatExitGuestMF;
981 STAMCOUNTER StatExitGuestBP;
982 STAMCOUNTER StatExitGuestXF;
983 STAMCOUNTER StatExitGuestXcpUnk;
984 STAMCOUNTER StatExitCli;
985 STAMCOUNTER StatExitSti;
986 STAMCOUNTER StatExitPushf;
987 STAMCOUNTER StatExitPopf;
988 STAMCOUNTER StatExitIret;
989 STAMCOUNTER StatExitInt;
990 STAMCOUNTER StatExitHlt;
991 STAMCOUNTER StatExitDRxWrite;
992 STAMCOUNTER StatExitDRxRead;
993 STAMCOUNTER StatExitCR0Read;
994 STAMCOUNTER StatExitCR2Read;
995 STAMCOUNTER StatExitCR3Read;
996 STAMCOUNTER StatExitCR4Read;
997 STAMCOUNTER StatExitCR8Read;
998 STAMCOUNTER StatExitCR0Write;
999 STAMCOUNTER StatExitCR2Write;
1000 STAMCOUNTER StatExitCR3Write;
1001 STAMCOUNTER StatExitCR4Write;
1002 STAMCOUNTER StatExitCR8Write;
1003 STAMCOUNTER StatExitRdmsr;
1004 STAMCOUNTER StatExitWrmsr;
1005 STAMCOUNTER StatExitClts;
1006 STAMCOUNTER StatExitXdtrAccess;
1007 STAMCOUNTER StatExitMwait;
1008 STAMCOUNTER StatExitMonitor;
1009 STAMCOUNTER StatExitLmsw;
1010 STAMCOUNTER StatExitIOWrite;
1011 STAMCOUNTER StatExitIORead;
1012 STAMCOUNTER StatExitIOStringWrite;
1013 STAMCOUNTER StatExitIOStringRead;
1014 STAMCOUNTER StatExitIntWindow;
1015 STAMCOUNTER StatExitExtInt;
1016 STAMCOUNTER StatExitHostNmiInGC;
1017 STAMCOUNTER StatExitPreemptTimer;
1018 STAMCOUNTER StatExitTprBelowThreshold;
1019 STAMCOUNTER StatExitTaskSwitch;
1020 STAMCOUNTER StatExitMtf;
1021 STAMCOUNTER StatExitApicAccess;
1022 STAMCOUNTER StatExitReasonNpf;
1023
1024 STAMCOUNTER StatNestedExitReasonNpf;
1025
1026 STAMCOUNTER StatFlushPage;
1027 STAMCOUNTER StatFlushPageManual;
1028 STAMCOUNTER StatFlushPhysPageManual;
1029 STAMCOUNTER StatFlushTlb;
1030 STAMCOUNTER StatFlushTlbManual;
1031 STAMCOUNTER StatFlushTlbWorldSwitch;
1032 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1033 STAMCOUNTER StatFlushEntire;
1034 STAMCOUNTER StatFlushAsid;
1035 STAMCOUNTER StatFlushNestedPaging;
1036 STAMCOUNTER StatFlushTlbInvlpgVirt;
1037 STAMCOUNTER StatFlushTlbInvlpgPhys;
1038 STAMCOUNTER StatTlbShootdown;
1039 STAMCOUNTER StatTlbShootdownFlush;
1040
1041 STAMCOUNTER StatSwitchPendingHostIrq;
1042 STAMCOUNTER StatSwitchTprMaskedIrq;
1043 STAMCOUNTER StatSwitchGuestIrq;
1044 STAMCOUNTER StatSwitchHmToR3FF;
1045 STAMCOUNTER StatSwitchExitToR3;
1046 STAMCOUNTER StatSwitchLongJmpToR3;
1047 STAMCOUNTER StatSwitchMaxResumeLoops;
1048 STAMCOUNTER StatSwitchHltToR3;
1049 STAMCOUNTER StatSwitchApicAccessToR3;
1050 STAMCOUNTER StatSwitchPreempt;
1051 STAMCOUNTER StatSwitchPreemptExportHostState;
1052
1053 STAMCOUNTER StatTscParavirt;
1054 STAMCOUNTER StatTscOffset;
1055 STAMCOUNTER StatTscIntercept;
1056
1057 STAMCOUNTER StatDRxArmed;
1058 STAMCOUNTER StatDRxContextSwitch;
1059 STAMCOUNTER StatDRxIoCheck;
1060
1061 STAMCOUNTER StatExportMinimal;
1062 STAMCOUNTER StatExportFull;
1063 STAMCOUNTER StatLoadGuestFpu;
1064
1065 STAMCOUNTER StatVmxCheckBadRmSelBase;
1066 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1067 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1068 STAMCOUNTER StatVmxCheckRmOk;
1069 STAMCOUNTER StatVmxCheckBadSel;
1070 STAMCOUNTER StatVmxCheckBadRpl;
1071 STAMCOUNTER StatVmxCheckPmOk;
1072
1073#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1074 STAMCOUNTER StatFpu64SwitchBack;
1075 STAMCOUNTER StatDebug64SwitchBack;
1076#endif
1077#ifdef VBOX_WITH_STATISTICS
1078 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1079 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1080 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1081 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1082 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1083 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1084#endif
1085#ifdef HM_PROFILE_EXIT_DISPATCH
1086 STAMPROFILEADV StatExitDispatch;
1087#endif
1088} HMCPU;
1089/** Pointer to HM VMCPU instance data. */
1090typedef HMCPU *PHMCPU;
1091AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1092AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1093AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx, 8);
1094AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) svm, 8);
1095AssertCompileMemberAlignment(HMCPU, Event, 8);
1096
1097#ifdef IN_RING0
1098VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1099VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu);
1100
1101# ifdef VBOX_STRICT
1102VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu);
1103VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1104# endif
1105
1106# ifdef VBOX_WITH_KERNEL_USING_XMM
1107DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu,
1108 PFNHMVMXSTARTVM pfnStartVM);
1109DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu,
1110 PFNHMSVMVMRUN pfnVMRun);
1111# endif
1112#endif /* IN_RING0 */
1113
1114int hmSvmEmulateMovTpr(PVMCPU pVCpu);
1115
1116/** @} */
1117
1118RT_C_DECLS_END
1119
1120#endif
1121
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