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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 76489

Last change on this file since 76489 was 76489, checked in by vboxsync, 6 years ago

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1/* $Id: HMInternal.h 76489 2018-12-27 05:12:31Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/dis.h>
25#include <VBox/vmm/hm.h>
26#include <VBox/vmm/hm_vmx.h>
27#include <VBox/vmm/hm_svm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <VBox/vmm/trpm.h>
31#include <iprt/memobj.h>
32#include <iprt/cpuset.h>
33#include <iprt/mp.h>
34#include <iprt/avl.h>
35#include <iprt/string.h>
36
37#if HC_ARCH_BITS == 32 && defined(RT_OS_DARWIN)
38# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
39#endif
40
41#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_64_BITS_GUESTS)
42/* Enable 64 bits guest support. */
43# define VBOX_ENABLE_64_BITS_GUESTS
44#endif
45
46#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
47# define VMX_USE_CACHED_VMCS_ACCESSES
48#endif
49
50/** @def HM_PROFILE_EXIT_DISPATCH
51 * Enables profiling of the VM exit handler dispatching. */
52#if 0 || defined(DOXYGEN_RUNNING)
53# define HM_PROFILE_EXIT_DISPATCH
54#endif
55
56RT_C_DECLS_BEGIN
57
58
59/** @defgroup grp_hm_int Internal
60 * @ingroup grp_hm
61 * @internal
62 * @{
63 */
64
65/** @name HM_CHANGED_XXX
66 * HM CPU-context changed flags.
67 *
68 * These flags are used to keep track of which registers and state has been
69 * modified since they were imported back into the guest-CPU context.
70 *
71 * @{
72 */
73#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
74#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
75#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
76
77#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
78#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
79#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
80#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
81#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
82#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
83#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
84#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
85#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
86#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
87
88#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
89#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
90#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
91#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
92#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
93#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
94#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
95
96#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
97#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
98#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
99#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
100#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
101
102#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
103#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
104#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
105#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
106#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
107
108#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
109#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
110
111#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
112#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
113#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
114#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
115
116#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
117#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
118#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
119#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
120
121#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
122#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
123#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
124#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
125#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
126#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
127#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
128#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
129#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
130 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
131 | HM_CHANGED_GUEST_SYSCALL_MSRS \
132 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
133 | HM_CHANGED_GUEST_TSC_AUX \
134 | HM_CHANGED_GUEST_OTHER_MSRS)
135
136#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
137#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
138
139#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
140
141#define HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
142#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
143#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
144#define HM_CHANGED_VMX_ENTRY_CTLS UINT64_C(0x0008000000000000)
145#define HM_CHANGED_VMX_EXIT_CTLS UINT64_C(0x0010000000000000)
146#define HM_CHANGED_VMX_MASK UINT64_C(0x001f000000000000)
147#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
148 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
149
150#define HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
151#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
152#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
153
154#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
155 | HM_CHANGED_KEEPER_STATE_MASK)
156
157/** Mask of what state might have changed when IEM raised an exception.
158 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
159#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
160 | HM_CHANGED_GUEST_RIP \
161 | HM_CHANGED_GUEST_RFLAGS \
162 | HM_CHANGED_GUEST_SS \
163 | HM_CHANGED_GUEST_CS \
164 | HM_CHANGED_GUEST_CR0 \
165 | HM_CHANGED_GUEST_CR3 \
166 | HM_CHANGED_GUEST_CR4 \
167 | HM_CHANGED_GUEST_APIC_TPR \
168 | HM_CHANGED_GUEST_EFER_MSR \
169 | HM_CHANGED_GUEST_DR7 \
170 | HM_CHANGED_GUEST_CR2 \
171 | HM_CHANGED_GUEST_SREG_MASK \
172 | HM_CHANGED_GUEST_TABLE_MASK)
173
174#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
175/** Mask of what state might have changed when \#VMEXIT is emulated. */
176# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
177 | HM_CHANGED_GUEST_RAX \
178 | HM_CHANGED_GUEST_RIP \
179 | HM_CHANGED_GUEST_RFLAGS \
180 | HM_CHANGED_GUEST_CS \
181 | HM_CHANGED_GUEST_SS \
182 | HM_CHANGED_GUEST_DS \
183 | HM_CHANGED_GUEST_ES \
184 | HM_CHANGED_GUEST_GDTR \
185 | HM_CHANGED_GUEST_IDTR \
186 | HM_CHANGED_GUEST_CR_MASK \
187 | HM_CHANGED_GUEST_EFER_MSR \
188 | HM_CHANGED_GUEST_DR6 \
189 | HM_CHANGED_GUEST_DR7 \
190 | HM_CHANGED_GUEST_OTHER_MSRS \
191 | HM_CHANGED_GUEST_HWVIRT \
192 | HM_CHANGED_SVM_MASK \
193 | HM_CHANGED_GUEST_APIC_TPR)
194
195/** Mask of what state might have changed when \#VMEXIT is emulated. */
196# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
197#endif
198/** @} */
199
200/** Maximum number of exit reason statistics counters. */
201#define MAX_EXITREASON_STAT 0x100
202#define MASK_EXITREASON_STAT 0xff
203#define MASK_INJECT_IRQ_STAT 0xff
204
205/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
206#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
207/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
208#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
209/** Total guest mapped memory needed. */
210#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
211
212
213/** @name Macros for enabling and disabling preemption.
214 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
215 * preemption has already been disabled when there is no context hook.
216 * @{ */
217#ifdef VBOX_STRICT
218# define HM_DISABLE_PREEMPT(a_pVCpu) \
219 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
220 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
221 RTThreadPreemptDisable(&PreemptStateInternal)
222#else
223# define HM_DISABLE_PREEMPT(a_pVCpu) \
224 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
225 RTThreadPreemptDisable(&PreemptStateInternal)
226#endif /* VBOX_STRICT */
227#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
228/** @} */
229
230
231/** @name HM saved state versions.
232 * @{
233 */
234#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
235#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
236#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
237#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
238#define HM_SAVED_STATE_VERSION_2_0_X 3
239/** @} */
240
241
242/**
243 * HM physical (host) CPU information.
244 */
245typedef struct HMPHYSCPU
246{
247 /** The CPU ID. */
248 RTCPUID idCpu;
249 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
250 RTR0MEMOBJ hMemObj;
251 /** The physical address of the first page in hMemObj (it's a
252 * physcially contigous allocation if it spans multiple pages). */
253 RTHCPHYS HCPhysMemObj;
254 /** The address of the memory (for pfnEnable). */
255 void *pvMemObj;
256 /** Current ASID (AMD-V) / VPID (Intel). */
257 uint32_t uCurrentAsid;
258 /** TLB flush count. */
259 uint32_t cTlbFlushes;
260 /** Whether to flush each new ASID/VPID before use. */
261 bool fFlushAsidBeforeUse;
262 /** Configured for VT-x or AMD-V. */
263 bool fConfigured;
264 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
265 bool fIgnoreAMDVInUseError;
266 /** In use by our code. (for power suspend) */
267 bool volatile fInUse;
268#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
269 /** Nested-guest union (put data common to SVM/VMX outside the union). */
270 union
271 {
272 /** Nested-guest SVM data. */
273 struct
274 {
275 /** The active nested-guest MSR permission bitmap memory backing. */
276 RTR0MEMOBJ hNstGstMsrpm;
277 /** The physical address of the first page in hNstGstMsrpm (physcially
278 * contiguous allocation). */
279 RTHCPHYS HCPhysNstGstMsrpm;
280 /** The address of the active nested-guest MSRPM. */
281 void *pvNstGstMsrpm;
282 } svm;
283 /** @todo Nested-VMX. */
284 } n;
285#endif
286} HMPHYSCPU;
287/** Pointer to HMPHYSCPU struct. */
288typedef HMPHYSCPU *PHMPHYSCPU;
289/** Pointer to a const HMPHYSCPU struct. */
290typedef const HMPHYSCPU *PCHMPHYSCPU;
291
292/**
293 * TPR-instruction type.
294 */
295typedef enum
296{
297 HMTPRINSTR_INVALID,
298 HMTPRINSTR_READ,
299 HMTPRINSTR_READ_SHR4,
300 HMTPRINSTR_WRITE_REG,
301 HMTPRINSTR_WRITE_IMM,
302 HMTPRINSTR_JUMP_REPLACEMENT,
303 /** The usual 32-bit paranoia. */
304 HMTPRINSTR_32BIT_HACK = 0x7fffffff
305} HMTPRINSTR;
306
307/**
308 * TPR patch information.
309 */
310typedef struct
311{
312 /** The key is the address of patched instruction. (32 bits GC ptr) */
313 AVLOU32NODECORE Core;
314 /** Original opcode. */
315 uint8_t aOpcode[16];
316 /** Instruction size. */
317 uint32_t cbOp;
318 /** Replacement opcode. */
319 uint8_t aNewOpcode[16];
320 /** Replacement instruction size. */
321 uint32_t cbNewOp;
322 /** Instruction type. */
323 HMTPRINSTR enmType;
324 /** Source operand. */
325 uint32_t uSrcOperand;
326 /** Destination operand. */
327 uint32_t uDstOperand;
328 /** Number of times the instruction caused a fault. */
329 uint32_t cFaults;
330 /** Patch address of the jump replacement. */
331 RTGCPTR32 pJumpTarget;
332} HMTPRPATCH;
333/** Pointer to HMTPRPATCH. */
334typedef HMTPRPATCH *PHMTPRPATCH;
335/** Pointer to a const HMTPRPATCH. */
336typedef const HMTPRPATCH *PCHMTPRPATCH;
337
338
339/**
340 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
341 *
342 * @returns 64-bit key
343 * @param a_uPC The RIP + CS.BASE value of the exit.
344 * @param a_uExit The exit code.
345 * @todo Add CPL?
346 */
347#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
348
349typedef struct HMEXITINFO
350{
351 /** See HMEXITSTAT_MAKE_KEY(). */
352 uint64_t uKey;
353 /** Number of recent hits (depreciates with time). */
354 uint32_t volatile cHits;
355 /** The age + lock. */
356 uint16_t volatile uAge;
357 /** Action or action table index. */
358 uint16_t iAction;
359} HMEXITINFO;
360AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
361
362typedef struct HMEXITHISTORY
363{
364 /** The exit timestamp. */
365 uint64_t uTscExit;
366 /** The index of the corresponding HMEXITINFO entry.
367 * UINT32_MAX if none (too many collisions, race, whatever). */
368 uint32_t iExitInfo;
369 /** Figure out later, needed for padding now. */
370 uint32_t uSomeClueOrSomething;
371} HMEXITHISTORY;
372
373/**
374 * Switcher function, HC to the special 64-bit RC.
375 *
376 * @param pVM The cross context VM structure.
377 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
378 * @returns Return code indicating the action to take.
379 */
380typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
381/** Pointer to switcher function. */
382typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
383
384/** @def HM_UNION_NM
385 * For compilers (like DTrace) that does not grok nameless unions, we have a
386 * little hack to make them palatable.
387 */
388/** @def HM_STRUCT_NM
389 * For compilers (like DTrace) that does not grok nameless structs (it is
390 * non-standard C++), we have a little hack to make them palatable.
391 */
392#ifdef VBOX_FOR_DTRACE_LIB
393# define HM_UNION_NM(a_Nm) a_Nm
394# define HM_STRUCT_NM(a_Nm) a_Nm
395#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
396# define HM_UNION_NM(a_Nm) a_Nm
397# define HM_STRUCT_NM(a_Nm) a_Nm
398#else
399# define HM_UNION_NM(a_Nm)
400# define HM_STRUCT_NM(a_Nm)
401#endif
402
403/**
404 * HM VM Instance data.
405 * Changes to this must checked against the padding of the hm union in VM!
406 */
407typedef struct HM
408{
409 /** Set when we've initialized VMX or SVM. */
410 bool fInitialized;
411 /** Set if nested paging is enabled. */
412 bool fNestedPaging;
413 /** Set if nested paging is allowed. */
414 bool fAllowNestedPaging;
415 /** Set if large pages are enabled (requires nested paging). */
416 bool fLargePages;
417 /** Set if we can support 64-bit guests or not. */
418 bool fAllow64BitGuests;
419 /** Set when TPR patching is allowed. */
420 bool fTprPatchingAllowed;
421 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
422 bool fGlobalInit;
423 /** Set when TPR patching is active. */
424 bool fTPRPatchingActive;
425 /** Set when the debug facility has breakpoints/events enabled that requires
426 * us to use the debug execution loop in ring-0. */
427 bool fUseDebugLoop;
428 /** Set if hardware APIC virtualization is enabled. */
429 bool fVirtApicRegs;
430 /** Set if posted interrupt processing is enabled. */
431 bool fPostedIntrs;
432 /** Set if indirect branch prediction barrier on VM exit. */
433 bool fIbpbOnVmExit;
434 /** Set if indirect branch prediction barrier on VM entry. */
435 bool fIbpbOnVmEntry;
436 /** Set if host manages speculation control settings. */
437 bool fSpecCtrlByHost;
438 /** Explicit padding. */
439 bool afPadding[2];
440
441 /** Maximum ASID allowed. */
442 uint32_t uMaxAsid;
443 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
444 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
445 uint32_t cMaxResumeLoops;
446
447 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
448 uint32_t fHostKernelFeatures;
449
450 /** Size of the guest patch memory block. */
451 uint32_t cbGuestPatchMem;
452 /** Guest allocated memory for patching purposes. */
453 RTGCPTR pGuestPatchMem;
454 /** Current free pointer inside the patch block. */
455 RTGCPTR pFreeGuestPatchMem;
456
457#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
458 /** 32 to 64 bits switcher entrypoint. */
459 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
460 RTR0PTR pvR0Alignment0;
461#endif
462
463 struct
464 {
465 /** Set by the ring-0 side of HM to indicate VMX is supported by the
466 * CPU. */
467 bool fSupported;
468 /** Set when we've enabled VMX. */
469 bool fEnabled;
470 /** Set if VPID is supported. */
471 bool fVpid;
472 /** Set if VT-x VPID is allowed. */
473 bool fAllowVpid;
474 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
475 bool fUnrestrictedGuest;
476 /** Set if unrestricted guest execution is allowed to be used. */
477 bool fAllowUnrestricted;
478 /** Set if the preemption timer is in use or not. */
479 bool fUsePreemptTimer;
480 /** The shift mask employed by the VMX-Preemption timer. */
481 uint8_t cPreemptTimerShift;
482
483 /** Virtual address of the TSS page used for real mode emulation. */
484 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
485 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
486 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
487
488 /** Physical address of the APIC-access page. */
489 RTHCPHYS HCPhysApicAccess;
490 /** R0 memory object for the APIC-access page. */
491 RTR0MEMOBJ hMemObjApicAccess;
492 /** Virtual address of the APIC-access page. */
493 R0PTRTYPE(uint8_t *) pbApicAccess;
494
495#ifdef VBOX_WITH_CRASHDUMP_MAGIC
496 RTHCPHYS HCPhysScratch;
497 RTR0MEMOBJ hMemObjScratch;
498 R0PTRTYPE(uint8_t *) pbScratch;
499#endif
500
501 /** Tagged-TLB flush type. */
502 VMXTLBFLUSHTYPE enmTlbFlushType;
503 /** Flush type to use for INVEPT. */
504 VMXTLBFLUSHEPT enmTlbFlushEpt;
505 /** Flush type to use for INVVPID. */
506 VMXTLBFLUSHVPID enmTlbFlushVpid;
507
508 /** Pause-loop exiting (PLE) gap in ticks. */
509 uint32_t cPleGapTicks;
510 /** Pause-loop exiting (PLE) window in ticks. */
511 uint32_t cPleWindowTicks;
512 uint32_t u32Alignment0;
513
514 /** Host CR4 value (set by ring-0 VMX init) */
515 uint64_t u64HostCr4;
516 /** Host SMM monitor control (set by ring-0 VMX init) */
517 uint64_t u64HostSmmMonitorCtl;
518 /** Host EFER value (set by ring-0 VMX init) */
519 uint64_t u64HostEfer;
520 /** Whether the CPU supports VMCS fields for swapping EFER. */
521 bool fSupportsVmcsEfer;
522 uint8_t u8Alignment2[7];
523
524 /** VMX MSR values. */
525 VMXMSRS Msrs;
526
527 /** Host-physical address for a failing VMXON instruction. */
528 RTHCPHYS HCPhysVmxEnableError;
529 } vmx;
530
531 struct
532 {
533 /** Set by the ring-0 side of HM to indicate SVM is supported by the
534 * CPU. */
535 bool fSupported;
536 /** Set when we've enabled SVM. */
537 bool fEnabled;
538 /** Set if erratum 170 affects the AMD cpu. */
539 bool fAlwaysFlushTLB;
540 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
541 bool fIgnoreInUseError;
542 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
543 bool fVirtVmsaveVmload;
544 /** Whether to use virtual GIF feature. */
545 bool fVGif;
546 uint8_t u8Alignment0[2];
547
548 /** Physical address of the IO bitmap (12kb). */
549 RTHCPHYS HCPhysIOBitmap;
550 /** R0 memory object for the IO bitmap (12kb). */
551 RTR0MEMOBJ hMemObjIOBitmap;
552 /** Virtual address of the IO bitmap. */
553 R0PTRTYPE(void *) pvIOBitmap;
554
555 /* HWCR MSR (for diagnostics) */
556 uint64_t u64MsrHwcr;
557
558 /** SVM revision. */
559 uint32_t u32Rev;
560 /** SVM feature bits from cpuid 0x8000000a */
561 uint32_t u32Features;
562
563 /** Pause filter counter. */
564 uint16_t cPauseFilter;
565 /** Pause filter treshold in ticks. */
566 uint16_t cPauseFilterThresholdTicks;
567 uint32_t u32Alignment0;
568 } svm;
569
570 /**
571 * AVL tree with all patches (active or disabled) sorted by guest instruction
572 * address.
573 */
574 AVLOU32TREE PatchTree;
575 uint32_t cPatches;
576 HMTPRPATCH aPatches[64];
577
578 /** Last recorded error code during HM ring-0 init. */
579 int32_t rcInit;
580
581 /** HMR0Init was run */
582 bool fHMR0Init;
583 bool u8Alignment1[3];
584
585 STAMCOUNTER StatTprPatchSuccess;
586 STAMCOUNTER StatTprPatchFailure;
587 STAMCOUNTER StatTprReplaceSuccessCr8;
588 STAMCOUNTER StatTprReplaceSuccessVmc;
589 STAMCOUNTER StatTprReplaceFailure;
590} HM;
591/** Pointer to HM VM instance data. */
592typedef HM *PHM;
593
594AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
595
596/* Maximum number of cached entries. */
597#define VMCSCACHE_MAX_ENTRY 128
598
599/**
600 * Structure for storing read and write VMCS actions.
601 */
602typedef struct VMCSCACHE
603{
604#ifdef VBOX_WITH_CRASHDUMP_MAGIC
605 /* Magic marker for searching in crash dumps. */
606 uint8_t aMagic[16];
607 uint64_t uMagic;
608 uint64_t u64TimeEntry;
609 uint64_t u64TimeSwitch;
610 uint64_t cResume;
611 uint64_t interPD;
612 uint64_t pSwitcher;
613 uint32_t uPos;
614 uint32_t idCpu;
615#endif
616 /* CR2 is saved here for EPT syncing. */
617 uint64_t cr2;
618 struct
619 {
620 uint32_t cValidEntries;
621 uint32_t uAlignment;
622 uint32_t aField[VMCSCACHE_MAX_ENTRY];
623 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
624 } Write;
625 struct
626 {
627 uint32_t cValidEntries;
628 uint32_t uAlignment;
629 uint32_t aField[VMCSCACHE_MAX_ENTRY];
630 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
631 } Read;
632#ifdef VBOX_STRICT
633 struct
634 {
635 RTHCPHYS HCPhysCpuPage;
636 RTHCPHYS HCPhysVmcs;
637 RTGCPTR pCache;
638 RTGCPTR pCtx;
639 } TestIn;
640 struct
641 {
642 RTHCPHYS HCPhysVmcs;
643 RTGCPTR pCache;
644 RTGCPTR pCtx;
645 uint64_t eflags;
646 uint64_t cr8;
647 } TestOut;
648 struct
649 {
650 uint64_t param1;
651 uint64_t param2;
652 uint64_t param3;
653 uint64_t param4;
654 } ScratchPad;
655#endif
656} VMCSCACHE;
657/** Pointer to VMCSCACHE. */
658typedef VMCSCACHE *PVMCSCACHE;
659AssertCompileSizeAlignment(VMCSCACHE, 8);
660
661/**
662 * VMX StartVM function.
663 *
664 * @returns VBox status code (no informational stuff).
665 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
666 * @param pCtx The CPU register context.
667 * @param pCache The VMCS cache.
668 * @param pVM Pointer to the cross context VM structure.
669 * @param pVCpu Pointer to the cross context per-CPU structure.
670 */
671typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
672/** Pointer to a VMX StartVM function. */
673typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
674
675/** SVM VMRun function. */
676typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
677/** Pointer to a SVM VMRun function. */
678typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
679
680/**
681 * HM VMCPU Instance data.
682 *
683 * Note! If you change members of this struct, make sure to check if the
684 * assembly counterpart in HMInternal.mac needs to be updated as well.
685 */
686typedef struct HMCPU
687{
688 /** Set when the TLB has been checked until we return from the world switch. */
689 bool volatile fCheckedTLBFlush;
690 /** Set if we need to flush the TLB during the world switch. */
691 bool fForceTLBFlush;
692 /** Set when we're using VT-x or AMD-V at that moment. */
693 bool fActive;
694 /** Whether we've completed the inner HM leave function. */
695 bool fLeaveDone;
696 /** Whether we're using the hyper DR7 or guest DR7. */
697 bool fUsingHyperDR7;
698 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
699 * execution. */
700 bool fLoadSaveGuestXcr0;
701
702 /** Whether we should use the debug loop because of single stepping or special
703 * debug breakpoints / events are armed. */
704 bool fUseDebugLoop;
705 /** Whether we are currently executing in the debug loop.
706 * Mainly for assertions. */
707 bool fUsingDebugLoop;
708 /** Set if we using the debug loop and wish to intercept RDTSC. */
709 bool fDebugWantRdTscExit;
710 /** Whether we're executing a single instruction. */
711 bool fSingleInstruction;
712 /** Set if we need to clear the trap flag because of single stepping. */
713 bool fClearTrapFlag;
714
715 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
716 bool fGIMTrapXcptUD;
717 /** Whether \#GP needs to be intercept for mesa driver workaround. */
718 bool fTrapXcptGpForLovelyMesaDrv;
719 uint8_t u8Alignment0[3];
720
721 /** World switch exit counter. */
722 uint32_t volatile cWorldSwitchExits;
723 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
724 RTCPUID idLastCpu;
725 /** TLB flush count. */
726 uint32_t cTlbFlushes;
727 /** Current ASID in use by the VM. */
728 uint32_t uCurrentAsid;
729 /** An additional error code used for some gurus. */
730 uint32_t u32HMError;
731 /** The last exit-to-ring-3 reason. */
732 int32_t rcLastExitToR3;
733 /** CPU-context changed flags (see HM_CHANGED_xxx). */
734 uint64_t fCtxChanged;
735 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
736 uint64_t u64HostTscAux;
737
738 union /* no tag! */
739 {
740 /** VT-x data. */
741 struct
742 {
743 /** Ring 0 handlers for VT-x. */
744 PFNHMVMXSTARTVM pfnStartVM;
745#if HC_ARCH_BITS == 32
746 uint32_t u32Alignment0;
747#endif
748
749 /** Current pin-based VM-execution controls. */
750 uint32_t u32PinCtls;
751 /** Current processor-based VM-execution controls. */
752 uint32_t u32ProcCtls;
753 /** Current secondary processor-based VM-execution controls. */
754 uint32_t u32ProcCtls2;
755 /** Current VM-entry controls. */
756 uint32_t u32EntryCtls;
757 /** Current VM-exit controls. */
758 uint32_t u32ExitCtls;
759 /** Current CR0 mask. */
760 uint32_t u32Cr0Mask;
761 /** Current CR4 mask. */
762 uint32_t u32Cr4Mask;
763 /** Current exception bitmap. */
764 uint32_t u32XcptBitmap;
765 /** Padding. */
766 uint32_t au32Alignment0[2];
767
768 /** Physical address of the VM control structure (VMCS). */
769 RTHCPHYS HCPhysVmcs;
770 /** R0 memory object for the VM control structure (VMCS). */
771 RTR0MEMOBJ hMemObjVmcs;
772 /** Virtual address of the VM control structure (VMCS). */
773 R0PTRTYPE(void *) pvVmcs;
774
775 /** Physical address of the virtual APIC page for TPR caching. */
776 RTHCPHYS HCPhysVirtApic;
777 /** Padding. */
778 R0PTRTYPE(void *) pvAlignment0;
779 /** Virtual address of the virtual APIC page for TPR caching. */
780 R0PTRTYPE(uint8_t *) pbVirtApic;
781
782 /** Physical address of the MSR bitmap. */
783 RTHCPHYS HCPhysMsrBitmap;
784 /** R0 memory object for the MSR bitmap. */
785 RTR0MEMOBJ hMemObjMsrBitmap;
786 /** Virtual address of the MSR bitmap. */
787 R0PTRTYPE(void *) pvMsrBitmap;
788
789 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
790 * for guest MSRs). */
791 RTHCPHYS HCPhysGuestMsr;
792 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
793 * (used for guest MSRs). */
794 RTR0MEMOBJ hMemObjGuestMsr;
795 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
796 * for guest MSRs). */
797 R0PTRTYPE(void *) pvGuestMsr;
798
799 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
800 RTHCPHYS HCPhysHostMsr;
801 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
802 RTR0MEMOBJ hMemObjHostMsr;
803 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
804 R0PTRTYPE(void *) pvHostMsr;
805
806 /** Physical address of the current EPTP. */
807 RTHCPHYS HCPhysEPTP;
808
809 /** Number of guest/host MSR pairs in the auto-load/store area. */
810 uint32_t cMsrs;
811 /** Whether the host MSR values are up-to-date in the auto-load/store area. */
812 bool fUpdatedHostMsrs;
813 uint8_t au8Alignment0[3];
814
815 /** Host LSTAR MSR value to restore lazily while leaving VT-x. */
816 uint64_t u64HostLStarMsr;
817 /** Host STAR MSR value to restore lazily while leaving VT-x. */
818 uint64_t u64HostStarMsr;
819 /** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
820 uint64_t u64HostSFMaskMsr;
821 /** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
822 uint64_t u64HostKernelGSBaseMsr;
823 /** A mask of which MSRs have been swapped and need restoration. */
824 uint32_t fLazyMsrs;
825 uint32_t u32Alignment1;
826
827 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
828 uint64_t u64MsrApicBase;
829 /** Last use TSC offset value. (cached) */
830 uint64_t u64TscOffset;
831
832 /** VMCS cache. */
833 VMCSCACHE VMCSCache;
834
835 /** Real-mode emulation state. */
836 struct
837 {
838 X86DESCATTR AttrCS;
839 X86DESCATTR AttrDS;
840 X86DESCATTR AttrES;
841 X86DESCATTR AttrFS;
842 X86DESCATTR AttrGS;
843 X86DESCATTR AttrSS;
844 X86EFLAGS Eflags;
845 bool fRealOnV86Active;
846 } RealMode;
847
848 /** VT-x error-reporting (mainly for ring-3 propagation). */
849 struct
850 {
851 uint64_t u64VmcsPhys;
852 uint32_t u32VmcsRev;
853 uint32_t u32InstrError;
854 uint32_t u32ExitReason;
855 uint32_t u32Alignment0;
856 RTCPUID idEnteredCpu;
857 RTCPUID idCurrentCpu;
858 } LastError;
859
860 /** Current state of the VMCS. */
861 uint32_t fVmcsState;
862 /** Which host-state bits to restore before being preempted. */
863 uint32_t fRestoreHostFlags;
864 /** The host-state restoration structure. */
865 VMXRESTOREHOST RestoreHost;
866
867 /** Set if guest was executing in real mode (extra checks). */
868 bool fWasInRealMode;
869 /** Set if guest switched to 64-bit mode on a 32-bit host. */
870 bool fSwitchedTo64on32;
871 /** Padding. */
872 uint8_t au8Alignment1[6];
873 } vmx;
874
875 /** SVM data. */
876 struct
877 {
878 /** Ring 0 handlers for VT-x. */
879 PFNHMSVMVMRUN pfnVMRun;
880#if HC_ARCH_BITS == 32
881 uint32_t u32Alignment0;
882#endif
883
884 /** Physical address of the host VMCB which holds additional host-state. */
885 RTHCPHYS HCPhysVmcbHost;
886 /** R0 memory object for the host VMCB which holds additional host-state. */
887 RTR0MEMOBJ hMemObjVmcbHost;
888 /** Padding. */
889 R0PTRTYPE(void *) pvPadding;
890
891 /** Physical address of the guest VMCB. */
892 RTHCPHYS HCPhysVmcb;
893 /** R0 memory object for the guest VMCB. */
894 RTR0MEMOBJ hMemObjVmcb;
895 /** Pointer to the guest VMCB. */
896 R0PTRTYPE(PSVMVMCB) pVmcb;
897
898 /** Physical address of the MSR bitmap (8 KB). */
899 RTHCPHYS HCPhysMsrBitmap;
900 /** R0 memory object for the MSR bitmap (8 KB). */
901 RTR0MEMOBJ hMemObjMsrBitmap;
902 /** Pointer to the MSR bitmap. */
903 R0PTRTYPE(void *) pvMsrBitmap;
904
905 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
906 * we should check if the VTPR changed on every VM-exit. */
907 bool fSyncVTpr;
908 uint8_t au8Alignment0[7];
909
910 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
911 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
912 SVMNESTEDVMCBCACHE NstGstVmcbCache;
913 } svm;
914 } HM_UNION_NM(u);
915
916 /** Event injection state. */
917 struct
918 {
919 uint32_t fPending;
920 uint32_t u32ErrCode;
921 uint32_t cbInstr;
922 uint32_t u32Padding; /**< Explicit alignment padding. */
923 uint64_t u64IntInfo;
924 RTGCUINTPTR GCPtrFaultAddress;
925 } Event;
926
927 /** The PAE PDPEs used with Nested Paging (only valid when
928 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
929 X86PDPE aPdpes[4];
930
931 /** Current shadow paging mode for updating CR4. */
932 PGMMODE enmShadowMode;
933
934 /** The CPU ID of the CPU currently owning the VMCS. Set in
935 * HMR0Enter and cleared in HMR0Leave. */
936 RTCPUID idEnteredCpu;
937
938 /** For saving stack space, the disassembler state is allocated here instead of
939 * on the stack. */
940 DISCPUSTATE DisState;
941
942 STAMPROFILEADV StatEntry;
943 STAMPROFILEADV StatPreExit;
944 STAMPROFILEADV StatExitHandling;
945 STAMPROFILEADV StatExitIO;
946 STAMPROFILEADV StatExitMovCRx;
947 STAMPROFILEADV StatExitXcptNmi;
948 STAMPROFILEADV StatImportGuestState;
949 STAMPROFILEADV StatExportGuestState;
950 STAMPROFILEADV StatLoadGuestFpuState;
951 STAMPROFILEADV StatInGC;
952#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
953 STAMPROFILEADV StatWorldSwitch3264;
954#endif
955 STAMPROFILEADV StatPoke;
956 STAMPROFILEADV StatSpinPoke;
957 STAMPROFILEADV StatSpinPokeFailed;
958
959 STAMCOUNTER StatInjectInterrupt;
960 STAMCOUNTER StatInjectXcpt;
961 STAMCOUNTER StatInjectPendingReflect;
962 STAMCOUNTER StatInjectPendingInterpret;
963
964 STAMCOUNTER StatExitAll;
965 STAMCOUNTER StatExitShadowNM;
966 STAMCOUNTER StatExitGuestNM;
967 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
968 STAMCOUNTER StatExitShadowPFEM;
969 STAMCOUNTER StatExitGuestPF;
970 STAMCOUNTER StatExitGuestUD;
971 STAMCOUNTER StatExitGuestSS;
972 STAMCOUNTER StatExitGuestNP;
973 STAMCOUNTER StatExitGuestTS;
974 STAMCOUNTER StatExitGuestGP;
975 STAMCOUNTER StatExitGuestDE;
976 STAMCOUNTER StatExitGuestDB;
977 STAMCOUNTER StatExitGuestMF;
978 STAMCOUNTER StatExitGuestBP;
979 STAMCOUNTER StatExitGuestXF;
980 STAMCOUNTER StatExitGuestXcpUnk;
981 STAMCOUNTER StatExitCli;
982 STAMCOUNTER StatExitSti;
983 STAMCOUNTER StatExitPushf;
984 STAMCOUNTER StatExitPopf;
985 STAMCOUNTER StatExitIret;
986 STAMCOUNTER StatExitInt;
987 STAMCOUNTER StatExitHlt;
988 STAMCOUNTER StatExitDRxWrite;
989 STAMCOUNTER StatExitDRxRead;
990 STAMCOUNTER StatExitCR0Read;
991 STAMCOUNTER StatExitCR2Read;
992 STAMCOUNTER StatExitCR3Read;
993 STAMCOUNTER StatExitCR4Read;
994 STAMCOUNTER StatExitCR8Read;
995 STAMCOUNTER StatExitCR0Write;
996 STAMCOUNTER StatExitCR2Write;
997 STAMCOUNTER StatExitCR3Write;
998 STAMCOUNTER StatExitCR4Write;
999 STAMCOUNTER StatExitCR8Write;
1000 STAMCOUNTER StatExitRdmsr;
1001 STAMCOUNTER StatExitWrmsr;
1002 STAMCOUNTER StatExitClts;
1003 STAMCOUNTER StatExitXdtrAccess;
1004 STAMCOUNTER StatExitMwait;
1005 STAMCOUNTER StatExitMonitor;
1006 STAMCOUNTER StatExitLmsw;
1007 STAMCOUNTER StatExitIOWrite;
1008 STAMCOUNTER StatExitIORead;
1009 STAMCOUNTER StatExitIOStringWrite;
1010 STAMCOUNTER StatExitIOStringRead;
1011 STAMCOUNTER StatExitIntWindow;
1012 STAMCOUNTER StatExitExtInt;
1013 STAMCOUNTER StatExitHostNmiInGC;
1014 STAMCOUNTER StatExitPreemptTimer;
1015 STAMCOUNTER StatExitTprBelowThreshold;
1016 STAMCOUNTER StatExitTaskSwitch;
1017 STAMCOUNTER StatExitMtf;
1018 STAMCOUNTER StatExitApicAccess;
1019 STAMCOUNTER StatExitReasonNpf;
1020
1021 STAMCOUNTER StatNestedExitReasonNpf;
1022
1023 STAMCOUNTER StatFlushPage;
1024 STAMCOUNTER StatFlushPageManual;
1025 STAMCOUNTER StatFlushPhysPageManual;
1026 STAMCOUNTER StatFlushTlb;
1027 STAMCOUNTER StatFlushTlbManual;
1028 STAMCOUNTER StatFlushTlbWorldSwitch;
1029 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1030 STAMCOUNTER StatFlushEntire;
1031 STAMCOUNTER StatFlushAsid;
1032 STAMCOUNTER StatFlushNestedPaging;
1033 STAMCOUNTER StatFlushTlbInvlpgVirt;
1034 STAMCOUNTER StatFlushTlbInvlpgPhys;
1035 STAMCOUNTER StatTlbShootdown;
1036 STAMCOUNTER StatTlbShootdownFlush;
1037
1038 STAMCOUNTER StatSwitchPendingHostIrq;
1039 STAMCOUNTER StatSwitchTprMaskedIrq;
1040 STAMCOUNTER StatSwitchGuestIrq;
1041 STAMCOUNTER StatSwitchHmToR3FF;
1042 STAMCOUNTER StatSwitchExitToR3;
1043 STAMCOUNTER StatSwitchLongJmpToR3;
1044 STAMCOUNTER StatSwitchMaxResumeLoops;
1045 STAMCOUNTER StatSwitchHltToR3;
1046 STAMCOUNTER StatSwitchApicAccessToR3;
1047 STAMCOUNTER StatSwitchPreempt;
1048 STAMCOUNTER StatSwitchPreemptExportHostState;
1049
1050 STAMCOUNTER StatTscParavirt;
1051 STAMCOUNTER StatTscOffset;
1052 STAMCOUNTER StatTscIntercept;
1053
1054 STAMCOUNTER StatDRxArmed;
1055 STAMCOUNTER StatDRxContextSwitch;
1056 STAMCOUNTER StatDRxIoCheck;
1057
1058 STAMCOUNTER StatExportMinimal;
1059 STAMCOUNTER StatExportFull;
1060 STAMCOUNTER StatLoadGuestFpu;
1061
1062 STAMCOUNTER StatVmxCheckBadRmSelBase;
1063 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1064 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1065 STAMCOUNTER StatVmxCheckRmOk;
1066 STAMCOUNTER StatVmxCheckBadSel;
1067 STAMCOUNTER StatVmxCheckBadRpl;
1068 STAMCOUNTER StatVmxCheckPmOk;
1069
1070#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1071 STAMCOUNTER StatFpu64SwitchBack;
1072 STAMCOUNTER StatDebug64SwitchBack;
1073#endif
1074#ifdef VBOX_WITH_STATISTICS
1075 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1076 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1077 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1078 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1079 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1080 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1081#endif
1082#ifdef HM_PROFILE_EXIT_DISPATCH
1083 STAMPROFILEADV StatExitDispatch;
1084#endif
1085} HMCPU;
1086/** Pointer to HM VMCPU instance data. */
1087typedef HMCPU *PHMCPU;
1088AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1089AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1090AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx, 8);
1091AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) svm, 8);
1092AssertCompileMemberAlignment(HMCPU, Event, 8);
1093
1094#ifdef IN_RING0
1095VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1096VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu);
1097
1098# ifdef VBOX_STRICT
1099VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu);
1100VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1101# endif
1102
1103# ifdef VBOX_WITH_KERNEL_USING_XMM
1104DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu,
1105 PFNHMVMXSTARTVM pfnStartVM);
1106DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu,
1107 PFNHMSVMVMRUN pfnVMRun);
1108# endif
1109#endif /* IN_RING0 */
1110
1111int hmSvmEmulateMovTpr(PVMCPU pVCpu);
1112
1113/** @} */
1114
1115RT_C_DECLS_END
1116
1117#endif
1118
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