HMInternal.h@ 71007

Last change on this file since 71007 was 70606, checked in by vboxsync, 7 years ago
updates (bugref:9087)
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1	/* $Id: HMInternal.h 70606 2018-01-16 19:05:36Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/pgm.h>
30	#include <VBox/vmm/cpum.h>
31	#include <VBox/vmm/trpm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35	#include <iprt/avl.h>
36	#include <iprt/string.h>
37
38	#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
39	# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
40	#endif
41
42	#if HC_ARCH_BITS == 64 \|\| defined (VBOX_WITH_64_BITS_GUESTS)
43	/* Enable 64 bits guest support. */
44	# define VBOX_ENABLE_64_BITS_GUESTS
45	#endif
46
47	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
48	# define VMX_USE_CACHED_VMCS_ACCESSES
49	#endif
50
51	/** @def HM_PROFILE_EXIT_DISPATCH
52	* Enables profiling of the VM exit handler dispatching. */
53	#if 0 \|\| defined(DOXYGEN_RUNNING)
54	# define HM_PROFILE_EXIT_DISPATCH
55	#endif
56
57	RT_C_DECLS_BEGIN
58
59
60	/** @defgroup grp_hm_int Internal
61	* @ingroup grp_hm
62	* @internal
63	* @{
64	*/
65
66	/** @def HMCPU_CF_CLEAR
67	* Clears a HM-context flag.
68	*
69	* @param pVCpu The cross context virtual CPU structure.
70	* @param fFlag The flag to clear.
71	*/
72	#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
73
74	/** @def HMCPU_CF_SET
75	* Sets a HM-context flag.
76	*
77	* @param pVCpu The cross context virtual CPU structure.
78	* @param fFlag The flag to set.
79	*/
80	#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
81
82	/** @def HMCPU_CF_IS_SET
83	* Checks if all the flags in the specified HM-context set is pending.
84	*
85	* @param pVCpu The cross context virtual CPU structure.
86	* @param fFlag The flag to check.
87	*/
88	#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
89
90	/** @def HMCPU_CF_IS_PENDING
91	* Checks if one or more of the flags in the specified HM-context set is
92	* pending.
93	*
94	* @param pVCpu The cross context virtual CPU structure.
95	* @param fFlags The flags to check for.
96	*/
97	#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
98
99	/** @def HMCPU_CF_IS_PENDING_ONLY
100	* Checks if -only- one or more of the specified HM-context flags is pending.
101	*
102	* @param pVCpu The cross context virtual CPU structure.
103	* @param fFlags The flags to check for.
104	*/
105	#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
106
107	/** @def HMCPU_CF_IS_SET_ONLY
108	* Checks if -only- all the flags in the specified HM-context set is pending.
109	*
110	* @param pVCpu The cross context virtual CPU structure.
111	* @param fFlags The flags to check for.
112	*/
113	#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
114
115	/** @def HMCPU_CF_RESET_TO
116	* Resets the HM-context flags to the specified value.
117	*
118	* @param pVCpu The cross context virtual CPU structure.
119	* @param fFlags The new value.
120	*/
121	#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
122
123	/** @def HMCPU_CF_VALUE
124	* Returns the current HM-context flags value.
125	*
126	* @param pVCpu The cross context virtual CPU structure.
127	*/
128	#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
129
130
131	/** Resets/initializes the VM-exit/\#VMEXIT history array. */
132	#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
133
134	/** Updates the VM-exit/\#VMEXIT history array. */
135	#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
136	do { \
137	AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
138	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
139	if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
140	(pVCpu)->hm.s.idxExitHistoryFree = 0; \
141	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
142	} while (0)
143
144	/** Maximum number of exit reason statistics counters. */
145	#define MAX_EXITREASON_STAT 0x100
146	#define MASK_EXITREASON_STAT 0xff
147	#define MASK_INJECT_IRQ_STAT 0xff
148
149	/** @name HM changed flags.
150	* These flags are used to keep track of which important registers that have
151	* been changed since last they were reset.
152	*
153	* Flags marked "shared" are used for registers that are common to both the host
154	* and guest (i.e. without dedicated VMCS/VMCB fields for guest bits).
155	*
156	* @{
157	*/
158	#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
159	#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
160	#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
161	#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
162	#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
163	#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
164	#define HM_CHANGED_GUEST_TR RT_BIT(6)
165	#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
166	#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
167	#define HM_CHANGED_GUEST_RIP RT_BIT(9)
168	#define HM_CHANGED_GUEST_RSP RT_BIT(10)
169	#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
170	#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
171	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
172	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
173	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
174	#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
175	#define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(17) /* Shared / /* @todo Move this to VT-x specific? */
176	#define HM_CHANGED_GUEST_XCPT_INTERCEPTS RT_BIT(18)
177	/* VT-x specific state. */
178	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(19)
179	#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(20)
180	#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(21)
181	#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(22)
182	#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(23)
183	/* AMD-V specific state. */
184	#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(19)
185	#define HM_CHANGED_SVM_RESERVED1 RT_BIT(20)
186	#define HM_CHANGED_SVM_RESERVED2 RT_BIT(21)
187	#define HM_CHANGED_SVM_RESERVED3 RT_BIT(22)
188	#define HM_CHANGED_SVM_RESERVED4 RT_BIT(23)
189
190	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
191	\| HM_CHANGED_GUEST_CR3 \
192	\| HM_CHANGED_GUEST_CR4 \
193	\| HM_CHANGED_GUEST_GDTR \
194	\| HM_CHANGED_GUEST_IDTR \
195	\| HM_CHANGED_GUEST_LDTR \
196	\| HM_CHANGED_GUEST_TR \
197	\| HM_CHANGED_GUEST_SEGMENT_REGS \
198	\| HM_CHANGED_GUEST_DEBUG \
199	\| HM_CHANGED_GUEST_RIP \
200	\| HM_CHANGED_GUEST_RSP \
201	\| HM_CHANGED_GUEST_RFLAGS \
202	\| HM_CHANGED_GUEST_CR2 \
203	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR \
204	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
205	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
206	\| HM_CHANGED_GUEST_EFER_MSR \
207	\| HM_CHANGED_GUEST_LAZY_MSRS \
208	\| HM_CHANGED_GUEST_XCPT_INTERCEPTS \
209	\| HM_CHANGED_VMX_GUEST_AUTO_MSRS \
210	\| HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
211	\| HM_CHANGED_VMX_GUEST_APIC_STATE \
212	\| HM_CHANGED_VMX_ENTRY_CTLS \
213	\| HM_CHANGED_VMX_EXIT_CTLS)
214
215	#define HM_CHANGED_HOST_CONTEXT RT_BIT(24)
216
217	/* Bits shared between host and guest. */
218	#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
219	\| HM_CHANGED_GUEST_DEBUG \
220	\| HM_CHANGED_GUEST_LAZY_MSRS)
221	/** @} */
222
223	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
224	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
225	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
226	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
227	/** Total guest mapped memory needed. */
228	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
229
230
231	/** @name Macros for enabling and disabling preemption.
232	* These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
233	* preemption has already been disabled when there is no context hook.
234	* @{ */
235	#ifdef VBOX_STRICT
236	# define HM_DISABLE_PREEMPT() \
237	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
238	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) \|\| VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
239	RTThreadPreemptDisable(&PreemptStateInternal)
240	#else
241	# define HM_DISABLE_PREEMPT() \
242	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
243	RTThreadPreemptDisable(&PreemptStateInternal)
244	#endif /* VBOX_STRICT */
245	#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
246	/** @} */
247
248
249	/** Enable for TPR guest patching. */
250	#define VBOX_HM_WITH_GUEST_PATCHING
251
252	/** @name HM saved state versions
253	* @{
254	*/
255	#ifdef VBOX_HM_WITH_GUEST_PATCHING
256	# define HM_SAVED_STATE_VERSION 5
257	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
258	#else
259	# define HM_SAVED_STATE_VERSION 4
260	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
261	#endif
262	#define HM_SAVED_STATE_VERSION_2_0_X 3
263	/** @} */
264
265	/**
266	* Global per-cpu information. (host)
267	*/
268	typedef struct HMGLOBALCPUINFO
269	{
270	/** The CPU ID. */
271	RTCPUID idCpu;
272	/** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
273	RTR0MEMOBJ hMemObj;
274	/** The physical address of the first page in hMemObj (it's a
275	* physcially contigous allocation if it spans multiple pages). */
276	RTHCPHYS HCPhysMemObj;
277	/** The address of the memory (for pfnEnable). */
278	void *pvMemObj;
279	/** Current ASID (AMD-V) / VPID (Intel). */
280	uint32_t uCurrentAsid;
281	/** TLB flush count. */
282	uint32_t cTlbFlushes;
283	/** Whether to flush each new ASID/VPID before use. */
284	bool fFlushAsidBeforeUse;
285	/** Configured for VT-x or AMD-V. */
286	bool fConfigured;
287	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
288	bool fIgnoreAMDVInUseError;
289	/** In use by our code. (for power suspend) */
290	volatile bool fInUse;
291	} HMGLOBALCPUINFO;
292	/** Pointer to the per-cpu global information. */
293	typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
294
295	typedef enum
296	{
297	HMPENDINGIO_INVALID = 0,
298	HMPENDINGIO_PORT_READ,
299	/* not implemented: HMPENDINGIO_STRING_READ, */
300	/* not implemented: HMPENDINGIO_STRING_WRITE, */
301	/** The usual 32-bit paranoia. */
302	HMPENDINGIO_32BIT_HACK = 0x7fffffff
303	} HMPENDINGIO;
304
305
306	typedef enum
307	{
308	HMTPRINSTR_INVALID,
309	HMTPRINSTR_READ,
310	HMTPRINSTR_READ_SHR4,
311	HMTPRINSTR_WRITE_REG,
312	HMTPRINSTR_WRITE_IMM,
313	HMTPRINSTR_JUMP_REPLACEMENT,
314	/** The usual 32-bit paranoia. */
315	HMTPRINSTR_32BIT_HACK = 0x7fffffff
316	} HMTPRINSTR;
317
318	typedef struct
319	{
320	/** The key is the address of patched instruction. (32 bits GC ptr) */
321	AVLOU32NODECORE Core;
322	/** Original opcode. */
323	uint8_t aOpcode[16];
324	/** Instruction size. */
325	uint32_t cbOp;
326	/** Replacement opcode. */
327	uint8_t aNewOpcode[16];
328	/** Replacement instruction size. */
329	uint32_t cbNewOp;
330	/** Instruction type. */
331	HMTPRINSTR enmType;
332	/** Source operand. */
333	uint32_t uSrcOperand;
334	/** Destination operand. */
335	uint32_t uDstOperand;
336	/** Number of times the instruction caused a fault. */
337	uint32_t cFaults;
338	/** Patch address of the jump replacement. */
339	RTGCPTR32 pJumpTarget;
340	} HMTPRPATCH;
341	/** Pointer to HMTPRPATCH. */
342	typedef HMTPRPATCH *PHMTPRPATCH;
343
344
345	/**
346	* Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
347	*
348	* @returns 64-bit key
349	* @param a_uPC The RIP + CS.BASE value of the exit.
350	* @param a_uExit The exit code.
351	* @todo Add CPL?
352	*/
353	#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) \| (uint64_t)(a_uExit) << 48)
354
355	typedef struct HMEXITINFO
356	{
357	/** See HMEXITSTAT_MAKE_KEY(). */
358	uint64_t uKey;
359	/** Number of recent hits (depreciates with time). */
360	uint32_t volatile cHits;
361	/** The age + lock. */
362	uint16_t volatile uAge;
363	/** Action or action table index. */
364	uint16_t iAction;
365	} HMEXITINFO;
366	AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
367
368	typedef struct HMEXITHISTORY
369	{
370	/** The exit timestamp. */
371	uint64_t uTscExit;
372	/** The index of the corresponding HMEXITINFO entry.
373	* UINT32_MAX if none (too many collisions, race, whatever). */
374	uint32_t iExitInfo;
375	/** Figure out later, needed for padding now. */
376	uint32_t uSomeClueOrSomething;
377	} HMEXITHISTORY;
378
379	/**
380	* Switcher function, HC to the special 64-bit RC.
381	*
382	* @param pVM The cross context VM structure.
383	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
384	* @returns Return code indicating the action to take.
385	*/
386	typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
387	/** Pointer to switcher function. */
388	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
389
390	/**
391	* HM VM Instance data.
392	* Changes to this must checked against the padding of the hm union in VM!
393	*/
394	typedef struct HM
395	{
396	/** Set when we've initialized VMX or SVM. */
397	bool fInitialized;
398	/** Set if nested paging is enabled. */
399	bool fNestedPaging;
400	/** Set if nested paging is allowed. */
401	bool fAllowNestedPaging;
402	/** Set if large pages are enabled (requires nested paging). */
403	bool fLargePages;
404	/** Set if we can support 64-bit guests or not. */
405	bool fAllow64BitGuests;
406	/** Set when TPR patching is allowed. */
407	bool fTprPatchingAllowed;
408	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
409	bool fGlobalInit;
410	/** Set when TPR patching is active. */
411	bool fTPRPatchingActive;
412	/** Set when the debug facility has breakpoints/events enabled that requires
413	* us to use the debug execution loop in ring-0. */
414	bool fUseDebugLoop;
415	/** Set if hardware APIC virtualization is enabled. */
416	bool fVirtApicRegs;
417	/** Set if posted interrupt processing is enabled. */
418	bool fPostedIntrs;
419	/** Set if indirect branch prediction barrier on VM exit. */
420	bool fIbpbOnVmExit;
421	/** Set if indirect branch prediction barrier on VM entry. */
422	bool fIbpbOnVmEntry;
423	/** Explicit padding. */
424	bool afPadding[3];
425
426	/** Maximum ASID allowed. */
427	uint32_t uMaxAsid;
428	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
429	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
430	uint32_t cMaxResumeLoops;
431
432	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
433	uint32_t fHostKernelFeatures;
434
435	/** Size of the guest patch memory block. */
436	uint32_t cbGuestPatchMem;
437	/** Guest allocated memory for patching purposes. */
438	RTGCPTR pGuestPatchMem;
439	/** Current free pointer inside the patch block. */
440	RTGCPTR pFreeGuestPatchMem;
441
442	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
443	/** 32 to 64 bits switcher entrypoint. */
444	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
445	RTR0PTR pvR0Alignment0;
446	#endif
447
448	struct
449	{
450	/** Set by the ring-0 side of HM to indicate VMX is supported by the
451	* CPU. */
452	bool fSupported;
453	/** Set when we've enabled VMX. */
454	bool fEnabled;
455	/** Set if VPID is supported. */
456	bool fVpid;
457	/** Set if VT-x VPID is allowed. */
458	bool fAllowVpid;
459	/** Set if unrestricted guest execution is in use (real and protected mode without paging). */
460	bool fUnrestrictedGuest;
461	/** Set if unrestricted guest execution is allowed to be used. */
462	bool fAllowUnrestricted;
463	/** Whether we're using the preemption timer or not. */
464	bool fUsePreemptTimer;
465	/** The shift mask employed by the VMX-Preemption timer. */
466	uint8_t cPreemptTimerShift;
467
468	/** Virtual address of the TSS page used for real mode emulation. */
469	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
470	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
471	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
472
473	/** Physical address of the APIC-access page. */
474	RTHCPHYS HCPhysApicAccess;
475	/** R0 memory object for the APIC-access page. */
476	RTR0MEMOBJ hMemObjApicAccess;
477	/** Virtual address of the APIC-access page. */
478	R0PTRTYPE(uint8_t *) pbApicAccess;
479
480	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
481	RTHCPHYS HCPhysScratch;
482	RTR0MEMOBJ hMemObjScratch;
483	R0PTRTYPE(uint8_t *) pbScratch;
484	#endif
485
486	/** Internal Id of which flush-handler to use for tagged-TLB entries. */
487	uint32_t uFlushTaggedTlb;
488
489	/** Pause-loop exiting (PLE) gap in ticks. */
490	uint32_t cPleGapTicks;
491	/** Pause-loop exiting (PLE) window in ticks. */
492	uint32_t cPleWindowTicks;
493	uint32_t u32Alignment0;
494
495	/** Host CR4 value (set by ring-0 VMX init) */
496	uint64_t u64HostCr4;
497	/** Host SMM monitor control (set by ring-0 VMX init) */
498	uint64_t u64HostSmmMonitorCtl;
499	/** Host EFER value (set by ring-0 VMX init) */
500	uint64_t u64HostEfer;
501	/** Whether the CPU supports VMCS fields for swapping EFER. */
502	bool fSupportsVmcsEfer;
503	uint8_t u8Alignment2[7];
504
505	/** VMX MSR values. */
506	VMXMSRS Msrs;
507
508	/** Flush types for invept & invvpid; they depend on capabilities. */
509	VMXFLUSHEPT enmFlushEpt;
510	VMXFLUSHVPID enmFlushVpid;
511
512	/** Host-physical address for a failing VMXON instruction. */
513	RTHCPHYS HCPhysVmxEnableError;
514	} vmx;
515
516	struct
517	{
518	/** Set by the ring-0 side of HM to indicate SVM is supported by the
519	* CPU. */
520	bool fSupported;
521	/** Set when we've enabled SVM. */
522	bool fEnabled;
523	/** Set if erratum 170 affects the AMD cpu. */
524	bool fAlwaysFlushTLB;
525	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
526	bool fIgnoreInUseError;
527	/** Whether to use virtualized VMSAVE/VMLOAD feature. */
528	bool fVirtVmsaveVmload;
529	/** Whether to use virtual GIF feature. */
530	bool fVGif;
531	uint8_t u8Alignment0[2];
532
533	/** Physical address of the IO bitmap (12kb). */
534	RTHCPHYS HCPhysIOBitmap;
535	/** R0 memory object for the IO bitmap (12kb). */
536	RTR0MEMOBJ hMemObjIOBitmap;
537	/** Virtual address of the IO bitmap. */
538	R0PTRTYPE(void *) pvIOBitmap;
539
540	/* HWCR MSR (for diagnostics) */
541	uint64_t u64MsrHwcr;
542
543	/** SVM revision. */
544	uint32_t u32Rev;
545	/** SVM feature bits from cpuid 0x8000000a */
546	uint32_t u32Features;
547
548	/** Pause filter counter. */
549	uint16_t cPauseFilter;
550	/** Pause filter treshold in ticks. */
551	uint16_t cPauseFilterThresholdTicks;
552	uint32_t u32Alignment0;
553	} svm;
554
555	/**
556	* AVL tree with all patches (active or disabled) sorted by guest instruction
557	* address.
558	*/
559	AVLOU32TREE PatchTree;
560	uint32_t cPatches;
561	HMTPRPATCH aPatches[64];
562
563	struct
564	{
565	uint32_t u32AMDFeatureECX;
566	uint32_t u32AMDFeatureEDX;
567	} cpuid;
568
569	/** Saved error from detection */
570	int32_t lLastError;
571
572	/** HMR0Init was run */
573	bool fHMR0Init;
574	bool u8Alignment1[3];
575
576	STAMCOUNTER StatTprPatchSuccess;
577	STAMCOUNTER StatTprPatchFailure;
578	STAMCOUNTER StatTprReplaceSuccessCr8;
579	STAMCOUNTER StatTprReplaceSuccessVmc;
580	STAMCOUNTER StatTprReplaceFailure;
581	} HM;
582	/** Pointer to HM VM instance data. */
583	typedef HM *PHM;
584
585	AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
586
587	/* Maximum number of cached entries. */
588	#define VMCSCACHE_MAX_ENTRY 128
589
590	/**
591	* Structure for storing read and write VMCS actions.
592	*/
593	typedef struct VMCSCACHE
594	{
595	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
596	/* Magic marker for searching in crash dumps. */
597	uint8_t aMagic[16];
598	uint64_t uMagic;
599	uint64_t u64TimeEntry;
600	uint64_t u64TimeSwitch;
601	uint64_t cResume;
602	uint64_t interPD;
603	uint64_t pSwitcher;
604	uint32_t uPos;
605	uint32_t idCpu;
606	#endif
607	/* CR2 is saved here for EPT syncing. */
608	uint64_t cr2;
609	struct
610	{
611	uint32_t cValidEntries;
612	uint32_t uAlignment;
613	uint32_t aField[VMCSCACHE_MAX_ENTRY];
614	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
615	} Write;
616	struct
617	{
618	uint32_t cValidEntries;
619	uint32_t uAlignment;
620	uint32_t aField[VMCSCACHE_MAX_ENTRY];
621	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
622	} Read;
623	#ifdef VBOX_STRICT
624	struct
625	{
626	RTHCPHYS HCPhysCpuPage;
627	RTHCPHYS HCPhysVmcs;
628	RTGCPTR pCache;
629	RTGCPTR pCtx;
630	} TestIn;
631	struct
632	{
633	RTHCPHYS HCPhysVmcs;
634	RTGCPTR pCache;
635	RTGCPTR pCtx;
636	uint64_t eflags;
637	uint64_t cr8;
638	} TestOut;
639	struct
640	{
641	uint64_t param1;
642	uint64_t param2;
643	uint64_t param3;
644	uint64_t param4;
645	} ScratchPad;
646	#endif
647	} VMCSCACHE;
648	/** Pointer to VMCSCACHE. */
649	typedef VMCSCACHE *PVMCSCACHE;
650	AssertCompileSizeAlignment(VMCSCACHE, 8);
651
652	/**
653	* VMX StartVM function.
654	*
655	* @returns VBox status code (no informational stuff).
656	* @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
657	* @param pCtx The CPU register context.
658	* @param pCache The VMCS cache.
659	* @param pVM Pointer to the cross context VM structure.
660	* @param pVCpu Pointer to the cross context per-CPU structure.
661	*/
662	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
663	/** Pointer to a VMX StartVM function. */
664	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
665
666	/** SVM VMRun function. */
667	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
668	/** Pointer to a SVM VMRun function. */
669	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
670
671	/**
672	* HM VMCPU Instance data.
673	*
674	* Note! If you change members of this struct, make sure to check if the
675	* assembly counterpart in HMInternal.mac needs to be updated as well.
676	*/
677	typedef struct HMCPU
678	{
679	/** Set if we need to flush the TLB during the world switch. */
680	bool fForceTLBFlush;
681	/** Set when we're using VT-x or AMD-V at that moment. */
682	bool fActive;
683	/** Set when the TLB has been checked until we return from the world switch. */
684	volatile bool fCheckedTLBFlush;
685	/** Whether we've completed the inner HM leave function. */
686	bool fLeaveDone;
687	/** Whether we're using the hyper DR7 or guest DR7. */
688	bool fUsingHyperDR7;
689	/** Whether to preload the guest-FPU state to avoid \#NM VM-exit overhead. */
690	bool fPreloadGuestFpu;
691	/** Set if XCR0 needs to be loaded and saved when entering and exiting guest
692	* code execution. */
693	bool fLoadSaveGuestXcr0;
694
695	/** Whether we should use the debug loop because of single stepping or special
696	* debug breakpoints / events are armed. */
697	bool fUseDebugLoop;
698	/** Whether we are currently executing in the debug loop.
699	* Mainly for assertions. */
700	bool fUsingDebugLoop;
701	/** Set if we using the debug loop and wish to intercept RDTSC. */
702	bool fDebugWantRdTscExit;
703	/** Whether we're executing a single instruction. */
704	bool fSingleInstruction;
705	/** Set if we need to clear the trap flag because of single stepping. */
706	bool fClearTrapFlag;
707
708	/** Whether \#UD needs to be intercepted (required by certain GIM providers). */
709	bool fGIMTrapXcptUD;
710	/** Whether paravirt. hypercalls are enabled. */
711	bool fHypercallsEnabled;
712	uint8_t u8Alignment0[2];
713
714	/** World switch exit counter. */
715	volatile uint32_t cWorldSwitchExits;
716	/** HM_CHANGED_* flags. */
717	volatile uint32_t fContextUseFlags;
718	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
719	* time). */
720	RTCPUID idLastCpu;
721	/** TLB flush count. */
722	uint32_t cTlbFlushes;
723	/** Current ASID in use by the VM. */
724	uint32_t uCurrentAsid;
725	/** An additional error code used for some gurus. */
726	uint32_t u32HMError;
727	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
728	uint64_t u64HostTscAux;
729
730	struct
731	{
732	/** Ring 0 handlers for VT-x. */
733	PFNHMVMXSTARTVM pfnStartVM;
734	#if HC_ARCH_BITS == 32
735	uint32_t u32Alignment0;
736	#endif
737	/** Current VMX_VMCS32_CTRL_PIN_EXEC. */
738	uint32_t u32PinCtls;
739	/** Current VMX_VMCS32_CTRL_PROC_EXEC. */
740	uint32_t u32ProcCtls;
741	/** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
742	uint32_t u32ProcCtls2;
743	/** Current VMX_VMCS32_CTRL_EXIT. */
744	uint32_t u32ExitCtls;
745	/** Current VMX_VMCS32_CTRL_ENTRY. */
746	uint32_t u32EntryCtls;
747
748	/** Current CR0 mask. */
749	uint32_t u32CR0Mask;
750	/** Current CR4 mask. */
751	uint32_t u32CR4Mask;
752	/** Current exception bitmap. */
753	uint32_t u32XcptBitmap;
754	/** The updated-guest-state mask. */
755	volatile uint32_t fUpdatedGuestState;
756	uint32_t u32Alignment1;
757
758	/** Physical address of the VM control structure (VMCS). */
759	RTHCPHYS HCPhysVmcs;
760	/** R0 memory object for the VM control structure (VMCS). */
761	RTR0MEMOBJ hMemObjVmcs;
762	/** Virtual address of the VM control structure (VMCS). */
763	R0PTRTYPE(void *) pvVmcs;
764
765	/** Physical address of the virtual APIC page for TPR caching. */
766	RTHCPHYS HCPhysVirtApic;
767	/** Padding. */
768	R0PTRTYPE(void *) pvAlignment0;
769	/** Virtual address of the virtual APIC page for TPR caching. */
770	R0PTRTYPE(uint8_t *) pbVirtApic;
771
772	/** Physical address of the MSR bitmap. */
773	RTHCPHYS HCPhysMsrBitmap;
774	/** R0 memory object for the MSR bitmap. */
775	RTR0MEMOBJ hMemObjMsrBitmap;
776	/** Virtual address of the MSR bitmap. */
777	R0PTRTYPE(void *) pvMsrBitmap;
778
779	/** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
780	* for guest MSRs). */
781	RTHCPHYS HCPhysGuestMsr;
782	/** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
783	* (used for guest MSRs). */
784	RTR0MEMOBJ hMemObjGuestMsr;
785	/** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
786	* for guest MSRs). */
787	R0PTRTYPE(void *) pvGuestMsr;
788
789	/** Physical address of the VM-exit MSR-load area (used for host MSRs). */
790	RTHCPHYS HCPhysHostMsr;
791	/** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
792	RTR0MEMOBJ hMemObjHostMsr;
793	/** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
794	R0PTRTYPE(void *) pvHostMsr;
795
796	/** Current EPTP. */
797	RTHCPHYS HCPhysEPTP;
798
799	/** Number of guest/host MSR pairs in the auto-load/store area. */
800	uint32_t cMsrs;
801	/** Whether the host MSR values are up-to-date in the auto-load/store area. */
802	bool fUpdatedHostMsrs;
803	uint8_t u8Alignment0[3];
804
805	/** Host LSTAR MSR value to restore lazily while leaving VT-x. */
806	uint64_t u64HostLStarMsr;
807	/** Host STAR MSR value to restore lazily while leaving VT-x. */
808	uint64_t u64HostStarMsr;
809	/** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
810	uint64_t u64HostSFMaskMsr;
811	/** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
812	uint64_t u64HostKernelGSBaseMsr;
813	/** A mask of which MSRs have been swapped and need restoration. */
814	uint32_t fLazyMsrs;
815	uint32_t u32Alignment2;
816
817	/** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
818	uint64_t u64MsrApicBase;
819	/** Last use TSC offset value. (cached) */
820	uint64_t u64TSCOffset;
821
822	/** VMCS cache. */
823	VMCSCACHE VMCSCache;
824
825	/** Real-mode emulation state. */
826	struct
827	{
828	X86DESCATTR AttrCS;
829	X86DESCATTR AttrDS;
830	X86DESCATTR AttrES;
831	X86DESCATTR AttrFS;
832	X86DESCATTR AttrGS;
833	X86DESCATTR AttrSS;
834	X86EFLAGS Eflags;
835	uint32_t fRealOnV86Active;
836	} RealMode;
837
838	/** VT-x error-reporting (mainly for ring-3 propagation). */
839	struct
840	{
841	uint64_t u64VMCSPhys;
842	uint32_t u32VMCSRevision;
843	uint32_t u32InstrError;
844	uint32_t u32ExitReason;
845	RTCPUID idEnteredCpu;
846	RTCPUID idCurrentCpu;
847	uint32_t u32Alignment0;
848	} LastError;
849
850	/** Current state of the VMCS. */
851	uint32_t uVmcsState;
852	/** Which host-state bits to restore before being preempted. */
853	uint32_t fRestoreHostFlags;
854	/** The host-state restoration structure. */
855	VMXRESTOREHOST RestoreHost;
856
857	/** Set if guest was executing in real mode (extra checks). */
858	bool fWasInRealMode;
859	/** Set if guest switched to 64-bit mode on a 32-bit host. */
860	bool fSwitchedTo64on32;
861
862	uint8_t u8Alignment1[6];
863	} vmx;
864
865	struct
866	{
867	/** Ring 0 handlers for VT-x. */
868	PFNHMSVMVMRUN pfnVMRun;
869	#if HC_ARCH_BITS == 32
870	uint32_t u32Alignment0;
871	#endif
872
873	/** Physical address of the host VMCB which holds additional host-state. */
874	RTHCPHYS HCPhysVmcbHost;
875	/** R0 memory object for the host VMCB which holds additional host-state. */
876	RTR0MEMOBJ hMemObjVmcbHost;
877	/** Padding. */
878	R0PTRTYPE(void *) pvPadding;
879
880	/** Physical address of the guest VMCB. */
881	RTHCPHYS HCPhysVmcb;
882	/** R0 memory object for the guest VMCB. */
883	RTR0MEMOBJ hMemObjVmcb;
884	/** Pointer to the guest VMCB. */
885	R0PTRTYPE(PSVMVMCB) pVmcb;
886
887	/** Physical address of the MSR bitmap (8 KB). */
888	RTHCPHYS HCPhysMsrBitmap;
889	/** R0 memory object for the MSR bitmap (8 KB). */
890	RTR0MEMOBJ hMemObjMsrBitmap;
891	/** Pointer to the MSR bitmap. */
892	R0PTRTYPE(void *) pvMsrBitmap;
893
894	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
895	* we should check if the VTPR changed on every VM-exit. */
896	bool fSyncVTpr;
897	uint8_t u8Alignment0[7];
898
899	/** Cache of the nested-guest's VMCB fields that we modify in order to run the
900	* nested-guest using AMD-V. This will be restored on \#VMEXIT. */
901	SVMNESTEDVMCBCACHE NstGstVmcbCache;
902	} svm;
903
904	/** Event injection state. */
905	struct
906	{
907	uint32_t fPending;
908	uint32_t u32ErrCode;
909	uint32_t cbInstr;
910	uint32_t u32Padding; /*< Explicit alignment padding. /
911	uint64_t u64IntInfo;
912	RTGCUINTPTR GCPtrFaultAddress;
913	} Event;
914
915	/** IO Block emulation state. */
916	struct
917	{
918	bool fEnabled;
919	uint8_t u8Align[7];
920
921	/** RIP at the start of the io code we wish to emulate in the recompiler. */
922	RTGCPTR GCPtrFunctionEip;
923
924	uint64_t cr0;
925	} EmulateIoBlock;
926
927	/* */
928	struct
929	{
930	/** Pending IO operation type. */
931	HMPENDINGIO enmType;
932	uint32_t u32Alignment0;
933	RTGCPTR GCPtrRip;
934	RTGCPTR GCPtrRipNext;
935	union
936	{
937	struct
938	{
939	uint32_t uPort;
940	uint32_t uAndVal;
941	uint32_t cbSize;
942	} Port;
943	uint64_t aRaw[2];
944	} s;
945	} PendingIO;
946
947	/** The PAE PDPEs used with Nested Paging (only valid when
948	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
949	X86PDPE aPdpes[4];
950
951	/** Current shadow paging mode. */
952	PGMMODE enmShadowMode;
953
954	/** The CPU ID of the CPU currently owning the VMCS. Set in
955	* HMR0Enter and cleared in HMR0Leave. */
956	RTCPUID idEnteredCpu;
957
958	/** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
959	uint16_t auExitHistory[31];
960	/** The index of the next free slot in the history array. */
961	uint16_t idxExitHistoryFree;
962
963	/** For saving stack space, the disassembler state is allocated here instead of
964	* on the stack. */
965	DISCPUSTATE DisState;
966
967	STAMPROFILEADV StatEntry;
968	STAMPROFILEADV StatExit1;
969	STAMPROFILEADV StatExit2;
970	STAMPROFILEADV StatExitIO;
971	STAMPROFILEADV StatExitMovCRx;
972	STAMPROFILEADV StatExitXcptNmi;
973	STAMPROFILEADV StatLoadGuestState;
974	STAMPROFILEADV StatInGC;
975
976	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
977	STAMPROFILEADV StatWorldSwitch3264;
978	#endif
979	STAMPROFILEADV StatPoke;
980	STAMPROFILEADV StatSpinPoke;
981	STAMPROFILEADV StatSpinPokeFailed;
982
983	STAMCOUNTER StatInjectInterrupt;
984	STAMCOUNTER StatInjectXcpt;
985	STAMCOUNTER StatInjectPendingReflect;
986	STAMCOUNTER StatInjectPendingInterpret;
987
988	STAMCOUNTER StatExitAll;
989	STAMCOUNTER StatExitShadowNM;
990	STAMCOUNTER StatExitGuestNM;
991	STAMCOUNTER StatExitShadowPF; /*< Misleading, currently used for MMIO \#PFs as well. /
992	STAMCOUNTER StatExitShadowPFEM;
993	STAMCOUNTER StatExitGuestPF;
994	STAMCOUNTER StatExitGuestUD;
995	STAMCOUNTER StatExitGuestSS;
996	STAMCOUNTER StatExitGuestNP;
997	STAMCOUNTER StatExitGuestTS;
998	STAMCOUNTER StatExitGuestGP;
999	STAMCOUNTER StatExitGuestDE;
1000	STAMCOUNTER StatExitGuestDB;
1001	STAMCOUNTER StatExitGuestMF;
1002	STAMCOUNTER StatExitGuestBP;
1003	STAMCOUNTER StatExitGuestXF;
1004	STAMCOUNTER StatExitGuestXcpUnk;
1005	STAMCOUNTER StatExitInvlpg;
1006	STAMCOUNTER StatExitInvd;
1007	STAMCOUNTER StatExitWbinvd;
1008	STAMCOUNTER StatExitPause;
1009	STAMCOUNTER StatExitCpuid;
1010	STAMCOUNTER StatExitRdtsc;
1011	STAMCOUNTER StatExitRdtscp;
1012	STAMCOUNTER StatExitRdpmc;
1013	STAMCOUNTER StatExitVmcall;
1014	STAMCOUNTER StatExitRdrand;
1015	STAMCOUNTER StatExitCli;
1016	STAMCOUNTER StatExitSti;
1017	STAMCOUNTER StatExitPushf;
1018	STAMCOUNTER StatExitPopf;
1019	STAMCOUNTER StatExitIret;
1020	STAMCOUNTER StatExitInt;
1021	STAMCOUNTER StatExitCRxWrite[16];
1022	STAMCOUNTER StatExitCRxRead[16];
1023	STAMCOUNTER StatExitDRxWrite;
1024	STAMCOUNTER StatExitDRxRead;
1025	STAMCOUNTER StatExitRdmsr;
1026	STAMCOUNTER StatExitWrmsr;
1027	STAMCOUNTER StatExitClts;
1028	STAMCOUNTER StatExitXdtrAccess;
1029	STAMCOUNTER StatExitHlt;
1030	STAMCOUNTER StatExitMwait;
1031	STAMCOUNTER StatExitMonitor;
1032	STAMCOUNTER StatExitLmsw;
1033	STAMCOUNTER StatExitIOWrite;
1034	STAMCOUNTER StatExitIORead;
1035	STAMCOUNTER StatExitIOStringWrite;
1036	STAMCOUNTER StatExitIOStringRead;
1037	STAMCOUNTER StatExitIntWindow;
1038	STAMCOUNTER StatExitExtInt;
1039	STAMCOUNTER StatExitHostNmiInGC;
1040	STAMCOUNTER StatExitPreemptTimer;
1041	STAMCOUNTER StatExitTprBelowThreshold;
1042	STAMCOUNTER StatExitTaskSwitch;
1043	STAMCOUNTER StatExitMtf;
1044	STAMCOUNTER StatExitApicAccess;
1045	STAMCOUNTER StatPendingHostIrq;
1046
1047	STAMCOUNTER StatFlushPage;
1048	STAMCOUNTER StatFlushPageManual;
1049	STAMCOUNTER StatFlushPhysPageManual;
1050	STAMCOUNTER StatFlushTlb;
1051	STAMCOUNTER StatFlushTlbManual;
1052	STAMCOUNTER StatFlushTlbWorldSwitch;
1053	STAMCOUNTER StatNoFlushTlbWorldSwitch;
1054	STAMCOUNTER StatFlushEntire;
1055	STAMCOUNTER StatFlushAsid;
1056	STAMCOUNTER StatFlushNestedPaging;
1057	STAMCOUNTER StatFlushTlbInvlpgVirt;
1058	STAMCOUNTER StatFlushTlbInvlpgPhys;
1059	STAMCOUNTER StatTlbShootdown;
1060	STAMCOUNTER StatTlbShootdownFlush;
1061
1062	STAMCOUNTER StatSwitchTprMaskedIrq;
1063	STAMCOUNTER StatSwitchGuestIrq;
1064	STAMCOUNTER StatSwitchHmToR3FF;
1065	STAMCOUNTER StatSwitchExitToR3;
1066	STAMCOUNTER StatSwitchLongJmpToR3;
1067	STAMCOUNTER StatSwitchMaxResumeLoops;
1068	STAMCOUNTER StatSwitchHltToR3;
1069	STAMCOUNTER StatSwitchApicAccessToR3;
1070	STAMCOUNTER StatSwitchPreempt;
1071	STAMCOUNTER StatSwitchPreemptSaveHostState;
1072
1073	STAMCOUNTER StatTscParavirt;
1074	STAMCOUNTER StatTscOffset;
1075	STAMCOUNTER StatTscIntercept;
1076
1077	STAMCOUNTER StatExitReasonNpf;
1078	STAMCOUNTER StatDRxArmed;
1079	STAMCOUNTER StatDRxContextSwitch;
1080	STAMCOUNTER StatDRxIoCheck;
1081
1082	STAMCOUNTER StatLoadMinimal;
1083	STAMCOUNTER StatLoadFull;
1084
1085	STAMCOUNTER StatVmxCheckBadRmSelBase;
1086	STAMCOUNTER StatVmxCheckBadRmSelLimit;
1087	STAMCOUNTER StatVmxCheckRmOk;
1088
1089	STAMCOUNTER StatVmxCheckBadSel;
1090	STAMCOUNTER StatVmxCheckBadRpl;
1091	STAMCOUNTER StatVmxCheckBadLdt;
1092	STAMCOUNTER StatVmxCheckBadTr;
1093	STAMCOUNTER StatVmxCheckPmOk;
1094
1095	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1096	STAMCOUNTER StatFpu64SwitchBack;
1097	STAMCOUNTER StatDebug64SwitchBack;
1098	#endif
1099
1100	#ifdef VBOX_WITH_STATISTICS
1101	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1102	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1103	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1104	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1105	#endif
1106	#ifdef HM_PROFILE_EXIT_DISPATCH
1107	STAMPROFILEADV StatExitDispatch;
1108	#endif
1109	} HMCPU;
1110	/** Pointer to HM VMCPU instance data. */
1111	typedef HMCPU *PHMCPU;
1112	AssertCompileMemberAlignment(HMCPU, vmx, 8);
1113	AssertCompileMemberAlignment(HMCPU, svm, 8);
1114	AssertCompileMemberAlignment(HMCPU, Event, 8);
1115
1116	#ifdef IN_RING0
1117	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void);
1118
1119	# ifdef VBOX_STRICT
1120	VMMR0_INT_DECL(void) hmR0DumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1121	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1122	# else
1123	# define hmR0DumpRegs(a, b ,c) do { } while (0)
1124	# define hmR0DumpDescriptor(a, b, c) do { } while (0)
1125	# endif /* VBOX_STRICT */
1126
1127	# ifdef VBOX_WITH_KERNEL_USING_XMM
1128	DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1129	DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1130	# endif
1131
1132	#endif /* IN_RING0 */
1133
1134	/** @} */
1135
1136	RT_C_DECLS_END
1137
1138	#endif
1139

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 71007

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