VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 62890

Last change on this file since 62890 was 62478, checked in by vboxsync, 8 years ago

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1/* $Id: HMInternal.h 62478 2016-07-22 18:29:06Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34#include <iprt/string.h>
35
36#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
37# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
38#endif
39
40#if HC_ARCH_BITS == 64 || defined (VBOX_WITH_64_BITS_GUESTS)
41/* Enable 64 bits guest support. */
42# define VBOX_ENABLE_64_BITS_GUESTS
43#endif
44
45#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
46# define VMX_USE_CACHED_VMCS_ACCESSES
47#endif
48
49/** @def HM_PROFILE_EXIT_DISPATCH
50 * Enables profiling of the VM exit handler dispatching. */
51#if 0 || defined(DOXYGEN_RUNNING)
52# define HM_PROFILE_EXIT_DISPATCH
53#endif
54
55RT_C_DECLS_BEGIN
56
57
58/** @defgroup grp_hm_int Internal
59 * @ingroup grp_hm
60 * @internal
61 * @{
62 */
63
64/** @def HMCPU_CF_CLEAR
65 * Clears a HM-context flag.
66 *
67 * @param pVCpu The cross context virtual CPU structure.
68 * @param fFlag The flag to clear.
69 */
70#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
71
72/** @def HMCPU_CF_SET
73 * Sets a HM-context flag.
74 *
75 * @param pVCpu The cross context virtual CPU structure.
76 * @param fFlag The flag to set.
77 */
78#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
79
80/** @def HMCPU_CF_IS_SET
81 * Checks if all the flags in the specified HM-context set is pending.
82 *
83 * @param pVCpu The cross context virtual CPU structure.
84 * @param fFlag The flag to check.
85 */
86#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
87
88/** @def HMCPU_CF_IS_PENDING
89 * Checks if one or more of the flags in the specified HM-context set is
90 * pending.
91 *
92 * @param pVCpu The cross context virtual CPU structure.
93 * @param fFlags The flags to check for.
94 */
95#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
96
97/** @def HMCPU_CF_IS_PENDING_ONLY
98 * Checks if -only- one or more of the specified HM-context flags is pending.
99 *
100 * @param pVCpu The cross context virtual CPU structure.
101 * @param fFlags The flags to check for.
102 */
103#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
104
105/** @def HMCPU_CF_IS_SET_ONLY
106 * Checks if -only- all the flags in the specified HM-context set is pending.
107 *
108 * @param pVCpu The cross context virtual CPU structure.
109 * @param fFlags The flags to check for.
110 */
111#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
112
113/** @def HMCPU_CF_RESET_TO
114 * Resets the HM-context flags to the specified value.
115 *
116 * @param pVCpu The cross context virtual CPU structure.
117 * @param fFlags The new value.
118 */
119#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
120
121/** @def HMCPU_CF_VALUE
122 * Returns the current HM-context flags value.
123 *
124 * @param pVCpu The cross context virtual CPU structure.
125 */
126#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
127
128
129/** Resets/initializes the VM-exit/\#VMEXIT history array. */
130#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
131
132/** Updates the VM-exit/\#VMEXIT history array. */
133#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
134 do { \
135 AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
136 (pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
137 if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
138 (pVCpu)->hm.s.idxExitHistoryFree = 0; \
139 (pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
140 } while (0)
141
142/** Maximum number of exit reason statistics counters. */
143#define MAX_EXITREASON_STAT 0x100
144#define MASK_EXITREASON_STAT 0xff
145#define MASK_INJECT_IRQ_STAT 0xff
146
147/** @name HM changed flags.
148 * These flags are used to keep track of which important registers that
149 * have been changed since last they were reset.
150 * @{
151 */
152#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
153#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
154#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
155#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
156#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
157#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
158#define HM_CHANGED_GUEST_TR RT_BIT(6)
159#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
160#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
161#define HM_CHANGED_GUEST_RIP RT_BIT(9)
162#define HM_CHANGED_GUEST_RSP RT_BIT(10)
163#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
164#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
165#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
166#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
167#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
168#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
169#define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(17) /* Shared */
170#define HM_CHANGED_GUEST_XCPT_INTERCEPTS RT_BIT(18)
171/* VT-x specific state. */
172#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(19)
173#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(20)
174#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(21)
175#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(22)
176#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(23)
177/* AMD-V specific state. */
178#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(19)
179#define HM_CHANGED_SVM_RESERVED1 RT_BIT(20)
180#define HM_CHANGED_SVM_RESERVED2 RT_BIT(21)
181#define HM_CHANGED_SVM_RESERVED3 RT_BIT(22)
182#define HM_CHANGED_SVM_RESERVED4 RT_BIT(23)
183
184#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
185 | HM_CHANGED_GUEST_CR3 \
186 | HM_CHANGED_GUEST_CR4 \
187 | HM_CHANGED_GUEST_GDTR \
188 | HM_CHANGED_GUEST_IDTR \
189 | HM_CHANGED_GUEST_LDTR \
190 | HM_CHANGED_GUEST_TR \
191 | HM_CHANGED_GUEST_SEGMENT_REGS \
192 | HM_CHANGED_GUEST_DEBUG \
193 | HM_CHANGED_GUEST_RIP \
194 | HM_CHANGED_GUEST_RSP \
195 | HM_CHANGED_GUEST_RFLAGS \
196 | HM_CHANGED_GUEST_CR2 \
197 | HM_CHANGED_GUEST_SYSENTER_CS_MSR \
198 | HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
199 | HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_LAZY_MSRS \
202 | HM_CHANGED_GUEST_XCPT_INTERCEPTS \
203 | HM_CHANGED_VMX_GUEST_AUTO_MSRS \
204 | HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
205 | HM_CHANGED_VMX_GUEST_APIC_STATE \
206 | HM_CHANGED_VMX_ENTRY_CTLS \
207 | HM_CHANGED_VMX_EXIT_CTLS)
208
209#define HM_CHANGED_HOST_CONTEXT RT_BIT(24)
210
211/* Bits shared between host and guest. */
212#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
213 | HM_CHANGED_GUEST_DEBUG \
214 | HM_CHANGED_GUEST_LAZY_MSRS)
215/** @} */
216
217/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
218#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
219/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
220#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
221/** Total guest mapped memory needed. */
222#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
223
224
225/** @name Macros for enabling and disabling preemption.
226 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
227 * preemption has already been disabled when there is no context hook.
228 * @{ */
229#ifdef VBOX_STRICT
230# define HM_DISABLE_PREEMPT() \
231 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
232 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
233 RTThreadPreemptDisable(&PreemptStateInternal)
234#else
235# define HM_DISABLE_PREEMPT() \
236 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
237 RTThreadPreemptDisable(&PreemptStateInternal)
238#endif /* VBOX_STRICT */
239#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
240/** @} */
241
242
243/** Enable for TPR guest patching. */
244#define VBOX_HM_WITH_GUEST_PATCHING
245
246/** @name HM saved state versions
247 * @{
248 */
249#ifdef VBOX_HM_WITH_GUEST_PATCHING
250# define HM_SAVED_STATE_VERSION 5
251# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
252#else
253# define HM_SAVED_STATE_VERSION 4
254# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
255#endif
256#define HM_SAVED_STATE_VERSION_2_0_X 3
257/** @} */
258
259/**
260 * Global per-cpu information. (host)
261 */
262typedef struct HMGLOBALCPUINFO
263{
264 /** The CPU ID. */
265 RTCPUID idCpu;
266 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
267 RTR0MEMOBJ hMemObj;
268 /** The physical address of the first page in hMemObj (it's a
269 * physcially contigous allocation if it spans multiple pages). */
270 RTHCPHYS HCPhysMemObj;
271 /** The address of the memory (for pfnEnable). */
272 void *pvMemObj;
273 /** Current ASID (AMD-V) / VPID (Intel). */
274 uint32_t uCurrentAsid;
275 /** TLB flush count. */
276 uint32_t cTlbFlushes;
277 /** Whether to flush each new ASID/VPID before use. */
278 bool fFlushAsidBeforeUse;
279 /** Configured for VT-x or AMD-V. */
280 bool fConfigured;
281 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
282 bool fIgnoreAMDVInUseError;
283 /** In use by our code. (for power suspend) */
284 volatile bool fInUse;
285} HMGLOBALCPUINFO;
286/** Pointer to the per-cpu global information. */
287typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
288
289typedef enum
290{
291 HMPENDINGIO_INVALID = 0,
292 HMPENDINGIO_PORT_READ,
293 /* not implemented: HMPENDINGIO_STRING_READ, */
294 /* not implemented: HMPENDINGIO_STRING_WRITE, */
295 /** The usual 32-bit paranoia. */
296 HMPENDINGIO_32BIT_HACK = 0x7fffffff
297} HMPENDINGIO;
298
299
300typedef enum
301{
302 HMTPRINSTR_INVALID,
303 HMTPRINSTR_READ,
304 HMTPRINSTR_READ_SHR4,
305 HMTPRINSTR_WRITE_REG,
306 HMTPRINSTR_WRITE_IMM,
307 HMTPRINSTR_JUMP_REPLACEMENT,
308 /** The usual 32-bit paranoia. */
309 HMTPRINSTR_32BIT_HACK = 0x7fffffff
310} HMTPRINSTR;
311
312typedef struct
313{
314 /** The key is the address of patched instruction. (32 bits GC ptr) */
315 AVLOU32NODECORE Core;
316 /** Original opcode. */
317 uint8_t aOpcode[16];
318 /** Instruction size. */
319 uint32_t cbOp;
320 /** Replacement opcode. */
321 uint8_t aNewOpcode[16];
322 /** Replacement instruction size. */
323 uint32_t cbNewOp;
324 /** Instruction type. */
325 HMTPRINSTR enmType;
326 /** Source operand. */
327 uint32_t uSrcOperand;
328 /** Destination operand. */
329 uint32_t uDstOperand;
330 /** Number of times the instruction caused a fault. */
331 uint32_t cFaults;
332 /** Patch address of the jump replacement. */
333 RTGCPTR32 pJumpTarget;
334} HMTPRPATCH;
335/** Pointer to HMTPRPATCH. */
336typedef HMTPRPATCH *PHMTPRPATCH;
337
338
339/**
340 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
341 *
342 * @returns 64-bit key
343 * @param a_uPC The RIP + CS.BASE value of the exit.
344 * @param a_uExit The exit code.
345 * @todo Add CPL?
346 */
347#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
348
349typedef struct HMEXITINFO
350{
351 /** See HMEXITSTAT_MAKE_KEY(). */
352 uint64_t uKey;
353 /** Number of recent hits (depreciates with time). */
354 uint32_t volatile cHits;
355 /** The age + lock. */
356 uint16_t volatile uAge;
357 /** Action or action table index. */
358 uint16_t iAction;
359} HMEXITINFO;
360AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
361
362typedef struct HMEXITHISTORY
363{
364 /** The exit timestamp. */
365 uint64_t uTscExit;
366 /** The index of the corresponding HMEXITINFO entry.
367 * UINT32_MAX if none (too many collisions, race, whatever). */
368 uint32_t iExitInfo;
369 /** Figure out later, needed for padding now. */
370 uint32_t uSomeClueOrSomething;
371} HMEXITHISTORY;
372
373/**
374 * Switcher function, HC to the special 64-bit RC.
375 *
376 * @param pVM The cross context VM structure.
377 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
378 * @returns Return code indicating the action to take.
379 */
380typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
381/** Pointer to switcher function. */
382typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
383
384/**
385 * HM VM Instance data.
386 * Changes to this must checked against the padding of the hm union in VM!
387 */
388typedef struct HM
389{
390 /** Set when we've initialized VMX or SVM. */
391 bool fInitialized;
392 /** Set if nested paging is enabled. */
393 bool fNestedPaging;
394 /** Set if nested paging is allowed. */
395 bool fAllowNestedPaging;
396 /** Set if large pages are enabled (requires nested paging). */
397 bool fLargePages;
398 /** Set if we can support 64-bit guests or not. */
399 bool fAllow64BitGuests;
400 /** Set if an IO-APIC is configured for this VM. */
401 bool fHasIoApic;
402 /** Set when TPR patching is allowed. */
403 bool fTprPatchingAllowed;
404 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
405 bool fGlobalInit;
406 /** Set when TPR patching is active. */
407 bool fTPRPatchingActive;
408 /** Set when the debug facility has breakpoints/events enabled that requires
409 * us to use the debug execution loop in ring-0. */
410 bool fUseDebugLoop;
411 /** Set if hardware APIC virtualization is enabled. */
412 bool fVirtApicRegs;
413 /** Set if posted interrupt processing is enabled. */
414 bool fPostedIntrs;
415
416 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
417 uint32_t fHostKernelFeatures;
418
419 /** Maximum ASID allowed. */
420 uint32_t uMaxAsid;
421 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
422 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
423 uint32_t cMaxResumeLoops;
424
425 /** Guest allocated memory for patching purposes. */
426 RTGCPTR pGuestPatchMem;
427 /** Current free pointer inside the patch block. */
428 RTGCPTR pFreeGuestPatchMem;
429 /** Size of the guest patch memory block. */
430 uint32_t cbGuestPatchMem;
431 uint32_t u32Alignment0;
432
433#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
434 /** 32 to 64 bits switcher entrypoint. */
435 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
436 RTR0PTR pvR0Alignment0;
437#endif
438
439 struct
440 {
441 /** Set by the ring-0 side of HM to indicate VMX is supported by the
442 * CPU. */
443 bool fSupported;
444 /** Set when we've enabled VMX. */
445 bool fEnabled;
446 /** Set if VPID is supported. */
447 bool fVpid;
448 /** Set if VT-x VPID is allowed. */
449 bool fAllowVpid;
450 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
451 bool fUnrestrictedGuest;
452 /** Set if unrestricted guest execution is allowed to be used. */
453 bool fAllowUnrestricted;
454 /** Whether we're using the preemption timer or not. */
455 bool fUsePreemptTimer;
456 /** The shift mask employed by the VMX-Preemption timer. */
457 uint8_t cPreemptTimerShift;
458
459 /** Virtual address of the TSS page used for real mode emulation. */
460 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
461 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
462 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
463
464 /** Physical address of the APIC-access page. */
465 RTHCPHYS HCPhysApicAccess;
466 /** R0 memory object for the APIC-access page. */
467 RTR0MEMOBJ hMemObjApicAccess;
468 /** Virtual address of the APIC-access page. */
469 R0PTRTYPE(uint8_t *) pbApicAccess;
470
471#ifdef VBOX_WITH_CRASHDUMP_MAGIC
472 RTHCPHYS HCPhysScratch;
473 RTR0MEMOBJ hMemObjScratch;
474 R0PTRTYPE(uint8_t *) pbScratch;
475#endif
476
477 /** Internal Id of which flush-handler to use for tagged-TLB entries. */
478 uint32_t uFlushTaggedTlb;
479
480 /** Pause-loop exiting (PLE) gap in ticks. */
481 uint32_t cPleGapTicks;
482 /** Pause-loop exiting (PLE) window in ticks. */
483 uint32_t cPleWindowTicks;
484 uint32_t u32Alignment0;
485
486 /** Host CR4 value (set by ring-0 VMX init) */
487 uint64_t u64HostCr4;
488 /** Host SMM monitor control (set by ring-0 VMX init) */
489 uint64_t u64HostSmmMonitorCtl;
490 /** Host EFER value (set by ring-0 VMX init) */
491 uint64_t u64HostEfer;
492 /** Whether the CPU supports VMCS fields for swapping EFER. */
493 bool fSupportsVmcsEfer;
494 uint8_t u8Alignment2[7];
495
496 /** VMX MSR values. */
497 VMXMSRS Msrs;
498
499 /** Flush types for invept & invvpid; they depend on capabilities. */
500 VMXFLUSHEPT enmFlushEpt;
501 VMXFLUSHVPID enmFlushVpid;
502
503 /** Host-physical address for a failing VMXON instruction. */
504 RTHCPHYS HCPhysVmxEnableError;
505 } vmx;
506
507 struct
508 {
509 /** Set by the ring-0 side of HM to indicate SVM is supported by the
510 * CPU. */
511 bool fSupported;
512 /** Set when we've enabled SVM. */
513 bool fEnabled;
514 /** Set if erratum 170 affects the AMD cpu. */
515 bool fAlwaysFlushTLB;
516 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
517 bool fIgnoreInUseError;
518 uint8_t u8Alignment0[4];
519
520 /** Physical address of the IO bitmap (12kb). */
521 RTHCPHYS HCPhysIOBitmap;
522 /** R0 memory object for the IO bitmap (12kb). */
523 RTR0MEMOBJ hMemObjIOBitmap;
524 /** Virtual address of the IO bitmap. */
525 R0PTRTYPE(void *) pvIOBitmap;
526
527 /* HWCR MSR (for diagnostics) */
528 uint64_t u64MsrHwcr;
529
530 /** SVM revision. */
531 uint32_t u32Rev;
532 /** SVM feature bits from cpuid 0x8000000a */
533 uint32_t u32Features;
534
535 /** Pause filter counter. */
536 uint16_t cPauseFilter;
537 /** Pause filter treshold in ticks. */
538 uint16_t cPauseFilterThresholdTicks;
539 uint32_t u32Alignment0;
540 } svm;
541
542 /**
543 * AVL tree with all patches (active or disabled) sorted by guest instruction
544 * address.
545 */
546 AVLOU32TREE PatchTree;
547 uint32_t cPatches;
548 HMTPRPATCH aPatches[64];
549
550 struct
551 {
552 uint32_t u32AMDFeatureECX;
553 uint32_t u32AMDFeatureEDX;
554 } cpuid;
555
556 /** Saved error from detection */
557 int32_t lLastError;
558
559 /** HMR0Init was run */
560 bool fHMR0Init;
561 bool u8Alignment1[3];
562
563 STAMCOUNTER StatTprPatchSuccess;
564 STAMCOUNTER StatTprPatchFailure;
565 STAMCOUNTER StatTprReplaceSuccessCr8;
566 STAMCOUNTER StatTprReplaceSuccessVmc;
567 STAMCOUNTER StatTprReplaceFailure;
568} HM;
569/** Pointer to HM VM instance data. */
570typedef HM *PHM;
571
572AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
573
574/* Maximum number of cached entries. */
575#define VMCSCACHE_MAX_ENTRY 128
576
577/**
578 * Structure for storing read and write VMCS actions.
579 */
580typedef struct VMCSCACHE
581{
582#ifdef VBOX_WITH_CRASHDUMP_MAGIC
583 /* Magic marker for searching in crash dumps. */
584 uint8_t aMagic[16];
585 uint64_t uMagic;
586 uint64_t u64TimeEntry;
587 uint64_t u64TimeSwitch;
588 uint64_t cResume;
589 uint64_t interPD;
590 uint64_t pSwitcher;
591 uint32_t uPos;
592 uint32_t idCpu;
593#endif
594 /* CR2 is saved here for EPT syncing. */
595 uint64_t cr2;
596 struct
597 {
598 uint32_t cValidEntries;
599 uint32_t uAlignment;
600 uint32_t aField[VMCSCACHE_MAX_ENTRY];
601 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
602 } Write;
603 struct
604 {
605 uint32_t cValidEntries;
606 uint32_t uAlignment;
607 uint32_t aField[VMCSCACHE_MAX_ENTRY];
608 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
609 } Read;
610#ifdef VBOX_STRICT
611 struct
612 {
613 RTHCPHYS HCPhysCpuPage;
614 RTHCPHYS HCPhysVmcs;
615 RTGCPTR pCache;
616 RTGCPTR pCtx;
617 } TestIn;
618 struct
619 {
620 RTHCPHYS HCPhysVmcs;
621 RTGCPTR pCache;
622 RTGCPTR pCtx;
623 uint64_t eflags;
624 uint64_t cr8;
625 } TestOut;
626 struct
627 {
628 uint64_t param1;
629 uint64_t param2;
630 uint64_t param3;
631 uint64_t param4;
632 } ScratchPad;
633#endif
634} VMCSCACHE;
635/** Pointer to VMCSCACHE. */
636typedef VMCSCACHE *PVMCSCACHE;
637AssertCompileSizeAlignment(VMCSCACHE, 8);
638
639/**
640 * VMX StartVM function.
641 *
642 * @returns VBox status code (no informational stuff).
643 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
644 * @param pCtx The CPU register context.
645 * @param pCache The VMCS cache.
646 * @param pVM Pointer to the cross context VM structure.
647 * @param pVCpu Pointer to the cross context per-CPU structure.
648 */
649typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
650/** Pointer to a VMX StartVM function. */
651typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
652
653/** SVM VMRun function. */
654typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
655/** Pointer to a SVM VMRun function. */
656typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
657
658/**
659 * HM VMCPU Instance data.
660 *
661 * Note! If you change members of this struct, make sure to check if the
662 * assembly counterpart in HMInternal.mac needs to be updated as well.
663 */
664typedef struct HMCPU
665{
666 /** Set if we need to flush the TLB during the world switch. */
667 bool fForceTLBFlush;
668 /** Set when we're using VT-x or AMD-V at that moment. */
669 bool fActive;
670 /** Set when the TLB has been checked until we return from the world switch. */
671 volatile bool fCheckedTLBFlush;
672 /** Whether we've completed the inner HM leave function. */
673 bool fLeaveDone;
674 /** Whether we're using the hyper DR7 or guest DR7. */
675 bool fUsingHyperDR7;
676 /** Whether to preload the guest-FPU state to avoid \#NM VM-exit overhead. */
677 bool fPreloadGuestFpu;
678 /** Set if XCR0 needs to be loaded and saved when entering and exiting guest
679 * code execution. */
680 bool fLoadSaveGuestXcr0;
681
682 /** Whether we should use the debug loop because of single stepping or special
683 * debug breakpoints / events are armed. */
684 bool fUseDebugLoop;
685 /** Whether we are currently executing in the debug loop.
686 * Mainly for assertions. */
687 bool fUsingDebugLoop;
688 /** Set if we using the debug loop and wish to intercept RDTSC. */
689 bool fDebugWantRdTscExit;
690 /** Whether we're executing a single instruction. */
691 bool fSingleInstruction;
692 /** Set if we need to clear the trap flag because of single stepping. */
693 bool fClearTrapFlag;
694
695 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
696 bool fGIMTrapXcptUD;
697 /** Whether paravirt. hypercalls are enabled. */
698 bool fHypercallsEnabled;
699 uint8_t u8Alignment0[2];
700
701 /** World switch exit counter. */
702 volatile uint32_t cWorldSwitchExits;
703 /** HM_CHANGED_* flags. */
704 volatile uint32_t fContextUseFlags;
705 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
706 * time). */
707 RTCPUID idLastCpu;
708 /** TLB flush count. */
709 uint32_t cTlbFlushes;
710 /** Current ASID in use by the VM. */
711 uint32_t uCurrentAsid;
712 /** An additional error code used for some gurus. */
713 uint32_t u32HMError;
714 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
715 uint64_t u64HostTscAux;
716
717 struct
718 {
719 /** Ring 0 handlers for VT-x. */
720 PFNHMVMXSTARTVM pfnStartVM;
721#if HC_ARCH_BITS == 32
722 uint32_t u32Alignment0;
723#endif
724 /** Current VMX_VMCS32_CTRL_PIN_EXEC. */
725 uint32_t u32PinCtls;
726 /** Current VMX_VMCS32_CTRL_PROC_EXEC. */
727 uint32_t u32ProcCtls;
728 /** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
729 uint32_t u32ProcCtls2;
730 /** Current VMX_VMCS32_CTRL_EXIT. */
731 uint32_t u32ExitCtls;
732 /** Current VMX_VMCS32_CTRL_ENTRY. */
733 uint32_t u32EntryCtls;
734
735 /** Current CR0 mask. */
736 uint32_t u32CR0Mask;
737 /** Current CR4 mask. */
738 uint32_t u32CR4Mask;
739 /** Current exception bitmap. */
740 uint32_t u32XcptBitmap;
741 /** The updated-guest-state mask. */
742 volatile uint32_t fUpdatedGuestState;
743 uint32_t u32Alignment1;
744
745 /** Physical address of the VM control structure (VMCS). */
746 RTHCPHYS HCPhysVmcs;
747 /** R0 memory object for the VM control structure (VMCS). */
748 RTR0MEMOBJ hMemObjVmcs;
749 /** Virtual address of the VM control structure (VMCS). */
750 R0PTRTYPE(void *) pvVmcs;
751
752 /** Physical address of the virtual APIC page for TPR caching. */
753 RTHCPHYS HCPhysVirtApic;
754 /** R0 memory object for the virtual APIC page for TPR caching. */
755 RTR0MEMOBJ hMemObjVirtApic;
756 /** Virtual address of the virtual APIC page for TPR caching. */
757 R0PTRTYPE(uint8_t *) pbVirtApic;
758
759 /** Physical address of the MSR bitmap. */
760 RTHCPHYS HCPhysMsrBitmap;
761 /** R0 memory object for the MSR bitmap. */
762 RTR0MEMOBJ hMemObjMsrBitmap;
763 /** Virtual address of the MSR bitmap. */
764 R0PTRTYPE(void *) pvMsrBitmap;
765
766 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
767 * for guest MSRs). */
768 RTHCPHYS HCPhysGuestMsr;
769 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
770 * (used for guest MSRs). */
771 RTR0MEMOBJ hMemObjGuestMsr;
772 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
773 * for guest MSRs). */
774 R0PTRTYPE(void *) pvGuestMsr;
775
776 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
777 RTHCPHYS HCPhysHostMsr;
778 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
779 RTR0MEMOBJ hMemObjHostMsr;
780 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
781 R0PTRTYPE(void *) pvHostMsr;
782
783 /** Current EPTP. */
784 RTHCPHYS HCPhysEPTP;
785
786 /** Number of guest/host MSR pairs in the auto-load/store area. */
787 uint32_t cMsrs;
788 /** Whether the host MSR values are up-to-date in the auto-load/store area. */
789 bool fUpdatedHostMsrs;
790 uint8_t u8Alignment0[3];
791
792 /** Host LSTAR MSR value to restore lazily while leaving VT-x. */
793 uint64_t u64HostLStarMsr;
794 /** Host STAR MSR value to restore lazily while leaving VT-x. */
795 uint64_t u64HostStarMsr;
796 /** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
797 uint64_t u64HostSFMaskMsr;
798 /** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
799 uint64_t u64HostKernelGSBaseMsr;
800 /** A mask of which MSRs have been swapped and need restoration. */
801 uint32_t fLazyMsrs;
802 uint32_t u32Alignment2;
803
804 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
805 uint64_t u64MsrApicBase;
806 /** Last use TSC offset value. (cached) */
807 uint64_t u64TSCOffset;
808
809 /** VMCS cache. */
810 VMCSCACHE VMCSCache;
811
812 /** Real-mode emulation state. */
813 struct
814 {
815 X86DESCATTR AttrCS;
816 X86DESCATTR AttrDS;
817 X86DESCATTR AttrES;
818 X86DESCATTR AttrFS;
819 X86DESCATTR AttrGS;
820 X86DESCATTR AttrSS;
821 X86EFLAGS Eflags;
822 uint32_t fRealOnV86Active;
823 } RealMode;
824
825 /** VT-x error-reporting (mainly for ring-3 propagation). */
826 struct
827 {
828 uint64_t u64VMCSPhys;
829 uint32_t u32VMCSRevision;
830 uint32_t u32InstrError;
831 uint32_t u32ExitReason;
832 RTCPUID idEnteredCpu;
833 RTCPUID idCurrentCpu;
834 uint32_t u32Alignment0;
835 } LastError;
836
837 /** Current state of the VMCS. */
838 uint32_t uVmcsState;
839 /** Which host-state bits to restore before being preempted. */
840 uint32_t fRestoreHostFlags;
841 /** The host-state restoration structure. */
842 VMXRESTOREHOST RestoreHost;
843
844 /** Set if guest was executing in real mode (extra checks). */
845 bool fWasInRealMode;
846 /** Set if guest switched to 64-bit mode on a 32-bit host. */
847 bool fSwitchedTo64on32;
848
849 uint8_t u8Alignment1[6];
850 } vmx;
851
852 struct
853 {
854 /** Ring 0 handlers for VT-x. */
855 PFNHMSVMVMRUN pfnVMRun;
856#if HC_ARCH_BITS == 32
857 uint32_t u32Alignment0;
858#endif
859
860 /** Physical address of the host VMCB which holds additional host-state. */
861 RTHCPHYS HCPhysVmcbHost;
862 /** R0 memory object for the host VMCB which holds additional host-state. */
863 RTR0MEMOBJ hMemObjVmcbHost;
864 /** Virtual address of the host VMCB which holds additional host-state. */
865 R0PTRTYPE(void *) pvVmcbHost;
866
867 /** Physical address of the guest VMCB. */
868 RTHCPHYS HCPhysVmcb;
869 /** R0 memory object for the guest VMCB. */
870 RTR0MEMOBJ hMemObjVmcb;
871 /** Virtual address of the guest VMCB. */
872 R0PTRTYPE(void *) pvVmcb;
873
874 /** Physical address of the MSR bitmap (8 KB). */
875 RTHCPHYS HCPhysMsrBitmap;
876 /** R0 memory object for the MSR bitmap (8 KB). */
877 RTR0MEMOBJ hMemObjMsrBitmap;
878 /** Virtual address of the MSR bitmap. */
879 R0PTRTYPE(void *) pvMsrBitmap;
880
881 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
882 * we should check if the VTPR changed on every VM-exit. */
883 bool fSyncVTpr;
884 uint8_t u8Alignment0[7];
885 } svm;
886
887 /** Event injection state. */
888 struct
889 {
890 uint32_t fPending;
891 uint32_t u32ErrCode;
892 uint32_t cbInstr;
893 uint32_t u32Padding; /**< Explicit alignment padding. */
894 uint64_t u64IntInfo;
895 RTGCUINTPTR GCPtrFaultAddress;
896 } Event;
897
898 /** IO Block emulation state. */
899 struct
900 {
901 bool fEnabled;
902 uint8_t u8Align[7];
903
904 /** RIP at the start of the io code we wish to emulate in the recompiler. */
905 RTGCPTR GCPtrFunctionEip;
906
907 uint64_t cr0;
908 } EmulateIoBlock;
909
910 /* */
911 struct
912 {
913 /** Pending IO operation type. */
914 HMPENDINGIO enmType;
915 uint32_t u32Alignment0;
916 RTGCPTR GCPtrRip;
917 RTGCPTR GCPtrRipNext;
918 union
919 {
920 struct
921 {
922 uint32_t uPort;
923 uint32_t uAndVal;
924 uint32_t cbSize;
925 } Port;
926 uint64_t aRaw[2];
927 } s;
928 } PendingIO;
929
930 /** The PAE PDPEs used with Nested Paging (only valid when
931 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
932 X86PDPE aPdpes[4];
933
934 /** Current shadow paging mode. */
935 PGMMODE enmShadowMode;
936
937 /** The CPU ID of the CPU currently owning the VMCS. Set in
938 * HMR0Enter and cleared in HMR0Leave. */
939 RTCPUID idEnteredCpu;
940
941 /** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
942 uint16_t auExitHistory[31];
943 /** The index of the next free slot in the history array. */
944 uint16_t idxExitHistoryFree;
945
946 /** For saving stack space, the disassembler state is allocated here instead of
947 * on the stack. */
948 DISCPUSTATE DisState;
949
950 STAMPROFILEADV StatEntry;
951 STAMPROFILEADV StatExit1;
952 STAMPROFILEADV StatExit2;
953 STAMPROFILEADV StatExitIO;
954 STAMPROFILEADV StatExitMovCRx;
955 STAMPROFILEADV StatExitXcptNmi;
956 STAMPROFILEADV StatLoadGuestState;
957 STAMPROFILEADV StatInGC;
958
959#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
960 STAMPROFILEADV StatWorldSwitch3264;
961#endif
962 STAMPROFILEADV StatPoke;
963 STAMPROFILEADV StatSpinPoke;
964 STAMPROFILEADV StatSpinPokeFailed;
965
966 STAMCOUNTER StatInjectInterrupt;
967 STAMCOUNTER StatInjectXcpt;
968 STAMCOUNTER StatInjectPendingReflect;
969 STAMCOUNTER StatInjectPendingInterpret;
970
971 STAMCOUNTER StatExitAll;
972 STAMCOUNTER StatExitShadowNM;
973 STAMCOUNTER StatExitGuestNM;
974 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
975 STAMCOUNTER StatExitShadowPFEM;
976 STAMCOUNTER StatExitGuestPF;
977 STAMCOUNTER StatExitGuestUD;
978 STAMCOUNTER StatExitGuestSS;
979 STAMCOUNTER StatExitGuestNP;
980 STAMCOUNTER StatExitGuestTS;
981 STAMCOUNTER StatExitGuestGP;
982 STAMCOUNTER StatExitGuestDE;
983 STAMCOUNTER StatExitGuestDB;
984 STAMCOUNTER StatExitGuestMF;
985 STAMCOUNTER StatExitGuestBP;
986 STAMCOUNTER StatExitGuestXF;
987 STAMCOUNTER StatExitGuestXcpUnk;
988 STAMCOUNTER StatExitInvlpg;
989 STAMCOUNTER StatExitInvd;
990 STAMCOUNTER StatExitWbinvd;
991 STAMCOUNTER StatExitPause;
992 STAMCOUNTER StatExitCpuid;
993 STAMCOUNTER StatExitRdtsc;
994 STAMCOUNTER StatExitRdtscp;
995 STAMCOUNTER StatExitRdpmc;
996 STAMCOUNTER StatExitVmcall;
997 STAMCOUNTER StatExitRdrand;
998 STAMCOUNTER StatExitCli;
999 STAMCOUNTER StatExitSti;
1000 STAMCOUNTER StatExitPushf;
1001 STAMCOUNTER StatExitPopf;
1002 STAMCOUNTER StatExitIret;
1003 STAMCOUNTER StatExitInt;
1004 STAMCOUNTER StatExitCRxWrite[16];
1005 STAMCOUNTER StatExitCRxRead[16];
1006 STAMCOUNTER StatExitDRxWrite;
1007 STAMCOUNTER StatExitDRxRead;
1008 STAMCOUNTER StatExitRdmsr;
1009 STAMCOUNTER StatExitWrmsr;
1010 STAMCOUNTER StatExitClts;
1011 STAMCOUNTER StatExitXdtrAccess;
1012 STAMCOUNTER StatExitHlt;
1013 STAMCOUNTER StatExitMwait;
1014 STAMCOUNTER StatExitMonitor;
1015 STAMCOUNTER StatExitLmsw;
1016 STAMCOUNTER StatExitIOWrite;
1017 STAMCOUNTER StatExitIORead;
1018 STAMCOUNTER StatExitIOStringWrite;
1019 STAMCOUNTER StatExitIOStringRead;
1020 STAMCOUNTER StatExitIntWindow;
1021 STAMCOUNTER StatExitExtInt;
1022 STAMCOUNTER StatExitHostNmiInGC;
1023 STAMCOUNTER StatExitPreemptTimer;
1024 STAMCOUNTER StatExitTprBelowThreshold;
1025 STAMCOUNTER StatExitTaskSwitch;
1026 STAMCOUNTER StatExitMtf;
1027 STAMCOUNTER StatExitApicAccess;
1028 STAMCOUNTER StatPendingHostIrq;
1029
1030 STAMCOUNTER StatFlushPage;
1031 STAMCOUNTER StatFlushPageManual;
1032 STAMCOUNTER StatFlushPhysPageManual;
1033 STAMCOUNTER StatFlushTlb;
1034 STAMCOUNTER StatFlushTlbManual;
1035 STAMCOUNTER StatFlushTlbWorldSwitch;
1036 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1037 STAMCOUNTER StatFlushEntire;
1038 STAMCOUNTER StatFlushAsid;
1039 STAMCOUNTER StatFlushNestedPaging;
1040 STAMCOUNTER StatFlushTlbInvlpgVirt;
1041 STAMCOUNTER StatFlushTlbInvlpgPhys;
1042 STAMCOUNTER StatTlbShootdown;
1043 STAMCOUNTER StatTlbShootdownFlush;
1044
1045 STAMCOUNTER StatSwitchTprMaskedIrq;
1046 STAMCOUNTER StatSwitchGuestIrq;
1047 STAMCOUNTER StatSwitchHmToR3FF;
1048 STAMCOUNTER StatSwitchExitToR3;
1049 STAMCOUNTER StatSwitchLongJmpToR3;
1050 STAMCOUNTER StatSwitchMaxResumeLoops;
1051 STAMCOUNTER StatSwitchHltToR3;
1052 STAMCOUNTER StatSwitchApicAccessToR3;
1053 STAMCOUNTER StatSwitchPreempt;
1054 STAMCOUNTER StatSwitchPreemptSaveHostState;
1055
1056 STAMCOUNTER StatTscParavirt;
1057 STAMCOUNTER StatTscOffset;
1058 STAMCOUNTER StatTscIntercept;
1059
1060 STAMCOUNTER StatExitReasonNpf;
1061 STAMCOUNTER StatDRxArmed;
1062 STAMCOUNTER StatDRxContextSwitch;
1063 STAMCOUNTER StatDRxIoCheck;
1064
1065 STAMCOUNTER StatLoadMinimal;
1066 STAMCOUNTER StatLoadFull;
1067
1068 STAMCOUNTER StatVmxCheckBadRmSelBase;
1069 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1070 STAMCOUNTER StatVmxCheckRmOk;
1071
1072 STAMCOUNTER StatVmxCheckBadSel;
1073 STAMCOUNTER StatVmxCheckBadRpl;
1074 STAMCOUNTER StatVmxCheckBadLdt;
1075 STAMCOUNTER StatVmxCheckBadTr;
1076 STAMCOUNTER StatVmxCheckPmOk;
1077
1078#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1079 STAMCOUNTER StatFpu64SwitchBack;
1080 STAMCOUNTER StatDebug64SwitchBack;
1081#endif
1082
1083#ifdef VBOX_WITH_STATISTICS
1084 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1085 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1086 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1087 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1088#endif
1089#ifdef HM_PROFILE_EXIT_DISPATCH
1090 STAMPROFILEADV StatExitDispatch;
1091#endif
1092} HMCPU;
1093/** Pointer to HM VMCPU instance data. */
1094typedef HMCPU *PHMCPU;
1095AssertCompileMemberAlignment(HMCPU, vmx, 8);
1096AssertCompileMemberAlignment(HMCPU, svm, 8);
1097AssertCompileMemberAlignment(HMCPU, Event, 8);
1098
1099
1100#ifdef IN_RING0
1101/** @todo r=bird: s/[[:space:]]HM/ hm/ - internal functions starts with a
1102 * lower cased prefix. HMInternal.h is an internal header, so
1103 * everything here must be internal. */
1104VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void);
1105VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
1106
1107
1108# ifdef VBOX_STRICT
1109VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1110VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1111# else
1112# define HMDumpRegs(a, b ,c) do { } while (0)
1113# define HMR0DumpDescriptor(a, b, c) do { } while (0)
1114# endif /* VBOX_STRICT */
1115
1116# ifdef VBOX_WITH_KERNEL_USING_XMM
1117DECLASM(int) HMR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1118DECLASM(int) HMR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1119# endif
1120
1121#endif /* IN_RING0 */
1122
1123/** @} */
1124
1125RT_C_DECLS_END
1126
1127#endif
1128
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