HMInternal.h@ 58912

Last change on this file since 58912 was 58912, checked in by vboxsync, 9 years ago
HMGLOBALCPUINFO: Cache the RTR0MemObjGetPagePhysAddr and RTR0MemObjAddress results as they aren't necessiarly all that fast.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 41.5 KB

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1	/* $Id: HMInternal.h 58912 2015-11-29 20:08:14Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/pgm.h>
29	#include <VBox/vmm/cpum.h>
30	#include <iprt/memobj.h>
31	#include <iprt/cpuset.h>
32	#include <iprt/mp.h>
33	#include <iprt/avl.h>
34	#include <iprt/string.h>
35
36	#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
37	# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
38	#endif
39
40	#if HC_ARCH_BITS == 64 \|\| defined (VBOX_WITH_64_BITS_GUESTS)
41	/* Enable 64 bits guest support. */
42	# define VBOX_ENABLE_64_BITS_GUESTS
43	#endif
44
45	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
46	# define VMX_USE_CACHED_VMCS_ACCESSES
47	#endif
48
49	/** @def HM_PROFILE_EXIT_DISPATCH
50	* Enables profiling of the VM exit handler dispatching. */
51	#if 0 \|\| defined(DOXYGEN_RUNNING)
52	# define HM_PROFILE_EXIT_DISPATCH
53	#endif
54
55	RT_C_DECLS_BEGIN
56
57
58	/** @defgroup grp_hm_int Internal
59	* @ingroup grp_hm
60	* @internal
61	* @{
62	*/
63
64	/** @def HMCPU_CF_CLEAR
65	* Clears a HM-context flag.
66	*
67	* @param pVCpu The cross context virtual CPU structure.
68	* @param fFlag The flag to clear.
69	*/
70	#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
71
72	/** @def HMCPU_CF_SET
73	* Sets a HM-context flag.
74	*
75	* @param pVCpu The cross context virtual CPU structure.
76	* @param fFlag The flag to set.
77	*/
78	#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
79
80	/** @def HMCPU_CF_IS_SET
81	* Checks if all the flags in the specified HM-context set is pending.
82	*
83	* @param pVCpu The cross context virtual CPU structure.
84	* @param fFlag The flag to check.
85	*/
86	#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
87
88	/** @def HMCPU_CF_IS_PENDING
89	* Checks if one or more of the flags in the specified HM-context set is
90	* pending.
91	*
92	* @param pVCpu The cross context virtual CPU structure.
93	* @param fFlags The flags to check for.
94	*/
95	#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
96
97	/** @def HMCPU_CF_IS_PENDING_ONLY
98	* Checks if -only- one or more of the specified HM-context flags is pending.
99	*
100	* @param pVCpu The cross context virtual CPU structure.
101	* @param fFlags The flags to check for.
102	*/
103	#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
104
105	/** @def HMCPU_CF_IS_SET_ONLY
106	* Checks if -only- all the flags in the specified HM-context set is pending.
107	*
108	* @param pVCpu The cross context virtual CPU structure.
109	* @param fFlags The flags to check for.
110	*/
111	#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
112
113	/** @def HMCPU_CF_RESET_TO
114	* Resets the HM-context flags to the specified value.
115	*
116	* @param pVCpu The cross context virtual CPU structure.
117	* @param fFlags The new value.
118	*/
119	#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
120
121	/** @def HMCPU_CF_VALUE
122	* Returns the current HM-context flags value.
123	*
124	* @param pVCpu The cross context virtual CPU structure.
125	*/
126	#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
127
128
129	/** Resets/initializes the VM-exit/\#VMEXIT history array. */
130	#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
131
132	/** Updates the VM-exit/\#VMEXIT history array. */
133	#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
134	do { \
135	AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
136	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
137	if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
138	(pVCpu)->hm.s.idxExitHistoryFree = 0; \
139	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
140	} while (0)
141
142	/** Maximum number of exit reason statistics counters. */
143	#define MAX_EXITREASON_STAT 0x100
144	#define MASK_EXITREASON_STAT 0xff
145	#define MASK_INJECT_IRQ_STAT 0xff
146
147	/** @name HM changed flags.
148	* These flags are used to keep track of which important registers that
149	* have been changed since last they were reset.
150	* @{
151	*/
152	#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
153	#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
154	#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
155	#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
156	#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
157	#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
158	#define HM_CHANGED_GUEST_TR RT_BIT(6)
159	#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
160	#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
161	#define HM_CHANGED_GUEST_RIP RT_BIT(9)
162	#define HM_CHANGED_GUEST_RSP RT_BIT(10)
163	#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
164	#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
165	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
166	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
167	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
168	#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
169	#define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(17) /* Shared */
170	#define HM_CHANGED_GUEST_XCPT_INTERCEPTS RT_BIT(18)
171	/* VT-x specific state. */
172	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(19)
173	#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(20)
174	#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(21)
175	#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(22)
176	#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(23)
177	/* AMD-V specific state. */
178	#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(19)
179	#define HM_CHANGED_SVM_RESERVED1 RT_BIT(20)
180	#define HM_CHANGED_SVM_RESERVED2 RT_BIT(21)
181	#define HM_CHANGED_SVM_RESERVED3 RT_BIT(22)
182	#define HM_CHANGED_SVM_RESERVED4 RT_BIT(23)
183
184	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
185	\| HM_CHANGED_GUEST_CR3 \
186	\| HM_CHANGED_GUEST_CR4 \
187	\| HM_CHANGED_GUEST_GDTR \
188	\| HM_CHANGED_GUEST_IDTR \
189	\| HM_CHANGED_GUEST_LDTR \
190	\| HM_CHANGED_GUEST_TR \
191	\| HM_CHANGED_GUEST_SEGMENT_REGS \
192	\| HM_CHANGED_GUEST_DEBUG \
193	\| HM_CHANGED_GUEST_RIP \
194	\| HM_CHANGED_GUEST_RSP \
195	\| HM_CHANGED_GUEST_RFLAGS \
196	\| HM_CHANGED_GUEST_CR2 \
197	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR \
198	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
199	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
200	\| HM_CHANGED_GUEST_EFER_MSR \
201	\| HM_CHANGED_GUEST_LAZY_MSRS \
202	\| HM_CHANGED_GUEST_XCPT_INTERCEPTS \
203	\| HM_CHANGED_VMX_GUEST_AUTO_MSRS \
204	\| HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
205	\| HM_CHANGED_VMX_GUEST_APIC_STATE \
206	\| HM_CHANGED_VMX_ENTRY_CTLS \
207	\| HM_CHANGED_VMX_EXIT_CTLS)
208
209	#define HM_CHANGED_HOST_CONTEXT RT_BIT(24)
210
211	/* Bits shared between host and guest. */
212	#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
213	\| HM_CHANGED_GUEST_DEBUG \
214	\| HM_CHANGED_GUEST_LAZY_MSRS)
215	/** @} */
216
217	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
218	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
219	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
220	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
221	/** Total guest mapped memory needed. */
222	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
223
224
225	/** @name Macros for enabling and disabling preemption.
226	* These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
227	* preemption has already been disabled when there is no context hook.
228	* @{ */
229	#ifdef VBOX_STRICT
230	# define HM_DISABLE_PREEMPT() \
231	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
232	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) \|\| VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
233	RTThreadPreemptDisable(&PreemptStateInternal)
234	#else
235	# define HM_DISABLE_PREEMPT() \
236	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
237	RTThreadPreemptDisable(&PreemptStateInternal)
238	#endif /* VBOX_STRICT */
239	#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
240	/** @} */
241
242
243	/** Enable for TPR guest patching. */
244	#define VBOX_HM_WITH_GUEST_PATCHING
245
246	/** @name HM saved state versions
247	* @{
248	*/
249	#ifdef VBOX_HM_WITH_GUEST_PATCHING
250	# define HM_SAVED_STATE_VERSION 5
251	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
252	#else
253	# define HM_SAVED_STATE_VERSION 4
254	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
255	#endif
256	#define HM_SAVED_STATE_VERSION_2_0_X 3
257	/** @} */
258
259	/**
260	* Global per-cpu information. (host)
261	*/
262	typedef struct HMGLOBALCPUINFO
263	{
264	/** The CPU ID. */
265	RTCPUID idCpu;
266	/** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
267	RTR0MEMOBJ hMemObj;
268	/** The physical address of the first page in hMemObj (it's a
269	* physcially contigous allocation if it spans multiple pages). */
270	RTHCPHYS HCPhysMemObj;
271	/** The address of the memory (for pfnEnable). */
272	void *pvMemObj;
273	/** Current ASID (AMD-V) / VPID (Intel). */
274	uint32_t uCurrentAsid;
275	/** TLB flush count. */
276	uint32_t cTlbFlushes;
277	/** Whether to flush each new ASID/VPID before use. */
278	bool fFlushAsidBeforeUse;
279	/** Configured for VT-x or AMD-V. */
280	bool fConfigured;
281	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
282	bool fIgnoreAMDVInUseError;
283	/** In use by our code. (for power suspend) */
284	volatile bool fInUse;
285	} HMGLOBALCPUINFO;
286	/** Pointer to the per-cpu global information. */
287	typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
288
289	typedef enum
290	{
291	HMPENDINGIO_INVALID = 0,
292	HMPENDINGIO_PORT_READ,
293	HMPENDINGIO_PORT_WRITE,
294	HMPENDINGIO_STRING_READ,
295	HMPENDINGIO_STRING_WRITE,
296	/** The usual 32-bit paranoia. */
297	HMPENDINGIO_32BIT_HACK = 0x7fffffff
298	} HMPENDINGIO;
299
300
301	typedef enum
302	{
303	HMTPRINSTR_INVALID,
304	HMTPRINSTR_READ,
305	HMTPRINSTR_READ_SHR4,
306	HMTPRINSTR_WRITE_REG,
307	HMTPRINSTR_WRITE_IMM,
308	HMTPRINSTR_JUMP_REPLACEMENT,
309	/** The usual 32-bit paranoia. */
310	HMTPRINSTR_32BIT_HACK = 0x7fffffff
311	} HMTPRINSTR;
312
313	typedef struct
314	{
315	/** The key is the address of patched instruction. (32 bits GC ptr) */
316	AVLOU32NODECORE Core;
317	/** Original opcode. */
318	uint8_t aOpcode[16];
319	/** Instruction size. */
320	uint32_t cbOp;
321	/** Replacement opcode. */
322	uint8_t aNewOpcode[16];
323	/** Replacement instruction size. */
324	uint32_t cbNewOp;
325	/** Instruction type. */
326	HMTPRINSTR enmType;
327	/** Source operand. */
328	uint32_t uSrcOperand;
329	/** Destination operand. */
330	uint32_t uDstOperand;
331	/** Number of times the instruction caused a fault. */
332	uint32_t cFaults;
333	/** Patch address of the jump replacement. */
334	RTGCPTR32 pJumpTarget;
335	} HMTPRPATCH;
336	/** Pointer to HMTPRPATCH. */
337	typedef HMTPRPATCH *PHMTPRPATCH;
338
339	/**
340	* Switcher function, HC to the special 64-bit RC.
341	*
342	* @param pVM The cross context VM structure.
343	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
344	* @returns Return code indicating the action to take.
345	*/
346	typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
347	/** Pointer to switcher function. */
348	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
349
350	/**
351	* HM VM Instance data.
352	* Changes to this must checked against the padding of the hm union in VM!
353	*/
354	typedef struct HM
355	{
356	/** Set when we've initialized VMX or SVM. */
357	bool fInitialized;
358	/** Set if nested paging is enabled. */
359	bool fNestedPaging;
360	/** Set if nested paging is allowed. */
361	bool fAllowNestedPaging;
362	/** Set if large pages are enabled (requires nested paging). */
363	bool fLargePages;
364	/** Set if we can support 64-bit guests or not. */
365	bool fAllow64BitGuests;
366	/** Set if an IO-APIC is configured for this VM. */
367	bool fHasIoApic;
368	/** Set when TPR patching is allowed. */
369	bool fTprPatchingAllowed;
370	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
371	bool fGlobalInit;
372	/** Set when TPR patching is active. */
373	bool fTPRPatchingActive;
374	bool u8Alignment[3];
375
376	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
377	uint32_t fHostKernelFeatures;
378
379	/** Maximum ASID allowed. */
380	uint32_t uMaxAsid;
381	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
382	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
383	uint32_t cMaxResumeLoops;
384
385	/** Guest allocated memory for patching purposes. */
386	RTGCPTR pGuestPatchMem;
387	/** Current free pointer inside the patch block. */
388	RTGCPTR pFreeGuestPatchMem;
389	/** Size of the guest patch memory block. */
390	uint32_t cbGuestPatchMem;
391	uint32_t u32Alignment0;
392
393	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
394	/** 32 to 64 bits switcher entrypoint. */
395	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
396	RTR0PTR pvR0Alignment0;
397	#endif
398
399	struct
400	{
401	/** Set by the ring-0 side of HM to indicate VMX is supported by the
402	* CPU. */
403	bool fSupported;
404	/** Set when we've enabled VMX. */
405	bool fEnabled;
406	/** Set if VPID is supported. */
407	bool fVpid;
408	/** Set if VT-x VPID is allowed. */
409	bool fAllowVpid;
410	/** Set if unrestricted guest execution is in use (real and protected mode without paging). */
411	bool fUnrestrictedGuest;
412	/** Set if unrestricted guest execution is allowed to be used. */
413	bool fAllowUnrestricted;
414	/** Whether we're using the preemption timer or not. */
415	bool fUsePreemptTimer;
416	/** The shift mask employed by the VMX-Preemption timer. */
417	uint8_t cPreemptTimerShift;
418
419	/** Virtual address of the TSS page used for real mode emulation. */
420	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
421	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
422	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
423
424	/** Physical address of the APIC-access page. */
425	RTHCPHYS HCPhysApicAccess;
426	/** R0 memory object for the APIC-access page. */
427	RTR0MEMOBJ hMemObjApicAccess;
428	/** Virtual address of the APIC-access page. */
429	R0PTRTYPE(uint8_t *) pbApicAccess;
430
431	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
432	RTHCPHYS HCPhysScratch;
433	RTR0MEMOBJ hMemObjScratch;
434	R0PTRTYPE(uint8_t *) pbScratch;
435	#endif
436
437	/** Internal Id of which flush-handler to use for tagged-TLB entries. */
438	uint32_t uFlushTaggedTlb;
439
440	/** Pause-loop exiting (PLE) gap in ticks. */
441	uint32_t cPleGapTicks;
442	/** Pause-loop exiting (PLE) window in ticks. */
443	uint32_t cPleWindowTicks;
444	uint32_t u32Alignment0;
445
446	/** Host CR4 value (set by ring-0 VMX init) */
447	uint64_t u64HostCr4;
448
449	/** Host EFER value (set by ring-0 VMX init) */
450	uint64_t u64HostEfer;
451	/** Whether the CPU supports VMCS fields for swapping EFER. */
452	bool fSupportsVmcsEfer;
453	uint8_t u8Alignment2[7];
454
455	/** VMX MSR values. */
456	VMXMSRS Msrs;
457
458	/** Flush types for invept & invvpid; they depend on capabilities. */
459	VMXFLUSHEPT enmFlushEpt;
460	VMXFLUSHVPID enmFlushVpid;
461
462	/** Host-physical address for a failing VMXON instruction. */
463	RTHCPHYS HCPhysVmxEnableError;
464	} vmx;
465
466	struct
467	{
468	/** Set by the ring-0 side of HM to indicate SVM is supported by the
469	* CPU. */
470	bool fSupported;
471	/** Set when we've enabled SVM. */
472	bool fEnabled;
473	/** Set if erratum 170 affects the AMD cpu. */
474	bool fAlwaysFlushTLB;
475	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
476	bool fIgnoreInUseError;
477	uint8_t u8Alignment0[4];
478
479	/** Physical address of the IO bitmap (12kb). */
480	RTHCPHYS HCPhysIOBitmap;
481	/** R0 memory object for the IO bitmap (12kb). */
482	RTR0MEMOBJ hMemObjIOBitmap;
483	/** Virtual address of the IO bitmap. */
484	R0PTRTYPE(void *) pvIOBitmap;
485
486	/* HWCR MSR (for diagnostics) */
487	uint64_t u64MsrHwcr;
488
489	/** SVM revision. */
490	uint32_t u32Rev;
491	/** SVM feature bits from cpuid 0x8000000a */
492	uint32_t u32Features;
493
494	/** Pause filter counter. */
495	uint16_t cPauseFilter;
496	/** Pause filter treshold in ticks. */
497	uint16_t cPauseFilterThresholdTicks;
498	uint32_t u32Alignment0;
499	} svm;
500
501	/**
502	* AVL tree with all patches (active or disabled) sorted by guest instruction
503	* address.
504	*/
505	AVLOU32TREE PatchTree;
506	uint32_t cPatches;
507	HMTPRPATCH aPatches[64];
508
509	struct
510	{
511	uint32_t u32AMDFeatureECX;
512	uint32_t u32AMDFeatureEDX;
513	} cpuid;
514
515	/** Saved error from detection */
516	int32_t lLastError;
517
518	/** HMR0Init was run */
519	bool fHMR0Init;
520	bool u8Alignment1[3];
521
522	STAMCOUNTER StatTprPatchSuccess;
523	STAMCOUNTER StatTprPatchFailure;
524	STAMCOUNTER StatTprReplaceSuccessCr8;
525	STAMCOUNTER StatTprReplaceSuccessVmc;
526	STAMCOUNTER StatTprReplaceFailure;
527	} HM;
528	/** Pointer to HM VM instance data. */
529	typedef HM *PHM;
530
531	AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
532
533	/* Maximum number of cached entries. */
534	#define VMCSCACHE_MAX_ENTRY 128
535
536	/**
537	* Structure for storing read and write VMCS actions.
538	*/
539	typedef struct VMCSCACHE
540	{
541	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
542	/* Magic marker for searching in crash dumps. */
543	uint8_t aMagic[16];
544	uint64_t uMagic;
545	uint64_t u64TimeEntry;
546	uint64_t u64TimeSwitch;
547	uint64_t cResume;
548	uint64_t interPD;
549	uint64_t pSwitcher;
550	uint32_t uPos;
551	uint32_t idCpu;
552	#endif
553	/* CR2 is saved here for EPT syncing. */
554	uint64_t cr2;
555	struct
556	{
557	uint32_t cValidEntries;
558	uint32_t uAlignment;
559	uint32_t aField[VMCSCACHE_MAX_ENTRY];
560	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
561	} Write;
562	struct
563	{
564	uint32_t cValidEntries;
565	uint32_t uAlignment;
566	uint32_t aField[VMCSCACHE_MAX_ENTRY];
567	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
568	} Read;
569	#ifdef VBOX_STRICT
570	struct
571	{
572	RTHCPHYS HCPhysCpuPage;
573	RTHCPHYS HCPhysVmcs;
574	RTGCPTR pCache;
575	RTGCPTR pCtx;
576	} TestIn;
577	struct
578	{
579	RTHCPHYS HCPhysVmcs;
580	RTGCPTR pCache;
581	RTGCPTR pCtx;
582	uint64_t eflags;
583	uint64_t cr8;
584	} TestOut;
585	struct
586	{
587	uint64_t param1;
588	uint64_t param2;
589	uint64_t param3;
590	uint64_t param4;
591	} ScratchPad;
592	#endif
593	} VMCSCACHE;
594	/** Pointer to VMCSCACHE. */
595	typedef VMCSCACHE *PVMCSCACHE;
596	AssertCompileSizeAlignment(VMCSCACHE, 8);
597
598	/** VMX StartVM function. */
599	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
600	/** Pointer to a VMX StartVM function. */
601	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
602
603	/** SVM VMRun function. */
604	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
605	/** Pointer to a SVM VMRun function. */
606	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
607
608	/**
609	* HM VMCPU Instance data.
610	*
611	* Note! If you change members of this struct, make sure to check if the
612	* assembly counterpart in HMInternal.mac needs to be updated as well.
613	*/
614	typedef struct HMCPU
615	{
616	/** Set if we need to flush the TLB during the world switch. */
617	bool fForceTLBFlush;
618	/** Set when we're using VT-x or AMD-V at that moment. */
619	bool fActive;
620	/** Set when the TLB has been checked until we return from the world switch. */
621	volatile bool fCheckedTLBFlush;
622	/** Whether we're executing a single instruction. */
623	bool fSingleInstruction;
624	/** Set if we need to clear the trap flag because of single stepping. */
625	bool fClearTrapFlag;
626	/** Whether we've completed the inner HM leave function. */
627	bool fLeaveDone;
628	/** Whether we're using the hyper DR7 or guest DR7. */
629	bool fUsingHyperDR7;
630	/** Whether to preload the guest-FPU state to avoid \#NM VM-exit overhead. */
631	bool fPreloadGuestFpu;
632	/** Set if XCR0 needs to be loaded and saved when entering and exiting guest
633	* code execution. */
634	bool fLoadSaveGuestXcr0;
635
636	/** Whether \#UD needs to be intercepted (required by certain GIM providers). */
637	bool fGIMTrapXcptUD;
638	/** Whether paravirt. hypercalls are enabled. */
639	bool fHypercallsEnabled;
640	uint8_t u8Alignment0[5];
641
642	/** World switch exit counter. */
643	volatile uint32_t cWorldSwitchExits;
644	/** HM_CHANGED_* flags. */
645	volatile uint32_t fContextUseFlags;
646	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
647	* time). */
648	RTCPUID idLastCpu;
649	/** TLB flush count. */
650	uint32_t cTlbFlushes;
651	/** Current ASID in use by the VM. */
652	uint32_t uCurrentAsid;
653	/** An additional error code used for some gurus. */
654	uint32_t u32HMError;
655	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
656	uint64_t u64HostTscAux;
657
658	struct
659	{
660	/** Ring 0 handlers for VT-x. */
661	PFNHMVMXSTARTVM pfnStartVM;
662	#if HC_ARCH_BITS == 32
663	uint32_t u32Alignment0;
664	#endif
665	/** Current VMX_VMCS32_CTRL_PIN_EXEC. */
666	uint32_t u32PinCtls;
667	/** Current VMX_VMCS32_CTRL_PROC_EXEC. */
668	uint32_t u32ProcCtls;
669	/** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
670	uint32_t u32ProcCtls2;
671	/** Current VMX_VMCS32_CTRL_EXIT. */
672	uint32_t u32ExitCtls;
673	/** Current VMX_VMCS32_CTRL_ENTRY. */
674	uint32_t u32EntryCtls;
675
676	/** Current CR0 mask. */
677	uint32_t u32CR0Mask;
678	/** Current CR4 mask. */
679	uint32_t u32CR4Mask;
680	/** Current exception bitmap. */
681	uint32_t u32XcptBitmap;
682	/** The updated-guest-state mask. */
683	volatile uint32_t fUpdatedGuestState;
684	uint32_t u32Alignment1;
685
686	/** Physical address of the VM control structure (VMCS). */
687	RTHCPHYS HCPhysVmcs;
688	/** R0 memory object for the VM control structure (VMCS). */
689	RTR0MEMOBJ hMemObjVmcs;
690	/** Virtual address of the VM control structure (VMCS). */
691	R0PTRTYPE(void *) pvVmcs;
692
693	/** Physical address of the virtual APIC page for TPR caching. */
694	RTHCPHYS HCPhysVirtApic;
695	/** R0 memory object for the virtual APIC page for TPR caching. */
696	RTR0MEMOBJ hMemObjVirtApic;
697	/** Virtual address of the virtual APIC page for TPR caching. */
698	R0PTRTYPE(uint8_t *) pbVirtApic;
699
700	/** Physical address of the MSR bitmap. */
701	RTHCPHYS HCPhysMsrBitmap;
702	/** R0 memory object for the MSR bitmap. */
703	RTR0MEMOBJ hMemObjMsrBitmap;
704	/** Virtual address of the MSR bitmap. */
705	R0PTRTYPE(void *) pvMsrBitmap;
706
707	/** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
708	* for guest MSRs). */
709	RTHCPHYS HCPhysGuestMsr;
710	/** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
711	* (used for guest MSRs). */
712	RTR0MEMOBJ hMemObjGuestMsr;
713	/** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
714	* for guest MSRs). */
715	R0PTRTYPE(void *) pvGuestMsr;
716
717	/** Physical address of the VM-exit MSR-load area (used for host MSRs). */
718	RTHCPHYS HCPhysHostMsr;
719	/** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
720	RTR0MEMOBJ hMemObjHostMsr;
721	/** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
722	R0PTRTYPE(void *) pvHostMsr;
723
724	/** Current EPTP. */
725	RTHCPHYS HCPhysEPTP;
726
727	/** Number of guest/host MSR pairs in the auto-load/store area. */
728	uint32_t cMsrs;
729	/** Whether the host MSR values are up-to-date in the auto-load/store area. */
730	bool fUpdatedHostMsrs;
731	uint8_t u8Alignment0[3];
732
733	/** Host LSTAR MSR value to restore lazily while leaving VT-x. */
734	uint64_t u64HostLStarMsr;
735	/** Host STAR MSR value to restore lazily while leaving VT-x. */
736	uint64_t u64HostStarMsr;
737	/** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
738	uint64_t u64HostSFMaskMsr;
739	/** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
740	uint64_t u64HostKernelGSBaseMsr;
741	/** A mask of which MSRs have been swapped and need restoration. */
742	uint32_t fLazyMsrs;
743	uint32_t u32Alignment2;
744
745	/** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
746	uint64_t u64MsrApicBase;
747	/** Last use TSC offset value. (cached) */
748	uint64_t u64TSCOffset;
749
750	/** VMCS cache. */
751	VMCSCACHE VMCSCache;
752
753	/** Real-mode emulation state. */
754	struct
755	{
756	X86DESCATTR AttrCS;
757	X86DESCATTR AttrDS;
758	X86DESCATTR AttrES;
759	X86DESCATTR AttrFS;
760	X86DESCATTR AttrGS;
761	X86DESCATTR AttrSS;
762	X86EFLAGS Eflags;
763	uint32_t fRealOnV86Active;
764	} RealMode;
765
766	/** VT-x error-reporting (mainly for ring-3 propagation). */
767	struct
768	{
769	uint64_t u64VMCSPhys;
770	uint32_t u32VMCSRevision;
771	uint32_t u32InstrError;
772	uint32_t u32ExitReason;
773	RTCPUID idEnteredCpu;
774	RTCPUID idCurrentCpu;
775	uint32_t u32Alignment0;
776	} LastError;
777
778	/** Current state of the VMCS. */
779	uint32_t uVmcsState;
780	/** Which host-state bits to restore before being preempted. */
781	uint32_t fRestoreHostFlags;
782	/** The host-state restoration structure. */
783	VMXRESTOREHOST RestoreHost;
784
785	/** Set if guest was executing in real mode (extra checks). */
786	bool fWasInRealMode;
787	uint8_t u8Alignment1[7];
788	} vmx;
789
790	struct
791	{
792	/** Ring 0 handlers for VT-x. */
793	PFNHMSVMVMRUN pfnVMRun;
794	#if HC_ARCH_BITS == 32
795	uint32_t u32Alignment0;
796	#endif
797
798	/** Physical address of the host VMCB which holds additional host-state. */
799	RTHCPHYS HCPhysVmcbHost;
800	/** R0 memory object for the host VMCB which holds additional host-state. */
801	RTR0MEMOBJ hMemObjVmcbHost;
802	/** Virtual address of the host VMCB which holds additional host-state. */
803	R0PTRTYPE(void *) pvVmcbHost;
804
805	/** Physical address of the guest VMCB. */
806	RTHCPHYS HCPhysVmcb;
807	/** R0 memory object for the guest VMCB. */
808	RTR0MEMOBJ hMemObjVmcb;
809	/** Virtual address of the guest VMCB. */
810	R0PTRTYPE(void *) pvVmcb;
811
812	/** Physical address of the MSR bitmap (8 KB). */
813	RTHCPHYS HCPhysMsrBitmap;
814	/** R0 memory object for the MSR bitmap (8 KB). */
815	RTR0MEMOBJ hMemObjMsrBitmap;
816	/** Virtual address of the MSR bitmap. */
817	R0PTRTYPE(void *) pvMsrBitmap;
818
819	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
820	* we should check if the VTPR changed on every VM-exit. */
821	bool fSyncVTpr;
822	uint8_t u8Alignment0[7];
823	} svm;
824
825	/** Event injection state. */
826	struct
827	{
828	uint32_t fPending;
829	uint32_t u32ErrCode;
830	uint32_t cbInstr;
831	uint32_t u32Padding; /*< Explicit alignment padding. /
832	uint64_t u64IntInfo;
833	RTGCUINTPTR GCPtrFaultAddress;
834	} Event;
835
836	/** IO Block emulation state. */
837	struct
838	{
839	bool fEnabled;
840	uint8_t u8Align[7];
841
842	/** RIP at the start of the io code we wish to emulate in the recompiler. */
843	RTGCPTR GCPtrFunctionEip;
844
845	uint64_t cr0;
846	} EmulateIoBlock;
847
848	struct
849	{
850	/** Pending IO operation type. */
851	HMPENDINGIO enmType;
852	uint32_t u32Alignment0;
853	RTGCPTR GCPtrRip;
854	RTGCPTR GCPtrRipNext;
855	union
856	{
857	struct
858	{
859	uint32_t uPort;
860	uint32_t uAndVal;
861	uint32_t cbSize;
862	} Port;
863	uint64_t aRaw[2];
864	} s;
865	} PendingIO;
866
867	/** The PAE PDPEs used with Nested Paging (only valid when
868	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
869	X86PDPE aPdpes[4];
870
871	/** Current shadow paging mode. */
872	PGMMODE enmShadowMode;
873
874	/** The CPU ID of the CPU currently owning the VMCS. Set in
875	* HMR0Enter and cleared in HMR0Leave. */
876	RTCPUID idEnteredCpu;
877
878	/** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
879	uint16_t auExitHistory[31];
880	/** The index of the next free slot in the history array. */
881	uint16_t idxExitHistoryFree;
882
883	/** For saving stack space, the disassembler state is allocated here instead of
884	* on the stack. */
885	DISCPUSTATE DisState;
886
887	STAMPROFILEADV StatEntry;
888	STAMPROFILEADV StatExit1;
889	STAMPROFILEADV StatExit2;
890	STAMPROFILEADV StatExitIO;
891	STAMPROFILEADV StatExitMovCRx;
892	STAMPROFILEADV StatExitXcptNmi;
893	STAMPROFILEADV StatLoadGuestState;
894	STAMPROFILEADV StatInGC;
895
896	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
897	STAMPROFILEADV StatWorldSwitch3264;
898	#endif
899	STAMPROFILEADV StatPoke;
900	STAMPROFILEADV StatSpinPoke;
901	STAMPROFILEADV StatSpinPokeFailed;
902
903	STAMCOUNTER StatInjectInterrupt;
904	STAMCOUNTER StatInjectXcpt;
905	STAMCOUNTER StatInjectPendingReflect;
906
907	STAMCOUNTER StatExitAll;
908	STAMCOUNTER StatExitShadowNM;
909	STAMCOUNTER StatExitGuestNM;
910	STAMCOUNTER StatExitShadowPF; /*< Misleading, currently used for MMIO \#PFs as well. /
911	STAMCOUNTER StatExitShadowPFEM;
912	STAMCOUNTER StatExitGuestPF;
913	STAMCOUNTER StatExitGuestUD;
914	STAMCOUNTER StatExitGuestSS;
915	STAMCOUNTER StatExitGuestNP;
916	STAMCOUNTER StatExitGuestTS;
917	STAMCOUNTER StatExitGuestGP;
918	STAMCOUNTER StatExitGuestDE;
919	STAMCOUNTER StatExitGuestDB;
920	STAMCOUNTER StatExitGuestMF;
921	STAMCOUNTER StatExitGuestBP;
922	STAMCOUNTER StatExitGuestXF;
923	STAMCOUNTER StatExitGuestXcpUnk;
924	STAMCOUNTER StatExitInvlpg;
925	STAMCOUNTER StatExitInvd;
926	STAMCOUNTER StatExitWbinvd;
927	STAMCOUNTER StatExitPause;
928	STAMCOUNTER StatExitCpuid;
929	STAMCOUNTER StatExitRdtsc;
930	STAMCOUNTER StatExitRdtscp;
931	STAMCOUNTER StatExitRdpmc;
932	STAMCOUNTER StatExitVmcall;
933	STAMCOUNTER StatExitRdrand;
934	STAMCOUNTER StatExitCli;
935	STAMCOUNTER StatExitSti;
936	STAMCOUNTER StatExitPushf;
937	STAMCOUNTER StatExitPopf;
938	STAMCOUNTER StatExitIret;
939	STAMCOUNTER StatExitInt;
940	STAMCOUNTER StatExitCRxWrite[16];
941	STAMCOUNTER StatExitCRxRead[16];
942	STAMCOUNTER StatExitDRxWrite;
943	STAMCOUNTER StatExitDRxRead;
944	STAMCOUNTER StatExitRdmsr;
945	STAMCOUNTER StatExitWrmsr;
946	STAMCOUNTER StatExitClts;
947	STAMCOUNTER StatExitXdtrAccess;
948	STAMCOUNTER StatExitHlt;
949	STAMCOUNTER StatExitMwait;
950	STAMCOUNTER StatExitMonitor;
951	STAMCOUNTER StatExitLmsw;
952	STAMCOUNTER StatExitIOWrite;
953	STAMCOUNTER StatExitIORead;
954	STAMCOUNTER StatExitIOStringWrite;
955	STAMCOUNTER StatExitIOStringRead;
956	STAMCOUNTER StatExitIntWindow;
957	STAMCOUNTER StatExitExtInt;
958	STAMCOUNTER StatExitHostNmiInGC;
959	STAMCOUNTER StatExitPreemptTimer;
960	STAMCOUNTER StatExitTprBelowThreshold;
961	STAMCOUNTER StatExitTaskSwitch;
962	STAMCOUNTER StatExitMtf;
963	STAMCOUNTER StatExitApicAccess;
964	STAMCOUNTER StatPendingHostIrq;
965
966	STAMCOUNTER StatFlushPage;
967	STAMCOUNTER StatFlushPageManual;
968	STAMCOUNTER StatFlushPhysPageManual;
969	STAMCOUNTER StatFlushTlb;
970	STAMCOUNTER StatFlushTlbManual;
971	STAMCOUNTER StatFlushTlbWorldSwitch;
972	STAMCOUNTER StatNoFlushTlbWorldSwitch;
973	STAMCOUNTER StatFlushEntire;
974	STAMCOUNTER StatFlushAsid;
975	STAMCOUNTER StatFlushNestedPaging;
976	STAMCOUNTER StatFlushTlbInvlpgVirt;
977	STAMCOUNTER StatFlushTlbInvlpgPhys;
978	STAMCOUNTER StatTlbShootdown;
979	STAMCOUNTER StatTlbShootdownFlush;
980
981	STAMCOUNTER StatSwitchGuestIrq;
982	STAMCOUNTER StatSwitchHmToR3FF;
983	STAMCOUNTER StatSwitchExitToR3;
984	STAMCOUNTER StatSwitchLongJmpToR3;
985	STAMCOUNTER StatSwitchMaxResumeLoops;
986	STAMCOUNTER StatSwitchHltToR3;
987	STAMCOUNTER StatSwitchApicAccessToR3;
988	STAMCOUNTER StatSwitchPreempt;
989	STAMCOUNTER StatSwitchPreemptSaveHostState;
990
991	STAMCOUNTER StatTscParavirt;
992	STAMCOUNTER StatTscOffset;
993	STAMCOUNTER StatTscIntercept;
994
995	STAMCOUNTER StatExitReasonNpf;
996	STAMCOUNTER StatDRxArmed;
997	STAMCOUNTER StatDRxContextSwitch;
998	STAMCOUNTER StatDRxIoCheck;
999
1000	STAMCOUNTER StatLoadMinimal;
1001	STAMCOUNTER StatLoadFull;
1002
1003	STAMCOUNTER StatVmxCheckBadRmSelBase;
1004	STAMCOUNTER StatVmxCheckBadRmSelLimit;
1005	STAMCOUNTER StatVmxCheckRmOk;
1006
1007	STAMCOUNTER StatVmxCheckBadSel;
1008	STAMCOUNTER StatVmxCheckBadRpl;
1009	STAMCOUNTER StatVmxCheckBadLdt;
1010	STAMCOUNTER StatVmxCheckBadTr;
1011	STAMCOUNTER StatVmxCheckPmOk;
1012
1013	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1014	STAMCOUNTER StatFpu64SwitchBack;
1015	STAMCOUNTER StatDebug64SwitchBack;
1016	#endif
1017
1018	#ifdef VBOX_WITH_STATISTICS
1019	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1020	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1021	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1022	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1023	#endif
1024	#ifdef HM_PROFILE_EXIT_DISPATCH
1025	STAMPROFILEADV StatExitDispatch;
1026	#endif
1027	} HMCPU;
1028	/** Pointer to HM VMCPU instance data. */
1029	typedef HMCPU *PHMCPU;
1030	AssertCompileMemberAlignment(HMCPU, vmx, 8);
1031	AssertCompileMemberAlignment(HMCPU, svm, 8);
1032	AssertCompileMemberAlignment(HMCPU, Event, 8);
1033
1034
1035	#ifdef IN_RING0
1036	/** @todo r=bird: s/[[:space:]]HM/ hm/ - internal functions starts with a
1037	* lower cased prefix. HMInternal.h is an internal header, so
1038	* everything here must be internal. */
1039	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void);
1040	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
1041
1042
1043	# ifdef VBOX_STRICT
1044	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1045	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1046	# else
1047	# define HMDumpRegs(a, b ,c) do { } while (0)
1048	# define HMR0DumpDescriptor(a, b, c) do { } while (0)
1049	# endif /* VBOX_STRICT */
1050
1051	# ifdef VBOX_WITH_KERNEL_USING_XMM
1052	DECLASM(int) HMR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1053	DECLASM(int) HMR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1054	# endif
1055
1056	#endif /* IN_RING0 */
1057
1058	/** @} */
1059
1060	RT_C_DECLS_END
1061
1062	#endif
1063

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 58912

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