VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 45786

Last change on this file since 45786 was 45786, checked in by vboxsync, 12 years ago

Move HMRCA.asm into the switcher code so we don't need VMMRC.rc.
  • Property svn:eol-style set to native
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File size: 34.7 KB
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1/* $Id: HMInternal.h 45786 2013-04-26 22:35:59Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34
35#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
36/* Enable 64 bits guest support. */
37# define VBOX_ENABLE_64_BITS_GUESTS
38#endif
39
40#ifdef VBOX_WITH_OLD_VTX_CODE
41# define VMX_USE_CACHED_VMCS_ACCESSES
42#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
43# define VMX_USE_CACHED_VMCS_ACCESSES
44#endif
45
46/** @def HM_PROFILE_EXIT_DISPATCH
47 * Enables profiling of the VM exit handler dispatching. */
48#if 0
49# define HM_PROFILE_EXIT_DISPATCH
50#endif
51
52/* The MSR auto load/store does not work for KERNEL_GS_BASE MSR, thus we
53 * handle this MSR manually. See @bugref{6208}. This is clearly visible while
54 * booting Solaris 11 (11.1 b19) VMs with 2 Cpus.
55 *
56 * Note: don't forget to update the assembly files while modifying this!
57 */
58# define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
59
60RT_C_DECLS_BEGIN
61
62
63/** @defgroup grp_hm_int Internal
64 * @ingroup grp_hm
65 * @internal
66 * @{
67 */
68
69
70/** Maximum number of exit reason statistics counters. */
71#define MAX_EXITREASON_STAT 0x100
72#define MASK_EXITREASON_STAT 0xff
73#define MASK_INJECT_IRQ_STAT 0xff
74
75/** @name Changed flags
76 * These flags are used to keep track of which important registers that
77 * have been changed since last they were reset.
78 * @{
79 */
80#ifdef VBOX_WITH_OLD_VTX_CODE
81# define HM_CHANGED_GUEST_FPU RT_BIT(0)
82# define HM_CHANGED_GUEST_CR0 RT_BIT(1)
83# define HM_CHANGED_GUEST_CR3 RT_BIT(2)
84# define HM_CHANGED_GUEST_CR4 RT_BIT(3)
85# define HM_CHANGED_GUEST_GDTR RT_BIT(4)
86# define HM_CHANGED_GUEST_IDTR RT_BIT(5)
87# define HM_CHANGED_GUEST_LDTR RT_BIT(6)
88# define HM_CHANGED_GUEST_TR RT_BIT(7)
89# define HM_CHANGED_GUEST_MSR RT_BIT(8)
90# define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
91# define HM_CHANGED_GUEST_DEBUG RT_BIT(10)
92# define HM_CHANGED_HOST_CONTEXT RT_BIT(11)
93# define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_SEGMENT_REGS \
94 | HM_CHANGED_GUEST_CR0 \
95 | HM_CHANGED_GUEST_CR3 \
96 | HM_CHANGED_GUEST_CR4 \
97 | HM_CHANGED_GUEST_GDTR \
98 | HM_CHANGED_GUEST_IDTR \
99 | HM_CHANGED_GUEST_LDTR \
100 | HM_CHANGED_GUEST_TR \
101 | HM_CHANGED_GUEST_MSR \
102 | HM_CHANGED_GUEST_DEBUG \
103 | HM_CHANGED_GUEST_FPU)
104#else
105# define HM_CHANGED_GUEST_RIP RT_BIT(0)
106# define HM_CHANGED_GUEST_RSP RT_BIT(1)
107# define HM_CHANGED_GUEST_RFLAGS RT_BIT(2)
108# define HM_CHANGED_GUEST_CR0 RT_BIT(3)
109# define HM_CHANGED_GUEST_CR3 RT_BIT(4)
110# define HM_CHANGED_GUEST_CR4 RT_BIT(5)
111# define HM_CHANGED_GUEST_GDTR RT_BIT(6)
112# define HM_CHANGED_GUEST_IDTR RT_BIT(7)
113# define HM_CHANGED_GUEST_LDTR RT_BIT(8)
114# define HM_CHANGED_GUEST_TR RT_BIT(9)
115# define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(10)
116# define HM_CHANGED_GUEST_DEBUG RT_BIT(11)
117# define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(12)
118# define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(13)
119# define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(14)
120# define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(15)
121# define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(16)
122# define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(17)
123# define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(18)
124# define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(19)
125
126# define HM_CHANGED_HOST_CONTEXT RT_BIT(20)
127
128# define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_RIP \
129 | HM_CHANGED_GUEST_RSP \
130 | HM_CHANGED_GUEST_RFLAGS \
131 | HM_CHANGED_GUEST_CR0 \
132 | HM_CHANGED_GUEST_CR3 \
133 | HM_CHANGED_GUEST_CR4 \
134 | HM_CHANGED_GUEST_GDTR \
135 | HM_CHANGED_GUEST_IDTR \
136 | HM_CHANGED_GUEST_LDTR \
137 | HM_CHANGED_GUEST_TR \
138 | HM_CHANGED_GUEST_SEGMENT_REGS \
139 | HM_CHANGED_GUEST_DEBUG \
140 | HM_CHANGED_GUEST_SYSENTER_CS_MSR \
141 | HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
142 | HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
143 | HM_CHANGED_VMX_GUEST_AUTO_MSRS \
144 | HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
145 | HM_CHANGED_VMX_GUEST_APIC_STATE \
146 | HM_CHANGED_VMX_ENTRY_CTLS \
147 | HM_CHANGED_VMX_EXIT_CTLS)
148#endif
149
150#define HM_CHANGED_ALL (HM_CHANGED_ALL_GUEST | HM_CHANGED_HOST_CONTEXT)
151/** @} */
152
153/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
154#define HM_MAX_TLB_SHOOTDOWN_PAGES 8
155
156/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
157#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
158/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
159#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
160/** Total guest mapped memory needed. */
161#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
162
163/** Enable for TPR guest patching. */
164#define VBOX_HM_WITH_GUEST_PATCHING
165
166/** HM SSM version
167 */
168#ifdef VBOX_HM_WITH_GUEST_PATCHING
169# define HM_SSM_VERSION 5
170# define HM_SSM_VERSION_NO_PATCHING 4
171#else
172# define HM_SSM_VERSION 4
173# define HM_SSM_VERSION_NO_PATCHING 4
174#endif
175#define HM_SSM_VERSION_2_0_X 3
176
177/**
178 * Global per-cpu information. (host)
179 */
180typedef struct HMGLOBLCPUINFO
181{
182 /** The CPU ID. */
183 RTCPUID idCpu;
184 /** The memory object */
185 RTR0MEMOBJ hMemObj;
186 /** Current ASID (AMD-V) / VPID (Intel). */
187 uint32_t uCurrentAsid;
188 /** TLB flush count. */
189 uint32_t cTlbFlushes;
190 /** Whether to flush each new ASID/VPID before use. */
191 bool fFlushAsidBeforeUse;
192 /** Configured for VT-x or AMD-V. */
193 bool fConfigured;
194 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
195 bool fIgnoreAMDVInUseError;
196 /** In use by our code. (for power suspend) */
197 volatile bool fInUse;
198} HMGLOBLCPUINFO;
199/** Pointer to the per-cpu global information. */
200typedef HMGLOBLCPUINFO *PHMGLOBLCPUINFO;
201
202typedef enum
203{
204 HMPENDINGIO_INVALID = 0,
205 HMPENDINGIO_PORT_READ,
206 HMPENDINGIO_PORT_WRITE,
207 HMPENDINGIO_STRING_READ,
208 HMPENDINGIO_STRING_WRITE,
209 /** The usual 32-bit paranoia. */
210 HMPENDINGIO_32BIT_HACK = 0x7fffffff
211} HMPENDINGIO;
212
213
214typedef enum
215{
216 HMTPRINSTR_INVALID,
217 HMTPRINSTR_READ,
218 HMTPRINSTR_READ_SHR4,
219 HMTPRINSTR_WRITE_REG,
220 HMTPRINSTR_WRITE_IMM,
221 HMTPRINSTR_JUMP_REPLACEMENT,
222 /** The usual 32-bit paranoia. */
223 HMTPRINSTR_32BIT_HACK = 0x7fffffff
224} HMTPRINSTR;
225
226typedef struct
227{
228 /** The key is the address of patched instruction. (32 bits GC ptr) */
229 AVLOU32NODECORE Core;
230 /** Original opcode. */
231 uint8_t aOpcode[16];
232 /** Instruction size. */
233 uint32_t cbOp;
234 /** Replacement opcode. */
235 uint8_t aNewOpcode[16];
236 /** Replacement instruction size. */
237 uint32_t cbNewOp;
238 /** Instruction type. */
239 HMTPRINSTR enmType;
240 /** Source operand. */
241 uint32_t uSrcOperand;
242 /** Destination operand. */
243 uint32_t uDstOperand;
244 /** Number of times the instruction caused a fault. */
245 uint32_t cFaults;
246 /** Patch address of the jump replacement. */
247 RTGCPTR32 pJumpTarget;
248} HMTPRPATCH;
249/** Pointer to HMTPRPATCH. */
250typedef HMTPRPATCH *PHMTPRPATCH;
251
252/**
253 * Switcher function, HC to the special 64-bit RC.
254 *
255 * @param pVM Pointer to the VM.
256 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
257 * @returns Return code indicating the action to take.
258 */
259typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
260/** Pointer to switcher function. */
261typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
262
263/**
264 * HM VM Instance data.
265 * Changes to this must checked against the padding of the hm union in VM!
266 */
267typedef struct HM
268{
269 /** Set when we've initialized VMX or SVM. */
270 bool fInitialized;
271
272 /** Set if nested paging is enabled. */
273 bool fNestedPaging;
274
275 /** Set if nested paging is allowed. */
276 bool fAllowNestedPaging;
277
278 /** Set if large pages are enabled (requires nested paging). */
279 bool fLargePages;
280
281 /** Set if we can support 64-bit guests or not. */
282 bool fAllow64BitGuests;
283
284 /** Set if an IO-APIC is configured for this VM. */
285 bool fHasIoApic;
286
287 /** Set when TPR patching is allowed. */
288 bool fTRPPatchingAllowed;
289
290 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
291 bool fGlobalInit;
292
293 /** Set when TPR patching is active. */
294 bool fTPRPatchingActive;
295 bool u8Alignment[7];
296
297 /** And mask for copying register contents. */
298 uint64_t u64RegisterMask;
299
300 /** Maximum ASID allowed. */
301 uint32_t uMaxAsid;
302
303 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
304 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
305 uint32_t cMaxResumeLoops;
306
307 /** Guest allocated memory for patching purposes. */
308 RTGCPTR pGuestPatchMem;
309 /** Current free pointer inside the patch block. */
310 RTGCPTR pFreeGuestPatchMem;
311 /** Size of the guest patch memory block. */
312 uint32_t cbGuestPatchMem;
313 uint32_t uPadding1;
314
315#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
316 /** 32 to 64 bits switcher entrypoint. */
317 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
318 RTR0PTR uPadding2;
319#endif
320
321 struct
322 {
323 /** Set by the ring-0 side of HM to indicate VMX is supported by the
324 * CPU. */
325 bool fSupported;
326
327 /** Set when we've enabled VMX. */
328 bool fEnabled;
329
330 /** Set if VPID is supported. */
331 bool fVpid;
332
333 /** Set if VT-x VPID is allowed. */
334 bool fAllowVpid;
335
336 /** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
337 bool fUnrestrictedGuest;
338
339 /** Whether we're using the preemption timer or not. */
340 bool fUsePreemptTimer;
341 /** The shift mask employed by the VMX-Preemption timer. */
342 uint8_t cPreemptTimerShift;
343
344 bool uAlignment[1];
345
346 /** Virtual address of the TSS page used for real mode emulation. */
347 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
348
349 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
350 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
351
352 /** R0 memory object for the APIC-access page. */
353 RTR0MEMOBJ hMemObjApicAccess;
354 /** Physical address of the APIC-access page. */
355 RTHCPHYS HCPhysApicAccess;
356 /** Virtual address of the APIC-access page. */
357 R0PTRTYPE(uint8_t *) pbApicAccess;
358
359#ifdef VBOX_WITH_CRASHDUMP_MAGIC
360 RTR0MEMOBJ hMemObjScratch;
361 RTHCPHYS HCPhysScratch;
362 R0PTRTYPE(uint8_t *) pbScratch;
363#endif
364
365#ifndef VBOX_WITH_OLD_VTX_CODE
366 unsigned uFlushTaggedTlb;
367#else
368 /** Ring 0 handlers for VT-x. */
369 DECLR0CALLBACKMEMBER(void, pfnFlushTaggedTlb, (PVM pVM, PVMCPU pVCpu));
370#endif
371
372#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
373 uint32_t u32Alignment;
374#endif
375 /** Host CR4 value (set by ring-0 VMX init) */
376 uint64_t hostCR4;
377
378 /** Host EFER value (set by ring-0 VMX init) */
379 uint64_t hostEFER;
380
381 /** VMX MSR values */
382 struct
383 {
384 uint64_t feature_ctrl;
385 uint64_t vmx_basic_info;
386 VMX_CAPABILITY vmx_pin_ctls;
387 VMX_CAPABILITY vmx_proc_ctls;
388 VMX_CAPABILITY vmx_proc_ctls2;
389 VMX_CAPABILITY vmx_exit;
390 VMX_CAPABILITY vmx_entry;
391 uint64_t vmx_misc;
392 uint64_t vmx_cr0_fixed0;
393 uint64_t vmx_cr0_fixed1;
394 uint64_t vmx_cr4_fixed0;
395 uint64_t vmx_cr4_fixed1;
396 uint64_t vmx_vmcs_enum;
397 uint64_t vmx_ept_vpid_caps;
398 } msr;
399
400 /** Flush types for invept & invvpid; they depend on capabilities. */
401 VMX_FLUSH_EPT enmFlushEpt;
402 VMX_FLUSH_VPID enmFlushVpid;
403 } vmx;
404
405 struct
406 {
407 /** Set by the ring-0 side of HM to indicate SVM is supported by the
408 * CPU. */
409 bool fSupported;
410 /** Set when we've enabled SVM. */
411 bool fEnabled;
412 /** Set if erratum 170 affects the AMD cpu. */
413 bool fAlwaysFlushTLB;
414 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
415 bool fIgnoreInUseError;
416
417 /** R0 memory object for the IO bitmap (12kb). */
418 RTR0MEMOBJ hMemObjIOBitmap;
419 /** Physical address of the IO bitmap (12kb). */
420 RTHCPHYS HCPhysIOBitmap;
421 /** Virtual address of the IO bitmap. */
422 R0PTRTYPE(void *) pvIOBitmap;
423
424 /* HWCR MSR (for diagnostics) */
425 uint64_t msrHwcr;
426
427 /** SVM revision. */
428 uint32_t u32Rev;
429
430 /** SVM feature bits from cpuid 0x8000000a */
431 uint32_t u32Features;
432 } svm;
433
434 /**
435 * AVL tree with all patches (active or disabled) sorted by guest instruction address
436 */
437 AVLOU32TREE PatchTree;
438 uint32_t cPatches;
439 HMTPRPATCH aPatches[64];
440
441 struct
442 {
443 uint32_t u32AMDFeatureECX;
444 uint32_t u32AMDFeatureEDX;
445 } cpuid;
446
447 /** Saved error from detection */
448 int32_t lLastError;
449
450 /** HMR0Init was run */
451 bool fHMR0Init;
452 bool u8Alignment1[7];
453
454 STAMCOUNTER StatTprPatchSuccess;
455 STAMCOUNTER StatTprPatchFailure;
456 STAMCOUNTER StatTprReplaceSuccess;
457 STAMCOUNTER StatTprReplaceFailure;
458} HM;
459/** Pointer to HM VM instance data. */
460typedef HM *PHM;
461
462/* Maximum number of cached entries. */
463#define VMCSCACHE_MAX_ENTRY 128
464
465/* Structure for storing read and write VMCS actions. */
466typedef struct VMCSCACHE
467{
468#ifdef VBOX_WITH_CRASHDUMP_MAGIC
469 /* Magic marker for searching in crash dumps. */
470 uint8_t aMagic[16];
471 uint64_t uMagic;
472 uint64_t u64TimeEntry;
473 uint64_t u64TimeSwitch;
474 uint64_t cResume;
475 uint64_t interPD;
476 uint64_t pSwitcher;
477 uint32_t uPos;
478 uint32_t idCpu;
479#endif
480 /* CR2 is saved here for EPT syncing. */
481 uint64_t cr2;
482 struct
483 {
484 uint32_t cValidEntries;
485 uint32_t uAlignment;
486 uint32_t aField[VMCSCACHE_MAX_ENTRY];
487 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
488 } Write;
489 struct
490 {
491 uint32_t cValidEntries;
492 uint32_t uAlignment;
493 uint32_t aField[VMCSCACHE_MAX_ENTRY];
494 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
495 } Read;
496#ifdef DEBUG
497 struct
498 {
499 RTHCPHYS HCPhysCpuPage;
500 RTHCPHYS HCPhysVmcs;
501 RTGCPTR pCache;
502 RTGCPTR pCtx;
503 } TestIn;
504 struct
505 {
506 RTHCPHYS HCPhysVmcs;
507 RTGCPTR pCache;
508 RTGCPTR pCtx;
509 uint64_t eflags;
510 uint64_t cr8;
511 } TestOut;
512 struct
513 {
514 uint64_t param1;
515 uint64_t param2;
516 uint64_t param3;
517 uint64_t param4;
518 } ScratchPad;
519#endif
520} VMCSCACHE;
521/** Pointer to VMCSCACHE. */
522typedef VMCSCACHE *PVMCSCACHE;
523
524/** VMX StartVM function. */
525typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
526/** Pointer to a VMX StartVM function. */
527typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
528
529/** SVM VMRun function. */
530typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
531/** Pointer to a SVM VMRun function. */
532typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
533
534/**
535 * HM VMCPU Instance data.
536 */
537typedef struct HMCPU
538{
539 /** Old style FPU reporting trap mask override performed (optimization) */
540 bool fFPUOldStyleOverride;
541 /** Set if we don't have to flush the TLB on VM entry. */
542 bool fResumeVM;
543 /** Set if we need to flush the TLB during the world switch. */
544 bool fForceTLBFlush;
545 /** Set when we're using VT-x or AMD-V at that moment. */
546 bool fActive;
547 /** Set when the TLB has been checked until we return from the world switch. */
548 volatile bool fCheckedTLBFlush;
549 uint8_t u8Alignment[3];
550
551 /** World switch exit counter. */
552 volatile uint32_t cWorldSwitchExits;
553 /** HM_CHANGED_* flags. */
554 uint32_t fContextUseFlags;
555 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
556 RTCPUID idLastCpu;
557 /** TLB flush count */
558 uint32_t cTlbFlushes;
559 /** Current ASID in use by the VM */
560 uint32_t uCurrentAsid;
561 uint32_t u32Alignment;
562
563 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
564 uint64_t u64HostTscAux;
565
566 struct
567 {
568 /** Physical address of the VM control structure (VMCS). */
569 RTHCPHYS HCPhysVmcs;
570 /** R0 memory object for the VM control structure (VMCS). */
571 RTR0MEMOBJ hMemObjVmcs;
572 /** Virtual address of the VM control structure (VMCS). */
573 R0PTRTYPE(void *) pvVmcs;
574 /** Ring 0 handlers for VT-x. */
575 PFNHMVMXSTARTVM pfnStartVM;
576#if HC_ARCH_BITS == 32
577 uint32_t u32Alignment1;
578#endif
579
580 /** Current VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS. */
581 uint32_t u32PinCtls;
582 /** Current VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS. */
583 uint32_t u32ProcCtls;
584 /** Current VMX_VMCS32_CTRL_PROC_EXEC2_CONTROLS. */
585 uint32_t u32ProcCtls2;
586 /** Current VMX_VMCS32_CTRL_EXIT_CONTROLS. */
587 uint32_t u32ExitCtls;
588 /** Current VMX_VMCS32_CTRL_ENTRY_CONTROLS. */
589 uint32_t u32EntryCtls;
590 /** Physical address of the virtual APIC page for TPR caching. */
591 RTHCPHYS HCPhysVirtApic;
592 /** R0 memory object for the virtual APIC page for TPR caching. */
593 RTR0MEMOBJ hMemObjVirtApic;
594 /** Virtual address of the virtual APIC page for TPR caching. */
595 R0PTRTYPE(uint8_t *) pbVirtApic;
596#if HC_ARCH_BITS == 32
597 uint32_t u32Alignment2;
598#endif
599
600 /** Current CR0 mask. */
601 uint64_t cr0_mask;
602 /** Current CR4 mask. */
603 uint64_t cr4_mask;
604 /** Current exception bitmap. */
605 uint32_t u32XcptBitmap;
606 /** The updated-guest-state mask. */
607 uint32_t fUpdatedGuestState;
608 /** Current EPTP. */
609 RTHCPHYS HCPhysEPTP;
610
611 /** Physical address of the MSR bitmap. */
612 RTHCPHYS HCPhysMsrBitmap;
613 /** R0 memory object for the MSR bitmap. */
614 RTR0MEMOBJ hMemObjMsrBitmap;
615 /** Virtual address of the MSR bitmap. */
616 R0PTRTYPE(void *) pvMsrBitmap;
617
618#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
619 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
620 * for guest MSRs). */
621 RTHCPHYS HCPhysGuestMsr;
622 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
623 * (used for guest MSRs). */
624 RTR0MEMOBJ hMemObjGuestMsr;
625 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
626 * for guest MSRs). */
627 R0PTRTYPE(void *) pvGuestMsr;
628
629 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
630 RTHCPHYS HCPhysHostMsr;
631 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
632 RTR0MEMOBJ hMemObjHostMsr;
633 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
634 R0PTRTYPE(void *) pvHostMsr;
635
636 /** Number of automatically loaded/restored guest MSRs during the world switch. */
637 uint32_t cGuestMsrs;
638 uint32_t uAlignment;
639#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
640
641 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
642 uint64_t u64MsrApicBase;
643 /** Last use TSC offset value. (cached) */
644 uint64_t u64TSCOffset;
645 /** VMCS cache. */
646 VMCSCACHE VMCSCache;
647
648 /** Real-mode emulation state. */
649 struct
650 {
651 X86DESCATTR uAttrCS;
652 X86DESCATTR uAttrDS;
653 X86DESCATTR uAttrES;
654 X86DESCATTR uAttrFS;
655 X86DESCATTR uAttrGS;
656 X86DESCATTR uAttrSS;
657 X86EFLAGS eflags;
658 uint32_t fRealOnV86Active;
659 } RealMode;
660
661 struct
662 {
663 uint64_t u64VMCSPhys;
664 uint32_t u32VMCSRevision;
665 uint32_t u32InstrError;
666 uint32_t u32ExitReason;
667 RTCPUID idEnteredCpu;
668 RTCPUID idCurrentCpu;
669 uint32_t padding;
670 } lasterror;
671
672#ifdef VBOX_WITH_OLD_VTX_CODE
673 /** The last seen guest paging mode (by VT-x). */
674 PGMMODE enmLastSeenGuestMode;
675 /** Current guest paging mode (as seen by HMR3PagingModeChanged). */
676 PGMMODE enmCurrGuestMode;
677 /** Previous guest paging mode (as seen by HMR3PagingModeChanged). */
678 PGMMODE enmPrevGuestMode;
679#else
680 /** Set if guest was executing in real mode (extra checks). */
681 bool fWasInRealMode;
682#endif
683 } vmx;
684
685 struct
686 {
687 /** R0 memory object for the host VM control block (VMCB). */
688 RTR0MEMOBJ hMemObjVMCBHost;
689 /** Physical address of the host VM control block (VMCB). */
690 RTHCPHYS HCPhysVMCBHost;
691 /** Virtual address of the host VM control block (VMCB). */
692 R0PTRTYPE(void *) pvVMCBHost;
693
694 /** R0 memory object for the VM control block (VMCB). */
695 RTR0MEMOBJ hMemObjVMCB;
696 /** Physical address of the VM control block (VMCB). */
697 RTHCPHYS HCPhysVMCB;
698 /** Virtual address of the VM control block (VMCB). */
699 R0PTRTYPE(void *) pvVMCB;
700
701 /** Ring 0 handlers for VT-x. */
702 PFNHMSVMVMRUN pfnVMRun;
703
704 /** R0 memory object for the MSR bitmap (8kb). */
705 RTR0MEMOBJ hMemObjMsrBitmap;
706 /** Physical address of the MSR bitmap (8kb). */
707 RTHCPHYS HCPhysMsrBitmap;
708 /** Virtual address of the MSR bitmap. */
709 R0PTRTYPE(void *) pvMsrBitmap;
710 } svm;
711
712 /** Event injection state. */
713 struct
714 {
715 uint32_t fPending;
716 uint32_t u32ErrCode;
717 uint32_t cbInstr;
718 uint32_t u32Padding; /**< Explicit alignment padding. */
719 uint64_t u64IntrInfo;
720 RTGCUINTPTR GCPtrFaultAddress;
721 } Event;
722
723 /** IO Block emulation state. */
724 struct
725 {
726 bool fEnabled;
727 uint8_t u8Align[7];
728
729 /** RIP at the start of the io code we wish to emulate in the recompiler. */
730 RTGCPTR GCPtrFunctionEip;
731
732 uint64_t cr0;
733 } EmulateIoBlock;
734
735 struct
736 {
737 /** Pending IO operation type. */
738 HMPENDINGIO enmType;
739 uint32_t uPadding;
740 RTGCPTR GCPtrRip;
741 RTGCPTR GCPtrRipNext;
742 union
743 {
744 struct
745 {
746 uint32_t uPort;
747 uint32_t uAndVal;
748 uint32_t cbSize;
749 } Port;
750 uint64_t aRaw[2];
751 } s;
752 } PendingIO;
753
754 /** The PAE PDPEs used with Nested Paging (only valid when
755 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
756 X86PDPE aPdpes[4];
757
758 /** Current shadow paging mode. */
759 PGMMODE enmShadowMode;
760
761 /** The CPU ID of the CPU currently owning the VMCS. Set in
762 * HMR0Enter and cleared in HMR0Leave. */
763 RTCPUID idEnteredCpu;
764
765 /** To keep track of pending TLB shootdown pages. (SMP guest only) */
766 struct
767 {
768 RTGCPTR aPages[HM_MAX_TLB_SHOOTDOWN_PAGES];
769 uint32_t cPages;
770 uint32_t u32Padding; /**< Explicit alignment padding. */
771 } TlbShootdown;
772
773 /** For saving stack space, the disassembler state is allocated here instead of
774 * on the stack. */
775 DISCPUSTATE DisState;
776
777 STAMPROFILEADV StatEntry;
778 STAMPROFILEADV StatExit1;
779 STAMPROFILEADV StatExit2;
780 STAMPROFILEADV StatExitIO;
781 STAMPROFILEADV StatExitMovCRx;
782 STAMPROFILEADV StatExitXcptNmi;
783 STAMPROFILEADV StatLoadGuestState;
784 STAMPROFILEADV StatInGC;
785
786#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
787 STAMPROFILEADV StatWorldSwitch3264;
788#endif
789 STAMPROFILEADV StatPoke;
790 STAMPROFILEADV StatSpinPoke;
791 STAMPROFILEADV StatSpinPokeFailed;
792
793 STAMCOUNTER StatIntInject;
794
795 STAMCOUNTER StatExitShadowNM;
796 STAMCOUNTER StatExitGuestNM;
797 STAMCOUNTER StatExitShadowPF; /* Misleading, currently used for MMIO #PFs as well. */
798 STAMCOUNTER StatExitShadowPFEM;
799 STAMCOUNTER StatExitGuestPF;
800 STAMCOUNTER StatExitGuestUD;
801 STAMCOUNTER StatExitGuestSS;
802 STAMCOUNTER StatExitGuestNP;
803 STAMCOUNTER StatExitGuestGP;
804 STAMCOUNTER StatExitGuestDE;
805 STAMCOUNTER StatExitGuestDB;
806 STAMCOUNTER StatExitGuestMF;
807 STAMCOUNTER StatExitGuestBP;
808 STAMCOUNTER StatExitGuestXF;
809 STAMCOUNTER StatExitGuestXcpUnk;
810 STAMCOUNTER StatExitInvlpg;
811 STAMCOUNTER StatExitInvd;
812 STAMCOUNTER StatExitWbinvd;
813 STAMCOUNTER StatExitPause;
814 STAMCOUNTER StatExitCpuid;
815 STAMCOUNTER StatExitRdtsc;
816 STAMCOUNTER StatExitRdtscp;
817 STAMCOUNTER StatExitRdpmc;
818 STAMCOUNTER StatExitRdrand;
819 STAMCOUNTER StatExitCli;
820 STAMCOUNTER StatExitSti;
821 STAMCOUNTER StatExitPushf;
822 STAMCOUNTER StatExitPopf;
823 STAMCOUNTER StatExitIret;
824 STAMCOUNTER StatExitInt;
825 STAMCOUNTER StatExitCRxWrite[16];
826 STAMCOUNTER StatExitCRxRead[16];
827 STAMCOUNTER StatExitDRxWrite;
828 STAMCOUNTER StatExitDRxRead;
829 STAMCOUNTER StatExitRdmsr;
830 STAMCOUNTER StatExitWrmsr;
831 STAMCOUNTER StatExitClts;
832 STAMCOUNTER StatExitXdtrAccess;
833 STAMCOUNTER StatExitHlt;
834 STAMCOUNTER StatExitMwait;
835 STAMCOUNTER StatExitMonitor;
836 STAMCOUNTER StatExitLmsw;
837 STAMCOUNTER StatExitIOWrite;
838 STAMCOUNTER StatExitIORead;
839 STAMCOUNTER StatExitIOStringWrite;
840 STAMCOUNTER StatExitIOStringRead;
841 STAMCOUNTER StatExitIntWindow;
842 STAMCOUNTER StatExitMaxResume;
843 STAMCOUNTER StatExitExtInt;
844 STAMCOUNTER StatExitPreemptTimer;
845 STAMCOUNTER StatExitTprBelowThreshold;
846 STAMCOUNTER StatExitTaskSwitch;
847 STAMCOUNTER StatExitMtf;
848 STAMCOUNTER StatExitApicAccess;
849 STAMCOUNTER StatIntReinject;
850 STAMCOUNTER StatPendingHostIrq;
851
852 STAMCOUNTER StatFlushPage;
853 STAMCOUNTER StatFlushPageManual;
854 STAMCOUNTER StatFlushPhysPageManual;
855 STAMCOUNTER StatFlushTlb;
856 STAMCOUNTER StatFlushTlbManual;
857 STAMCOUNTER StatFlushTlbWorldSwitch;
858 STAMCOUNTER StatNoFlushTlbWorldSwitch;
859 STAMCOUNTER StatFlushAsid;
860 STAMCOUNTER StatFlushNestedPaging;
861 STAMCOUNTER StatFlushTlbInvlpgVirt;
862 STAMCOUNTER StatFlushTlbInvlpgPhys;
863 STAMCOUNTER StatTlbShootdown;
864 STAMCOUNTER StatTlbShootdownFlush;
865
866 STAMCOUNTER StatSwitchGuestIrq;
867 STAMCOUNTER StatSwitchHmToR3FF;
868 STAMCOUNTER StatSwitchExitToR3;
869 STAMCOUNTER StatSwitchLongJmpToR3;
870
871 STAMCOUNTER StatTscOffset;
872 STAMCOUNTER StatTscIntercept;
873 STAMCOUNTER StatTscInterceptOverFlow;
874
875 STAMCOUNTER StatExitReasonNpf;
876 STAMCOUNTER StatDRxArmed;
877 STAMCOUNTER StatDRxContextSwitch;
878 STAMCOUNTER StatDRxIoCheck;
879
880 STAMCOUNTER StatLoadMinimal;
881 STAMCOUNTER StatLoadFull;
882
883#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
884 STAMCOUNTER StatFpu64SwitchBack;
885 STAMCOUNTER StatDebug64SwitchBack;
886#endif
887
888#ifdef VBOX_WITH_STATISTICS
889 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
890 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
891 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
892 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
893#endif
894#ifdef HM_PROFILE_EXIT_DISPATCH
895 STAMPROFILEADV StatExitDispatch;
896#endif
897} HMCPU;
898/** Pointer to HM VM instance data. */
899typedef HMCPU *PHMCPU;
900
901
902#ifdef IN_RING0
903
904VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpu(void);
905VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
906
907
908#ifdef VBOX_STRICT
909VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
910VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
911#else
912# define HMDumpRegs(a, b ,c) do { } while (0)
913# define HMR0DumpDescriptor(a, b, c) do { } while (0)
914#endif
915
916# ifdef VBOX_WITH_KERNEL_USING_XMM
917DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
918DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
919# endif
920
921# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
922/**
923 * Gets 64-bit GDTR and IDTR on darwin.
924 * @param pGdtr Where to store the 64-bit GDTR.
925 * @param pIdtr Where to store the 64-bit IDTR.
926 */
927DECLASM(void) hmR0Get64bitGdtrAndIdtr(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
928
929/**
930 * Gets 64-bit CR3 on darwin.
931 * @returns CR3
932 */
933DECLASM(uint64_t) hmR0Get64bitCR3(void);
934# endif
935
936#endif /* IN_RING0 */
937
938/** @} */
939
940RT_C_DECLS_END
941
942#endif
943
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