HMInternal.h@ 69288

Last change on this file since 69288 was 69142, checked in by vboxsync, 7 years ago
VMM: Nested Hw.virt: SVM fixes.
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1	/* $Id: HMInternal.h 69142 2017-10-20 09:59:27Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/pgm.h>
30	#include <VBox/vmm/cpum.h>
31	#include <VBox/vmm/trpm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35	#include <iprt/avl.h>
36	#include <iprt/string.h>
37
38	#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
39	# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
40	#endif
41
42	#if HC_ARCH_BITS == 64 \|\| defined (VBOX_WITH_64_BITS_GUESTS)
43	/* Enable 64 bits guest support. */
44	# define VBOX_ENABLE_64_BITS_GUESTS
45	#endif
46
47	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
48	# define VMX_USE_CACHED_VMCS_ACCESSES
49	#endif
50
51	/** @def HM_PROFILE_EXIT_DISPATCH
52	* Enables profiling of the VM exit handler dispatching. */
53	#if 0 \|\| defined(DOXYGEN_RUNNING)
54	# define HM_PROFILE_EXIT_DISPATCH
55	#endif
56
57	RT_C_DECLS_BEGIN
58
59
60	/** @defgroup grp_hm_int Internal
61	* @ingroup grp_hm
62	* @internal
63	* @{
64	*/
65
66	/** @def HMCPU_CF_CLEAR
67	* Clears a HM-context flag.
68	*
69	* @param pVCpu The cross context virtual CPU structure.
70	* @param fFlag The flag to clear.
71	*/
72	#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
73
74	/** @def HMCPU_CF_SET
75	* Sets a HM-context flag.
76	*
77	* @param pVCpu The cross context virtual CPU structure.
78	* @param fFlag The flag to set.
79	*/
80	#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
81
82	/** @def HMCPU_CF_IS_SET
83	* Checks if all the flags in the specified HM-context set is pending.
84	*
85	* @param pVCpu The cross context virtual CPU structure.
86	* @param fFlag The flag to check.
87	*/
88	#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
89
90	/** @def HMCPU_CF_IS_PENDING
91	* Checks if one or more of the flags in the specified HM-context set is
92	* pending.
93	*
94	* @param pVCpu The cross context virtual CPU structure.
95	* @param fFlags The flags to check for.
96	*/
97	#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
98
99	/** @def HMCPU_CF_IS_PENDING_ONLY
100	* Checks if -only- one or more of the specified HM-context flags is pending.
101	*
102	* @param pVCpu The cross context virtual CPU structure.
103	* @param fFlags The flags to check for.
104	*/
105	#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
106
107	/** @def HMCPU_CF_IS_SET_ONLY
108	* Checks if -only- all the flags in the specified HM-context set is pending.
109	*
110	* @param pVCpu The cross context virtual CPU structure.
111	* @param fFlags The flags to check for.
112	*/
113	#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
114
115	/** @def HMCPU_CF_RESET_TO
116	* Resets the HM-context flags to the specified value.
117	*
118	* @param pVCpu The cross context virtual CPU structure.
119	* @param fFlags The new value.
120	*/
121	#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
122
123	/** @def HMCPU_CF_VALUE
124	* Returns the current HM-context flags value.
125	*
126	* @param pVCpu The cross context virtual CPU structure.
127	*/
128	#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
129
130
131	/** Resets/initializes the VM-exit/\#VMEXIT history array. */
132	#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
133
134	/** Updates the VM-exit/\#VMEXIT history array. */
135	#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
136	do { \
137	AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
138	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
139	if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
140	(pVCpu)->hm.s.idxExitHistoryFree = 0; \
141	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
142	} while (0)
143
144	/** Maximum number of exit reason statistics counters. */
145	#define MAX_EXITREASON_STAT 0x100
146	#define MASK_EXITREASON_STAT 0xff
147	#define MASK_INJECT_IRQ_STAT 0xff
148
149	/** @name HM changed flags.
150	* These flags are used to keep track of which important registers that have
151	* been changed since last they were reset.
152	*
153	* Flags marked "shared" are used for registers that are common to both the host
154	* and guest (i.e. without dedicated VMCS/VMCB fields for guest bits).
155	*
156	* @{
157	*/
158	#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
159	#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
160	#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
161	#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
162	#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
163	#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
164	#define HM_CHANGED_GUEST_TR RT_BIT(6)
165	#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
166	#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
167	#define HM_CHANGED_GUEST_RIP RT_BIT(9)
168	#define HM_CHANGED_GUEST_RSP RT_BIT(10)
169	#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
170	#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
171	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
172	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
173	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
174	#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
175	#define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(17) /* Shared / /* @todo Move this to VT-x specific? */
176	#define HM_CHANGED_GUEST_XCPT_INTERCEPTS RT_BIT(18)
177	/* VT-x specific state. */
178	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(19)
179	#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(20)
180	#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(21)
181	#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(22)
182	#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(23)
183	/* AMD-V specific state. */
184	#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(19)
185	#define HM_CHANGED_SVM_RESERVED1 RT_BIT(20)
186	#define HM_CHANGED_SVM_RESERVED2 RT_BIT(21)
187	#define HM_CHANGED_SVM_RESERVED3 RT_BIT(22)
188	#define HM_CHANGED_SVM_RESERVED4 RT_BIT(23)
189
190	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
191	\| HM_CHANGED_GUEST_CR3 \
192	\| HM_CHANGED_GUEST_CR4 \
193	\| HM_CHANGED_GUEST_GDTR \
194	\| HM_CHANGED_GUEST_IDTR \
195	\| HM_CHANGED_GUEST_LDTR \
196	\| HM_CHANGED_GUEST_TR \
197	\| HM_CHANGED_GUEST_SEGMENT_REGS \
198	\| HM_CHANGED_GUEST_DEBUG \
199	\| HM_CHANGED_GUEST_RIP \
200	\| HM_CHANGED_GUEST_RSP \
201	\| HM_CHANGED_GUEST_RFLAGS \
202	\| HM_CHANGED_GUEST_CR2 \
203	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR \
204	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
205	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
206	\| HM_CHANGED_GUEST_EFER_MSR \
207	\| HM_CHANGED_GUEST_LAZY_MSRS \
208	\| HM_CHANGED_GUEST_XCPT_INTERCEPTS \
209	\| HM_CHANGED_VMX_GUEST_AUTO_MSRS \
210	\| HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
211	\| HM_CHANGED_VMX_GUEST_APIC_STATE \
212	\| HM_CHANGED_VMX_ENTRY_CTLS \
213	\| HM_CHANGED_VMX_EXIT_CTLS)
214
215	#define HM_CHANGED_HOST_CONTEXT RT_BIT(24)
216
217	/* Bits shared between host and guest. */
218	#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
219	\| HM_CHANGED_GUEST_DEBUG \
220	\| HM_CHANGED_GUEST_LAZY_MSRS)
221	/** @} */
222
223	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
224	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
225	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
226	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
227	/** Total guest mapped memory needed. */
228	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
229
230
231	/** @name Macros for enabling and disabling preemption.
232	* These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
233	* preemption has already been disabled when there is no context hook.
234	* @{ */
235	#ifdef VBOX_STRICT
236	# define HM_DISABLE_PREEMPT() \
237	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
238	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) \|\| VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
239	RTThreadPreemptDisable(&PreemptStateInternal)
240	#else
241	# define HM_DISABLE_PREEMPT() \
242	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
243	RTThreadPreemptDisable(&PreemptStateInternal)
244	#endif /* VBOX_STRICT */
245	#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
246	/** @} */
247
248
249	/** Enable for TPR guest patching. */
250	#define VBOX_HM_WITH_GUEST_PATCHING
251
252	/** @name HM saved state versions
253	* @{
254	*/
255	#ifdef VBOX_HM_WITH_GUEST_PATCHING
256	# define HM_SAVED_STATE_VERSION 5
257	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
258	#else
259	# define HM_SAVED_STATE_VERSION 4
260	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
261	#endif
262	#define HM_SAVED_STATE_VERSION_2_0_X 3
263	/** @} */
264
265	/**
266	* Global per-cpu information. (host)
267	*/
268	typedef struct HMGLOBALCPUINFO
269	{
270	/** The CPU ID. */
271	RTCPUID idCpu;
272	/** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
273	RTR0MEMOBJ hMemObj;
274	/** The physical address of the first page in hMemObj (it's a
275	* physcially contigous allocation if it spans multiple pages). */
276	RTHCPHYS HCPhysMemObj;
277	/** The address of the memory (for pfnEnable). */
278	void *pvMemObj;
279	/** Current ASID (AMD-V) / VPID (Intel). */
280	uint32_t uCurrentAsid;
281	/** TLB flush count. */
282	uint32_t cTlbFlushes;
283	/** Whether to flush each new ASID/VPID before use. */
284	bool fFlushAsidBeforeUse;
285	/** Configured for VT-x or AMD-V. */
286	bool fConfigured;
287	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
288	bool fIgnoreAMDVInUseError;
289	/** In use by our code. (for power suspend) */
290	volatile bool fInUse;
291	} HMGLOBALCPUINFO;
292	/** Pointer to the per-cpu global information. */
293	typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
294
295	typedef enum
296	{
297	HMPENDINGIO_INVALID = 0,
298	HMPENDINGIO_PORT_READ,
299	/* not implemented: HMPENDINGIO_STRING_READ, */
300	/* not implemented: HMPENDINGIO_STRING_WRITE, */
301	/** The usual 32-bit paranoia. */
302	HMPENDINGIO_32BIT_HACK = 0x7fffffff
303	} HMPENDINGIO;
304
305
306	typedef enum
307	{
308	HMTPRINSTR_INVALID,
309	HMTPRINSTR_READ,
310	HMTPRINSTR_READ_SHR4,
311	HMTPRINSTR_WRITE_REG,
312	HMTPRINSTR_WRITE_IMM,
313	HMTPRINSTR_JUMP_REPLACEMENT,
314	/** The usual 32-bit paranoia. */
315	HMTPRINSTR_32BIT_HACK = 0x7fffffff
316	} HMTPRINSTR;
317
318	typedef struct
319	{
320	/** The key is the address of patched instruction. (32 bits GC ptr) */
321	AVLOU32NODECORE Core;
322	/** Original opcode. */
323	uint8_t aOpcode[16];
324	/** Instruction size. */
325	uint32_t cbOp;
326	/** Replacement opcode. */
327	uint8_t aNewOpcode[16];
328	/** Replacement instruction size. */
329	uint32_t cbNewOp;
330	/** Instruction type. */
331	HMTPRINSTR enmType;
332	/** Source operand. */
333	uint32_t uSrcOperand;
334	/** Destination operand. */
335	uint32_t uDstOperand;
336	/** Number of times the instruction caused a fault. */
337	uint32_t cFaults;
338	/** Patch address of the jump replacement. */
339	RTGCPTR32 pJumpTarget;
340	} HMTPRPATCH;
341	/** Pointer to HMTPRPATCH. */
342	typedef HMTPRPATCH *PHMTPRPATCH;
343
344
345	/**
346	* Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
347	*
348	* @returns 64-bit key
349	* @param a_uPC The RIP + CS.BASE value of the exit.
350	* @param a_uExit The exit code.
351	* @todo Add CPL?
352	*/
353	#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) \| (uint64_t)(a_uExit) << 48)
354
355	typedef struct HMEXITINFO
356	{
357	/** See HMEXITSTAT_MAKE_KEY(). */
358	uint64_t uKey;
359	/** Number of recent hits (depreciates with time). */
360	uint32_t volatile cHits;
361	/** The age + lock. */
362	uint16_t volatile uAge;
363	/** Action or action table index. */
364	uint16_t iAction;
365	} HMEXITINFO;
366	AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
367
368	typedef struct HMEXITHISTORY
369	{
370	/** The exit timestamp. */
371	uint64_t uTscExit;
372	/** The index of the corresponding HMEXITINFO entry.
373	* UINT32_MAX if none (too many collisions, race, whatever). */
374	uint32_t iExitInfo;
375	/** Figure out later, needed for padding now. */
376	uint32_t uSomeClueOrSomething;
377	} HMEXITHISTORY;
378
379	/**
380	* Switcher function, HC to the special 64-bit RC.
381	*
382	* @param pVM The cross context VM structure.
383	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
384	* @returns Return code indicating the action to take.
385	*/
386	typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
387	/** Pointer to switcher function. */
388	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
389
390	/**
391	* HM VM Instance data.
392	* Changes to this must checked against the padding of the hm union in VM!
393	*/
394	typedef struct HM
395	{
396	/** Set when we've initialized VMX or SVM. */
397	bool fInitialized;
398	/** Set if nested paging is enabled. */
399	bool fNestedPaging;
400	/** Set if nested paging is allowed. */
401	bool fAllowNestedPaging;
402	/** Set if large pages are enabled (requires nested paging). */
403	bool fLargePages;
404	/** Set if we can support 64-bit guests or not. */
405	bool fAllow64BitGuests;
406	/** Set when TPR patching is allowed. */
407	bool fTprPatchingAllowed;
408	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
409	bool fGlobalInit;
410	/** Set when TPR patching is active. */
411	bool fTPRPatchingActive;
412	/** Set when the debug facility has breakpoints/events enabled that requires
413	* us to use the debug execution loop in ring-0. */
414	bool fUseDebugLoop;
415	/** Set if hardware APIC virtualization is enabled. */
416	bool fVirtApicRegs;
417	/** Set if posted interrupt processing is enabled. */
418	bool fPostedIntrs;
419	/** Alignment. */
420	bool fAlignment0;
421
422	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
423	uint32_t fHostKernelFeatures;
424
425	/** Maximum ASID allowed. */
426	uint32_t uMaxAsid;
427	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
428	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
429	uint32_t cMaxResumeLoops;
430
431	/** Guest allocated memory for patching purposes. */
432	RTGCPTR pGuestPatchMem;
433	/** Current free pointer inside the patch block. */
434	RTGCPTR pFreeGuestPatchMem;
435	/** Size of the guest patch memory block. */
436	uint32_t cbGuestPatchMem;
437	uint32_t u32Alignment0;
438
439	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
440	/** 32 to 64 bits switcher entrypoint. */
441	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
442	RTR0PTR pvR0Alignment0;
443	#endif
444
445	struct
446	{
447	/** Set by the ring-0 side of HM to indicate VMX is supported by the
448	* CPU. */
449	bool fSupported;
450	/** Set when we've enabled VMX. */
451	bool fEnabled;
452	/** Set if VPID is supported. */
453	bool fVpid;
454	/** Set if VT-x VPID is allowed. */
455	bool fAllowVpid;
456	/** Set if unrestricted guest execution is in use (real and protected mode without paging). */
457	bool fUnrestrictedGuest;
458	/** Set if unrestricted guest execution is allowed to be used. */
459	bool fAllowUnrestricted;
460	/** Whether we're using the preemption timer or not. */
461	bool fUsePreemptTimer;
462	/** The shift mask employed by the VMX-Preemption timer. */
463	uint8_t cPreemptTimerShift;
464
465	/** Virtual address of the TSS page used for real mode emulation. */
466	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
467	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
468	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
469
470	/** Physical address of the APIC-access page. */
471	RTHCPHYS HCPhysApicAccess;
472	/** R0 memory object for the APIC-access page. */
473	RTR0MEMOBJ hMemObjApicAccess;
474	/** Virtual address of the APIC-access page. */
475	R0PTRTYPE(uint8_t *) pbApicAccess;
476
477	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
478	RTHCPHYS HCPhysScratch;
479	RTR0MEMOBJ hMemObjScratch;
480	R0PTRTYPE(uint8_t *) pbScratch;
481	#endif
482
483	/** Internal Id of which flush-handler to use for tagged-TLB entries. */
484	uint32_t uFlushTaggedTlb;
485
486	/** Pause-loop exiting (PLE) gap in ticks. */
487	uint32_t cPleGapTicks;
488	/** Pause-loop exiting (PLE) window in ticks. */
489	uint32_t cPleWindowTicks;
490	uint32_t u32Alignment0;
491
492	/** Host CR4 value (set by ring-0 VMX init) */
493	uint64_t u64HostCr4;
494	/** Host SMM monitor control (set by ring-0 VMX init) */
495	uint64_t u64HostSmmMonitorCtl;
496	/** Host EFER value (set by ring-0 VMX init) */
497	uint64_t u64HostEfer;
498	/** Whether the CPU supports VMCS fields for swapping EFER. */
499	bool fSupportsVmcsEfer;
500	uint8_t u8Alignment2[7];
501
502	/** VMX MSR values. */
503	VMXMSRS Msrs;
504
505	/** Flush types for invept & invvpid; they depend on capabilities. */
506	VMXFLUSHEPT enmFlushEpt;
507	VMXFLUSHVPID enmFlushVpid;
508
509	/** Host-physical address for a failing VMXON instruction. */
510	RTHCPHYS HCPhysVmxEnableError;
511	} vmx;
512
513	struct
514	{
515	/** Set by the ring-0 side of HM to indicate SVM is supported by the
516	* CPU. */
517	bool fSupported;
518	/** Set when we've enabled SVM. */
519	bool fEnabled;
520	/** Set if erratum 170 affects the AMD cpu. */
521	bool fAlwaysFlushTLB;
522	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
523	bool fIgnoreInUseError;
524	uint8_t u8Alignment0[4];
525
526	/** Physical address of the IO bitmap (12kb). */
527	RTHCPHYS HCPhysIOBitmap;
528	/** R0 memory object for the IO bitmap (12kb). */
529	RTR0MEMOBJ hMemObjIOBitmap;
530	/** Virtual address of the IO bitmap. */
531	R0PTRTYPE(void *) pvIOBitmap;
532
533	/* HWCR MSR (for diagnostics) */
534	uint64_t u64MsrHwcr;
535
536	/** SVM revision. */
537	uint32_t u32Rev;
538	/** SVM feature bits from cpuid 0x8000000a */
539	uint32_t u32Features;
540
541	/** Pause filter counter. */
542	uint16_t cPauseFilter;
543	/** Pause filter treshold in ticks. */
544	uint16_t cPauseFilterThresholdTicks;
545	uint32_t u32Alignment0;
546	} svm;
547
548	/**
549	* AVL tree with all patches (active or disabled) sorted by guest instruction
550	* address.
551	*/
552	AVLOU32TREE PatchTree;
553	uint32_t cPatches;
554	HMTPRPATCH aPatches[64];
555
556	struct
557	{
558	uint32_t u32AMDFeatureECX;
559	uint32_t u32AMDFeatureEDX;
560	} cpuid;
561
562	/** Saved error from detection */
563	int32_t lLastError;
564
565	/** HMR0Init was run */
566	bool fHMR0Init;
567	bool u8Alignment1[3];
568
569	STAMCOUNTER StatTprPatchSuccess;
570	STAMCOUNTER StatTprPatchFailure;
571	STAMCOUNTER StatTprReplaceSuccessCr8;
572	STAMCOUNTER StatTprReplaceSuccessVmc;
573	STAMCOUNTER StatTprReplaceFailure;
574	} HM;
575	/** Pointer to HM VM instance data. */
576	typedef HM *PHM;
577
578	AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
579
580	/* Maximum number of cached entries. */
581	#define VMCSCACHE_MAX_ENTRY 128
582
583	/**
584	* Structure for storing read and write VMCS actions.
585	*/
586	typedef struct VMCSCACHE
587	{
588	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
589	/* Magic marker for searching in crash dumps. */
590	uint8_t aMagic[16];
591	uint64_t uMagic;
592	uint64_t u64TimeEntry;
593	uint64_t u64TimeSwitch;
594	uint64_t cResume;
595	uint64_t interPD;
596	uint64_t pSwitcher;
597	uint32_t uPos;
598	uint32_t idCpu;
599	#endif
600	/* CR2 is saved here for EPT syncing. */
601	uint64_t cr2;
602	struct
603	{
604	uint32_t cValidEntries;
605	uint32_t uAlignment;
606	uint32_t aField[VMCSCACHE_MAX_ENTRY];
607	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
608	} Write;
609	struct
610	{
611	uint32_t cValidEntries;
612	uint32_t uAlignment;
613	uint32_t aField[VMCSCACHE_MAX_ENTRY];
614	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
615	} Read;
616	#ifdef VBOX_STRICT
617	struct
618	{
619	RTHCPHYS HCPhysCpuPage;
620	RTHCPHYS HCPhysVmcs;
621	RTGCPTR pCache;
622	RTGCPTR pCtx;
623	} TestIn;
624	struct
625	{
626	RTHCPHYS HCPhysVmcs;
627	RTGCPTR pCache;
628	RTGCPTR pCtx;
629	uint64_t eflags;
630	uint64_t cr8;
631	} TestOut;
632	struct
633	{
634	uint64_t param1;
635	uint64_t param2;
636	uint64_t param3;
637	uint64_t param4;
638	} ScratchPad;
639	#endif
640	} VMCSCACHE;
641	/** Pointer to VMCSCACHE. */
642	typedef VMCSCACHE *PVMCSCACHE;
643	AssertCompileSizeAlignment(VMCSCACHE, 8);
644
645	/**
646	* VMX StartVM function.
647	*
648	* @returns VBox status code (no informational stuff).
649	* @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
650	* @param pCtx The CPU register context.
651	* @param pCache The VMCS cache.
652	* @param pVM Pointer to the cross context VM structure.
653	* @param pVCpu Pointer to the cross context per-CPU structure.
654	*/
655	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
656	/** Pointer to a VMX StartVM function. */
657	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
658
659	/** SVM VMRun function. */
660	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
661	/** Pointer to a SVM VMRun function. */
662	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
663
664	/**
665	* HM VMCPU Instance data.
666	*
667	* Note! If you change members of this struct, make sure to check if the
668	* assembly counterpart in HMInternal.mac needs to be updated as well.
669	*/
670	typedef struct HMCPU
671	{
672	/** Set if we need to flush the TLB during the world switch. */
673	bool fForceTLBFlush;
674	/** Set when we're using VT-x or AMD-V at that moment. */
675	bool fActive;
676	/** Set when the TLB has been checked until we return from the world switch. */
677	volatile bool fCheckedTLBFlush;
678	/** Whether we've completed the inner HM leave function. */
679	bool fLeaveDone;
680	/** Whether we're using the hyper DR7 or guest DR7. */
681	bool fUsingHyperDR7;
682	/** Whether to preload the guest-FPU state to avoid \#NM VM-exit overhead. */
683	bool fPreloadGuestFpu;
684	/** Set if XCR0 needs to be loaded and saved when entering and exiting guest
685	* code execution. */
686	bool fLoadSaveGuestXcr0;
687
688	/** Whether we should use the debug loop because of single stepping or special
689	* debug breakpoints / events are armed. */
690	bool fUseDebugLoop;
691	/** Whether we are currently executing in the debug loop.
692	* Mainly for assertions. */
693	bool fUsingDebugLoop;
694	/** Set if we using the debug loop and wish to intercept RDTSC. */
695	bool fDebugWantRdTscExit;
696	/** Whether we're executing a single instruction. */
697	bool fSingleInstruction;
698	/** Set if we need to clear the trap flag because of single stepping. */
699	bool fClearTrapFlag;
700
701	/** Whether \#UD needs to be intercepted (required by certain GIM providers). */
702	bool fGIMTrapXcptUD;
703	/** Whether paravirt. hypercalls are enabled. */
704	bool fHypercallsEnabled;
705	uint8_t u8Alignment0[2];
706
707	/** World switch exit counter. */
708	volatile uint32_t cWorldSwitchExits;
709	/** HM_CHANGED_* flags. */
710	volatile uint32_t fContextUseFlags;
711	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
712	* time). */
713	RTCPUID idLastCpu;
714	/** TLB flush count. */
715	uint32_t cTlbFlushes;
716	/** Current ASID in use by the VM. */
717	uint32_t uCurrentAsid;
718	/** An additional error code used for some gurus. */
719	uint32_t u32HMError;
720	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
721	uint64_t u64HostTscAux;
722
723	struct
724	{
725	/** Ring 0 handlers for VT-x. */
726	PFNHMVMXSTARTVM pfnStartVM;
727	#if HC_ARCH_BITS == 32
728	uint32_t u32Alignment0;
729	#endif
730	/** Current VMX_VMCS32_CTRL_PIN_EXEC. */
731	uint32_t u32PinCtls;
732	/** Current VMX_VMCS32_CTRL_PROC_EXEC. */
733	uint32_t u32ProcCtls;
734	/** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
735	uint32_t u32ProcCtls2;
736	/** Current VMX_VMCS32_CTRL_EXIT. */
737	uint32_t u32ExitCtls;
738	/** Current VMX_VMCS32_CTRL_ENTRY. */
739	uint32_t u32EntryCtls;
740
741	/** Current CR0 mask. */
742	uint32_t u32CR0Mask;
743	/** Current CR4 mask. */
744	uint32_t u32CR4Mask;
745	/** Current exception bitmap. */
746	uint32_t u32XcptBitmap;
747	/** The updated-guest-state mask. */
748	volatile uint32_t fUpdatedGuestState;
749	uint32_t u32Alignment1;
750
751	/** Physical address of the VM control structure (VMCS). */
752	RTHCPHYS HCPhysVmcs;
753	/** R0 memory object for the VM control structure (VMCS). */
754	RTR0MEMOBJ hMemObjVmcs;
755	/** Virtual address of the VM control structure (VMCS). */
756	R0PTRTYPE(void *) pvVmcs;
757
758	/** Physical address of the virtual APIC page for TPR caching. */
759	RTHCPHYS HCPhysVirtApic;
760	/** Padding. */
761	R0PTRTYPE(void *) pvAlignment0;
762	/** Virtual address of the virtual APIC page for TPR caching. */
763	R0PTRTYPE(uint8_t *) pbVirtApic;
764
765	/** Physical address of the MSR bitmap. */
766	RTHCPHYS HCPhysMsrBitmap;
767	/** R0 memory object for the MSR bitmap. */
768	RTR0MEMOBJ hMemObjMsrBitmap;
769	/** Virtual address of the MSR bitmap. */
770	R0PTRTYPE(void *) pvMsrBitmap;
771
772	/** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
773	* for guest MSRs). */
774	RTHCPHYS HCPhysGuestMsr;
775	/** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
776	* (used for guest MSRs). */
777	RTR0MEMOBJ hMemObjGuestMsr;
778	/** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
779	* for guest MSRs). */
780	R0PTRTYPE(void *) pvGuestMsr;
781
782	/** Physical address of the VM-exit MSR-load area (used for host MSRs). */
783	RTHCPHYS HCPhysHostMsr;
784	/** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
785	RTR0MEMOBJ hMemObjHostMsr;
786	/** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
787	R0PTRTYPE(void *) pvHostMsr;
788
789	/** Current EPTP. */
790	RTHCPHYS HCPhysEPTP;
791
792	/** Number of guest/host MSR pairs in the auto-load/store area. */
793	uint32_t cMsrs;
794	/** Whether the host MSR values are up-to-date in the auto-load/store area. */
795	bool fUpdatedHostMsrs;
796	uint8_t u8Alignment0[3];
797
798	/** Host LSTAR MSR value to restore lazily while leaving VT-x. */
799	uint64_t u64HostLStarMsr;
800	/** Host STAR MSR value to restore lazily while leaving VT-x. */
801	uint64_t u64HostStarMsr;
802	/** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
803	uint64_t u64HostSFMaskMsr;
804	/** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
805	uint64_t u64HostKernelGSBaseMsr;
806	/** A mask of which MSRs have been swapped and need restoration. */
807	uint32_t fLazyMsrs;
808	uint32_t u32Alignment2;
809
810	/** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
811	uint64_t u64MsrApicBase;
812	/** Last use TSC offset value. (cached) */
813	uint64_t u64TSCOffset;
814
815	/** VMCS cache. */
816	VMCSCACHE VMCSCache;
817
818	/** Real-mode emulation state. */
819	struct
820	{
821	X86DESCATTR AttrCS;
822	X86DESCATTR AttrDS;
823	X86DESCATTR AttrES;
824	X86DESCATTR AttrFS;
825	X86DESCATTR AttrGS;
826	X86DESCATTR AttrSS;
827	X86EFLAGS Eflags;
828	uint32_t fRealOnV86Active;
829	} RealMode;
830
831	/** VT-x error-reporting (mainly for ring-3 propagation). */
832	struct
833	{
834	uint64_t u64VMCSPhys;
835	uint32_t u32VMCSRevision;
836	uint32_t u32InstrError;
837	uint32_t u32ExitReason;
838	RTCPUID idEnteredCpu;
839	RTCPUID idCurrentCpu;
840	uint32_t u32Alignment0;
841	} LastError;
842
843	/** Current state of the VMCS. */
844	uint32_t uVmcsState;
845	/** Which host-state bits to restore before being preempted. */
846	uint32_t fRestoreHostFlags;
847	/** The host-state restoration structure. */
848	VMXRESTOREHOST RestoreHost;
849
850	/** Set if guest was executing in real mode (extra checks). */
851	bool fWasInRealMode;
852	/** Set if guest switched to 64-bit mode on a 32-bit host. */
853	bool fSwitchedTo64on32;
854
855	uint8_t u8Alignment1[6];
856	} vmx;
857
858	struct
859	{
860	/** Ring 0 handlers for VT-x. */
861	PFNHMSVMVMRUN pfnVMRun;
862	#if HC_ARCH_BITS == 32
863	uint32_t u32Alignment0;
864	#endif
865
866	/** Physical address of the host VMCB which holds additional host-state. */
867	RTHCPHYS HCPhysVmcbHost;
868	/** R0 memory object for the host VMCB which holds additional host-state. */
869	RTR0MEMOBJ hMemObjVmcbHost;
870	/** Padding. */
871	R0PTRTYPE(void *) pvPadding;
872
873	/** Physical address of the guest VMCB. */
874	RTHCPHYS HCPhysVmcb;
875	/** R0 memory object for the guest VMCB. */
876	RTR0MEMOBJ hMemObjVmcb;
877	/** Pointer to the guest VMCB. */
878	R0PTRTYPE(PSVMVMCB) pVmcb;
879
880	/** Physical address of the MSR bitmap (8 KB). */
881	RTHCPHYS HCPhysMsrBitmap;
882	/** R0 memory object for the MSR bitmap (8 KB). */
883	RTR0MEMOBJ hMemObjMsrBitmap;
884	/** Pointer to the MSR bitmap. */
885	R0PTRTYPE(void *) pvMsrBitmap;
886
887	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
888	* we should check if the VTPR changed on every VM-exit. */
889	bool fSyncVTpr;
890	uint8_t u8Alignment0[7];
891
892	/** Cache of the nested-guest's VMCB fields that we modify in order to run the
893	* nested-guest using AMD-V. This will be restored on \#VMEXIT. */
894	SVMNESTEDVMCBCACHE NstGstVmcbCache;
895	} svm;
896
897	/** Event injection state. */
898	struct
899	{
900	uint32_t fPending;
901	uint32_t u32ErrCode;
902	uint32_t cbInstr;
903	uint32_t u32Padding; /*< Explicit alignment padding. /
904	uint64_t u64IntInfo;
905	RTGCUINTPTR GCPtrFaultAddress;
906	} Event;
907
908	/** IO Block emulation state. */
909	struct
910	{
911	bool fEnabled;
912	uint8_t u8Align[7];
913
914	/** RIP at the start of the io code we wish to emulate in the recompiler. */
915	RTGCPTR GCPtrFunctionEip;
916
917	uint64_t cr0;
918	} EmulateIoBlock;
919
920	/* */
921	struct
922	{
923	/** Pending IO operation type. */
924	HMPENDINGIO enmType;
925	uint32_t u32Alignment0;
926	RTGCPTR GCPtrRip;
927	RTGCPTR GCPtrRipNext;
928	union
929	{
930	struct
931	{
932	uint32_t uPort;
933	uint32_t uAndVal;
934	uint32_t cbSize;
935	} Port;
936	uint64_t aRaw[2];
937	} s;
938	} PendingIO;
939
940	/** The PAE PDPEs used with Nested Paging (only valid when
941	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
942	X86PDPE aPdpes[4];
943
944	/** Current shadow paging mode. */
945	PGMMODE enmShadowMode;
946
947	/** The CPU ID of the CPU currently owning the VMCS. Set in
948	* HMR0Enter and cleared in HMR0Leave. */
949	RTCPUID idEnteredCpu;
950
951	/** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
952	uint16_t auExitHistory[31];
953	/** The index of the next free slot in the history array. */
954	uint16_t idxExitHistoryFree;
955
956	/** For saving stack space, the disassembler state is allocated here instead of
957	* on the stack. */
958	DISCPUSTATE DisState;
959
960	STAMPROFILEADV StatEntry;
961	STAMPROFILEADV StatExit1;
962	STAMPROFILEADV StatExit2;
963	STAMPROFILEADV StatExitIO;
964	STAMPROFILEADV StatExitMovCRx;
965	STAMPROFILEADV StatExitXcptNmi;
966	STAMPROFILEADV StatLoadGuestState;
967	STAMPROFILEADV StatInGC;
968
969	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
970	STAMPROFILEADV StatWorldSwitch3264;
971	#endif
972	STAMPROFILEADV StatPoke;
973	STAMPROFILEADV StatSpinPoke;
974	STAMPROFILEADV StatSpinPokeFailed;
975
976	STAMCOUNTER StatInjectInterrupt;
977	STAMCOUNTER StatInjectXcpt;
978	STAMCOUNTER StatInjectPendingReflect;
979	STAMCOUNTER StatInjectPendingInterpret;
980
981	STAMCOUNTER StatExitAll;
982	STAMCOUNTER StatExitShadowNM;
983	STAMCOUNTER StatExitGuestNM;
984	STAMCOUNTER StatExitShadowPF; /*< Misleading, currently used for MMIO \#PFs as well. /
985	STAMCOUNTER StatExitShadowPFEM;
986	STAMCOUNTER StatExitGuestPF;
987	STAMCOUNTER StatExitGuestUD;
988	STAMCOUNTER StatExitGuestSS;
989	STAMCOUNTER StatExitGuestNP;
990	STAMCOUNTER StatExitGuestTS;
991	STAMCOUNTER StatExitGuestGP;
992	STAMCOUNTER StatExitGuestDE;
993	STAMCOUNTER StatExitGuestDB;
994	STAMCOUNTER StatExitGuestMF;
995	STAMCOUNTER StatExitGuestBP;
996	STAMCOUNTER StatExitGuestXF;
997	STAMCOUNTER StatExitGuestXcpUnk;
998	STAMCOUNTER StatExitInvlpg;
999	STAMCOUNTER StatExitInvd;
1000	STAMCOUNTER StatExitWbinvd;
1001	STAMCOUNTER StatExitPause;
1002	STAMCOUNTER StatExitCpuid;
1003	STAMCOUNTER StatExitRdtsc;
1004	STAMCOUNTER StatExitRdtscp;
1005	STAMCOUNTER StatExitRdpmc;
1006	STAMCOUNTER StatExitVmcall;
1007	STAMCOUNTER StatExitRdrand;
1008	STAMCOUNTER StatExitCli;
1009	STAMCOUNTER StatExitSti;
1010	STAMCOUNTER StatExitPushf;
1011	STAMCOUNTER StatExitPopf;
1012	STAMCOUNTER StatExitIret;
1013	STAMCOUNTER StatExitInt;
1014	STAMCOUNTER StatExitCRxWrite[16];
1015	STAMCOUNTER StatExitCRxRead[16];
1016	STAMCOUNTER StatExitDRxWrite;
1017	STAMCOUNTER StatExitDRxRead;
1018	STAMCOUNTER StatExitRdmsr;
1019	STAMCOUNTER StatExitWrmsr;
1020	STAMCOUNTER StatExitClts;
1021	STAMCOUNTER StatExitXdtrAccess;
1022	STAMCOUNTER StatExitHlt;
1023	STAMCOUNTER StatExitMwait;
1024	STAMCOUNTER StatExitMonitor;
1025	STAMCOUNTER StatExitLmsw;
1026	STAMCOUNTER StatExitIOWrite;
1027	STAMCOUNTER StatExitIORead;
1028	STAMCOUNTER StatExitIOStringWrite;
1029	STAMCOUNTER StatExitIOStringRead;
1030	STAMCOUNTER StatExitIntWindow;
1031	STAMCOUNTER StatExitExtInt;
1032	STAMCOUNTER StatExitHostNmiInGC;
1033	STAMCOUNTER StatExitPreemptTimer;
1034	STAMCOUNTER StatExitTprBelowThreshold;
1035	STAMCOUNTER StatExitTaskSwitch;
1036	STAMCOUNTER StatExitMtf;
1037	STAMCOUNTER StatExitApicAccess;
1038	STAMCOUNTER StatPendingHostIrq;
1039
1040	STAMCOUNTER StatFlushPage;
1041	STAMCOUNTER StatFlushPageManual;
1042	STAMCOUNTER StatFlushPhysPageManual;
1043	STAMCOUNTER StatFlushTlb;
1044	STAMCOUNTER StatFlushTlbManual;
1045	STAMCOUNTER StatFlushTlbWorldSwitch;
1046	STAMCOUNTER StatNoFlushTlbWorldSwitch;
1047	STAMCOUNTER StatFlushEntire;
1048	STAMCOUNTER StatFlushAsid;
1049	STAMCOUNTER StatFlushNestedPaging;
1050	STAMCOUNTER StatFlushTlbInvlpgVirt;
1051	STAMCOUNTER StatFlushTlbInvlpgPhys;
1052	STAMCOUNTER StatTlbShootdown;
1053	STAMCOUNTER StatTlbShootdownFlush;
1054
1055	STAMCOUNTER StatSwitchTprMaskedIrq;
1056	STAMCOUNTER StatSwitchGuestIrq;
1057	STAMCOUNTER StatSwitchHmToR3FF;
1058	STAMCOUNTER StatSwitchExitToR3;
1059	STAMCOUNTER StatSwitchLongJmpToR3;
1060	STAMCOUNTER StatSwitchMaxResumeLoops;
1061	STAMCOUNTER StatSwitchHltToR3;
1062	STAMCOUNTER StatSwitchApicAccessToR3;
1063	STAMCOUNTER StatSwitchPreempt;
1064	STAMCOUNTER StatSwitchPreemptSaveHostState;
1065
1066	STAMCOUNTER StatTscParavirt;
1067	STAMCOUNTER StatTscOffset;
1068	STAMCOUNTER StatTscIntercept;
1069
1070	STAMCOUNTER StatExitReasonNpf;
1071	STAMCOUNTER StatDRxArmed;
1072	STAMCOUNTER StatDRxContextSwitch;
1073	STAMCOUNTER StatDRxIoCheck;
1074
1075	STAMCOUNTER StatLoadMinimal;
1076	STAMCOUNTER StatLoadFull;
1077
1078	STAMCOUNTER StatVmxCheckBadRmSelBase;
1079	STAMCOUNTER StatVmxCheckBadRmSelLimit;
1080	STAMCOUNTER StatVmxCheckRmOk;
1081
1082	STAMCOUNTER StatVmxCheckBadSel;
1083	STAMCOUNTER StatVmxCheckBadRpl;
1084	STAMCOUNTER StatVmxCheckBadLdt;
1085	STAMCOUNTER StatVmxCheckBadTr;
1086	STAMCOUNTER StatVmxCheckPmOk;
1087
1088	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1089	STAMCOUNTER StatFpu64SwitchBack;
1090	STAMCOUNTER StatDebug64SwitchBack;
1091	#endif
1092
1093	#ifdef VBOX_WITH_STATISTICS
1094	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1095	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1096	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1097	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1098	#endif
1099	#ifdef HM_PROFILE_EXIT_DISPATCH
1100	STAMPROFILEADV StatExitDispatch;
1101	#endif
1102	} HMCPU;
1103	/** Pointer to HM VMCPU instance data. */
1104	typedef HMCPU *PHMCPU;
1105	AssertCompileMemberAlignment(HMCPU, vmx, 8);
1106	AssertCompileMemberAlignment(HMCPU, svm, 8);
1107	AssertCompileMemberAlignment(HMCPU, Event, 8);
1108
1109	#ifdef IN_RING0
1110	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void);
1111
1112	# ifdef VBOX_STRICT
1113	VMMR0_INT_DECL(void) hmR0DumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1114	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1115	# else
1116	# define hmR0DumpRegs(a, b ,c) do { } while (0)
1117	# define hmR0DumpDescriptor(a, b, c) do { } while (0)
1118	# endif /* VBOX_STRICT */
1119
1120	# ifdef VBOX_WITH_KERNEL_USING_XMM
1121	DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1122	DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1123	# endif
1124
1125	#endif /* IN_RING0 */
1126
1127	/** @} */
1128
1129	RT_C_DECLS_END
1130
1131	#endif
1132

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 69288

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