VirtualBox

source: vbox/trunk/src/VBox/VMM/include/GIMHvInternal.h@ 93115

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1/* $Id: GIMHvInternal.h 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * GIM - Hyper-V, Internal header file.
4 */
5
6/*
7 * Copyright (C) 2014-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_GIMHvInternal_h
19#define VMM_INCLUDED_SRC_include_GIMHvInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/vmm/gim.h>
25#include <VBox/vmm/cpum.h>
26
27#include <iprt/net.h>
28
29/** @name Hyper-V base feature identification.
30 * Features based on current partition privileges (per-VM).
31 * @{
32 */
33/** Virtual processor runtime MSR available. */
34#define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
35/** Partition reference counter MSR available. */
36#define GIM_HV_BASE_FEAT_PART_TIME_REF_COUNT_MSR RT_BIT(1)
37/** Basic Synthetic Interrupt Controller MSRs available. */
38#define GIM_HV_BASE_FEAT_BASIC_SYNIC_MSRS RT_BIT(2)
39/** Synthetic Timer MSRs available. */
40#define GIM_HV_BASE_FEAT_STIMER_MSRS RT_BIT(3)
41/** APIC access MSRs (EOI, ICR, TPR) available. */
42#define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4)
43/** Hypercall MSRs available. */
44#define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5)
45/** Access to VCPU index MSR available. */
46#define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6)
47/** Virtual system reset MSR available. */
48#define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7)
49/** Statistic pages MSRs available. */
50#define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8)
51/** Paritition reference TSC MSR available. */
52#define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9)
53/** Virtual guest idle state MSR available. */
54#define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10)
55/** Timer frequency MSRs (TSC and APIC) available. */
56#define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11)
57/** Debug MSRs available. */
58#define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12)
59/** @} */
60
61/** @name Hyper-V partition-creation feature identification.
62 * Indicates flags specified during partition creation.
63 * @{
64 */
65/** Create partitions. */
66#define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
67/** Access partition Id. */
68#define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1)
69/** Access memory pool. */
70#define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2)
71/** Adjust message buffers. */
72#define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3)
73/** Post messages. */
74#define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4)
75/** Signal events. */
76#define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5)
77/** Create port. */
78#define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6)
79/** Connect port. */
80#define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7)
81/** Access statistics. */
82#define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8)
83/** Debugging.*/
84#define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11)
85/** CPU management. */
86#define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12)
87/** CPU profiler. */
88#define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13)
89/** Enable expanded stack walking. */
90#define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14)
91/** Access VSM. */
92#define GIM_HV_PART_FLAGS_ACCESS_VSM RT_BIT(16)
93/** Access VP registers. */
94#define GIM_HV_PART_FLAGS_ACCESS_VP_REGS RT_BIT(17)
95/** Enable extended hypercalls. */
96#define GIM_HV_PART_FLAGS_EXTENDED_HYPERCALLS RT_BIT(20)
97/** Start virtual processor. */
98#define GIM_HV_PART_FLAGS_START_VP RT_BIT(21)
99/** @} */
100
101/** @name Hyper-V power management feature identification.
102 * @{
103 */
104/** Maximum CPU power state C0. */
105#define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
106/** Maximum CPU power state C1. */
107#define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1)
108/** Maximum CPU power state C2. */
109#define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2)
110/** Maximum CPU power state C3. */
111#define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3)
112/** HPET is required to enter C3 power state. */
113#define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4)
114/** @} */
115
116/** @name Hyper-V miscellaneous feature identification.
117 * Miscellaneous features available for the current partition.
118 * @{
119 */
120/** MWAIT instruction available. */
121#define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
122/** Guest debugging support available. */
123#define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1)
124/** Performance monitor support is available. */
125#define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2)
126/** Support for physical CPU dynamic partitioning events. */
127#define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3)
128/** Support for passing hypercall input parameter block via XMM registers. */
129#define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4)
130/** Support for virtual guest idle state. */
131#define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5)
132/** Support for hypervisor sleep state. */
133#define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6)
134/** Support for querying NUMA distances. */
135#define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7)
136/** Support for determining timer frequencies. */
137#define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8)
138/** Support for injecting synthetic machine checks. */
139#define GIM_HV_MISC_FEAT_INJECT_SYNMC_XCPT RT_BIT(9)
140/** Support for guest crash MSRs. */
141#define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10)
142/** Support for debug MSRs. */
143#define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11)
144/** Npiep1 Available */ /** @todo What the heck is this? */
145#define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12)
146/** Disable hypervisor available. */
147#define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13)
148/** Extended GVA ranges for FlushVirtualAddressList available. */
149#define GIM_HV_MISC_FEAT_EXT_GVA_RANGE_FOR_FLUSH_VA_LIST RT_BIT(14)
150/** Support for returning hypercall output via XMM registers. */
151#define GIM_HV_MISC_FEAT_HYPERCALL_OUTPUT_XMM RT_BIT(15)
152/** Synthetic interrupt source polling mode available. */
153#define GIM_HV_MISC_FEAT_SINT_POLLING_MODE RT_BIT(17)
154/** Hypercall MSR lock available. */
155#define GIM_HV_MISC_FEAT_HYPERCALL_MSR_LOCK RT_BIT(18)
156/** Use direct synthetic MSRs. */
157#define GIM_HV_MISC_FEAT_USE_DIRECT_SYNTH_MSRS RT_BIT(19)
158/** @} */
159
160/** @name Hyper-V implementation recommendations.
161 * Recommendations from the hypervisor for the guest for optimal performance.
162 * @{
163 */
164/** Use hypercall for address space switches rather than MOV CR3. */
165#define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
166/** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */
167#define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1)
168/** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
169#define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2)
170/** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
171#define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3)
172/** Use hypervisor provided MSR for a system reset. */
173#define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4)
174/** Relax timer-related checks (watchdogs/deadman timeouts) that rely on
175 * timely deliver of external interrupts. */
176#define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5)
177/** Recommend using DMA remapping. */
178#define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6)
179/** Recommend using interrupt remapping. */
180#define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7)
181/** Recommend using X2APIC MSRs rather than MMIO. */
182#define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8)
183/** Recommend deprecating Auto EOI (end of interrupt). */
184#define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9)
185/** Recommend using SyntheticClusterIpi hypercall. */
186#define GIM_HV_HINT_SYNTH_CLUSTER_IPI_HYPERCALL RT_BIT(10)
187/** Recommend using newer ExProcessMasks interface. */
188#define GIM_HV_HINT_EX_PROC_MASKS_INTERFACE RT_BIT(11)
189/** Indicate that Hyper-V is nested within a Hyper-V partition. */
190#define GIM_HV_HINT_NESTED_HYPERV RT_BIT(12)
191/** Recommend using INT for MBEC system calls. */
192#define GIM_HV_HINT_INT_FOR_MBEC_SYSCALLS RT_BIT(13)
193/** Recommend using enlightened VMCS interfacea and nested enlightenments. */
194#define GIM_HV_HINT_NESTED_ENLIGHTENED_VMCS_INTERFACE RT_BIT(14)
195/** @} */
196
197
198/** @name Hyper-V implementation hardware features.
199 * Which hardware features are in use by the hypervisor.
200 * @{
201 */
202/** APIC overlay is used. */
203#define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
204/** MSR bitmaps is used. */
205#define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1)
206/** Architectural performance counter supported. */
207#define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2)
208/** Nested paging is used. */
209#define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3)
210/** DMA remapping is used. */
211#define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4)
212/** Interrupt remapping is used. */
213#define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5)
214/** Memory patrol scrubber is present. */
215#define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6)
216/** DMA protection is in use. */
217#define GIM_HV_HOST_FEAT_DMA_PROT_IN_USE RT_BIT(7)
218/** HPET is requested. */
219#define GIM_HV_HOST_FEAT_HPET_REQUESTED RT_BIT(8)
220/** Synthetic timers are volatile. */
221#define GIM_HV_HOST_FEAT_STIMER_VOLATILE RT_BIT(9)
222/** @} */
223
224
225/** @name Hyper-V MSRs.
226 * @{
227 */
228/** Start of range 0. */
229#define MSR_GIM_HV_RANGE0_FIRST UINT32_C(0x40000000)
230/** Guest OS identification (R/W) */
231#define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000)
232/** Enable hypercall interface (R/W) */
233#define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001)
234/** Virtual processor's (VCPU) index (R) */
235#define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002)
236/** Reset operation (R/W) */
237#define MSR_GIM_HV_RESET UINT32_C(0x40000003)
238/** End of range 0. */
239#define MSR_GIM_HV_RANGE0_LAST MSR_GIM_HV_RESET
240
241/** Start of range 1. */
242#define MSR_GIM_HV_RANGE1_FIRST UINT32_C(0x40000010)
243/** Virtual processor's (VCPU) runtime (R) */
244#define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010)
245/** End of range 1. */
246#define MSR_GIM_HV_RANGE1_LAST MSR_GIM_HV_VP_RUNTIME
247
248/** Start of range 2. */
249#define MSR_GIM_HV_RANGE2_FIRST UINT32_C(0x40000020)
250/** Per-VM reference counter (R) */
251#define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020)
252/** Per-VM TSC page (R/W) */
253#define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021)
254/** Frequency of TSC in Hz as reported by the hypervisor (R) */
255#define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022)
256/** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
257#define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023)
258/** End of range 2. */
259#define MSR_GIM_HV_RANGE2_LAST MSR_GIM_HV_APIC_FREQ
260
261/** Start of range 3. */
262#define MSR_GIM_HV_RANGE3_FIRST UINT32_C(0x40000070)
263/** Access to APIC EOI (End-Of-Interrupt) register (W) */
264#define MSR_GIM_HV_EOI UINT32_C(0x40000070)
265/** Access to APIC ICR (Interrupt Command) register (R/W) */
266#define MSR_GIM_HV_ICR UINT32_C(0x40000071)
267/** Access to APIC TPR (Task Priority) register (R/W) */
268#define MSR_GIM_HV_TPR UINT32_C(0x40000072)
269/** Enables lazy EOI processing (R/W) */
270#define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073)
271/** End of range 3. */
272#define MSR_GIM_HV_RANGE3_LAST MSR_GIM_HV_APIC_ASSIST_PAGE
273
274/** Start of range 4. */
275#define MSR_GIM_HV_RANGE4_FIRST UINT32_C(0x40000080)
276/** Control behaviour of synthetic interrupt controller (R/W) */
277#define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080)
278/** Synthetic interrupt controller version (R) */
279#define MSR_GIM_HV_SVERSION UINT32_C(0x40000081)
280/** Base address of synthetic interrupt event flag (R/W) */
281#define MSR_GIM_HV_SIEFP UINT32_C(0x40000082)
282/** Base address of synthetic interrupt message page (R/W) */
283#define MSR_GIM_HV_SIMP UINT32_C(0x40000083)
284/** End-Of-Message in synthetic interrupt parameter page (W) */
285#define MSR_GIM_HV_EOM UINT32_C(0x40000084)
286/** End of range 4. */
287#define MSR_GIM_HV_RANGE4_LAST MSR_GIM_HV_EOM
288
289/** Start of range 5. */
290#define MSR_GIM_HV_RANGE5_FIRST UINT32_C(0x40000090)
291/** Configures synthetic interrupt source 0 (R/W) */
292#define MSR_GIM_HV_SINT0 UINT32_C(0x40000090)
293/** Configures synthetic interrupt source 1 (R/W) */
294#define MSR_GIM_HV_SINT1 UINT32_C(0x40000091)
295/** Configures synthetic interrupt source 2 (R/W) */
296#define MSR_GIM_HV_SINT2 UINT32_C(0x40000092)
297/** Configures synthetic interrupt source 3 (R/W) */
298#define MSR_GIM_HV_SINT3 UINT32_C(0x40000093)
299/** Configures synthetic interrupt source 4 (R/W) */
300#define MSR_GIM_HV_SINT4 UINT32_C(0x40000094)
301/** Configures synthetic interrupt source 5 (R/W) */
302#define MSR_GIM_HV_SINT5 UINT32_C(0x40000095)
303/** Configures synthetic interrupt source 6 (R/W) */
304#define MSR_GIM_HV_SINT6 UINT32_C(0x40000096)
305/** Configures synthetic interrupt source 7 (R/W) */
306#define MSR_GIM_HV_SINT7 UINT32_C(0x40000097)
307/** Configures synthetic interrupt source 8 (R/W) */
308#define MSR_GIM_HV_SINT8 UINT32_C(0x40000098)
309/** Configures synthetic interrupt source 9 (R/W) */
310#define MSR_GIM_HV_SINT9 UINT32_C(0x40000099)
311/** Configures synthetic interrupt source 10 (R/W) */
312#define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A)
313/** Configures synthetic interrupt source 11 (R/W) */
314#define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B)
315/** Configures synthetic interrupt source 12 (R/W) */
316#define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C)
317/** Configures synthetic interrupt source 13 (R/W) */
318#define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D)
319/** Configures synthetic interrupt source 14 (R/W) */
320#define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E)
321/** Configures synthetic interrupt source 15 (R/W) */
322#define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F)
323/** End of range 5. */
324#define MSR_GIM_HV_RANGE5_LAST MSR_GIM_HV_SINT15
325
326/** Start of range 6. */
327#define MSR_GIM_HV_RANGE6_FIRST UINT32_C(0x400000B0)
328/** Configures register for synthetic timer 0 (R/W) */
329#define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0)
330/** Expiration time or period for synthetic timer 0 (R/W) */
331#define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1)
332/** Configures register for synthetic timer 1 (R/W) */
333#define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2)
334/** Expiration time or period for synthetic timer 1 (R/W) */
335#define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3)
336/** Configures register for synthetic timer 2 (R/W) */
337#define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4)
338/** Expiration time or period for synthetic timer 2 (R/W) */
339#define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5)
340/** Configures register for synthetic timer 3 (R/W) */
341#define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6)
342/** Expiration time or period for synthetic timer 3 (R/W) */
343#define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7)
344/** End of range 6. */
345#define MSR_GIM_HV_RANGE6_LAST MSR_GIM_HV_STIMER3_COUNT
346
347/** Start of range 7. */
348#define MSR_GIM_HV_RANGE7_FIRST UINT32_C(0x400000C1)
349/** Trigger to transition to power state C1 (R) */
350#define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1)
351/** Trigger to transition to power state C2 (R) */
352#define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2)
353/** Trigger to transition to power state C3 (R) */
354#define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3)
355/** End of range 7. */
356#define MSR_GIM_HV_RANGE7_LAST MSR_GIM_HV_POWER_STATE_TRIGGER_C3
357
358/** Start of range 8. */
359#define MSR_GIM_HV_RANGE8_FIRST UINT32_C(0x400000D1)
360/** Configure the recipe for power state transitions to C1 (R/W) */
361#define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1)
362/** Configure the recipe for power state transitions to C2 (R/W) */
363#define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2)
364/** Configure the recipe for power state transitions to C3 (R/W) */
365#define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3)
366/** End of range 8. */
367#define MSR_GIM_HV_RANGE8_LAST MSR_GIM_HV_POWER_STATE_CONFIG_C3
368
369/** Start of range 9. */
370#define MSR_GIM_HV_RANGE9_FIRST UINT32_C(0x400000E0)
371/** Map the guest's retail partition stats page (R/W) */
372#define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0)
373/** Map the guest's internal partition stats page (R/W) */
374#define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1)
375/** Map the guest's retail VP stats page (R/W) */
376#define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2)
377/** Map the guest's internal VP stats page (R/W) */
378#define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3)
379/** End of range 9. */
380#define MSR_GIM_HV_RANGE9_LAST MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
381
382/** Start of range 10. */
383#define MSR_GIM_HV_RANGE10_FIRST UINT32_C(0x400000F0)
384/** Trigger the guest's transition to idle power state (R) */
385#define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0)
386/** Synthetic debug control. */
387#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1)
388/** Synthetic debug status. */
389#define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2)
390/** Synthetic debug send buffer. */
391#define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3)
392/** Synthetic debug receive buffer. */
393#define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4)
394/** Synthetic debug pending buffer. */
395#define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5)
396/** End of range 10. */
397#define MSR_GIM_HV_RANGE10_LAST MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
398
399/** Start of range 11. */
400#define MSR_GIM_HV_RANGE11_FIRST UINT32_C(0x400000FF)
401/** Undocumented debug options MSR. */
402#define MSR_GIM_HV_DEBUG_OPTIONS_MSR UINT32_C(0x400000FF)
403/** End of range 11. */
404#define MSR_GIM_HV_RANGE11_LAST MSR_GIM_HV_DEBUG_OPTIONS_MSR
405
406/** Start of range 12. */
407#define MSR_GIM_HV_RANGE12_FIRST UINT32_C(0x40000100)
408/** Guest crash MSR 0. */
409#define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100)
410/** Guest crash MSR 1. */
411#define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101)
412/** Guest crash MSR 2. */
413#define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102)
414/** Guest crash MSR 3. */
415#define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103)
416/** Guest crash MSR 4. */
417#define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104)
418/** Guest crash control. */
419#define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105)
420/** End of range 12. */
421#define MSR_GIM_HV_RANGE12_LAST MSR_GIM_HV_CRASH_CTL
422/** @} */
423
424AssertCompile(MSR_GIM_HV_RANGE0_FIRST <= MSR_GIM_HV_RANGE0_LAST);
425AssertCompile(MSR_GIM_HV_RANGE1_FIRST <= MSR_GIM_HV_RANGE1_LAST);
426AssertCompile(MSR_GIM_HV_RANGE2_FIRST <= MSR_GIM_HV_RANGE2_LAST);
427AssertCompile(MSR_GIM_HV_RANGE3_FIRST <= MSR_GIM_HV_RANGE3_LAST);
428AssertCompile(MSR_GIM_HV_RANGE4_FIRST <= MSR_GIM_HV_RANGE4_LAST);
429AssertCompile(MSR_GIM_HV_RANGE5_FIRST <= MSR_GIM_HV_RANGE5_LAST);
430AssertCompile(MSR_GIM_HV_RANGE6_FIRST <= MSR_GIM_HV_RANGE6_LAST);
431AssertCompile(MSR_GIM_HV_RANGE7_FIRST <= MSR_GIM_HV_RANGE7_LAST);
432AssertCompile(MSR_GIM_HV_RANGE8_FIRST <= MSR_GIM_HV_RANGE8_LAST);
433AssertCompile(MSR_GIM_HV_RANGE9_FIRST <= MSR_GIM_HV_RANGE9_LAST);
434AssertCompile(MSR_GIM_HV_RANGE10_FIRST <= MSR_GIM_HV_RANGE10_LAST);
435AssertCompile(MSR_GIM_HV_RANGE11_FIRST <= MSR_GIM_HV_RANGE11_LAST);
436
437/** @name Hyper-V MSR - Reset (MSR_GIM_HV_RESET).
438 * @{
439 */
440/** The reset enable mask. */
441#define MSR_GIM_HV_RESET_ENABLE RT_BIT_64(0)
442/** Whether the reset MSR is enabled. */
443#define MSR_GIM_HV_RESET_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_RESET_ENABLE)
444/** @} */
445
446/** @name Hyper-V MSR - Hypercall (MSR_GIM_HV_HYPERCALL).
447 * @{
448 */
449/** Guest-physical page frame number of the hypercall-page. */
450#define MSR_GIM_HV_HYPERCALL_GUEST_PFN(a) ((a) >> 12)
451/** The hypercall enable mask. */
452#define MSR_GIM_HV_HYPERCALL_PAGE_ENABLE RT_BIT_64(0)
453/** Whether the hypercall-page is enabled or not. */
454#define MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE)
455/** @} */
456
457/** @name Hyper-V MSR - Reference TSC (MSR_GIM_HV_REF_TSC).
458 * @{
459 */
460/** Guest-physical page frame number of the TSC-page. */
461#define MSR_GIM_HV_REF_TSC_GUEST_PFN(a) ((a) >> 12)
462/** The TSC-page enable mask. */
463#define MSR_GIM_HV_REF_TSC_ENABLE RT_BIT_64(0)
464/** Whether the TSC-page is enabled or not. */
465#define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE)
466/** @} */
467
468/** @name Hyper-V MSR - Guest crash control (MSR_GIM_HV_CRASH_CTL).
469 * @{
470 */
471/** The Crash Control notify mask. */
472#define MSR_GIM_HV_CRASH_CTL_NOTIFY RT_BIT_64(63)
473/** @} */
474
475/** @name Hyper-V MSR - Guest OS ID (MSR_GIM_HV_GUEST_OS_ID).
476 * @{
477 */
478/** An open-source operating system. */
479#define MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(a) RT_BOOL((a) & RT_BIT_64(63))
480/** Vendor ID. */
481#define MSR_GIM_HV_GUEST_OS_ID_VENDOR(a) (uint32_t)(((a) >> 48) & 0xfff)
482/** Guest OS variant, depending on the vendor ID. */
483#define MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(a) (uint32_t)(((a) >> 40) & 0xff)
484/** Guest OS major version. */
485#define MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(a) (uint32_t)(((a) >> 32) & 0xff)
486/** Guest OS minor version. */
487#define MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(a) (uint32_t)(((a) >> 24) & 0xff)
488/** Guest OS service version (e.g. service pack number in case of Windows). */
489#define MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(a) (uint32_t)(((a) >> 16) & 0xff)
490/** Guest OS build number. */
491#define MSR_GIM_HV_GUEST_OS_ID_BUILD(a) (uint32_t)((a) & 0xffff)
492/** @} */
493
494/** @name Hyper-V MSR - APIC-assist page (MSR_GIM_HV_APIC_ASSIST_PAGE).
495 * @{
496 */
497/** Guest-physical page frame number of the APIC-assist page. */
498#define MSR_GIM_HV_APICASSIST_GUEST_PFN(a) ((a) >> 12)
499/** The APIC-assist page enable mask. */
500#define MSR_GIM_HV_APICASSIST_PAGE_ENABLE RT_BIT_64(0)
501/** Whether the APIC-assist page is enabled or not. */
502#define MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_APICASSIST_PAGE_ENABLE)
503/** @} */
504
505/** @name Hyper-V MSR - Synthetic Interrupt Event Flags page
506 * (MSR_GIM_HV_SIEFP).
507 * @{
508 */
509/** Guest-physical page frame number of the APIC-assist page. */
510#define MSR_GIM_HV_SIEF_GUEST_PFN(a) ((a) >> 12)
511/** The SIEF enable mask. */
512#define MSR_GIM_HV_SIEF_PAGE_ENABLE RT_BIT_64(0)
513/** Whether the SIEF page is enabled or not. */
514#define MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIEF_PAGE_ENABLE)
515/** @} */
516
517/** @name Hyper-V MSR - Synthetic Interrupt Control (MSR_GIM_HV_CONTROL).
518 * @{
519 */
520/** The SControl enable mask. */
521#define MSR_GIM_HV_SCONTROL_ENABLE RT_BIT_64(0)
522/** Whether SControl is enabled or not. */
523#define MSR_GIM_HV_SCONTROL_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SCONTROL_ENABLE)
524/** @} */
525
526/** @name Hyper-V MSR - Synthetic Timer Config (MSR_GIM_HV_STIMER_CONFIG).
527 * @{
528 */
529/** The Stimer enable mask. */
530#define MSR_GIM_HV_STIMER_ENABLE RT_BIT_64(0)
531/** Whether Stimer is enabled or not. */
532#define MSR_GIM_HV_STIMER_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_ENABLE)
533/** The Stimer periodic mask. */
534#define MSR_GIM_HV_STIMER_PERIODIC RT_BIT_64(1)
535/** Whether Stimer is enabled or not. */
536#define MSR_GIM_HV_STIMER_IS_PERIODIC(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_PERIODIC)
537/** The Stimer lazy mask. */
538#define MSR_GIM_HV_STIMER_LAZY RT_BIT_64(2)
539/** Whether Stimer is enabled or not. */
540#define MSR_GIM_HV_STIMER_IS_LAZY(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_LAZY)
541/** The Stimer auto-enable mask. */
542#define MSR_GIM_HV_STIMER_AUTO_ENABLE RT_BIT_64(3)
543/** Whether Stimer is enabled or not. */
544#define MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_AUTO_ENABLE)
545/** The Stimer SINTx mask (bits 16:19). */
546#define MSR_GIM_HV_STIMER_SINTX UINT64_C(0xf0000)
547/** Gets the Stimer synthetic interrupt source. */
548#define MSR_GIM_HV_STIMER_GET_SINTX(a) (((a) >> 16) & 0xf)
549/** The Stimer valid read/write mask. */
550#define MSR_GIM_HV_STIMER_RW_VALID ( MSR_GIM_HV_STIMER_ENABLE | MSR_GIM_HV_STIMER_PERIODIC \
551 | MSR_GIM_HV_STIMER_LAZY | MSR_GIM_HV_STIMER_AUTO_ENABLE \
552 | MSR_GIM_HV_STIMER_SINTX)
553/** @} */
554
555/**
556 * Hyper-V APIC-assist (HV_REFERENCE_TSC_PAGE) structure placed in the TSC
557 * reference page.
558 */
559typedef struct GIMHVAPICASSIST
560{
561 uint32_t fNoEoiRequired : 1;
562 uint32_t u31Reserved0 : 31;
563} GIMHVAPICASSIST;
564/** Pointer to Hyper-V reference TSC. */
565typedef GIMHVAPICASSIST *PGIMHVAPICASSIST;
566/** Pointer to a const Hyper-V reference TSC. */
567typedef GIMHVAPICASSIST const *PCGIMHVAPICASSIST;
568AssertCompileSize(GIMHVAPICASSIST, 4);
569
570/**
571 * Hypercall parameter type.
572 */
573typedef enum GIMHVHYPERCALLPARAM
574{
575 GIMHVHYPERCALLPARAM_IN = 0,
576 GIMHVHYPERCALLPARAM_OUT
577} GIMHVHYPERCALLPARAM;
578
579
580/** @name Hyper-V hypercall op codes.
581 * @{
582 */
583/** Post message to hypervisor or VMs. */
584#define GIM_HV_HYPERCALL_OP_POST_MESSAGE 0x5C
585/** Post debug data to hypervisor. */
586#define GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA 0x69
587/** Retreive debug data from hypervisor. */
588#define GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA 0x6A
589/** Reset debug session. */
590#define GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION 0x6B
591/** @} */
592
593/** @name Hyper-V extended hypercall op codes.
594 * @{
595 */
596/** Query extended hypercall capabilities. */
597#define GIM_HV_EXT_HYPERCALL_OP_QUERY_CAP 0x8001
598/** Query guest physical address range that has zero'd filled memory. */
599#define GIM_HV_EXT_HYPERCALL_OP_GET_BOOT_ZEROED_MEM 0x8002
600/** @} */
601
602
603/** @name Hyper-V Extended hypercall - HvExtCallQueryCapabilities.
604 * @{
605 */
606/** Boot time zeroed pages. */
607#define GIM_HV_EXT_HYPERCALL_CAP_ZERO_MEM RT_BIT_64(0)
608/** Whether boot time zeroed pages capability is enabled. */
609#define GIM_HV_EXT_HYPERCALL_CAP_IS_ZERO_MEM_ENABLED(a) RT_BOOL((a) & GIM_HV_EXT_HYPERCALL_CAP_ZERO_MEM)
610/** @} */
611
612
613/** @name Hyper-V hypercall inputs.
614 * @{
615 */
616/** The hypercall call operation code. */
617#define GIM_HV_HYPERCALL_IN_CALL_CODE(a) ((a) & UINT64_C(0xffff))
618/** Whether it's a fast (register based) hypercall or not (memory-based). */
619#define GIM_HV_HYPERCALL_IN_IS_FAST(a) RT_BOOL((a) & RT_BIT_64(16))
620/** Total number of reps for a rep hypercall. */
621#define GIM_HV_HYPERCALL_IN_REP_COUNT(a) (((a) << 32) & UINT64_C(0xfff))
622/** Rep start index for a rep hypercall. */
623#define GIM_HV_HYPERCALL_IN_REP_START_IDX(a) (((a) << 48) & UINT64_C(0xfff))
624/** Reserved bits range 1. */
625#define GIM_HV_HYPERCALL_IN_RSVD_1(a) (((a) << 17) & UINT64_C(0x7fff))
626/** Reserved bits range 2. */
627#define GIM_HV_HYPERCALL_IN_RSVD_2(a) (((a) << 44) & UINT64_C(0xf))
628/** Reserved bits range 3. */
629#define GIM_HV_HYPERCALL_IN_RSVD_3(a) (((a) << 60) & UINT64_C(0x7))
630/** @} */
631
632
633/** @name Hyper-V hypercall status codes.
634 * @{
635 */
636/** Success. */
637#define GIM_HV_STATUS_SUCCESS 0x00
638/** Unrecognized hypercall. */
639#define GIM_HV_STATUS_INVALID_HYPERCALL_CODE 0x02
640/** Invalid hypercall input (rep count, rsvd bits). */
641#define GIM_HV_STATUS_INVALID_HYPERCALL_INPUT 0x03
642/** Hypercall guest-physical address not 8-byte aligned or crosses page boundary. */
643#define GIM_HV_STATUS_INVALID_ALIGNMENT 0x04
644/** Invalid hypercall parameters. */
645#define GIM_HV_STATUS_INVALID_PARAMETER 0x05
646/** Access denied. */
647#define GIM_HV_STATUS_ACCESS_DENIED 0x06
648/** The partition state not valid for specified op. */
649#define GIM_HV_STATUS_INVALID_PARTITION_STATE 0x07
650/** The hypercall operation could not be performed. */
651#define GIM_HV_STATUS_OPERATION_DENIED 0x08
652/** Specified partition property ID not recognized. */
653#define GIM_HV_STATUS_UNKNOWN_PROPERTY 0x09
654/** Specified partition property value not within range. */
655#define GIM_HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0x0a
656/** Insufficient memory for performing the hypercall. */
657#define GIM_HV_STATUS_INSUFFICIENT_MEMORY 0x0b
658/** Maximum partition depth has been exceeded for the partition hierarchy. */
659#define GIM_HV_STATUS_PARTITION_TOO_DEEP 0x0c
660/** The specified partition ID is not valid. */
661#define GIM_HV_STATUS_INVALID_PARTITION_ID 0x0d
662/** The specified virtual processor index in invalid. */
663#define GIM_HV_STATUS_INVALID_VP_INDEX 0x0e
664/** The specified port ID is not unique or doesn't exist. */
665#define GIM_HV_STATUS_INVALID_PORT_ID 0x11
666/** The specified connection ID is not unique or doesn't exist. */
667#define GIM_HV_STATUS_INVALID_CONNECTION_ID 0x12
668/** The target port doesn't have sufficient buffers for the caller to post a message. */
669#define GIM_HV_STATUS_INSUFFICIENT_BUFFERS 0x13
670/** External interrupt not acknowledged.*/
671#define GIM_HV_STATUS_NOT_ACKNOWLEDGED 0x14
672/** External interrupt acknowledged. */
673#define GIM_HV_STATUS_ACKNOWLEDGED 0x16
674/** Invalid state due to misordering Hv[Save|Restore]PartitionState. */
675#define GIM_HV_STATUS_INVALID_SAVE_RESTORE_STATE 0x17
676/** Operation not perform due to a required feature of SynIc was disabled. */
677#define GIM_HV_STATUS_INVALID_SYNIC_STATE 0x18
678/** Object or value already in use. */
679#define GIM_HV_STATUS_OBJECT_IN_USE 0x19
680/** Invalid proximity domain information. */
681#define GIM_HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO 0x1A
682/** Attempt to retrieve data failed. */
683#define GIM_HV_STATUS_NO_DATA 0x1B
684/** Debug connection has not recieved any new data since the last time. */
685#define GIM_HV_STATUS_INACTIVE 0x1C
686/** A resource is unavailable for allocation. */
687#define GIM_HV_STATUS_NO_RESOURCES 0x1D
688/** A hypervisor feature is not available to the caller. */
689#define GIM_HV_STATUS_FEATURE_UNAVAILABLE 0x1E
690/** The debug packet returned is partial due to an I/O error. */
691#define GIM_HV_STATUS_PARTIAL_PACKET 0x1F
692/** Processor feature SSE3 unsupported. */
693#define GIM_HV_STATUS_PROC_FEAT_SSE3_NOT_SUPPORTED 0x20
694/** Processor feature LAHSAHF unsupported. */
695#define GIM_HV_STATUS_PROC_FEAT_LAHSAHF_NOT_SUPPORTED 0x21
696/** Processor feature SSSE3 unsupported. */
697#define GIM_HV_STATUS_PROC_FEAT_SSSE3_NOT_SUPPORTED 0x22
698/** Processor feature SSE4.1 unsupported. */
699#define GIM_HV_STATUS_PROC_FEAT_SSE4_1_NOT_SUPPORTED 0x23
700/** Processor feature SSE4.2 unsupported. */
701#define GIM_HV_STATUS_PROC_FEAT_SSE4_2_NOT_SUPPORTED 0x24
702/** Processor feature SSE4A unsupported. */
703#define GIM_HV_STATUS_PROC_FEAT_SSE4A_NOT_SUPPORTED 0x25
704/** Processor feature XOP unsupported. */
705#define GIM_HV_STATUS_PROC_FEAT_XOP_NOT_SUPPORTED 0x26
706/** Processor feature POPCNT unsupported. */
707#define GIM_HV_STATUS_PROC_FEAT_POPCNT_NOT_SUPPORTED 0x27
708/** Processor feature CMPXCHG16B unsupported. */
709#define GIM_HV_STATUS_PROC_FEAT_CMPXCHG16B_NOT_SUPPORTED 0x28
710/** Processor feature ALTMOVCR8 unsupported. */
711#define GIM_HV_STATUS_PROC_FEAT_ALTMOVCR8_NOT_SUPPORTED 0x29
712/** Processor feature LZCNT unsupported. */
713#define GIM_HV_STATUS_PROC_FEAT_LZCNT_NOT_SUPPORTED 0x2A
714/** Processor feature misaligned SSE unsupported. */
715#define GIM_HV_STATUS_PROC_FEAT_MISALIGNED_SSE_NOT_SUPPORTED 0x2B
716/** Processor feature MMX extensions unsupported. */
717#define GIM_HV_STATUS_PROC_FEAT_MMX_EXT_NOT_SUPPORTED 0x2C
718/** Processor feature 3DNow! unsupported. */
719#define GIM_HV_STATUS_PROC_FEAT_3DNOW_NOT_SUPPORTED 0x2D
720/** Processor feature Extended 3DNow! unsupported. */
721#define GIM_HV_STATUS_PROC_FEAT_EXTENDED_3DNOW_NOT_SUPPORTED 0x2E
722/** Processor feature 1GB large page unsupported. */
723#define GIM_HV_STATUS_PROC_FEAT_PAGE_1GB_NOT_SUPPORTED 0x2F
724/** Processor cache line flush size incompatible. */
725#define GIM_HV_STATUS_PROC_CACHE_LINE_FLUSH_SIZE_INCOMPATIBLE 0x30
726/** Processor feature XSAVE unsupported. */
727#define GIM_HV_STATUS_PROC_FEAT_XSAVE_NOT_SUPPORTED 0x31
728/** Processor feature XSAVEOPT unsupported. */
729#define GIM_HV_STATUS_PROC_FEAT_XSAVEOPT_NOT_SUPPORTED 0x32
730/** The specified buffer was too small for all requested data. */
731#define GIM_HV_STATUS_INSUFFICIENT_BUFFER 0x33
732/** Processor feature XSAVEOPT unsupported. */
733#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX_NOT_SUPPORTED 0x34
734/** Processor feature XSAVEOPT unsupported. */
735#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEAT_NOT_SUPPORTED 0x35 /** Huh, isn't this same as 0x31? */
736/** Processor feature XSAVEOPT unsupported. */
737#define GIM_HV_STATUS_PROC_FEAT_PAGE_XSAVE_SAVE_AREA_INCOMPATIBLE 0x36
738/** Processor architecture unsupoorted. */
739#define GIM_HV_STATUS_INCOMPATIBLE_PROCESSOR 0x37
740/** Max. domains for platform I/O remapping reached. */
741#define GIM_HV_STATUS_INSUFFICIENT_DEVICE_DOMAINS 0x38
742/** Processor feature AES unsupported. */
743#define GIM_HV_STATUS_PROC_FEAT_AES_NOT_SUPPORTED 0x39
744/** Processor feature PCMULQDQ unsupported. */
745#define GIM_HV_STATUS_PROC_FEAT_PCMULQDQ_NOT_SUPPORTED 0x3A
746/** Processor feature XSAVE features unsupported. */
747#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEATURES_INCOMPATIBLE 0x3B
748/** Generic CPUID validation error. */
749#define GIM_HV_STATUS_CPUID_FEAT_VALIDATION_ERROR 0x3C
750/** XSAVE CPUID validation error. */
751#define GIM_HV_STATUS_CPUID_XSAVE_FEAT_VALIDATION_ERROR 0x3D
752/** Processor startup timed out. */
753#define GIM_HV_STATUS_PROCESSOR_STARTUP_TIMEOUT 0x3E
754/** SMX enabled by the BIOS. */
755#define GIM_HV_STATUS_SMX_ENABLED 0x3F
756/** Processor feature PCID unsupported. */
757#define GIM_HV_STATUS_PROC_FEAT_PCID_NOT_SUPPORTED 0x40
758/** Invalid LP index. */
759#define GIM_HV_STATUS_INVALID_LP_INDEX 0x41
760/** Processor feature PCID unsupported. */
761#define GIM_HV_STATUS_FEAT_FMA4_NOT_SUPPORTED 0x42
762/** Processor feature PCID unsupported. */
763#define GIM_HV_STATUS_FEAT_F16C_NOT_SUPPORTED 0x43
764/** Processor feature PCID unsupported. */
765#define GIM_HV_STATUS_PROC_FEAT_RDRAND_NOT_SUPPORTED 0x44
766/** Processor feature RDWRFSGS unsupported. */
767#define GIM_HV_STATUS_PROC_FEAT_RDWRFSGS_NOT_SUPPORTED 0x45
768/** Processor feature SMEP unsupported. */
769#define GIM_HV_STATUS_PROC_FEAT_SMEP_NOT_SUPPORTED 0x46
770/** Processor feature enhanced fast string unsupported. */
771#define GIM_HV_STATUS_PROC_FEAT_ENHANCED_FAST_STRING_NOT_SUPPORTED 0x47
772/** Processor feature MOVBE unsupported. */
773#define GIM_HV_STATUS_PROC_FEAT_MOVBE_NOT_SUPPORTED 0x48
774/** Processor feature BMI1 unsupported. */
775#define GIM_HV_STATUS_PROC_FEAT_BMI1_NOT_SUPPORTED 0x49
776/** Processor feature BMI2 unsupported. */
777#define GIM_HV_STATUS_PROC_FEAT_BMI2_NOT_SUPPORTED 0x4A
778/** Processor feature HLE unsupported. */
779#define GIM_HV_STATUS_PROC_FEAT_HLE_NOT_SUPPORTED 0x4B
780/** Processor feature RTM unsupported. */
781#define GIM_HV_STATUS_PROC_FEAT_RTM_NOT_SUPPORTED 0x4C
782/** Processor feature XSAVE FMA unsupported. */
783#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FMA_NOT_SUPPORTED 0x4D
784/** Processor feature XSAVE AVX2 unsupported. */
785#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX2_NOT_SUPPORTED 0x4E
786/** Processor feature NPIEP1 unsupported. */
787#define GIM_HV_STATUS_PROC_FEAT_NPIEP1_NOT_SUPPORTED 0x4F
788/** @} */
789
790
791/** @name Hyper-V MSR - Debug control (MSR_GIM_HV_SYNTH_DEBUG_CONTROL).
792 * @{
793 */
794/** Perform debug write. */
795#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(a) RT_BOOL((a) & RT_BIT_64(0))
796/** Perform debug read. */
797#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(a) RT_BOOL((a) & RT_BIT_64(1))
798/** Returns length of the debug write buffer. */
799#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(a) (((a) & UINT64_C(0xffff0000)) >> 16)
800/** @} */
801
802
803/** @name Hyper-V MSR - Debug status (MSR_GIM_HV_SYNTH_DEBUG_STATUS).
804 * @{
805 */
806/** Debug send buffer operation success. */
807#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS RT_BIT_64(0)
808/** Debug receive buffer operation success. */
809#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS RT_BIT_64(2)
810/** Debug connection was reset. */
811#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_CONN_RESET RT_BIT_64(3)
812/** @} */
813
814
815/** @name Hyper-V MSR - synthetic interrupt (MSR_GIM_HV_SINTx).
816 * @{
817 */
818/** The interrupt masked mask. */
819#define MSR_GIM_HV_SINT_MASKED RT_BIT_64(16)
820/** Whether the interrupt source is masked. */
821#define MSR_GIM_HV_SINT_IS_MASKED(a) RT_BOOL((a) & MSR_GIM_HV_SINT_MASKED)
822/** Gets the interrupt vector. */
823#define MSR_GIM_HV_SINT_GET_VECTOR(a) ((a) & UINT64_C(0xff))
824/** The AutoEoi mask. */
825#define MSR_GIM_HV_SINT_AUTOEOI RT_BIT_64(17)
826/** Gets whether AutoEoi is enabled for the synthetic interrupt. */
827#define MSR_GIM_HV_SINT_IS_AUTOEOI(a) RT_BOOL((a) & MSR_GIM_HV_SINT_AUTOEOI)
828/** @} */
829
830
831/** @name Hyper-V MSR - synthetic interrupt message page (MSR_GIM_HV_SIMP).
832 * @{
833 */
834/** The SIMP enable mask. */
835#define MSR_GIM_HV_SIMP_ENABLE RT_BIT_64(0)
836/** Whether the SIMP is enabled. */
837#define MSR_GIM_HV_SIMP_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIMP_ENABLE)
838/** The SIMP guest-physical address. */
839#define MSR_GIM_HV_SIMP_GPA(a) ((a) & UINT64_C(0xfffffffffffff000))
840/** @} */
841
842
843/** @name Hyper-V hypercall debug options.
844 * @{ */
845/** Maximum debug data payload size in bytes. */
846#define GIM_HV_DEBUG_MAX_DATA_SIZE 4088
847
848/** The undocumented bit for MSR_GIM_HV_DEBUG_OPTIONS_MSR that makes it all
849 * work. */
850#define GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS RT_BIT(2)
851
852/** Guest will perform the HvPostDebugData hypercall until completion. */
853#define GIM_HV_DEBUG_POST_LOOP RT_BIT_32(0)
854/** Mask of valid HvPostDebugData options. */
855#define GIM_HV_DEBUG_POST_OPTIONS_MASK RT_BIT_32(0)
856
857/** Guest will perform the HvRetrieveDebugData hypercall until completion. */
858#define GIM_HV_DEBUG_RETREIVE_LOOP RT_BIT_32(0)
859/** Guest checks if any global debug session is active. */
860#define GIM_HV_DEBUG_RETREIVE_TEST_ACTIVITY RT_BIT_32(1)
861/** Mask of valid HvRetrieveDebugData options. */
862#define GIM_HV_DEBUG_RETREIVE_OPTIONS_MASK RT_BIT_32(0) | RT_BIT_32(1)
863
864/** Guest requests purging of incoming debug data. */
865#define GIM_HV_DEBUG_PURGE_INCOMING_DATA RT_BIT_32(0)
866/** Guest requests purging of outgoing debug data. */
867#define GIM_HV_DEBUG_PURGE_OUTGOING_DATA RT_BIT_32(1)
868/** @} */
869
870
871/** @name VMBus.
872 * These are just arbitrary definitions made up by Microsoft without
873 * any publicly available specification behind it.
874 * @{ */
875/** VMBus connection ID. */
876#define GIM_HV_VMBUS_MSG_CONNECTION_ID 1
877/** VMBus synthetic interrupt source (see VMBUS_MESSAGE_SINT in linux
878 * sources). */
879#define GIM_HV_VMBUS_MSG_SINT 2
880/** @} */
881
882/** @name SynIC.
883 * Synthetic Interrupt Controller definitions.
884 * @{ */
885/** SynIC version register. */
886#define GIM_HV_SVERSION 1
887/** Number of synthetic interrupt sources (warning, fixed in saved-states!). */
888#define GIM_HV_SINT_COUNT 16
889/** Lowest valid vector for synthetic interrupt. */
890#define GIM_HV_SINT_VECTOR_VALID_MIN 16
891/** Highest valid vector for synthetic interrupt. */
892#define GIM_HV_SINT_VECTOR_VALID_MAX 255
893/** Number of synthetic timers. */
894#define GIM_HV_STIMER_COUNT 4
895/** @} */
896
897/** @name Hyper-V synthetic interrupt message type.
898 * See 14.8.2 "SynIC Message Types"
899 * @{
900 */
901typedef enum GIMHVMSGTYPE
902{
903 GIMHVMSGTYPE_NONE = 0, /* Common messages */
904 GIMHVMSGTYPE_VMBUS = 1, /* Guest messages */
905 GIMHVMSGTYPE_UNMAPPEDGPA = 0x80000000, /* Hypervisor messages */
906 GIMHVMSGTYPE_GPAINTERCEPT = 0x80000001,
907 GIMHVMSGTYPE_TIMEREXPIRED = 0x80000010,
908 GIMHVMSGTYPE_INVALIDVPREGVAL = 0x80000020,
909 GIMHVMSGTYPE_UNRECOVERABLEXCPT = 0x80000021,
910 GIMHVMSGTYPE_UNSUPPORTEDFEAT = 0x80000022,
911 GIMHVMSGTYPE_APICEOI = 0x80000030,
912 GIMHVMSGTYPE_X64LEGACYFPERROR = 0x80000031,
913 GIMHVMSGTYPE_EVENTLOGBUFSCOMPLETE = 0x80000040,
914 GIMHVMSGTYPE_X64IOPORTINTERCEPT = 0x80010000,
915 GIMHVMSGTYPE_X64MSRINTERCEPT = 0x80010001,
916 GIMHVMSGTYPE_X64CPUIDINTERCEPT = 0x80010002,
917 GIMHVMSGTYPE_X64XCPTINTERCEPT = 0x80010003
918} GIMHVMSGTYPE;
919AssertCompileSize(GIMHVMSGTYPE, 4);
920/** @} */
921
922
923/** @name Hyper-V synthetic interrupt message format.
924 * @{ */
925#define GIM_HV_MSG_SIZE 256
926#define GIM_HV_MSG_MAX_PAYLOAD_SIZE 240
927#define GIM_HV_MSG_MAX_PAYLOAD_UNITS 30
928
929/**
930 * Synthetic interrupt message flags.
931 */
932typedef union GIMHVMSGFLAGS
933{
934 struct
935 {
936 uint8_t u1Pending : 1;
937 uint8_t u7Reserved : 7;
938 } n;
939 uint8_t u;
940} GIMHVMSGFLAGS;
941AssertCompileSize(GIMHVMSGFLAGS, sizeof(uint8_t));
942
943/**
944 * Synthetic interrupt message header.
945 *
946 * @remarks The layout of this structure differs from
947 * the Hyper-V spec. Aug 8, 2013 v4.0a. Layout
948 * in accordance w/ VMBus client expectations.
949 */
950typedef struct GIMHVMSGHDR
951{
952 GIMHVMSGTYPE enmMessageType;
953 uint8_t cbPayload;
954 GIMHVMSGFLAGS MessageFlags;
955 uint16_t uRsvd;
956 union
957 {
958 uint64_t uOriginatorId;
959 uint64_t uPartitionId;
960 uint64_t uPortId;
961 } msgid;
962} GIMHVMSGHDR;
963/** Pointer to a synthetic interrupt message header. */
964typedef GIMHVMSGHDR *PGIMHVMSGHDR;
965AssertCompileMemberOffset(GIMHVMSGHDR, cbPayload, 4);
966AssertCompileMemberOffset(GIMHVMSGHDR, MessageFlags, 5);
967AssertCompileMemberOffset(GIMHVMSGHDR, msgid, 8);
968AssertCompileSize(GIMHVMSGHDR, GIM_HV_MSG_SIZE - GIM_HV_MSG_MAX_PAYLOAD_SIZE);
969
970/**
971 * Synthetic interrupt message.
972 */
973typedef struct GIMHVMSG
974{
975 GIMHVMSGHDR MsgHdr;
976 uint64_t aPayload[GIM_HV_MSG_MAX_PAYLOAD_UNITS];
977} GIMHVMSG;
978/** Pointer to a synthetic interrupt message. */
979typedef GIMHVMSG *PGIMHVMSG;
980AssertCompileSize(GIMHVMSG, GIM_HV_MSG_SIZE);
981/** @} */
982
983
984/** @name Hyper-V hypercall parameters.
985 * @{ */
986/**
987 * HvPostMessage hypercall input.
988 */
989typedef struct GIMHVPOSTMESSAGEIN
990{
991 uint32_t uConnectionId;
992 uint32_t uPadding;
993 GIMHVMSGTYPE enmMessageType;
994 uint32_t cbPayload;
995} GIMHVPOSTMESSAGEIN;
996/** Pointer to a HvPostMessage input struct. */
997typedef GIMHVPOSTMESSAGEIN *PGIMHVPOSTMESSAGEIN;
998AssertCompileSize(GIMHVPOSTMESSAGEIN, 16);
999
1000/**
1001 * HvResetDebugData hypercall input.
1002 */
1003typedef struct GIMHVDEBUGRESETIN
1004{
1005 uint32_t fFlags;
1006 uint32_t uPadding;
1007} GIMHVDEBUGRESETIN;
1008/** Pointer to a HvResetDebugData input struct. */
1009typedef GIMHVDEBUGRESETIN *PGIMHVDEBUGRESETIN;
1010AssertCompileSize(GIMHVDEBUGRESETIN, 8);
1011
1012/**
1013 * HvPostDebugData hypercall input.
1014 */
1015typedef struct GIMHVDEBUGPOSTIN
1016{
1017 uint32_t cbWrite;
1018 uint32_t fFlags;
1019} GIMHVDEBUGPOSTIN;
1020/** Pointer to a HvPostDebugData input struct. */
1021typedef GIMHVDEBUGPOSTIN *PGIMHVDEBUGPOSTIN;
1022AssertCompileSize(GIMHVDEBUGPOSTIN, 8);
1023
1024/**
1025 * HvPostDebugData hypercall output.
1026 */
1027typedef struct GIMHVDEBUGPOSTOUT
1028{
1029 uint32_t cbPending;
1030 uint32_t uPadding;
1031} GIMHVDEBUGPOSTOUT;
1032/** Pointer to a HvPostDebugData output struct. */
1033typedef GIMHVDEBUGPOSTOUT *PGIMHVDEBUGPOSTOUT;
1034AssertCompileSize(GIMHVDEBUGPOSTOUT, 8);
1035
1036/**
1037 * HvRetrieveDebugData hypercall input.
1038 */
1039typedef struct GIMHVDEBUGRETRIEVEIN
1040{
1041 uint32_t cbRead;
1042 uint32_t fFlags;
1043 uint64_t u64Timeout;
1044} GIMHVDEBUGRETRIEVEIN;
1045/** Pointer to a HvRetrieveDebugData input struct. */
1046typedef GIMHVDEBUGRETRIEVEIN *PGIMHVDEBUGRETRIEVEIN;
1047AssertCompileSize(GIMHVDEBUGRETRIEVEIN, 16);
1048
1049/**
1050 * HvRetriveDebugData hypercall output.
1051 */
1052typedef struct GIMHVDEBUGRETRIEVEOUT
1053{
1054 uint32_t cbRead;
1055 uint32_t cbRemaining;
1056} GIMHVDEBUGRETRIEVEOUT;
1057/** Pointer to a HvRetrieveDebugData output struct. */
1058typedef GIMHVDEBUGRETRIEVEOUT *PGIMHVDEBUGRETRIEVEOUT;
1059AssertCompileSize(GIMHVDEBUGRETRIEVEOUT, 8);
1060
1061/**
1062 * HvExtCallQueryCapabilities hypercall output.
1063 */
1064typedef struct GIMHVEXTQUERYCAP
1065{
1066 uint64_t fCapabilities;
1067} GIMHVEXTQUERYCAP;
1068/** Pointer to a HvExtCallQueryCapabilities output struct. */
1069typedef GIMHVEXTQUERYCAP *PGIMHVEXTQUERYCAP;
1070AssertCompileSize(GIMHVEXTQUERYCAP, 8);
1071
1072/**
1073 * HvExtCallGetBootZeroedMemory hypercall output.
1074 */
1075typedef struct GIMHVEXTGETBOOTZEROMEM
1076{
1077 RTGCPHYS GCPhysStart;
1078 uint64_t cPages;
1079} GIMHVEXTGETBOOTZEROMEM;
1080/** Pointer to a HvExtCallGetBootZeroedMemory output struct. */
1081typedef GIMHVEXTGETBOOTZEROMEM *PGIMHVEXTGETBOOTZEROMEM;
1082AssertCompileSize(GIMHVEXTGETBOOTZEROMEM, 16);
1083/** @} */
1084
1085
1086/** Hyper-V page size. */
1087#define GIM_HV_PAGE_SIZE 4096
1088/** Hyper-V page shift. */
1089#define GIM_HV_PAGE_SHIFT 12
1090
1091/** Microsoft Hyper-V vendor signature. */
1092#define GIM_HV_VENDOR_MICROSOFT "Microsoft Hv"
1093
1094/**
1095 * MMIO2 region indices.
1096 */
1097/** The hypercall page region. */
1098#define GIM_HV_HYPERCALL_PAGE_REGION_IDX UINT8_C(0)
1099/** The TSC page region. */
1100#define GIM_HV_REF_TSC_PAGE_REGION_IDX UINT8_C(1)
1101/** The maximum region index (must be <= UINT8_MAX). */
1102#define GIM_HV_REGION_IDX_MAX GIM_HV_REF_TSC_PAGE_REGION_IDX
1103
1104/**
1105 * Hyper-V TSC (HV_REFERENCE_TSC_PAGE) structure placed in the TSC reference
1106 * page.
1107 */
1108typedef struct GIMHVREFTSC
1109{
1110 uint32_t u32TscSequence;
1111 uint32_t uReserved0;
1112 uint64_t u64TscScale;
1113 int64_t i64TscOffset;
1114} GIMHVTSCPAGE;
1115/** Pointer to Hyper-V reference TSC. */
1116typedef GIMHVREFTSC *PGIMHVREFTSC;
1117/** Pointer to a const Hyper-V reference TSC. */
1118typedef GIMHVREFTSC const *PCGIMHVREFTSC;
1119
1120/**
1121 * Type of the next reply to be sent to the debug connection of the guest.
1122 *
1123 * @remarks This is saved as part of saved-state, so don't re-order or
1124 * alter the size!
1125 */
1126typedef enum GIMHVDEBUGREPLY
1127{
1128 /** Send UDP packet. */
1129 GIMHVDEBUGREPLY_UDP = 0,
1130 /** Send DHCP offer for DHCP discover. */
1131 GIMHVDEBUGREPLY_DHCP_OFFER,
1132 /** DHCP offer sent. */
1133 GIMHVDEBUGREPLY_DHCP_OFFER_SENT,
1134 /** Send DHCP acknowledgement for DHCP request. */
1135 GIMHVDEBUGREPLY_DHCP_ACK,
1136 /** DHCP acknowledgement sent. */
1137 GIMHVDEBUGREPLY_DHCP_ACK_SENT,
1138 /** Sent ARP reply. */
1139 GIMHVDEBUGREPLY_ARP_REPLY,
1140 /** ARP reply sent. */
1141 GIMHVDEBUGREPLY_ARP_REPLY_SENT,
1142 /** Customary 32-bit type hack. */
1143 GIMHVDEBUGREPLY_32BIT_HACK = 0x7fffffff
1144} GIMHVDEBUGREPLY;
1145AssertCompileSize(GIMHVDEBUGREPLY, sizeof(uint32_t));
1146
1147/**
1148 * GIM Hyper-V VM instance data.
1149 * Changes to this must checked against the padding of the gim union in VM!
1150 */
1151typedef struct GIMHV
1152{
1153 /** @name Primary MSRs.
1154 * @{ */
1155 /** Guest OS identity MSR. */
1156 uint64_t u64GuestOsIdMsr;
1157 /** Hypercall MSR. */
1158 uint64_t u64HypercallMsr;
1159 /** Reference TSC page MSR. */
1160 uint64_t u64TscPageMsr;
1161 /** @} */
1162
1163 /** @name CPUID features.
1164 * @{ */
1165 /** Basic features. */
1166 uint32_t uBaseFeat;
1167 /** Partition flags. */
1168 uint32_t uPartFlags;
1169 /** Power management. */
1170 uint32_t uPowMgmtFeat;
1171 /** Miscellaneous. */
1172 uint32_t uMiscFeat;
1173 /** Hypervisor hints to the guest. */
1174 uint32_t uHyperHints;
1175 /** Hypervisor capabilities. */
1176 uint32_t uHyperCaps;
1177 /** @} */
1178
1179 /** @name Guest Crash MSRs.
1180 * @{
1181 */
1182 /** Guest crash control MSR. */
1183 uint64_t uCrashCtlMsr;
1184 /** Guest crash parameter 0 MSR. */
1185 uint64_t uCrashP0Msr;
1186 /** Guest crash parameter 1 MSR. */
1187 uint64_t uCrashP1Msr;
1188 /** Guest crash parameter 2 MSR. */
1189 uint64_t uCrashP2Msr;
1190 /** Guest crash parameter 3 MSR. */
1191 uint64_t uCrashP3Msr;
1192 /** Guest crash parameter 4 MSR. */
1193 uint64_t uCrashP4Msr;
1194 /** @} */
1195
1196 /** @name Time management.
1197 * @{ */
1198 /** Per-VM R0 Spinlock for protecting EMT writes to the TSC page. */
1199 RTSPINLOCK hSpinlockR0;
1200 /** The TSC frequency (in HZ) reported to the guest. */
1201 uint64_t cTscTicksPerSecond;
1202 /** @} */
1203
1204 /** @name Hypercalls.
1205 * @{ */
1206 /** Guest address of the hypercall input parameter page. */
1207 RTGCPHYS GCPhysHypercallIn;
1208 /** Guest address of the hypercall output parameter page. */
1209 RTGCPHYS GCPhysHypercallOut;
1210 /** Pointer to the hypercall input parameter page - R3. */
1211 R3PTRTYPE(uint8_t *) pbHypercallIn;
1212 /** Pointer to the hypercall output parameter page - R3. */
1213 R3PTRTYPE(uint8_t *) pbHypercallOut;
1214 /** @} */
1215
1216 /** @name Guest debugging.
1217 * @{ */
1218 /** Whether we're posing as the Microsoft vendor. */
1219 bool fIsVendorMsHv;
1220 /** Whether we're posing as the Microsoft virtualization service. */
1221 bool fIsInterfaceVs;
1222 /** Whether debugging support is enabled. */
1223 bool fDbgEnabled;
1224 /** Whether we should suggest a hypercall-based debug interface to the guest. */
1225 bool fDbgHypercallInterface;
1226 bool afAlignment0[4];
1227 /** The action to take while sending replies. */
1228 GIMHVDEBUGREPLY enmDbgReply;
1229 /** The IP address chosen by/assigned to the guest. */
1230 RTNETADDRIPV4 DbgGuestIp4Addr;
1231 /** Transaction ID for the BOOTP+DHCP sequence. */
1232 uint32_t uDbgBootpXId;
1233 /** The source UDP port used by the guest while sending debug packets. */
1234 uint16_t uUdpGuestSrcPort;
1235 /** The destination UDP port used by the guest while sending debug packets. */
1236 uint16_t uUdpGuestDstPort;
1237 /** Debug send buffer MSR. */
1238 uint64_t uDbgSendBufferMsr;
1239 /** Debug receive buffer MSR. */
1240 uint64_t uDbgRecvBufferMsr;
1241 /** Debug pending buffer MSR. */
1242 uint64_t uDbgPendingBufferMsr;
1243 /** Debug status MSR. */
1244 uint64_t uDbgStatusMsr;
1245 /** Intermediate debug I/O buffer. */
1246 R3PTRTYPE(void *) pvDbgBuffer;
1247 R3PTRTYPE(void *) pvAlignment0;
1248 /** @} */
1249
1250 /** Array of MMIO2 regions. */
1251 GIMMMIO2REGION aMmio2Regions[GIM_HV_REGION_IDX_MAX + 1];
1252} GIMHV;
1253/** Pointer to per-VM GIM Hyper-V instance data. */
1254typedef GIMHV *PGIMHV;
1255/** Pointer to const per-VM GIM Hyper-V instance data. */
1256typedef GIMHV const *PCGIMHV;
1257AssertCompileMemberAlignment(GIMHV, aMmio2Regions, 8);
1258AssertCompileMemberAlignment(GIMHV, hSpinlockR0, sizeof(uintptr_t));
1259
1260/**
1261 * Hyper-V per-VCPU synthetic timer.
1262 */
1263typedef struct GIMHVSTIMER
1264{
1265 /** Synthetic timer handle. */
1266 TMTIMERHANDLE hTimer;
1267 /** Virtual CPU ID this timer belongs to (for reverse mapping). */
1268 VMCPUID idCpu;
1269 /** The index of this timer in the auStimers array (for reverse mapping). */
1270 uint32_t idxStimer;
1271 /** Synthetic timer config MSR. */
1272 uint64_t uStimerConfigMsr;
1273 /** Synthetic timer count MSR. */
1274 uint64_t uStimerCountMsr;
1275} GIMHVSTIMER;
1276/** Pointer to per-VCPU Hyper-V synthetic timer. */
1277typedef GIMHVSTIMER *PGIMHVSTIMER;
1278/** Pointer to a const per-VCPU Hyper-V synthetic timer. */
1279typedef GIMHVSTIMER const *PCGIMHVSTIMER;
1280AssertCompileSizeAlignment(GIMHVSTIMER, 8);
1281
1282/**
1283 * Hyper-V VCPU instance data.
1284 * Changes to this must checked against the padding of the gim union in VMCPU!
1285 */
1286typedef struct GIMHVCPU
1287{
1288 /** @name Synthetic interrupt MSRs.
1289 * @{ */
1290 /** Synthetic interrupt message page MSR. */
1291 uint64_t uSimpMsr;
1292 /** Interrupt source MSRs. */
1293 uint64_t auSintMsrs[GIM_HV_SINT_COUNT];
1294 /** Synethtic interrupt events flag page MSR. */
1295 uint64_t uSiefpMsr;
1296 /** APIC-assist page MSR. */
1297 uint64_t uApicAssistPageMsr;
1298 /** Synthetic interrupt control MSR. */
1299 uint64_t uSControlMsr;
1300 /** Synthetic timers. */
1301 GIMHVSTIMER aStimers[GIM_HV_STIMER_COUNT];
1302 /** @} */
1303
1304 /** @name Statistics.
1305 * @{ */
1306 STAMCOUNTER aStatStimerFired[GIM_HV_STIMER_COUNT];
1307 /** @} */
1308} GIMHVCPU;
1309/** Pointer to per-VCPU GIM Hyper-V instance data. */
1310typedef GIMHVCPU *PGIMHVCPU;
1311/** Pointer to const per-VCPU GIM Hyper-V instance data. */
1312typedef GIMHVCPU const *PCGIMHVCPU;
1313
1314
1315RT_C_DECLS_BEGIN
1316
1317#ifdef IN_RING0
1318VMMR0_INT_DECL(int) gimR0HvInitVM(PVMCC pVM);
1319VMMR0_INT_DECL(int) gimR0HvTermVM(PVMCC pVM);
1320VMMR0_INT_DECL(int) gimR0HvUpdateParavirtTsc(PVMCC pVM, uint64_t u64Offset);
1321#endif /* IN_RING0 */
1322
1323#ifdef IN_RING3
1324VMMR3_INT_DECL(int) gimR3HvInit(PVM pVM, PCFGMNODE pGimCfg);
1325VMMR3_INT_DECL(int) gimR3HvInitCompleted(PVM pVM);
1326VMMR3_INT_DECL(int) gimR3HvTerm(PVM pVM);
1327VMMR3_INT_DECL(void) gimR3HvRelocate(PVM pVM, RTGCINTPTR offDelta);
1328VMMR3_INT_DECL(void) gimR3HvReset(PVM pVM);
1329VMMR3_INT_DECL(int) gimR3HvSave(PVM pVM, PSSMHANDLE pSSM);
1330VMMR3_INT_DECL(int) gimR3HvLoad(PVM pVM, PSSMHANDLE pSSM);
1331VMMR3_INT_DECL(int) gimR3HvLoadDone(PVM pVM, PSSMHANDLE pSSM);
1332VMMR3_INT_DECL(int) gimR3HvGetDebugSetup(PVM pVM, PGIMDEBUGSETUP pDbgSetup);
1333
1334VMMR3_INT_DECL(int) gimR3HvDisableSiefPage(PVMCPU pVCpu);
1335VMMR3_INT_DECL(int) gimR3HvEnableSiefPage(PVMCPU pVCpu, RTGCPHYS GCPhysSiefPage);
1336VMMR3_INT_DECL(int) gimR3HvEnableSimPage(PVMCPU pVCpu, RTGCPHYS GCPhysSimPage);
1337VMMR3_INT_DECL(int) gimR3HvDisableSimPage(PVMCPU pVCpu);
1338VMMR3_INT_DECL(int) gimR3HvDisableApicAssistPage(PVMCPU pVCpu);
1339VMMR3_INT_DECL(int) gimR3HvEnableApicAssistPage(PVMCPU pVCpu, RTGCPHYS GCPhysTscPage);
1340VMMR3_INT_DECL(int) gimR3HvDisableTscPage(PVM pVM);
1341VMMR3_INT_DECL(int) gimR3HvEnableTscPage(PVM pVM, RTGCPHYS GCPhysTscPage, bool fUseThisTscSeq, uint32_t uTscSeq);
1342VMMR3_INT_DECL(int) gimR3HvDisableHypercallPage(PVM pVM);
1343VMMR3_INT_DECL(int) gimR3HvEnableHypercallPage(PVM pVM, RTGCPHYS GCPhysHypercallPage);
1344
1345VMMR3_INT_DECL(int) gimR3HvHypercallPostDebugData(PVM pVM, int *prcHv);
1346VMMR3_INT_DECL(int) gimR3HvHypercallRetrieveDebugData(PVM pVM, int *prcHv);
1347VMMR3_INT_DECL(int) gimR3HvDebugWrite(PVM pVM, void *pvData, uint32_t cbWrite, uint32_t *pcbWritten, bool fUdpPkt);
1348VMMR3_INT_DECL(int) gimR3HvDebugRead(PVM pVM, void *pvBuf, uint32_t cbBuf, uint32_t cbRead, uint32_t *pcbRead,
1349 uint32_t cMsTimeout, bool fUdpPkt);
1350VMMR3_INT_DECL(int) gimR3HvHypercallExtQueryCap(PVM pVM, int *prcHv);
1351VMMR3_INT_DECL(int) gimR3HvHypercallExtGetBootZeroedMem(PVM pVM, int *prcHv);
1352
1353#endif /* IN_RING3 */
1354
1355VMM_INT_DECL(PGIMMMIO2REGION) gimHvGetMmio2Regions(PVM pVM, uint32_t *pcRegions);
1356VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM);
1357VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PCVM pVM);
1358VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu);
1359VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPUCC pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr);
1360VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPUCC pVCpu, PCPUMCTX pCtx);
1361VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercallEx(PVMCPUCC pVCpu, PCPUMCTX pCtx, unsigned uDisOpcode, uint8_t cbInstr);
1362VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
1363VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
1364
1365VMM_INT_DECL(void) gimHvStartStimer(PVMCPUCC pVCpu, PCGIMHVSTIMER pHvStimer);
1366
1367RT_C_DECLS_END
1368
1369#endif /* !VMM_INCLUDED_SRC_include_GIMHvInternal_h */
1370
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