VirtualBox

source: vbox/trunk/src/VBox/VMM/include/GIMHvInternal.h@ 69296

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1/* $Id: GIMHvInternal.h 69111 2017-10-17 14:26:02Z vboxsync $ */
2/** @file
3 * GIM - Hyper-V, Internal header file.
4 */
5
6/*
7 * Copyright (C) 2014-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___GIMHvInternal_h
19#define ___GIMHvInternal_h
20
21#include <VBox/vmm/gim.h>
22#include <VBox/vmm/cpum.h>
23
24#include <iprt/net.h>
25
26/** @name Hyper-V base feature identification.
27 * Features based on current partition privileges (per-VM).
28 * @{
29 */
30/** Virtual processor runtime MSR available. */
31#define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
32/** Partition reference counter MSR available. */
33#define GIM_HV_BASE_FEAT_PART_TIME_REF_COUNT_MSR RT_BIT(1)
34/** Basic Synthetic Interrupt Controller MSRs available. */
35#define GIM_HV_BASE_FEAT_BASIC_SYNIC_MSRS RT_BIT(2)
36/** Synthetic Timer MSRs available. */
37#define GIM_HV_BASE_FEAT_STIMER_MSRS RT_BIT(3)
38/** APIC access MSRs (EOI, ICR, TPR) available. */
39#define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4)
40/** Hypercall MSRs available. */
41#define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5)
42/** Access to VCPU index MSR available. */
43#define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6)
44/** Virtual system reset MSR available. */
45#define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7)
46/** Statistic pages MSRs available. */
47#define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8)
48/** Paritition reference TSC MSR available. */
49#define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9)
50/** Virtual guest idle state MSR available. */
51#define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10)
52/** Timer frequency MSRs (TSC and APIC) available. */
53#define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11)
54/** Debug MSRs available. */
55#define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12)
56/** @} */
57
58/** @name Hyper-V partition-creation feature identification.
59 * Indicates flags specified during partition creation.
60 * @{
61 */
62/** Create partitions. */
63#define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
64/** Access partition Id. */
65#define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1)
66/** Access memory pool. */
67#define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2)
68/** Adjust message buffers. */
69#define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3)
70/** Post messages. */
71#define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4)
72/** Signal events. */
73#define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5)
74/** Create port. */
75#define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6)
76/** Connect port. */
77#define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7)
78/** Access statistics. */
79#define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8)
80/** Debugging.*/
81#define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11)
82/** CPU management. */
83#define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12)
84/** CPU profiler. */
85#define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13)
86/** Enable expanded stack walking. */
87#define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14)
88/** @} */
89
90/** @name Hyper-V power management feature identification.
91 * @{
92 */
93/** Maximum CPU power state C0. */
94#define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
95/** Maximum CPU power state C1. */
96#define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1)
97/** Maximum CPU power state C2. */
98#define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2)
99/** Maximum CPU power state C3. */
100#define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3)
101/** HPET is required to enter C3 power state. */
102#define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4)
103/** @} */
104
105/** @name Hyper-V miscellaneous feature identification.
106 * Miscellaneous features available for the current partition.
107 * @{
108 */
109/** MWAIT instruction available. */
110#define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
111/** Guest debugging support available. */
112#define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1)
113/** Performance monitor support is available. */
114#define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2)
115/** Support for physical CPU dynamic partitioning events. */
116#define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3)
117/** Support for passing hypercall input parameter block via XMM registers. */
118#define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4)
119/** Support for virtual guest idle state. */
120#define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5)
121/** Support for hypervisor sleep state. */
122#define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6)
123/** Support for querying NUMA distances. */
124#define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7)
125/** Support for determining timer frequencies. */
126#define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8)
127/** Support for injecting synthetic machine checks. */
128#define GIM_HV_MISC_FEAT_INJECT_SYNMC_XCPT RT_BIT(9)
129/** Support for guest crash MSRs. */
130#define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10)
131/** Support for debug MSRs. */
132#define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11)
133/** Npiep1 Available */ /** @todo What the heck is this? */
134#define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12)
135/** Disable hypervisor available. */
136#define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13)
137/** @} */
138
139/** @name Hyper-V implementation recommendations.
140 * Recommendations from the hypervisor for the guest for optimal performance.
141 * @{
142 */
143/** Use hypercall for address space switches rather than MOV CR3. */
144#define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
145/** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */
146#define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1)
147/** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
148#define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2)
149/** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
150#define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3)
151/** Use hypervisor provided MSR for a system reset. */
152#define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4)
153/** Relax timer-related checks (watchdogs/deadman timeouts) that rely on
154 * timely deliver of external interrupts. */
155#define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5)
156/** Use DMA remapping. */
157#define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6)
158/** Use interrupt remapping. */
159#define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7)
160/** Use X2APIC MSRs rather than MMIO. */
161#define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8)
162/** Deprecate Auto EOI (end of interrupt). */
163#define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9)
164/** @} */
165
166
167/** @name Hyper-V implementation hardware features.
168 * Which hardware features are in use by the hypervisor.
169 * @{
170 */
171/** APIC overlay is used. */
172#define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
173/** MSR bitmaps is used. */
174#define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1)
175/** Architectural performance counter supported. */
176#define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2)
177/** Nested paging is used. */
178#define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3)
179/** DMA remapping is used. */
180#define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4)
181/** Interrupt remapping is used. */
182#define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5)
183/** Memory patrol scrubber is present. */
184#define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6)
185/** @} */
186
187
188/** @name Hyper-V MSRs.
189 * @{
190 */
191/** Start of range 0. */
192#define MSR_GIM_HV_RANGE0_START UINT32_C(0x40000000)
193/** Guest OS identification (R/W) */
194#define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000)
195/** Enable hypercall interface (R/W) */
196#define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001)
197/** Virtual processor's (VCPU) index (R) */
198#define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002)
199/** Reset operation (R/W) */
200#define MSR_GIM_HV_RESET UINT32_C(0x40000003)
201/** End of range 0. */
202#define MSR_GIM_HV_RANGE0_END MSR_GIM_HV_RESET
203
204/** Start of range 1. */
205#define MSR_GIM_HV_RANGE1_START UINT32_C(0x40000010)
206/** Virtual processor's (VCPU) runtime (R) */
207#define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010)
208/** End of range 1. */
209#define MSR_GIM_HV_RANGE1_END MSR_GIM_HV_VP_RUNTIME
210
211/** Start of range 2. */
212#define MSR_GIM_HV_RANGE2_START UINT32_C(0x40000020)
213/** Per-VM reference counter (R) */
214#define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020)
215/** Per-VM TSC page (R/W) */
216#define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021)
217/** Frequency of TSC in Hz as reported by the hypervisor (R) */
218#define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022)
219/** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
220#define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023)
221/** End of range 2. */
222#define MSR_GIM_HV_RANGE2_END MSR_GIM_HV_APIC_FREQ
223
224/** Start of range 3. */
225#define MSR_GIM_HV_RANGE3_START UINT32_C(0x40000070)
226/** Access to APIC EOI (End-Of-Interrupt) register (W) */
227#define MSR_GIM_HV_EOI UINT32_C(0x40000070)
228/** Access to APIC ICR (Interrupt Command) register (R/W) */
229#define MSR_GIM_HV_ICR UINT32_C(0x40000071)
230/** Access to APIC TPR (Task Priority) register (R/W) */
231#define MSR_GIM_HV_TPR UINT32_C(0x40000072)
232/** Enables lazy EOI processing (R/W) */
233#define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073)
234/** End of range 3. */
235#define MSR_GIM_HV_RANGE3_END MSR_GIM_HV_APIC_ASSIST_PAGE
236
237/** Start of range 4. */
238#define MSR_GIM_HV_RANGE4_START UINT32_C(0x40000080)
239/** Control behaviour of synthetic interrupt controller (R/W) */
240#define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080)
241/** Synthetic interrupt controller version (R) */
242#define MSR_GIM_HV_SVERSION UINT32_C(0x40000081)
243/** Base address of synthetic interrupt event flag (R/W) */
244#define MSR_GIM_HV_SIEFP UINT32_C(0x40000082)
245/** Base address of synthetic interrupt message page (R/W) */
246#define MSR_GIM_HV_SIMP UINT32_C(0x40000083)
247/** End-Of-Message in synthetic interrupt parameter page (W) */
248#define MSR_GIM_HV_EOM UINT32_C(0x40000084)
249/** End of range 4. */
250#define MSR_GIM_HV_RANGE4_END MSR_GIM_HV_EOM
251
252/** Start of range 5. */
253#define MSR_GIM_HV_RANGE5_START UINT32_C(0x40000090)
254/** Configures synthetic interrupt source 0 (R/W) */
255#define MSR_GIM_HV_SINT0 UINT32_C(0x40000090)
256/** Configures synthetic interrupt source 1 (R/W) */
257#define MSR_GIM_HV_SINT1 UINT32_C(0x40000091)
258/** Configures synthetic interrupt source 2 (R/W) */
259#define MSR_GIM_HV_SINT2 UINT32_C(0x40000092)
260/** Configures synthetic interrupt source 3 (R/W) */
261#define MSR_GIM_HV_SINT3 UINT32_C(0x40000093)
262/** Configures synthetic interrupt source 4 (R/W) */
263#define MSR_GIM_HV_SINT4 UINT32_C(0x40000094)
264/** Configures synthetic interrupt source 5 (R/W) */
265#define MSR_GIM_HV_SINT5 UINT32_C(0x40000095)
266/** Configures synthetic interrupt source 6 (R/W) */
267#define MSR_GIM_HV_SINT6 UINT32_C(0x40000096)
268/** Configures synthetic interrupt source 7 (R/W) */
269#define MSR_GIM_HV_SINT7 UINT32_C(0x40000097)
270/** Configures synthetic interrupt source 8 (R/W) */
271#define MSR_GIM_HV_SINT8 UINT32_C(0x40000098)
272/** Configures synthetic interrupt source 9 (R/W) */
273#define MSR_GIM_HV_SINT9 UINT32_C(0x40000099)
274/** Configures synthetic interrupt source 10 (R/W) */
275#define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A)
276/** Configures synthetic interrupt source 11 (R/W) */
277#define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B)
278/** Configures synthetic interrupt source 12 (R/W) */
279#define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C)
280/** Configures synthetic interrupt source 13 (R/W) */
281#define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D)
282/** Configures synthetic interrupt source 14 (R/W) */
283#define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E)
284/** Configures synthetic interrupt source 15 (R/W) */
285#define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F)
286/** End of range 5. */
287#define MSR_GIM_HV_RANGE5_END MSR_GIM_HV_SINT15
288
289/** Start of range 6. */
290#define MSR_GIM_HV_RANGE6_START UINT32_C(0x400000B0)
291/** Configures register for synthetic timer 0 (R/W) */
292#define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0)
293/** Expiration time or period for synthetic timer 0 (R/W) */
294#define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1)
295/** Configures register for synthetic timer 1 (R/W) */
296#define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2)
297/** Expiration time or period for synthetic timer 1 (R/W) */
298#define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3)
299/** Configures register for synthetic timer 2 (R/W) */
300#define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4)
301/** Expiration time or period for synthetic timer 2 (R/W) */
302#define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5)
303/** Configures register for synthetic timer 3 (R/W) */
304#define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6)
305/** Expiration time or period for synthetic timer 3 (R/W) */
306#define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7)
307/** End of range 6. */
308#define MSR_GIM_HV_RANGE6_END MSR_GIM_HV_STIMER3_COUNT
309
310/** Start of range 7. */
311#define MSR_GIM_HV_RANGE7_START UINT32_C(0x400000C1)
312/** Trigger to transition to power state C1 (R) */
313#define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1)
314/** Trigger to transition to power state C2 (R) */
315#define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2)
316/** Trigger to transition to power state C3 (R) */
317#define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3)
318/** End of range 7. */
319#define MSR_GIM_HV_RANGE7_END MSR_GIM_HV_POWER_STATE_TRIGGER_C3
320
321/** Start of range 8. */
322#define MSR_GIM_HV_RANGE8_START UINT32_C(0x400000D1)
323/** Configure the recipe for power state transitions to C1 (R/W) */
324#define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1)
325/** Configure the recipe for power state transitions to C2 (R/W) */
326#define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2)
327/** Configure the recipe for power state transitions to C3 (R/W) */
328#define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3)
329/** End of range 8. */
330#define MSR_GIM_HV_RANGE8_END MSR_GIM_HV_POWER_STATE_CONFIG_C3
331
332/** Start of range 9. */
333#define MSR_GIM_HV_RANGE9_START UINT32_C(0x400000E0)
334/** Map the guest's retail partition stats page (R/W) */
335#define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0)
336/** Map the guest's internal partition stats page (R/W) */
337#define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1)
338/** Map the guest's retail VP stats page (R/W) */
339#define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2)
340/** Map the guest's internal VP stats page (R/W) */
341#define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3)
342/** End of range 9. */
343#define MSR_GIM_HV_RANGE9_END MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
344
345/** Start of range 10. */
346#define MSR_GIM_HV_RANGE10_START UINT32_C(0x400000F0)
347/** Trigger the guest's transition to idle power state (R) */
348#define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0)
349/** Synthetic debug control. */
350#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1)
351/** Synthetic debug status. */
352#define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2)
353/** Synthetic debug send buffer. */
354#define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3)
355/** Synthetic debug receive buffer. */
356#define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4)
357/** Synthetic debug pending buffer. */
358#define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5)
359/** End of range 10. */
360#define MSR_GIM_HV_RANGE10_END MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
361
362/** Start of range 11. */
363#define MSR_GIM_HV_RANGE11_START UINT32_C(0x400000FF)
364/** Undocumented debug options MSR. */
365#define MSR_GIM_HV_DEBUG_OPTIONS_MSR UINT32_C(0x400000FF)
366/** End of range 11. */
367#define MSR_GIM_HV_RANGE11_END MSR_GIM_HV_DEBUG_OPTIONS_MSR
368
369/** Start of range 12. */
370#define MSR_GIM_HV_RANGE12_START UINT32_C(0x40000100)
371/** Guest crash MSR 0. */
372#define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100)
373/** Guest crash MSR 1. */
374#define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101)
375/** Guest crash MSR 2. */
376#define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102)
377/** Guest crash MSR 3. */
378#define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103)
379/** Guest crash MSR 4. */
380#define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104)
381/** Guest crash control. */
382#define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105)
383/** End of range 12. */
384#define MSR_GIM_HV_RANGE12_END MSR_GIM_HV_CRASH_CTL
385/** @} */
386
387AssertCompile(MSR_GIM_HV_RANGE0_START <= MSR_GIM_HV_RANGE0_END);
388AssertCompile(MSR_GIM_HV_RANGE1_START <= MSR_GIM_HV_RANGE1_END);
389AssertCompile(MSR_GIM_HV_RANGE2_START <= MSR_GIM_HV_RANGE2_END);
390AssertCompile(MSR_GIM_HV_RANGE3_START <= MSR_GIM_HV_RANGE3_END);
391AssertCompile(MSR_GIM_HV_RANGE4_START <= MSR_GIM_HV_RANGE4_END);
392AssertCompile(MSR_GIM_HV_RANGE5_START <= MSR_GIM_HV_RANGE5_END);
393AssertCompile(MSR_GIM_HV_RANGE6_START <= MSR_GIM_HV_RANGE6_END);
394AssertCompile(MSR_GIM_HV_RANGE7_START <= MSR_GIM_HV_RANGE7_END);
395AssertCompile(MSR_GIM_HV_RANGE8_START <= MSR_GIM_HV_RANGE8_END);
396AssertCompile(MSR_GIM_HV_RANGE9_START <= MSR_GIM_HV_RANGE9_END);
397AssertCompile(MSR_GIM_HV_RANGE10_START <= MSR_GIM_HV_RANGE10_END);
398AssertCompile(MSR_GIM_HV_RANGE11_START <= MSR_GIM_HV_RANGE11_END);
399
400/** @name Hyper-V MSR - Reset (MSR_GIM_HV_RESET).
401 * @{
402 */
403/** The reset enable mask. */
404#define MSR_GIM_HV_RESET_ENABLE RT_BIT_64(0)
405/** Whether the reset MSR is enabled. */
406#define MSR_GIM_HV_RESET_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_RESET_ENABLE)
407/** @} */
408
409/** @name Hyper-V MSR - Hypercall (MSR_GIM_HV_HYPERCALL).
410 * @{
411 */
412/** Guest-physical page frame number of the hypercall-page. */
413#define MSR_GIM_HV_HYPERCALL_GUEST_PFN(a) ((a) >> 12)
414/** The hypercall enable mask. */
415#define MSR_GIM_HV_HYPERCALL_PAGE_ENABLE RT_BIT_64(0)
416/** Whether the hypercall-page is enabled or not. */
417#define MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE)
418/** @} */
419
420/** @name Hyper-V MSR - Reference TSC (MSR_GIM_HV_REF_TSC).
421 * @{
422 */
423/** Guest-physical page frame number of the TSC-page. */
424#define MSR_GIM_HV_REF_TSC_GUEST_PFN(a) ((a) >> 12)
425/** The TSC-page enable mask. */
426#define MSR_GIM_HV_REF_TSC_ENABLE RT_BIT_64(0)
427/** Whether the TSC-page is enabled or not. */
428#define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE)
429/** @} */
430
431/** @name Hyper-V MSR - Guest crash control (MSR_GIM_HV_CRASH_CTL).
432 * @{
433 */
434/** The Crash Control notify mask. */
435#define MSR_GIM_HV_CRASH_CTL_NOTIFY RT_BIT_64(63)
436/** @} */
437
438/** @name Hyper-V MSR - Guest OS ID (MSR_GIM_HV_GUEST_OS_ID).
439 * @{
440 */
441/** An open-source operating system. */
442#define MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(a) RT_BOOL((a) & RT_BIT_64(63))
443/** Vendor ID. */
444#define MSR_GIM_HV_GUEST_OS_ID_VENDOR(a) (uint32_t)(((a) >> 48) & 0xfff)
445/** Guest OS variant, depending on the vendor ID. */
446#define MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(a) (uint32_t)(((a) >> 40) & 0xff)
447/** Guest OS major version. */
448#define MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(a) (uint32_t)(((a) >> 32) & 0xff)
449/** Guest OS minor version. */
450#define MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(a) (uint32_t)(((a) >> 24) & 0xff)
451/** Guest OS service version (e.g. service pack number in case of Windows). */
452#define MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(a) (uint32_t)(((a) >> 16) & 0xff)
453/** Guest OS build number. */
454#define MSR_GIM_HV_GUEST_OS_ID_BUILD(a) (uint32_t)((a) & 0xffff)
455/** @} */
456
457/** @name Hyper-V MSR - APIC-assist page (MSR_GIM_HV_APIC_ASSIST_PAGE).
458 * @{
459 */
460/** Guest-physical page frame number of the APIC-assist page. */
461#define MSR_GIM_HV_APICASSIST_GUEST_PFN(a) ((a) >> 12)
462/** The APIC-assist page enable mask. */
463#define MSR_GIM_HV_APICASSIST_PAGE_ENABLE RT_BIT_64(0)
464/** Whether the APIC-assist page is enabled or not. */
465#define MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_APICASSIST_PAGE_ENABLE)
466/** @} */
467
468/** @name Hyper-V MSR - Synthetic Interrupt Event Flags page
469 * (MSR_GIM_HV_SIEFP).
470 * @{
471 */
472/** Guest-physical page frame number of the APIC-assist page. */
473#define MSR_GIM_HV_SIEF_GUEST_PFN(a) ((a) >> 12)
474/** The SIEF enable mask. */
475#define MSR_GIM_HV_SIEF_PAGE_ENABLE RT_BIT_64(0)
476/** Whether the SIEF page is enabled or not. */
477#define MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIEF_PAGE_ENABLE)
478/** @} */
479
480/** @name Hyper-V MSR - Synthetic Interrupt Control (MSR_GIM_HV_CONTROL).
481 * @{
482 */
483/** The SControl enable mask. */
484#define MSR_GIM_HV_SCONTROL_ENABLE RT_BIT_64(0)
485/** Whether SControl is enabled or not. */
486#define MSR_GIM_HV_SCONTROL_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SCONTROL_ENABLE)
487/** @} */
488
489/** @name Hyper-V MSR - Synthetic Timer Config (MSR_GIM_HV_STIMER_CONFIG).
490 * @{
491 */
492/** The Stimer enable mask. */
493#define MSR_GIM_HV_STIMER_ENABLE RT_BIT_64(0)
494/** Whether Stimer is enabled or not. */
495#define MSR_GIM_HV_STIMER_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_ENABLE)
496/** The Stimer periodic mask. */
497#define MSR_GIM_HV_STIMER_PERIODIC RT_BIT_64(1)
498/** Whether Stimer is enabled or not. */
499#define MSR_GIM_HV_STIMER_IS_PERIODIC(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_PERIODIC)
500/** The Stimer lazy mask. */
501#define MSR_GIM_HV_STIMER_LAZY RT_BIT_64(2)
502/** Whether Stimer is enabled or not. */
503#define MSR_GIM_HV_STIMER_IS_LAZY(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_LAZY)
504/** The Stimer auto-enable mask. */
505#define MSR_GIM_HV_STIMER_AUTO_ENABLE RT_BIT_64(3)
506/** Whether Stimer is enabled or not. */
507#define MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_AUTO_ENABLE)
508/** The Stimer SINTx mask (bits 16:19). */
509#define MSR_GIM_HV_STIMER_SINTX UINT64_C(0xf0000)
510/** Gets the Stimer synthetic interrupt source. */
511#define MSR_GIM_HV_STIMER_GET_SINTX(a) (((a) >> 16) & 0xf)
512/** The Stimer valid read/write mask. */
513#define MSR_GIM_HV_STIMER_RW_VALID ( MSR_GIM_HV_STIMER_ENABLE | MSR_GIM_HV_STIMER_PERIODIC \
514 | MSR_GIM_HV_STIMER_LAZY | MSR_GIM_HV_STIMER_AUTO_ENABLE \
515 | MSR_GIM_HV_STIMER_SINTX)
516/** @} */
517
518/**
519 * Hyper-V APIC-assist (HV_REFERENCE_TSC_PAGE) structure placed in the TSC
520 * reference page.
521 */
522typedef struct GIMHVAPICASSIST
523{
524 uint32_t fNoEoiRequired : 1;
525 uint32_t u31Reserved0 : 31;
526} GIMHVAPICASSIST;
527/** Pointer to Hyper-V reference TSC. */
528typedef GIMHVAPICASSIST *PGIMHVAPICASSIST;
529/** Pointer to a const Hyper-V reference TSC. */
530typedef GIMHVAPICASSIST const *PCGIMHVAPICASSIST;
531AssertCompileSize(GIMHVAPICASSIST, 4);
532
533/**
534 * Hypercall parameter type.
535 */
536typedef enum GIMHVHYPERCALLPARAM
537{
538 GIMHVHYPERCALLPARAM_IN = 0,
539 GIMHVHYPERCALLPARAM_OUT
540} GIMHVHYPERCALLPARAM;
541
542
543/** @name Hyper-V hypercall op codes.
544 * @{
545 */
546/** Post message to hypervisor or VMs. */
547#define GIM_HV_HYPERCALL_OP_POST_MESSAGE 0x5C
548/** Post debug data to hypervisor. */
549#define GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA 0x69
550/** Retreive debug data from hypervisor. */
551#define GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA 0x6A
552/** Reset debug session. */
553#define GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION 0x6B
554/** @} */
555
556
557/** @name Hyper-V hypercall inputs.
558 * @{
559 */
560/** The hypercall call operation code. */
561#define GIM_HV_HYPERCALL_IN_CALL_CODE(a) ((a) & UINT64_C(0xffff))
562/** Whether it's a fast (register based) hypercall or not (memory-based). */
563#define GIM_HV_HYPERCALL_IN_IS_FAST(a) RT_BOOL((a) & RT_BIT_64(16))
564/** Total number of reps for a rep hypercall. */
565#define GIM_HV_HYPERCALL_IN_REP_COUNT(a) (((a) << 32) & UINT64_C(0xfff))
566/** Rep start index for a rep hypercall. */
567#define GIM_HV_HYPERCALL_IN_REP_START_IDX(a) (((a) << 48) & UINT64_C(0xfff))
568/** Reserved bits range 1. */
569#define GIM_HV_HYPERCALL_IN_RSVD_1(a) (((a) << 17) & UINT64_C(0x7fff))
570/** Reserved bits range 2. */
571#define GIM_HV_HYPERCALL_IN_RSVD_2(a) (((a) << 44) & UINT64_C(0xf))
572/** Reserved bits range 3. */
573#define GIM_HV_HYPERCALL_IN_RSVD_3(a) (((a) << 60) & UINT64_C(0x7))
574/** @} */
575
576
577/** @name Hyper-V hypercall status codes.
578 * @{
579 */
580/** Success. */
581#define GIM_HV_STATUS_SUCCESS 0x00
582/** Unrecognized hypercall. */
583#define GIM_HV_STATUS_INVALID_HYPERCALL_CODE 0x02
584/** Invalid hypercall input (rep count, rsvd bits). */
585#define GIM_HV_STATUS_INVALID_HYPERCALL_INPUT 0x03
586/** Hypercall guest-physical address not 8-byte aligned or crosses page boundary. */
587#define GIM_HV_STATUS_INVALID_ALIGNMENT 0x04
588/** Invalid hypercall parameters. */
589#define GIM_HV_STATUS_INVALID_PARAMETER 0x05
590/** Access denied. */
591#define GIM_HV_STATUS_ACCESS_DENIED 0x06
592/** The partition state not valid for specified op. */
593#define GIM_HV_STATUS_INVALID_PARTITION_STATE 0x07
594/** The hypercall operation could not be performed. */
595#define GIM_HV_STATUS_OPERATION_DENIED 0x08
596/** Specified partition property ID not recognized. */
597#define GIM_HV_STATUS_UNKNOWN_PROPERTY 0x09
598/** Specified partition property value not within range. */
599#define GIM_HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0x0a
600/** Insufficient memory for performing the hypercall. */
601#define GIM_HV_STATUS_INSUFFICIENT_MEMORY 0x0b
602/** Maximum partition depth has been exceeded for the partition hierarchy. */
603#define GIM_HV_STATUS_PARTITION_TOO_DEEP 0x0c
604/** The specified partition ID is not valid. */
605#define GIM_HV_STATUS_INVALID_PARTITION_ID 0x0d
606/** The specified virtual processor index in invalid. */
607#define GIM_HV_STATUS_INVALID_VP_INDEX 0x0e
608/** The specified port ID is not unique or doesn't exist. */
609#define GIM_HV_STATUS_INVALID_PORT_ID 0x11
610/** The specified connection ID is not unique or doesn't exist. */
611#define GIM_HV_STATUS_INVALID_CONNECTION_ID 0x12
612/** The target port doesn't have sufficient buffers for the caller to post a message. */
613#define GIM_HV_STATUS_INSUFFICIENT_BUFFERS 0x13
614/** External interrupt not acknowledged.*/
615#define GIM_HV_STATUS_NOT_ACKNOWLEDGED 0x14
616/** External interrupt acknowledged. */
617#define GIM_HV_STATUS_ACKNOWLEDGED 0x16
618/** Invalid state due to misordering Hv[Save|Restore]PartitionState. */
619#define GIM_HV_STATUS_INVALID_SAVE_RESTORE_STATE 0x17
620/** Operation not perform due to a required feature of SynIc was disabled. */
621#define GIM_HV_STATUS_INVALID_SYNIC_STATE 0x18
622/** Object or value already in use. */
623#define GIM_HV_STATUS_OBJECT_IN_USE 0x19
624/** Invalid proximity domain information. */
625#define GIM_HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO 0x1A
626/** Attempt to retrieve data failed. */
627#define GIM_HV_STATUS_NO_DATA 0x1B
628/** Debug connection has not recieved any new data since the last time. */
629#define GIM_HV_STATUS_INACTIVE 0x1C
630/** A resource is unavailable for allocation. */
631#define GIM_HV_STATUS_NO_RESOURCES 0x1D
632/** A hypervisor feature is not available to the caller. */
633#define GIM_HV_STATUS_FEATURE_UNAVAILABLE 0x1E
634/** The debug packet returned is partial due to an I/O error. */
635#define GIM_HV_STATUS_PARTIAL_PACKET 0x1F
636/** Processor feature SSE3 unsupported. */
637#define GIM_HV_STATUS_PROC_FEAT_SSE3_NOT_SUPPORTED 0x20
638/** Processor feature LAHSAHF unsupported. */
639#define GIM_HV_STATUS_PROC_FEAT_LAHSAHF_NOT_SUPPORTED 0x21
640/** Processor feature SSSE3 unsupported. */
641#define GIM_HV_STATUS_PROC_FEAT_SSSE3_NOT_SUPPORTED 0x22
642/** Processor feature SSE4.1 unsupported. */
643#define GIM_HV_STATUS_PROC_FEAT_SSE4_1_NOT_SUPPORTED 0x23
644/** Processor feature SSE4.2 unsupported. */
645#define GIM_HV_STATUS_PROC_FEAT_SSE4_2_NOT_SUPPORTED 0x24
646/** Processor feature SSE4A unsupported. */
647#define GIM_HV_STATUS_PROC_FEAT_SSE4A_NOT_SUPPORTED 0x25
648/** Processor feature XOP unsupported. */
649#define GIM_HV_STATUS_PROC_FEAT_XOP_NOT_SUPPORTED 0x26
650/** Processor feature POPCNT unsupported. */
651#define GIM_HV_STATUS_PROC_FEAT_POPCNT_NOT_SUPPORTED 0x27
652/** Processor feature CMPXCHG16B unsupported. */
653#define GIM_HV_STATUS_PROC_FEAT_CMPXCHG16B_NOT_SUPPORTED 0x28
654/** Processor feature ALTMOVCR8 unsupported. */
655#define GIM_HV_STATUS_PROC_FEAT_ALTMOVCR8_NOT_SUPPORTED 0x29
656/** Processor feature LZCNT unsupported. */
657#define GIM_HV_STATUS_PROC_FEAT_LZCNT_NOT_SUPPORTED 0x2A
658/** Processor feature misaligned SSE unsupported. */
659#define GIM_HV_STATUS_PROC_FEAT_MISALIGNED_SSE_NOT_SUPPORTED 0x2B
660/** Processor feature MMX extensions unsupported. */
661#define GIM_HV_STATUS_PROC_FEAT_MMX_EXT_NOT_SUPPORTED 0x2C
662/** Processor feature 3DNow! unsupported. */
663#define GIM_HV_STATUS_PROC_FEAT_3DNOW_NOT_SUPPORTED 0x2D
664/** Processor feature Extended 3DNow! unsupported. */
665#define GIM_HV_STATUS_PROC_FEAT_EXTENDED_3DNOW_NOT_SUPPORTED 0x2E
666/** Processor feature 1GB large page unsupported. */
667#define GIM_HV_STATUS_PROC_FEAT_PAGE_1GB_NOT_SUPPORTED 0x2F
668/** Processor cache line flush size incompatible. */
669#define GIM_HV_STATUS_PROC_CACHE_LINE_FLUSH_SIZE_INCOMPATIBLE 0x30
670/** Processor feature XSAVE unsupported. */
671#define GIM_HV_STATUS_PROC_FEAT_XSAVE_NOT_SUPPORTED 0x31
672/** Processor feature XSAVEOPT unsupported. */
673#define GIM_HV_STATUS_PROC_FEAT_XSAVEOPT_NOT_SUPPORTED 0x32
674/** The specified buffer was too small for all requested data. */
675#define GIM_HV_STATUS_INSUFFICIENT_BUFFER 0x33
676/** Processor feature XSAVEOPT unsupported. */
677#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX_NOT_SUPPORTED 0x34
678/** Processor feature XSAVEOPT unsupported. */
679#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEAT_NOT_SUPPORTED 0x35 /** Huh, isn't this same as 0x31? */
680/** Processor feature XSAVEOPT unsupported. */
681#define GIM_HV_STATUS_PROC_FEAT_PAGE_XSAVE_SAVE_AREA_INCOMPATIBLE 0x36
682/** Processor architecture unsupoorted. */
683#define GIM_HV_STATUS_INCOMPATIBLE_PROCESSOR 0x37
684/** Max. domains for platform I/O remapping reached. */
685#define GIM_HV_STATUS_INSUFFICIENT_DEVICE_DOMAINS 0x38
686/** Processor feature AES unsupported. */
687#define GIM_HV_STATUS_PROC_FEAT_AES_NOT_SUPPORTED 0x39
688/** Processor feature PCMULQDQ unsupported. */
689#define GIM_HV_STATUS_PROC_FEAT_PCMULQDQ_NOT_SUPPORTED 0x3A
690/** Processor feature XSAVE features unsupported. */
691#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEATURES_INCOMPATIBLE 0x3B
692/** Generic CPUID validation error. */
693#define GIM_HV_STATUS_CPUID_FEAT_VALIDATION_ERROR 0x3C
694/** XSAVE CPUID validation error. */
695#define GIM_HV_STATUS_CPUID_XSAVE_FEAT_VALIDATION_ERROR 0x3D
696/** Processor startup timed out. */
697#define GIM_HV_STATUS_PROCESSOR_STARTUP_TIMEOUT 0x3E
698/** SMX enabled by the BIOS. */
699#define GIM_HV_STATUS_SMX_ENABLED 0x3F
700/** Processor feature PCID unsupported. */
701#define GIM_HV_STATUS_PROC_FEAT_PCID_NOT_SUPPORTED 0x40
702/** Invalid LP index. */
703#define GIM_HV_STATUS_INVALID_LP_INDEX 0x41
704/** Processor feature PCID unsupported. */
705#define GIM_HV_STATUS_FEAT_FMA4_NOT_SUPPORTED 0x42
706/** Processor feature PCID unsupported. */
707#define GIM_HV_STATUS_FEAT_F16C_NOT_SUPPORTED 0x43
708/** Processor feature PCID unsupported. */
709#define GIM_HV_STATUS_PROC_FEAT_RDRAND_NOT_SUPPORTED 0x44
710/** Processor feature RDWRFSGS unsupported. */
711#define GIM_HV_STATUS_PROC_FEAT_RDWRFSGS_NOT_SUPPORTED 0x45
712/** Processor feature SMEP unsupported. */
713#define GIM_HV_STATUS_PROC_FEAT_SMEP_NOT_SUPPORTED 0x46
714/** Processor feature enhanced fast string unsupported. */
715#define GIM_HV_STATUS_PROC_FEAT_ENHANCED_FAST_STRING_NOT_SUPPORTED 0x47
716/** Processor feature MOVBE unsupported. */
717#define GIM_HV_STATUS_PROC_FEAT_MOVBE_NOT_SUPPORTED 0x48
718/** Processor feature BMI1 unsupported. */
719#define GIM_HV_STATUS_PROC_FEAT_BMI1_NOT_SUPPORTED 0x49
720/** Processor feature BMI2 unsupported. */
721#define GIM_HV_STATUS_PROC_FEAT_BMI2_NOT_SUPPORTED 0x4A
722/** Processor feature HLE unsupported. */
723#define GIM_HV_STATUS_PROC_FEAT_HLE_NOT_SUPPORTED 0x4B
724/** Processor feature RTM unsupported. */
725#define GIM_HV_STATUS_PROC_FEAT_RTM_NOT_SUPPORTED 0x4C
726/** Processor feature XSAVE FMA unsupported. */
727#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FMA_NOT_SUPPORTED 0x4D
728/** Processor feature XSAVE AVX2 unsupported. */
729#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX2_NOT_SUPPORTED 0x4E
730/** Processor feature NPIEP1 unsupported. */
731#define GIM_HV_STATUS_PROC_FEAT_NPIEP1_NOT_SUPPORTED 0x4F
732/** @} */
733
734
735/** @name Hyper-V MSR - Debug control (MSR_GIM_HV_SYNTH_DEBUG_CONTROL).
736 * @{
737 */
738/** Perform debug write. */
739#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(a) RT_BOOL((a) & RT_BIT_64(0))
740/** Perform debug read. */
741#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(a) RT_BOOL((a) & RT_BIT_64(1))
742/** Returns length of the debug write buffer. */
743#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(a) (((a) & UINT64_C(0xffff0000)) >> 16)
744/** @} */
745
746
747/** @name Hyper-V MSR - Debug status (MSR_GIM_HV_SYNTH_DEBUG_STATUS).
748 * @{
749 */
750/** Debug send buffer operation success. */
751#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS RT_BIT_64(0)
752/** Debug receive buffer operation success. */
753#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS RT_BIT_64(2)
754/** Debug connection was reset. */
755#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_CONN_RESET RT_BIT_64(3)
756/** @} */
757
758
759/** @name Hyper-V MSR - synthetic interrupt (MSR_GIM_HV_SINTx).
760 * @{
761 */
762/** The interrupt masked mask. */
763#define MSR_GIM_HV_SINT_MASKED RT_BIT_64(16)
764/** Whether the interrupt source is masked. */
765#define MSR_GIM_HV_SINT_IS_MASKED(a) RT_BOOL((a) & MSR_GIM_HV_SINT_MASKED)
766/** Gets the interrupt vector. */
767#define MSR_GIM_HV_SINT_GET_VECTOR(a) ((a) & UINT64_C(0xff))
768/** The AutoEoi mask. */
769#define MSR_GIM_HV_SINT_AUTOEOI RT_BIT_64(17)
770/** Gets whether AutoEoi is enabled for the synthetic interrupt. */
771#define MSR_GIM_HV_SINT_IS_AUTOEOI(a) RT_BOOL((a) & MSR_GIM_HV_SINT_AUTOEOI)
772/** @} */
773
774
775/** @name Hyper-V MSR - synthetic interrupt message page (MSR_GIM_HV_SIMP).
776 * @{
777 */
778/** The SIMP enable mask. */
779#define MSR_GIM_HV_SIMP_ENABLE RT_BIT_64(0)
780/** Whether the SIMP is enabled. */
781#define MSR_GIM_HV_SIMP_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIMP_ENABLE)
782/** The SIMP guest-physical address. */
783#define MSR_GIM_HV_SIMP_GPA(a) ((a) & UINT64_C(0xfffffffffffff000))
784/** @} */
785
786
787/** @name Hyper-V hypercall debug options.
788 * @{ */
789/** Maximum debug data payload size in bytes. */
790#define GIM_HV_DEBUG_MAX_DATA_SIZE 4088
791
792/** The undocumented bit for MSR_GIM_HV_DEBUG_OPTIONS_MSR that makes it all
793 * work. */
794#define GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS RT_BIT(2)
795
796/** Guest will perform the HvPostDebugData hypercall until completion. */
797#define GIM_HV_DEBUG_POST_LOOP RT_BIT_32(0)
798/** Mask of valid HvPostDebugData options. */
799#define GIM_HV_DEBUG_POST_OPTIONS_MASK RT_BIT_32(0)
800
801/** Guest will perform the HvRetrieveDebugData hypercall until completion. */
802#define GIM_HV_DEBUG_RETREIVE_LOOP RT_BIT_32(0)
803/** Guest checks if any global debug session is active. */
804#define GIM_HV_DEBUG_RETREIVE_TEST_ACTIVITY RT_BIT_32(1)
805/** Mask of valid HvRetrieveDebugData options. */
806#define GIM_HV_DEBUG_RETREIVE_OPTIONS_MASK RT_BIT_32(0) | RT_BIT_32(1)
807
808/** Guest requests purging of incoming debug data. */
809#define GIM_HV_DEBUG_PURGE_INCOMING_DATA RT_BIT_32(0)
810/** Guest requests purging of outgoing debug data. */
811#define GIM_HV_DEBUG_PURGE_OUTGOING_DATA RT_BIT_32(1)
812/** @}*/
813
814
815/** @name VMBus.
816 * These are just arbitrary definitions made up by Microsoft without
817 * any publicly available specification behind it.
818 * @{ */
819/** VMBus connection ID. */
820#define GIM_HV_VMBUS_MSG_CONNECTION_ID 1
821/** VMBus synthetic interrupt source (see VMBUS_MESSAGE_SINT in linux
822 * sources). */
823#define GIM_HV_VMBUS_MSG_SINT 2
824/** @} */
825
826/** @name SynIC.
827 * Synthetic Interrupt Controller definitions.
828 */
829/** SynIC version register. */
830#define GIM_HV_SVERSION 1
831/** Number of synthetic interrupt sources (warning, fixed in saved-states!). */
832#define GIM_HV_SINT_COUNT 16
833/** Lowest valid vector for synthetic interrupt. */
834#define GIM_HV_SINT_VECTOR_VALID_MIN 16
835/** Highest valid vector for synthetic interrupt. */
836#define GIM_HV_SINT_VECTOR_VALID_MAX 255
837/** Number of synthetic timers. */
838#define GIM_HV_STIMER_COUNT 4
839/** @} */
840
841/** @name Hyper-V synthetic interrupt message type.
842 * See 14.8.2 "SynIC Message Types"
843 * @{
844 */
845typedef enum GIMHVMSGTYPE
846{
847 GIMHVMSGTYPE_NONE = 0, /* Common messages */
848 GIMHVMSGTYPE_VMBUS = 1, /* Guest messages */
849 GIMHVMSGTYPE_UNMAPPEDGPA = 0x80000000, /* Hypervisor messages */
850 GIMHVMSGTYPE_GPAINTERCEPT = 0x80000001,
851 GIMHVMSGTYPE_TIMEREXPIRED = 0x80000010,
852 GIMHVMSGTYPE_INVALIDVPREGVAL = 0x80000020,
853 GIMHVMSGTYPE_UNRECOVERABLEXCPT = 0x80000021,
854 GIMHVMSGTYPE_UNSUPPORTEDFEAT = 0x80000022,
855 GIMHVMSGTYPE_APICEOI = 0x80000030,
856 GIMHVMSGTYPE_X64LEGACYFPERROR = 0x80000031,
857 GIMHVMSGTYPE_EVENTLOGBUFSCOMPLETE = 0x80000040,
858 GIMHVMSGTYPE_X64IOPORTINTERCEPT = 0x80010000,
859 GIMHVMSGTYPE_X64MSRINTERCEPT = 0x80010001,
860 GIMHVMSGTYPE_X64CPUIDINTERCEPT = 0x80010002,
861 GIMHVMSGTYPE_X64XCPTINTERCEPT = 0x80010003
862} GIMHVMSGTYPE;
863AssertCompileSize(GIMHVMSGTYPE, 4);
864/** @} */
865
866
867/** @name Hyper-V synthetic interrupt message format.
868 * @{ */
869#define GIM_HV_MSG_SIZE 256
870#define GIM_HV_MSG_MAX_PAYLOAD_SIZE 240
871#define GIM_HV_MSG_MAX_PAYLOAD_UNITS 30
872
873/**
874 * Synthetic interrupt message flags.
875 */
876typedef union GIMHVMSGFLAGS
877{
878 struct
879 {
880 uint8_t u1Pending : 1;
881 uint8_t u7Reserved : 7;
882 } n;
883 uint8_t u;
884} GIMHVMSGFLAGS;
885AssertCompileSize(GIMHVMSGFLAGS, sizeof(uint8_t));
886
887/**
888 * Synthetic interrupt message header.
889 *
890 * @remarks The layout of this structure differs from
891 * the Hyper-V spec. Aug 8, 2013 v4.0a. Layout
892 * in accordance w/ VMBus client expectations.
893 */
894typedef struct GIMHVMSGHDR
895{
896 GIMHVMSGTYPE enmMessageType;
897 uint8_t cbPayload;
898 GIMHVMSGFLAGS MessageFlags;
899 uint16_t uRsvd;
900 union
901 {
902 uint64_t uOriginatorId;
903 uint64_t uPartitionId;
904 uint64_t uPortId;
905 } msgid;
906} GIMHVMSGHDR;
907/** Pointer to a synthetic interrupt message header. */
908typedef GIMHVMSGHDR *PGIMHVMSGHDR;
909AssertCompileMemberOffset(GIMHVMSGHDR, cbPayload, 4);
910AssertCompileMemberOffset(GIMHVMSGHDR, MessageFlags, 5);
911AssertCompileMemberOffset(GIMHVMSGHDR, msgid, 8);
912AssertCompileSize(GIMHVMSGHDR, GIM_HV_MSG_SIZE - GIM_HV_MSG_MAX_PAYLOAD_SIZE);
913
914/**
915 * Synthetic interrupt message.
916 */
917typedef struct GIMHVMSG
918{
919 GIMHVMSGHDR MsgHdr;
920 uint64_t aPayload[GIM_HV_MSG_MAX_PAYLOAD_UNITS];
921} GIMHVMSG;
922/** Pointer to a synthetic interrupt message. */
923typedef GIMHVMSG *PGIMHVMSG;
924AssertCompileSize(GIMHVMSG, GIM_HV_MSG_SIZE);
925/** @} */
926
927
928/** @name Hyper-V hypercall parameters.
929 * @{ */
930/**
931 * HvPostMessage hypercall input.
932 */
933typedef struct GIMHVPOSTMESSAGEIN
934{
935 uint32_t uConnectionId;
936 uint32_t uPadding;
937 GIMHVMSGTYPE enmMessageType;
938 uint32_t cbPayload;
939} GIMHVPOSTMESSAGEIN;
940/** Pointer to a HvPostMessage input struct. */
941typedef GIMHVPOSTMESSAGEIN *PGIMHVPOSTMESSAGEIN;
942AssertCompileSize(GIMHVPOSTMESSAGEIN, 16);
943
944/**
945 * HvResetDebugData hypercall input.
946 */
947typedef struct GIMHVDEBUGRESETIN
948{
949 uint32_t fFlags;
950 uint32_t uPadding;
951} GIMHVDEBUGRESETIN;
952/** Pointer to a HvResetDebugData input struct. */
953typedef GIMHVDEBUGRESETIN *PGIMHVDEBUGRESETIN;
954AssertCompileSize(GIMHVDEBUGRESETIN, 8);
955
956/**
957 * HvPostDebugData hypercall input.
958 */
959typedef struct GIMHVDEBUGPOSTIN
960{
961 uint32_t cbWrite;
962 uint32_t fFlags;
963} GIMHVDEBUGPOSTIN;
964/** Pointer to a HvPostDebugData input struct. */
965typedef GIMHVDEBUGPOSTIN *PGIMHVDEBUGPOSTIN;
966AssertCompileSize(GIMHVDEBUGPOSTIN, 8);
967
968/**
969 * HvPostDebugData hypercall output.
970 */
971typedef struct GIMHVDEBUGPOSTOUT
972{
973 uint32_t cbPending;
974 uint32_t uPadding;
975} GIMHVDEBUGPOSTOUT;
976/** Pointer to a HvPostDebugData output struct. */
977typedef GIMHVDEBUGPOSTOUT *PGIMHVDEBUGPOSTOUT;
978AssertCompileSize(GIMHVDEBUGPOSTOUT, 8);
979
980/**
981 * HvRetrieveDebugData hypercall input.
982 */
983typedef struct GIMHVDEBUGRETRIEVEIN
984{
985 uint32_t cbRead;
986 uint32_t fFlags;
987 uint64_t u64Timeout;
988} GIMHVDEBUGRETRIEVEIN;
989/** Pointer to a HvRetrieveDebugData input struct. */
990typedef GIMHVDEBUGRETRIEVEIN *PGIMHVDEBUGRETRIEVEIN;
991AssertCompileSize(GIMHVDEBUGRETRIEVEIN, 16);
992
993/**
994 * HvRetriveDebugData hypercall output.
995 */
996typedef struct GIMHVDEBUGRETRIEVEOUT
997{
998 uint32_t cbRead;
999 uint32_t cbRemaining;
1000} GIMHVDEBUGRETRIEVEOUT;
1001/** Pointer to a HvRetrieveDebugData output struct. */
1002typedef GIMHVDEBUGRETRIEVEOUT *PGIMHVDEBUGRETRIEVEOUT;
1003AssertCompileSize(GIMHVDEBUGRETRIEVEOUT, 8);
1004/** @} */
1005
1006
1007/** Hyper-V page size. */
1008#define GIM_HV_PAGE_SIZE 4096
1009
1010/** Microsoft Hyper-V vendor signature. */
1011#define GIM_HV_VENDOR_MICROSOFT "Microsoft Hv"
1012
1013/**
1014 * MMIO2 region indices.
1015 */
1016/** The hypercall page region. */
1017#define GIM_HV_HYPERCALL_PAGE_REGION_IDX UINT8_C(0)
1018/** The TSC page region. */
1019#define GIM_HV_REF_TSC_PAGE_REGION_IDX UINT8_C(1)
1020/** The maximum region index (must be <= UINT8_MAX). */
1021#define GIM_HV_REGION_IDX_MAX GIM_HV_REF_TSC_PAGE_REGION_IDX
1022
1023/**
1024 * Hyper-V TSC (HV_REFERENCE_TSC_PAGE) structure placed in the TSC reference
1025 * page.
1026 */
1027typedef struct GIMHVREFTSC
1028{
1029 uint32_t u32TscSequence;
1030 uint32_t uReserved0;
1031 uint64_t u64TscScale;
1032 int64_t i64TscOffset;
1033} GIMHVTSCPAGE;
1034/** Pointer to Hyper-V reference TSC. */
1035typedef GIMHVREFTSC *PGIMHVREFTSC;
1036/** Pointer to a const Hyper-V reference TSC. */
1037typedef GIMHVREFTSC const *PCGIMHVREFTSC;
1038
1039/**
1040 * Type of the next reply to be sent to the debug connection of the guest.
1041 *
1042 * @remarks This is saved as part of saved-state, so don't re-order or
1043 * alter the size!
1044 */
1045typedef enum GIMHVDEBUGREPLY
1046{
1047 /** Send UDP packet. */
1048 GIMHVDEBUGREPLY_UDP = 0,
1049 /** Send DHCP offer for DHCP discover. */
1050 GIMHVDEBUGREPLY_DHCP_OFFER,
1051 /** DHCP offer sent. */
1052 GIMHVDEBUGREPLY_DHCP_OFFER_SENT,
1053 /** Send DHCP acknowledgement for DHCP request. */
1054 GIMHVDEBUGREPLY_DHCP_ACK,
1055 /** DHCP acknowledgement sent. */
1056 GIMHVDEBUGREPLY_DHCP_ACK_SENT,
1057 /** Sent ARP reply. */
1058 GIMHVDEBUGREPLY_ARP_REPLY,
1059 /** ARP reply sent. */
1060 GIMHVDEBUGREPLY_ARP_REPLY_SENT,
1061 /** Customary 32-bit type hack. */
1062 GIMHVDEBUGREPLY_32BIT_HACK = 0x7fffffff
1063} GIMHVDEBUGREPLY;
1064AssertCompileSize(GIMHVDEBUGREPLY, sizeof(uint32_t));
1065
1066/**
1067 * GIM Hyper-V VM instance data.
1068 * Changes to this must checked against the padding of the gim union in VM!
1069 */
1070typedef struct GIMHV
1071{
1072 /** @name Primary MSRs.
1073 * @{ */
1074 /** Guest OS identity MSR. */
1075 uint64_t u64GuestOsIdMsr;
1076 /** Hypercall MSR. */
1077 uint64_t u64HypercallMsr;
1078 /** Reference TSC page MSR. */
1079 uint64_t u64TscPageMsr;
1080 /** @} */
1081
1082 /** @name CPUID features.
1083 * @{ */
1084 /** Basic features. */
1085 uint32_t uBaseFeat;
1086 /** Partition flags. */
1087 uint32_t uPartFlags;
1088 /** Power management. */
1089 uint32_t uPowMgmtFeat;
1090 /** Miscellaneous. */
1091 uint32_t uMiscFeat;
1092 /** Hypervisor hints to the guest. */
1093 uint32_t uHyperHints;
1094 /** Hypervisor capabilities. */
1095 uint32_t uHyperCaps;
1096 /** @} */
1097
1098 /** @name Guest Crash MSRs.
1099 * @{
1100 */
1101 /** Guest crash control MSR. */
1102 uint64_t uCrashCtlMsr;
1103 /** Guest crash parameter 0 MSR. */
1104 uint64_t uCrashP0Msr;
1105 /** Guest crash parameter 1 MSR. */
1106 uint64_t uCrashP1Msr;
1107 /** Guest crash parameter 2 MSR. */
1108 uint64_t uCrashP2Msr;
1109 /** Guest crash parameter 3 MSR. */
1110 uint64_t uCrashP3Msr;
1111 /** Guest crash parameter 4 MSR. */
1112 uint64_t uCrashP4Msr;
1113 /** @} */
1114
1115 /** @name Time management.
1116 * @{ */
1117 /** Per-VM R0 Spinlock for protecting EMT writes to the TSC page. */
1118 RTSPINLOCK hSpinlockR0;
1119#if HC_ARCH_BITS == 32
1120 uint32_t u32Alignment1;
1121#endif
1122 /** The TSC frequency (in HZ) reported to the guest. */
1123 uint64_t cTscTicksPerSecond;
1124 /** @} */
1125
1126 /** @name Hypercalls. */
1127 /* @{ */
1128 /** Guest address of the hypercall input parameter page. */
1129 RTGCPHYS GCPhysHypercallIn;
1130 /** Guest address of the hypercall output parameter page. */
1131 RTGCPHYS GCPhysHypercallOut;
1132 /** Pointer to the hypercall input parameter page - R3. */
1133 R3PTRTYPE(uint8_t *) pbHypercallIn;
1134 /** Pointer to the hypercall output parameter page - R3. */
1135 R3PTRTYPE(uint8_t *) pbHypercallOut;
1136 /** @} */
1137
1138 /** @name Guest debugging.
1139 * @{ */
1140 /** Whether we're posing as the Microsoft vendor. */
1141 bool fIsVendorMsHv;
1142 /** Whether we're posing as the Microsoft virtualization service. */
1143 bool fIsInterfaceVs;
1144 /** Whether debugging support is enabled. */
1145 bool fDbgEnabled;
1146 /** Whether we should suggest a hypercall-based debug interface to the guest. */
1147 bool fDbgHypercallInterface;
1148 bool afAlignment0[4];
1149 /** The action to take while sending replies. */
1150 GIMHVDEBUGREPLY enmDbgReply;
1151 /** The IP address chosen by/assigned to the guest. */
1152 RTNETADDRIPV4 DbgGuestIp4Addr;
1153 /** Transaction ID for the BOOTP+DHCP sequence. */
1154 uint32_t uDbgBootpXId;
1155 /** The source UDP port used by the guest while sending debug packets. */
1156 uint16_t uUdpGuestSrcPort;
1157 /** The destination UDP port used by the guest while sending debug packets. */
1158 uint16_t uUdpGuestDstPort;
1159 /** Debug send buffer MSR. */
1160 uint64_t uDbgSendBufferMsr;
1161 /** Debug receive buffer MSR. */
1162 uint64_t uDbgRecvBufferMsr;
1163 /** Debug pending buffer MSR. */
1164 uint64_t uDbgPendingBufferMsr;
1165 /** Debug status MSR. */
1166 uint64_t uDbgStatusMsr;
1167 /** Intermediate debug I/O buffer. */
1168 R3PTRTYPE(void *) pvDbgBuffer;
1169 R3PTRTYPE(void *) pvAlignment0;
1170 /** @} */
1171
1172 /** Array of MMIO2 regions. */
1173 GIMMMIO2REGION aMmio2Regions[GIM_HV_REGION_IDX_MAX + 1];
1174} GIMHV;
1175/** Pointer to per-VM GIM Hyper-V instance data. */
1176typedef GIMHV *PGIMHV;
1177/** Pointer to const per-VM GIM Hyper-V instance data. */
1178typedef GIMHV const *PCGIMHV;
1179AssertCompileMemberAlignment(GIMHV, aMmio2Regions, 8);
1180AssertCompileMemberAlignment(GIMHV, hSpinlockR0, sizeof(uintptr_t));
1181
1182/**
1183 * Hyper-V per-VCPU synthetic timer.
1184 */
1185typedef struct GIMHVSTIMER
1186{
1187 /** Synthetic timer object - R0 ptr. */
1188 PTMTIMERR0 pTimerR0;
1189 /** Synthetic timer object - R3 ptr. */
1190 PTMTIMERR3 pTimerR3;
1191 /** Synthetic timer object - RC ptr. */
1192 PTMTIMERRC pTimerRC;
1193 /** RC alignment padding. */
1194 RTRCPTR uAlignment0;
1195 /** Virtual CPU ID this timer belongs to (for reverse mapping). */
1196 VMCPUID idCpu;
1197 /** The index of this timer in the auStimers array (for reverse mapping). */
1198 uint32_t idxStimer;
1199 /** Synthetic timer config MSR. */
1200 uint64_t uStimerConfigMsr;
1201 /** Synthetic timer count MSR. */
1202 uint64_t uStimerCountMsr;
1203 /** Timer description. */
1204 char szTimerDesc[24];
1205
1206} GIMHVSTIMER;
1207/** Pointer to per-VCPU Hyper-V synthetic timer. */
1208typedef GIMHVSTIMER *PGIMHVSTIMER;
1209/** Pointer to a const per-VCPU Hyper-V synthetic timer. */
1210typedef GIMHVSTIMER const *PCGIMHVSTIMER;
1211AssertCompileSizeAlignment(GIMHVSTIMER, 8);
1212
1213/**
1214 * Hyper-V VCPU instance data.
1215 * Changes to this must checked against the padding of the gim union in VMCPU!
1216 */
1217typedef struct GIMHVCPU
1218{
1219 /** @name Synthetic interrupt MSRs.
1220 * @{ */
1221 /** Synthetic interrupt message page MSR. */
1222 uint64_t uSimpMsr;
1223 /** Interrupt source MSRs. */
1224 uint64_t auSintMsrs[GIM_HV_SINT_COUNT];
1225 /** Synethtic interrupt events flag page MSR. */
1226 uint64_t uSiefpMsr;
1227 /** APIC-assist page MSR. */
1228 uint64_t uApicAssistPageMsr;
1229 /** Synthetic interrupt control MSR. */
1230 uint64_t uSControlMsr;
1231 /** Synthetic timers. */
1232 GIMHVSTIMER aStimers[GIM_HV_STIMER_COUNT];
1233 /** @} */
1234
1235 /** @name Statistics.
1236 * @{ */
1237 STAMCOUNTER aStatStimerFired[GIM_HV_STIMER_COUNT];
1238 /** @} */
1239} GIMHVCPU;
1240/** Pointer to per-VCPU GIM Hyper-V instance data. */
1241typedef GIMHVCPU *PGIMHVCPU;
1242/** Pointer to const per-VCPU GIM Hyper-V instance data. */
1243typedef GIMHVCPU const *PCGIMHVCPU;
1244
1245
1246RT_C_DECLS_BEGIN
1247
1248#ifdef IN_RING0
1249VMMR0_INT_DECL(int) gimR0HvInitVM(PVM pVM);
1250VMMR0_INT_DECL(int) gimR0HvTermVM(PVM pVM);
1251VMMR0_INT_DECL(int) gimR0HvUpdateParavirtTsc(PVM pVM, uint64_t u64Offset);
1252#endif /* IN_RING0 */
1253
1254#ifdef IN_RING3
1255VMMR3_INT_DECL(int) gimR3HvInit(PVM pVM, PCFGMNODE pGimCfg);
1256VMMR3_INT_DECL(int) gimR3HvInitCompleted(PVM pVM);
1257VMMR3_INT_DECL(int) gimR3HvTerm(PVM pVM);
1258VMMR3_INT_DECL(void) gimR3HvRelocate(PVM pVM, RTGCINTPTR offDelta);
1259VMMR3_INT_DECL(void) gimR3HvReset(PVM pVM);
1260VMMR3_INT_DECL(PGIMMMIO2REGION) gimR3HvGetMmio2Regions(PVM pVM, uint32_t *pcRegions);
1261VMMR3_INT_DECL(int) gimR3HvSave(PVM pVM, PSSMHANDLE pSSM);
1262VMMR3_INT_DECL(int) gimR3HvLoad(PVM pVM, PSSMHANDLE pSSM);
1263VMMR3_INT_DECL(int) gimR3HvGetDebugSetup(PVM pVM, PGIMDEBUGSETUP pDbgSetup);
1264
1265VMMR3_INT_DECL(int) gimR3HvDisableSiefPage(PVMCPU pVCpu);
1266VMMR3_INT_DECL(int) gimR3HvEnableSiefPage(PVMCPU pVCpu, RTGCPHYS GCPhysSiefPage);
1267VMMR3_INT_DECL(int) gimR3HvEnableSimPage(PVMCPU pVCpu, RTGCPHYS GCPhysSimPage);
1268VMMR3_INT_DECL(int) gimR3HvDisableSimPage(PVMCPU pVCpu);
1269VMMR3_INT_DECL(int) gimR3HvDisableApicAssistPage(PVMCPU pVCpu);
1270VMMR3_INT_DECL(int) gimR3HvEnableApicAssistPage(PVMCPU pVCpu, RTGCPHYS GCPhysTscPage);
1271VMMR3_INT_DECL(int) gimR3HvDisableTscPage(PVM pVM);
1272VMMR3_INT_DECL(int) gimR3HvEnableTscPage(PVM pVM, RTGCPHYS GCPhysTscPage, bool fUseThisTscSeq, uint32_t uTscSeq);
1273VMMR3_INT_DECL(int) gimR3HvDisableHypercallPage(PVM pVM);
1274VMMR3_INT_DECL(int) gimR3HvEnableHypercallPage(PVM pVM, RTGCPHYS GCPhysHypercallPage);
1275
1276VMMR3_INT_DECL(int) gimR3HvHypercallPostDebugData(PVM pVM, int *prcHv);
1277VMMR3_INT_DECL(int) gimR3HvHypercallRetrieveDebugData(PVM pVM, int *prcHv);
1278VMMR3_INT_DECL(int) gimR3HvDebugWrite(PVM pVM, void *pvData, uint32_t cbWrite, uint32_t *pcbWritten, bool fUdpPkt);
1279VMMR3_INT_DECL(int) gimR3HvDebugRead(PVM pVM, void *pvBuf, uint32_t cbBuf, uint32_t cbRead, uint32_t *pcbRead,
1280 uint32_t cMsTimeout, bool fUdpPkt);
1281#endif /* IN_RING3 */
1282
1283VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM);
1284VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu);
1285VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu);
1286VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr);
1287VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
1288VMM_INT_DECL(VBOXSTRICTRC) gimHvExecHypercallInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis);
1289VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
1290VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
1291
1292VMM_INT_DECL(void) gimHvStartStimer(PVMCPU pVCpu, PCGIMHVSTIMER pHvStimer);
1293
1294RT_C_DECLS_END
1295
1296#endif
1297
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