| 1 | /* $Id: GIMHvInternal.h 51333 2014-05-22 04:42:22Z vboxsync $ */
|
|---|
| 2 | /** @file
|
|---|
| 3 | * GIM - Hyper-V, Internal header file.
|
|---|
| 4 | */
|
|---|
| 5 |
|
|---|
| 6 | /*
|
|---|
| 7 | * Copyright (C) 2014 Oracle Corporation
|
|---|
| 8 | *
|
|---|
| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
|
|---|
| 10 | * available from http://www.virtualbox.org. This file is free software;
|
|---|
| 11 | * you can redistribute it and/or modify it under the terms of the GNU
|
|---|
| 12 | * General Public License (GPL) as published by the Free Software
|
|---|
| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
|
|---|
| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
|
|---|
| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
|
|---|
| 16 | */
|
|---|
| 17 |
|
|---|
| 18 | #ifndef ___GIMHvInternal_h
|
|---|
| 19 | #define ___GIMHvInternal_h
|
|---|
| 20 |
|
|---|
| 21 | #include <iprt/cdefs.h>
|
|---|
| 22 | #include <VBox/types.h>
|
|---|
| 23 | #include <VBox/vmm/cpum.h>
|
|---|
| 24 |
|
|---|
| 25 | /** @name Hyper-V base feature identification.
|
|---|
| 26 | * Base features based on current partition privileges.
|
|---|
| 27 | * @{
|
|---|
| 28 | */
|
|---|
| 29 | /** Virtual processor runtime MSR available. */
|
|---|
| 30 | #define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
|
|---|
| 31 | /** Partition reference counter MSR available. */
|
|---|
| 32 | #define GIM_HV_BASE_FEAT_PART_REF_COUNT_MSR RT_BIT(1)
|
|---|
| 33 | /** Basic Synthetic Interrupt Controller MSRs available. */
|
|---|
| 34 | #define GIM_HV_BASE_FEAT_BASIC_SYNTH_IC RT_BIT(2)
|
|---|
| 35 | /** Synthetic Timer MSRs available. */
|
|---|
| 36 | #define GIM_HV_BASE_FEAT_SYNTH_TIMER_MSRS RT_BIT(3)
|
|---|
| 37 | /** APIC access MSRs (EOI, ICR, TPR) available. */
|
|---|
| 38 | #define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4)
|
|---|
| 39 | /** Hypercall MSRs available. */
|
|---|
| 40 | #define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5)
|
|---|
| 41 | /** Access to VCPU index MSR available. */
|
|---|
| 42 | #define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6)
|
|---|
| 43 | /** Virtual system reset MSR available. */
|
|---|
| 44 | #define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7)
|
|---|
| 45 | /** Statistic pages MSRs available. */
|
|---|
| 46 | #define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8)
|
|---|
| 47 | /** Paritition reference TSC MSR available. */
|
|---|
| 48 | #define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9)
|
|---|
| 49 | /** Virtual guest idle state MSR available. */
|
|---|
| 50 | #define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10)
|
|---|
| 51 | /** Timer frequency MSRs available. */
|
|---|
| 52 | #define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11)
|
|---|
| 53 | /** Debug MSRs available. */
|
|---|
| 54 | #define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12)
|
|---|
| 55 | /** @} */
|
|---|
| 56 |
|
|---|
| 57 | /** @name Hyper-V partition-creation feature identification.
|
|---|
| 58 | * Indicates flags specified during partition creation.
|
|---|
| 59 | * @{
|
|---|
| 60 | */
|
|---|
| 61 | /** Create partitions. */
|
|---|
| 62 | #define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
|
|---|
| 63 | /** Access partition Id. */
|
|---|
| 64 | #define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1)
|
|---|
| 65 | /** Access memory pool. */
|
|---|
| 66 | #define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2)
|
|---|
| 67 | /** Adjust message buffers. */
|
|---|
| 68 | #define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3)
|
|---|
| 69 | /** Post messages. */
|
|---|
| 70 | #define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4)
|
|---|
| 71 | /** Signal events. */
|
|---|
| 72 | #define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5)
|
|---|
| 73 | /** Create port. */
|
|---|
| 74 | #define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6)
|
|---|
| 75 | /** Connect port. */
|
|---|
| 76 | #define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7)
|
|---|
| 77 | /** Access statistics. */
|
|---|
| 78 | #define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8)
|
|---|
| 79 | /** Debugging.*/
|
|---|
| 80 | #define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11)
|
|---|
| 81 | /** CPU management. */
|
|---|
| 82 | #define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12)
|
|---|
| 83 | /** CPU profiler. */
|
|---|
| 84 | #define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13)
|
|---|
| 85 | /** Enable expanded stack walking. */
|
|---|
| 86 | #define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14)
|
|---|
| 87 | /** @} */
|
|---|
| 88 |
|
|---|
| 89 | /** @name Hyper-V power management feature identification.
|
|---|
| 90 | * @{
|
|---|
| 91 | */
|
|---|
| 92 | /** Maximum CPU power state C0. */
|
|---|
| 93 | #define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
|
|---|
| 94 | /** Maximum CPU power state C1. */
|
|---|
| 95 | #define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1)
|
|---|
| 96 | /** Maximum CPU power state C2. */
|
|---|
| 97 | #define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2)
|
|---|
| 98 | /** Maximum CPU power state C3. */
|
|---|
| 99 | #define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3)
|
|---|
| 100 | /** HPET is required to enter C3 power state. */
|
|---|
| 101 | #define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4)
|
|---|
| 102 | /** @} */
|
|---|
| 103 |
|
|---|
| 104 | /** @name Hyper-V miscellaneous feature identification.
|
|---|
| 105 | * Miscellaneous features available for the current partition.
|
|---|
| 106 | * @{
|
|---|
| 107 | */
|
|---|
| 108 | /** MWAIT instruction available. */
|
|---|
| 109 | #define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
|
|---|
| 110 | /** Guest debugging support available. */
|
|---|
| 111 | #define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1)
|
|---|
| 112 | /** Performance monitor support is available. */
|
|---|
| 113 | #define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2)
|
|---|
| 114 | /** Support for physical CPU dynamic partitioning events. */
|
|---|
| 115 | #define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3)
|
|---|
| 116 | /** Support for passing hypercall input parameter block via XMM registers. */
|
|---|
| 117 | #define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4)
|
|---|
| 118 | /** Support for virtual guest idle state. */
|
|---|
| 119 | #define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5)
|
|---|
| 120 | /** Support for hypervisor sleep state. */
|
|---|
| 121 | #define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6)
|
|---|
| 122 | /** Support for querying NUMA distances. */
|
|---|
| 123 | #define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7)
|
|---|
| 124 | /** Support for determining timer frequencies. */
|
|---|
| 125 | #define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8)
|
|---|
| 126 | /** Support for injecting synthetic machine checks. */
|
|---|
| 127 | #define GIM_HV_MISC_FEAT_INJECT_SYNTH_MC_XCPT RT_BIT(9)
|
|---|
| 128 | /** Support for guest crash MSRs. */
|
|---|
| 129 | #define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10)
|
|---|
| 130 | /** Support for debug MSRs. */
|
|---|
| 131 | #define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11)
|
|---|
| 132 | /** Npiep1 Available */ /** @todo What the heck is this? */
|
|---|
| 133 | #define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12)
|
|---|
| 134 | /** Disable hypervisor available. */
|
|---|
| 135 | #define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13)
|
|---|
| 136 | /** @} */
|
|---|
| 137 |
|
|---|
| 138 | /** @name Hyper-V implementation recommendations.
|
|---|
| 139 | * Recommendations from the hypervisor for the guest for optimal performance.
|
|---|
| 140 | * @{
|
|---|
| 141 | */
|
|---|
| 142 | /** Use hypercall for address space switches rather than MOV CR3. */
|
|---|
| 143 | #define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
|
|---|
| 144 | /** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */
|
|---|
| 145 | #define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1)
|
|---|
| 146 | /** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
|
|---|
| 147 | #define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2)
|
|---|
| 148 | /** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
|
|---|
| 149 | #define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3)
|
|---|
| 150 | /** Use hypervisor provided MSR for a system reset. */
|
|---|
| 151 | #define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4)
|
|---|
| 152 | /** Relax timer-related checks (watchdogs/deadman timeouts) that rely on
|
|---|
| 153 | * timely deliver of external interrupts. */
|
|---|
| 154 | #define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5)
|
|---|
| 155 | /** Use DMA remapping. */
|
|---|
| 156 | #define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6)
|
|---|
| 157 | /** Use interrupt remapping. */
|
|---|
| 158 | #define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7)
|
|---|
| 159 | /** Use X2APIC MSRs rather than MMIO. */
|
|---|
| 160 | #define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8)
|
|---|
| 161 | /** Deprecate Auto EOI (end of interrupt). */
|
|---|
| 162 | #define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9)
|
|---|
| 163 | /** @} */
|
|---|
| 164 |
|
|---|
| 165 |
|
|---|
| 166 | /** @name Hyper-V implementation hardware features.
|
|---|
| 167 | * Which hardware features are in use by the hypervisor.
|
|---|
| 168 | * @{
|
|---|
| 169 | */
|
|---|
| 170 | /** APIC overlay is used. */
|
|---|
| 171 | #define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
|
|---|
| 172 | /** MSR bitmaps is used. */
|
|---|
| 173 | #define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1)
|
|---|
| 174 | /** Architectural performance counter supported. */
|
|---|
| 175 | #define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2)
|
|---|
| 176 | /** Nested paging is used. */
|
|---|
| 177 | #define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3)
|
|---|
| 178 | /** DMA remapping is used. */
|
|---|
| 179 | #define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4)
|
|---|
| 180 | /** Interrupt remapping is used. */
|
|---|
| 181 | #define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5)
|
|---|
| 182 | /** Memory patrol scrubber is present. */
|
|---|
| 183 | #define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6)
|
|---|
| 184 | /** @} */
|
|---|
| 185 |
|
|---|
| 186 |
|
|---|
| 187 | /** @name Hyper-V MSRs.
|
|---|
| 188 | * @{
|
|---|
| 189 | */
|
|---|
| 190 | /** Guest OS identification (R/W) */
|
|---|
| 191 | #define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000)
|
|---|
| 192 | /** Enable hypercall interface (R/W) */
|
|---|
| 193 | #define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001)
|
|---|
| 194 | /** Virtual processor's (VCPU) index (R) */
|
|---|
| 195 | #define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002)
|
|---|
| 196 | /** Reset operation (R/W) */
|
|---|
| 197 | #define MSR_GIM_HV_RESET UINT32_C(0x40000003)
|
|---|
| 198 | /** Virtual processor's (VCPU) runtime (R) */
|
|---|
| 199 | #define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010)
|
|---|
| 200 | /** Per-VM reference counter (R) */
|
|---|
| 201 | #define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020)
|
|---|
| 202 | /** Per-VM TSC (R) */
|
|---|
| 203 | #define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021)
|
|---|
| 204 | /** Frequency of TSC in Hz as reported by the hypervisor (R) */
|
|---|
| 205 | #define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022)
|
|---|
| 206 | /** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
|
|---|
| 207 | #define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023)
|
|---|
| 208 | /** Access to APIC EOI (End-Of-Interrupt) register (W) */
|
|---|
| 209 | #define MSR_GIM_HV_EOI UINT32_C(0x40000070)
|
|---|
| 210 | /** Access to APIC ICR (Interrupt Command) register (R/W) */
|
|---|
| 211 | #define MSR_GIM_HV_ICR UINT32_C(0x40000071)
|
|---|
| 212 | /** Access to APIC TPR (Task Priority) register (R/W) */
|
|---|
| 213 | #define MSR_GIM_HV_TPR UINT32_C(0x40000072)
|
|---|
| 214 | /** Enables lazy EOI processing (R/W) */
|
|---|
| 215 | #define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073)
|
|---|
| 216 | /** Control behaviour of synthetic interrupt controller (R/W) */
|
|---|
| 217 | #define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080)
|
|---|
| 218 | /** Synthetic interrupt controller version (R) */
|
|---|
| 219 | #define MSR_GIM_HV_SVERSION UINT32_C(0x40000081)
|
|---|
| 220 | /** Base address of synthetic interrupt event flag (R/W) */
|
|---|
| 221 | #define MSR_GIM_HV_SIEFP UINT32_C(0x40000082)
|
|---|
| 222 | /** Base address of synthetic interrupt parameter page (R/W) */
|
|---|
| 223 | #define MSR_GIM_HV_SIMP UINT32_C(0x40000083)
|
|---|
| 224 | /** End-Of-Message in synthetic interrupt parameter page (W) */
|
|---|
| 225 | #define MSR_GIM_HV_EOM UINT32_C(0x40000084)
|
|---|
| 226 | /** Configures synthetic interrupt source 0 (R/W) */
|
|---|
| 227 | #define MSR_GIM_HV_SINT0 UINT32_C(0x40000090)
|
|---|
| 228 | /** Configures synthetic interrupt source 1 (R/W) */
|
|---|
| 229 | #define MSR_GIM_HV_SINT1 UINT32_C(0x40000091)
|
|---|
| 230 | /** Configures synthetic interrupt source 2 (R/W) */
|
|---|
| 231 | #define MSR_GIM_HV_SINT2 UINT32_C(0x40000092)
|
|---|
| 232 | /** Configures synthetic interrupt source 3 (R/W) */
|
|---|
| 233 | #define MSR_GIM_HV_SINT3 UINT32_C(0x40000093)
|
|---|
| 234 | /** Configures synthetic interrupt source 4 (R/W) */
|
|---|
| 235 | #define MSR_GIM_HV_SINT4 UINT32_C(0x40000094)
|
|---|
| 236 | /** Configures synthetic interrupt source 5 (R/W) */
|
|---|
| 237 | #define MSR_GIM_HV_SINT5 UINT32_C(0x40000095)
|
|---|
| 238 | /** Configures synthetic interrupt source 6 (R/W) */
|
|---|
| 239 | #define MSR_GIM_HV_SINT6 UINT32_C(0x40000096)
|
|---|
| 240 | /** Configures synthetic interrupt source 7 (R/W) */
|
|---|
| 241 | #define MSR_GIM_HV_SINT7 UINT32_C(0x40000097)
|
|---|
| 242 | /** Configures synthetic interrupt source 8 (R/W) */
|
|---|
| 243 | #define MSR_GIM_HV_SINT8 UINT32_C(0x40000098)
|
|---|
| 244 | /** Configures synthetic interrupt source 9 (R/W) */
|
|---|
| 245 | #define MSR_GIM_HV_SINT9 UINT32_C(0x40000099)
|
|---|
| 246 | /** Configures synthetic interrupt source 10 (R/W) */
|
|---|
| 247 | #define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A)
|
|---|
| 248 | /** Configures synthetic interrupt source 11 (R/W) */
|
|---|
| 249 | #define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B)
|
|---|
| 250 | /** Configures synthetic interrupt source 12 (R/W) */
|
|---|
| 251 | #define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C)
|
|---|
| 252 | /** Configures synthetic interrupt source 13 (R/W) */
|
|---|
| 253 | #define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D)
|
|---|
| 254 | /** Configures synthetic interrupt source 14 (R/W) */
|
|---|
| 255 | #define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E)
|
|---|
| 256 | /** Configures synthetic interrupt source 15 (R/W) */
|
|---|
| 257 | #define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F)
|
|---|
| 258 | /** Configures register for synthetic timer 0 (R/W) */
|
|---|
| 259 | #define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0)
|
|---|
| 260 | /** Expiration time or period for synthetic timer 0 (R/W) */
|
|---|
| 261 | #define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1)
|
|---|
| 262 | /** Configures register for synthetic timer 1 (R/W) */
|
|---|
| 263 | #define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2)
|
|---|
| 264 | /** Expiration time or period for synthetic timer 1 (R/W) */
|
|---|
| 265 | #define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3)
|
|---|
| 266 | /** Configures register for synthetic timer 2 (R/W) */
|
|---|
| 267 | #define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4)
|
|---|
| 268 | /** Expiration time or period for synthetic timer 2 (R/W) */
|
|---|
| 269 | #define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5)
|
|---|
| 270 | /** Configures register for synthetic timer 3 (R/W) */
|
|---|
| 271 | #define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6)
|
|---|
| 272 | /** Expiration time or period for synthetic timer 3 (R/W) */
|
|---|
| 273 | #define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7)
|
|---|
| 274 | /** Trigger to transition to power state C1 (R) */
|
|---|
| 275 | #define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1)
|
|---|
| 276 | /** Trigger to transition to power state C2 (R) */
|
|---|
| 277 | #define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2)
|
|---|
| 278 | /** Trigger to transition to power state C3 (R) */
|
|---|
| 279 | #define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3)
|
|---|
| 280 | /** Configure the recipe for power state transitions to C1 (R/W) */
|
|---|
| 281 | #define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1)
|
|---|
| 282 | /** Configure the recipe for power state transitions to C2 (R/W) */
|
|---|
| 283 | #define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2)
|
|---|
| 284 | /** Configure the recipe for power state transitions to C3 (R/W) */
|
|---|
| 285 | #define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3)
|
|---|
| 286 | /** Map the guest's retail partition stats page (R/W) */
|
|---|
| 287 | #define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0)
|
|---|
| 288 | /** Map the guest's internal partition stats page (R/W) */
|
|---|
| 289 | #define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1)
|
|---|
| 290 | /** Map the guest's retail VP stats page (R/W) */
|
|---|
| 291 | #define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2)
|
|---|
| 292 | /** Map the guest's internal VP stats page (R/W) */
|
|---|
| 293 | #define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3)
|
|---|
| 294 | /** Trigger the guest's transition to idle power state (R) */
|
|---|
| 295 | #define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0)
|
|---|
| 296 | /** Synthetic debug control. */
|
|---|
| 297 | #define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1)
|
|---|
| 298 | /** Synthetic debug status. */
|
|---|
| 299 | #define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2)
|
|---|
| 300 | /** Synthetic debug send buffer. */
|
|---|
| 301 | #define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3)
|
|---|
| 302 | /** Synthetic debug receive buffer. */
|
|---|
| 303 | #define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4)
|
|---|
| 304 | /** Synthetic debug pending buffer. */
|
|---|
| 305 | #define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5)
|
|---|
| 306 | /** Guest crash MSR 0. */
|
|---|
| 307 | #define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100)
|
|---|
| 308 | /** Guest crash MSR 1. */
|
|---|
| 309 | #define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101)
|
|---|
| 310 | /** Guest crash MSR 2. */
|
|---|
| 311 | #define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102)
|
|---|
| 312 | /** Guest crash MSR 3. */
|
|---|
| 313 | #define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103)
|
|---|
| 314 | /** Guest crash MSR 4. */
|
|---|
| 315 | #define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104)
|
|---|
| 316 | /** Guest crash control. */
|
|---|
| 317 | #define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105)
|
|---|
| 318 | /** @} */
|
|---|
| 319 |
|
|---|
| 320 |
|
|---|
| 321 | RT_C_DECLS_BEGIN
|
|---|
| 322 |
|
|---|
| 323 | #ifdef IN_RING3
|
|---|
| 324 | VMMR3_INT_DECL(int) GIMR3HvInit(PVM pVM);
|
|---|
| 325 | VMMR3_INT_DECL(void) GIMR3HvRelocate(PVM pVM, RTGCINTPTR offDelta);
|
|---|
| 326 | #endif /* IN_RING3 */
|
|---|
| 327 |
|
|---|
| 328 | VMMDECL(int) GIMHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
|
|---|
| 329 | VMMDECL(int) GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
|
|---|
| 330 | VMMDECL(int) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue);
|
|---|
| 331 |
|
|---|
| 332 | RT_C_DECLS_END
|
|---|
| 333 |
|
|---|
| 334 | #endif /* ___GIMHvInternal_h */
|
|---|
| 335 |
|
|---|
