VirtualBox

source: vbox/trunk/src/VBox/VMM/include/GIMHvInternal.h@ 106400

Last change on this file since 106400 was 106061, checked in by vboxsync, 2 months ago

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1/* $Id: GIMHvInternal.h 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * GIM - Hyper-V, Internal header file.
4 */
5
6/*
7 * Copyright (C) 2014-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_GIMHvInternal_h
29#define VMM_INCLUDED_SRC_include_GIMHvInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/vmm/gim.h>
35#include <VBox/vmm/cpum.h>
36
37#include <iprt/net.h>
38
39/** @name Hyper-V base feature identification.
40 * Features based on current partition privileges (per-VM).
41 * @{
42 */
43/** Virtual processor runtime MSR available. */
44#define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
45/** Partition reference counter MSR available. */
46#define GIM_HV_BASE_FEAT_PART_TIME_REF_COUNT_MSR RT_BIT(1)
47/** Basic Synthetic Interrupt Controller MSRs available. */
48#define GIM_HV_BASE_FEAT_BASIC_SYNIC_MSRS RT_BIT(2)
49/** Synthetic Timer MSRs available. */
50#define GIM_HV_BASE_FEAT_STIMER_MSRS RT_BIT(3)
51/** APIC access MSRs (EOI, ICR, TPR) available. */
52#define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4)
53/** Hypercall MSRs available. */
54#define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5)
55/** Access to VCPU index MSR available. */
56#define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6)
57/** Virtual system reset MSR available. */
58#define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7)
59/** Statistic pages MSRs available. */
60#define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8)
61/** Paritition reference TSC MSR available. */
62#define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9)
63/** Virtual guest idle state MSR available. */
64#define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10)
65/** Timer frequency MSRs (TSC and APIC) available. */
66#define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11)
67/** Debug MSRs available. */
68#define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12)
69/** @} */
70
71/** @name Hyper-V partition-creation feature identification.
72 * Indicates flags specified during partition creation.
73 * @{
74 */
75/** Create partitions. */
76#define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
77/** Access partition Id. */
78#define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1)
79/** Access memory pool. */
80#define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2)
81/** Adjust message buffers. */
82#define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3)
83/** Post messages. */
84#define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4)
85/** Signal events. */
86#define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5)
87/** Create port. */
88#define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6)
89/** Connect port. */
90#define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7)
91/** Access statistics. */
92#define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8)
93/** Debugging.*/
94#define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11)
95/** CPU management. */
96#define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12)
97/** CPU profiler. */
98#define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13)
99/** Enable expanded stack walking. */
100#define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14)
101/** Access VSM. */
102#define GIM_HV_PART_FLAGS_ACCESS_VSM RT_BIT(16)
103/** Access VP registers. */
104#define GIM_HV_PART_FLAGS_ACCESS_VP_REGS RT_BIT(17)
105/** Enable extended hypercalls. */
106#define GIM_HV_PART_FLAGS_EXTENDED_HYPERCALLS RT_BIT(20)
107/** Start virtual processor. */
108#define GIM_HV_PART_FLAGS_START_VP RT_BIT(21)
109/** @} */
110
111/** @name Hyper-V power management feature identification.
112 * @{
113 */
114/** Maximum CPU power state C0. */
115#define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
116/** Maximum CPU power state C1. */
117#define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1)
118/** Maximum CPU power state C2. */
119#define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2)
120/** Maximum CPU power state C3. */
121#define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3)
122/** HPET is required to enter C3 power state. */
123#define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4)
124/** @} */
125
126/** @name Hyper-V miscellaneous feature identification.
127 * Miscellaneous features available for the current partition.
128 * @{
129 */
130/** MWAIT instruction available. */
131#define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
132/** Guest debugging support available. */
133#define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1)
134/** Performance monitor support is available. */
135#define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2)
136/** Support for physical CPU dynamic partitioning events. */
137#define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3)
138/** Support for passing hypercall input parameter block via XMM registers. */
139#define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4)
140/** Support for virtual guest idle state. */
141#define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5)
142/** Support for hypervisor sleep state. */
143#define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6)
144/** Support for querying NUMA distances. */
145#define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7)
146/** Support for determining timer frequencies. */
147#define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8)
148/** Support for injecting synthetic machine checks. */
149#define GIM_HV_MISC_FEAT_INJECT_SYNMC_XCPT RT_BIT(9)
150/** Support for guest crash MSRs. */
151#define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10)
152/** Support for debug MSRs. */
153#define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11)
154/** Npiep1 Available */ /** @todo What the heck is this? */
155#define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12)
156/** Disable hypervisor available. */
157#define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13)
158/** Extended GVA ranges for FlushVirtualAddressList available. */
159#define GIM_HV_MISC_FEAT_EXT_GVA_RANGE_FOR_FLUSH_VA_LIST RT_BIT(14)
160/** Support for returning hypercall output via XMM registers. */
161#define GIM_HV_MISC_FEAT_HYPERCALL_OUTPUT_XMM RT_BIT(15)
162/** Synthetic interrupt source polling mode available. */
163#define GIM_HV_MISC_FEAT_SINT_POLLING_MODE RT_BIT(17)
164/** Hypercall MSR lock available. */
165#define GIM_HV_MISC_FEAT_HYPERCALL_MSR_LOCK RT_BIT(18)
166/** Use direct synthetic MSRs. */
167#define GIM_HV_MISC_FEAT_USE_DIRECT_SYNTH_MSRS RT_BIT(19)
168/** @} */
169
170/** @name Hyper-V implementation recommendations.
171 * Recommendations from the hypervisor for the guest for optimal performance.
172 * @{
173 */
174/** Use hypercall for address space switches rather than MOV CR3. */
175#define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
176/** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */
177#define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1)
178/** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
179#define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2)
180/** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
181#define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3)
182/** Use hypervisor provided MSR for a system reset. */
183#define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4)
184/** Relax timer-related checks (watchdogs/deadman timeouts) that rely on
185 * timely deliver of external interrupts. */
186#define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5)
187/** Recommend using DMA remapping. */
188#define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6)
189/** Recommend using interrupt remapping. */
190#define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7)
191/** Recommend using X2APIC MSRs rather than MMIO. */
192#define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8)
193/** Recommend deprecating Auto EOI (end of interrupt). */
194#define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9)
195/** Recommend using SyntheticClusterIpi hypercall. */
196#define GIM_HV_HINT_SYNTH_CLUSTER_IPI_HYPERCALL RT_BIT(10)
197/** Recommend using newer ExProcessMasks interface. */
198#define GIM_HV_HINT_EX_PROC_MASKS_INTERFACE RT_BIT(11)
199/** Indicate that Hyper-V is nested within a Hyper-V partition. */
200#define GIM_HV_HINT_NESTED_HYPERV RT_BIT(12)
201/** Recommend using INT for MBEC system calls. */
202#define GIM_HV_HINT_INT_FOR_MBEC_SYSCALLS RT_BIT(13)
203/** Recommend using enlightened VMCS interfacea and nested enlightenments. */
204#define GIM_HV_HINT_NESTED_ENLIGHTENED_VMCS_INTERFACE RT_BIT(14)
205/** @} */
206
207
208/** @name Hyper-V implementation hardware features.
209 * Which hardware features are in use by the hypervisor.
210 * @{
211 */
212/** APIC overlay is used. */
213#define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
214/** MSR bitmaps is used. */
215#define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1)
216/** Architectural performance counter supported. */
217#define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2)
218/** Nested paging is used. */
219#define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3)
220/** DMA remapping is used. */
221#define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4)
222/** Interrupt remapping is used. */
223#define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5)
224/** Memory patrol scrubber is present. */
225#define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6)
226/** DMA protection is in use. */
227#define GIM_HV_HOST_FEAT_DMA_PROT_IN_USE RT_BIT(7)
228/** HPET is requested. */
229#define GIM_HV_HOST_FEAT_HPET_REQUESTED RT_BIT(8)
230/** Synthetic timers are volatile. */
231#define GIM_HV_HOST_FEAT_STIMER_VOLATILE RT_BIT(9)
232/** @} */
233
234
235/** @name Hyper-V MSRs.
236 * @{
237 */
238/** Start of range 0. */
239#define MSR_GIM_HV_RANGE0_FIRST UINT32_C(0x40000000)
240/** Guest OS identification (R/W) */
241#define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000)
242/** Enable hypercall interface (R/W) */
243#define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001)
244/** Virtual processor's (VCPU) index (R) */
245#define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002)
246/** Reset operation (R/W) */
247#define MSR_GIM_HV_RESET UINT32_C(0x40000003)
248/** End of range 0. */
249#define MSR_GIM_HV_RANGE0_LAST MSR_GIM_HV_RESET
250
251/** Start of range 1. */
252#define MSR_GIM_HV_RANGE1_FIRST UINT32_C(0x40000010)
253/** Virtual processor's (VCPU) runtime (R) */
254#define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010)
255/** End of range 1. */
256#define MSR_GIM_HV_RANGE1_LAST MSR_GIM_HV_VP_RUNTIME
257
258/** Start of range 2. */
259#define MSR_GIM_HV_RANGE2_FIRST UINT32_C(0x40000020)
260/** Per-VM reference counter (R) */
261#define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020)
262/** Per-VM TSC page (R/W) */
263#define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021)
264/** Frequency of TSC in Hz as reported by the hypervisor (R) */
265#define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022)
266/** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
267#define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023)
268/** End of range 2. */
269#define MSR_GIM_HV_RANGE2_LAST MSR_GIM_HV_APIC_FREQ
270
271/** Start of range 3. */
272#define MSR_GIM_HV_RANGE3_FIRST UINT32_C(0x40000070)
273/** Access to APIC EOI (End-Of-Interrupt) register (W) */
274#define MSR_GIM_HV_EOI UINT32_C(0x40000070)
275/** Access to APIC ICR (Interrupt Command) register (R/W) */
276#define MSR_GIM_HV_ICR UINT32_C(0x40000071)
277/** Access to APIC TPR (Task Priority) register (R/W) */
278#define MSR_GIM_HV_TPR UINT32_C(0x40000072)
279/** Enables lazy EOI processing (R/W) */
280#define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073)
281/** End of range 3. */
282#define MSR_GIM_HV_RANGE3_LAST MSR_GIM_HV_APIC_ASSIST_PAGE
283
284/** Start of range 4. */
285#define MSR_GIM_HV_RANGE4_FIRST UINT32_C(0x40000080)
286/** Control behaviour of synthetic interrupt controller (R/W) */
287#define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080)
288/** Synthetic interrupt controller version (R) */
289#define MSR_GIM_HV_SVERSION UINT32_C(0x40000081)
290/** Base address of synthetic interrupt event flag (R/W) */
291#define MSR_GIM_HV_SIEFP UINT32_C(0x40000082)
292/** Base address of synthetic interrupt message page (R/W) */
293#define MSR_GIM_HV_SIMP UINT32_C(0x40000083)
294/** End-Of-Message in synthetic interrupt parameter page (W) */
295#define MSR_GIM_HV_EOM UINT32_C(0x40000084)
296/** End of range 4. */
297#define MSR_GIM_HV_RANGE4_LAST MSR_GIM_HV_EOM
298
299/** Start of range 5. */
300#define MSR_GIM_HV_RANGE5_FIRST UINT32_C(0x40000090)
301/** Configures synthetic interrupt source 0 (R/W) */
302#define MSR_GIM_HV_SINT0 UINT32_C(0x40000090)
303/** Configures synthetic interrupt source 1 (R/W) */
304#define MSR_GIM_HV_SINT1 UINT32_C(0x40000091)
305/** Configures synthetic interrupt source 2 (R/W) */
306#define MSR_GIM_HV_SINT2 UINT32_C(0x40000092)
307/** Configures synthetic interrupt source 3 (R/W) */
308#define MSR_GIM_HV_SINT3 UINT32_C(0x40000093)
309/** Configures synthetic interrupt source 4 (R/W) */
310#define MSR_GIM_HV_SINT4 UINT32_C(0x40000094)
311/** Configures synthetic interrupt source 5 (R/W) */
312#define MSR_GIM_HV_SINT5 UINT32_C(0x40000095)
313/** Configures synthetic interrupt source 6 (R/W) */
314#define MSR_GIM_HV_SINT6 UINT32_C(0x40000096)
315/** Configures synthetic interrupt source 7 (R/W) */
316#define MSR_GIM_HV_SINT7 UINT32_C(0x40000097)
317/** Configures synthetic interrupt source 8 (R/W) */
318#define MSR_GIM_HV_SINT8 UINT32_C(0x40000098)
319/** Configures synthetic interrupt source 9 (R/W) */
320#define MSR_GIM_HV_SINT9 UINT32_C(0x40000099)
321/** Configures synthetic interrupt source 10 (R/W) */
322#define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A)
323/** Configures synthetic interrupt source 11 (R/W) */
324#define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B)
325/** Configures synthetic interrupt source 12 (R/W) */
326#define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C)
327/** Configures synthetic interrupt source 13 (R/W) */
328#define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D)
329/** Configures synthetic interrupt source 14 (R/W) */
330#define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E)
331/** Configures synthetic interrupt source 15 (R/W) */
332#define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F)
333/** End of range 5. */
334#define MSR_GIM_HV_RANGE5_LAST MSR_GIM_HV_SINT15
335
336/** Start of range 6. */
337#define MSR_GIM_HV_RANGE6_FIRST UINT32_C(0x400000B0)
338/** Configures register for synthetic timer 0 (R/W) */
339#define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0)
340/** Expiration time or period for synthetic timer 0 (R/W) */
341#define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1)
342/** Configures register for synthetic timer 1 (R/W) */
343#define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2)
344/** Expiration time or period for synthetic timer 1 (R/W) */
345#define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3)
346/** Configures register for synthetic timer 2 (R/W) */
347#define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4)
348/** Expiration time or period for synthetic timer 2 (R/W) */
349#define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5)
350/** Configures register for synthetic timer 3 (R/W) */
351#define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6)
352/** Expiration time or period for synthetic timer 3 (R/W) */
353#define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7)
354/** End of range 6. */
355#define MSR_GIM_HV_RANGE6_LAST MSR_GIM_HV_STIMER3_COUNT
356
357/** Start of range 7. */
358#define MSR_GIM_HV_RANGE7_FIRST UINT32_C(0x400000C1)
359/** Trigger to transition to power state C1 (R) */
360#define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1)
361/** Trigger to transition to power state C2 (R) */
362#define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2)
363/** Trigger to transition to power state C3 (R) */
364#define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3)
365/** End of range 7. */
366#define MSR_GIM_HV_RANGE7_LAST MSR_GIM_HV_POWER_STATE_TRIGGER_C3
367
368/** Start of range 8. */
369#define MSR_GIM_HV_RANGE8_FIRST UINT32_C(0x400000D1)
370/** Configure the recipe for power state transitions to C1 (R/W) */
371#define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1)
372/** Configure the recipe for power state transitions to C2 (R/W) */
373#define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2)
374/** Configure the recipe for power state transitions to C3 (R/W) */
375#define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3)
376/** End of range 8. */
377#define MSR_GIM_HV_RANGE8_LAST MSR_GIM_HV_POWER_STATE_CONFIG_C3
378
379/** Start of range 9. */
380#define MSR_GIM_HV_RANGE9_FIRST UINT32_C(0x400000E0)
381/** Map the guest's retail partition stats page (R/W) */
382#define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0)
383/** Map the guest's internal partition stats page (R/W) */
384#define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1)
385/** Map the guest's retail VP stats page (R/W) */
386#define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2)
387/** Map the guest's internal VP stats page (R/W) */
388#define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3)
389/** End of range 9. */
390#define MSR_GIM_HV_RANGE9_LAST MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
391
392/** Start of range 10. */
393#define MSR_GIM_HV_RANGE10_FIRST UINT32_C(0x400000F0)
394/** Trigger the guest's transition to idle power state (R) */
395#define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0)
396/** Synthetic debug control. */
397#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1)
398/** Synthetic debug status. */
399#define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2)
400/** Synthetic debug send buffer. */
401#define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3)
402/** Synthetic debug receive buffer. */
403#define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4)
404/** Synthetic debug pending buffer. */
405#define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5)
406/** End of range 10. */
407#define MSR_GIM_HV_RANGE10_LAST MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
408
409/** Start of range 11. */
410#define MSR_GIM_HV_RANGE11_FIRST UINT32_C(0x400000FF)
411/** Undocumented debug options MSR. */
412#define MSR_GIM_HV_DEBUG_OPTIONS_MSR UINT32_C(0x400000FF)
413/** End of range 11. */
414#define MSR_GIM_HV_RANGE11_LAST MSR_GIM_HV_DEBUG_OPTIONS_MSR
415
416/** Start of range 12. */
417#define MSR_GIM_HV_RANGE12_FIRST UINT32_C(0x40000100)
418/** Guest crash MSR 0. */
419#define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100)
420/** Guest crash MSR 1. */
421#define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101)
422/** Guest crash MSR 2. */
423#define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102)
424/** Guest crash MSR 3. */
425#define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103)
426/** Guest crash MSR 4. */
427#define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104)
428/** Guest crash control. */
429#define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105)
430/** End of range 12. */
431#define MSR_GIM_HV_RANGE12_LAST MSR_GIM_HV_CRASH_CTL
432/** @} */
433
434AssertCompile(MSR_GIM_HV_RANGE0_FIRST <= MSR_GIM_HV_RANGE0_LAST);
435AssertCompile(MSR_GIM_HV_RANGE1_FIRST <= MSR_GIM_HV_RANGE1_LAST);
436AssertCompile(MSR_GIM_HV_RANGE2_FIRST <= MSR_GIM_HV_RANGE2_LAST);
437AssertCompile(MSR_GIM_HV_RANGE3_FIRST <= MSR_GIM_HV_RANGE3_LAST);
438AssertCompile(MSR_GIM_HV_RANGE4_FIRST <= MSR_GIM_HV_RANGE4_LAST);
439AssertCompile(MSR_GIM_HV_RANGE5_FIRST <= MSR_GIM_HV_RANGE5_LAST);
440AssertCompile(MSR_GIM_HV_RANGE6_FIRST <= MSR_GIM_HV_RANGE6_LAST);
441AssertCompile(MSR_GIM_HV_RANGE7_FIRST <= MSR_GIM_HV_RANGE7_LAST);
442AssertCompile(MSR_GIM_HV_RANGE8_FIRST <= MSR_GIM_HV_RANGE8_LAST);
443AssertCompile(MSR_GIM_HV_RANGE9_FIRST <= MSR_GIM_HV_RANGE9_LAST);
444AssertCompile(MSR_GIM_HV_RANGE10_FIRST <= MSR_GIM_HV_RANGE10_LAST);
445AssertCompile(MSR_GIM_HV_RANGE11_FIRST <= MSR_GIM_HV_RANGE11_LAST);
446
447/** @name Hyper-V MSR - Reset (MSR_GIM_HV_RESET).
448 * @{
449 */
450/** The reset enable mask. */
451#define MSR_GIM_HV_RESET_ENABLE RT_BIT_64(0)
452/** Whether the reset MSR is enabled. */
453#define MSR_GIM_HV_RESET_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_RESET_ENABLE)
454/** @} */
455
456/** @name Hyper-V MSR - Hypercall (MSR_GIM_HV_HYPERCALL).
457 * @{
458 */
459/** Guest-physical page frame number of the hypercall-page. */
460#define MSR_GIM_HV_HYPERCALL_GUEST_PFN(a) ((a) >> 12)
461/** The hypercall enable mask. */
462#define MSR_GIM_HV_HYPERCALL_PAGE_ENABLE RT_BIT_64(0)
463/** Whether the hypercall-page is enabled or not. */
464#define MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE)
465/** @} */
466
467/** @name Hyper-V MSR - Reference TSC (MSR_GIM_HV_REF_TSC).
468 * @{
469 */
470/** Guest-physical page frame number of the TSC-page. */
471#define MSR_GIM_HV_REF_TSC_GUEST_PFN(a) ((a) >> 12)
472/** The TSC-page enable mask. */
473#define MSR_GIM_HV_REF_TSC_ENABLE RT_BIT_64(0)
474/** Whether the TSC-page is enabled or not. */
475#define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE)
476/** @} */
477
478/** @name Hyper-V MSR - Guest crash control (MSR_GIM_HV_CRASH_CTL).
479 * @{
480 */
481/** The Crash Control notify mask. */
482#define MSR_GIM_HV_CRASH_CTL_NOTIFY RT_BIT_64(63)
483/** @} */
484
485/** @name Hyper-V MSR - Guest OS ID (MSR_GIM_HV_GUEST_OS_ID).
486 * @{
487 */
488/** An open-source operating system. */
489#define MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(a) RT_BOOL((a) & RT_BIT_64(63))
490/** Vendor ID. */
491#define MSR_GIM_HV_GUEST_OS_ID_VENDOR(a) (uint32_t)(((a) >> 48) & 0xfff)
492/** Guest OS variant, depending on the vendor ID. */
493#define MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(a) (uint32_t)(((a) >> 40) & 0xff)
494/** Guest OS major version. */
495#define MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(a) (uint32_t)(((a) >> 32) & 0xff)
496/** Guest OS minor version. */
497#define MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(a) (uint32_t)(((a) >> 24) & 0xff)
498/** Guest OS service version (e.g. service pack number in case of Windows). */
499#define MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(a) (uint32_t)(((a) >> 16) & 0xff)
500/** Guest OS build number. */
501#define MSR_GIM_HV_GUEST_OS_ID_BUILD(a) (uint32_t)((a) & 0xffff)
502/** @} */
503
504/** @name Hyper-V MSR - APIC-assist page (MSR_GIM_HV_APIC_ASSIST_PAGE).
505 * @{
506 */
507/** Guest-physical page frame number of the APIC-assist page. */
508#define MSR_GIM_HV_APICASSIST_GUEST_PFN(a) ((a) >> 12)
509/** The APIC-assist page enable mask. */
510#define MSR_GIM_HV_APICASSIST_PAGE_ENABLE RT_BIT_64(0)
511/** Whether the APIC-assist page is enabled or not. */
512#define MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_APICASSIST_PAGE_ENABLE)
513/** @} */
514
515/** @name Hyper-V MSR - Synthetic Interrupt Event Flags page
516 * (MSR_GIM_HV_SIEFP).
517 * @{
518 */
519/** Guest-physical page frame number of the APIC-assist page. */
520#define MSR_GIM_HV_SIEF_GUEST_PFN(a) ((a) >> 12)
521/** The SIEF enable mask. */
522#define MSR_GIM_HV_SIEF_PAGE_ENABLE RT_BIT_64(0)
523/** Whether the SIEF page is enabled or not. */
524#define MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIEF_PAGE_ENABLE)
525/** @} */
526
527/** @name Hyper-V MSR - Synthetic Interrupt Control (MSR_GIM_HV_CONTROL).
528 * @{
529 */
530/** The SControl enable mask. */
531#define MSR_GIM_HV_SCONTROL_ENABLE RT_BIT_64(0)
532/** Whether SControl is enabled or not. */
533#define MSR_GIM_HV_SCONTROL_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SCONTROL_ENABLE)
534/** @} */
535
536/** @name Hyper-V MSR - Synthetic Timer Config (MSR_GIM_HV_STIMER_CONFIG).
537 * @{
538 */
539/** The Stimer enable mask. */
540#define MSR_GIM_HV_STIMER_ENABLE RT_BIT_64(0)
541/** Whether Stimer is enabled or not. */
542#define MSR_GIM_HV_STIMER_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_ENABLE)
543/** The Stimer periodic mask. */
544#define MSR_GIM_HV_STIMER_PERIODIC RT_BIT_64(1)
545/** Whether Stimer is enabled or not. */
546#define MSR_GIM_HV_STIMER_IS_PERIODIC(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_PERIODIC)
547/** The Stimer lazy mask. */
548#define MSR_GIM_HV_STIMER_LAZY RT_BIT_64(2)
549/** Whether Stimer is enabled or not. */
550#define MSR_GIM_HV_STIMER_IS_LAZY(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_LAZY)
551/** The Stimer auto-enable mask. */
552#define MSR_GIM_HV_STIMER_AUTO_ENABLE RT_BIT_64(3)
553/** Whether Stimer is enabled or not. */
554#define MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_AUTO_ENABLE)
555/** The Stimer SINTx mask (bits 16:19). */
556#define MSR_GIM_HV_STIMER_SINTX UINT64_C(0xf0000)
557/** Gets the Stimer synthetic interrupt source. */
558#define MSR_GIM_HV_STIMER_GET_SINTX(a) (((a) >> 16) & 0xf)
559/** The Stimer valid read/write mask. */
560#define MSR_GIM_HV_STIMER_RW_VALID ( MSR_GIM_HV_STIMER_ENABLE | MSR_GIM_HV_STIMER_PERIODIC \
561 | MSR_GIM_HV_STIMER_LAZY | MSR_GIM_HV_STIMER_AUTO_ENABLE \
562 | MSR_GIM_HV_STIMER_SINTX)
563/** @} */
564
565
566/** Hyper-V page size. */
567#define GIM_HV_PAGE_SIZE 4096
568/** Hyper-V page shift. */
569#define GIM_HV_PAGE_SHIFT 12
570
571/** Microsoft Hyper-V vendor signature. */
572#define GIM_HV_VENDOR_MICROSOFT "Microsoft Hv"
573
574/**
575 * Hyper-V APIC-assist (HV_REFERENCE_TSC_PAGE) structure placed in the TSC
576 * reference page.
577 */
578typedef struct GIMHVAPICASSIST
579{
580 uint32_t fNoEoiRequired : 1;
581 uint32_t u31Reserved0 : 31;
582} GIMHVAPICASSIST;
583/** Pointer to Hyper-V reference TSC. */
584typedef GIMHVAPICASSIST *PGIMHVAPICASSIST;
585/** Pointer to a const Hyper-V reference TSC. */
586typedef GIMHVAPICASSIST const *PCGIMHVAPICASSIST;
587AssertCompileSize(GIMHVAPICASSIST, 4);
588
589/**
590 * Hypercall parameter type.
591 */
592typedef enum GIMHVHYPERCALLPARAM
593{
594 GIMHVHYPERCALLPARAM_IN = 0,
595 GIMHVHYPERCALLPARAM_OUT
596} GIMHVHYPERCALLPARAM;
597
598
599/** @name Hyper-V hypercall op codes.
600 * @{
601 */
602/** Post message to hypervisor or VMs. */
603#define GIM_HV_HYPERCALL_OP_POST_MESSAGE 0x5C
604/** Post debug data to hypervisor. */
605#define GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA 0x69
606/** Retreive debug data from hypervisor. */
607#define GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA 0x6A
608/** Reset debug session. */
609#define GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION 0x6B
610/** @} */
611
612/** @name Hyper-V extended hypercall op codes.
613 * @{
614 */
615/** Query extended hypercall capabilities. */
616#define GIM_HV_EXT_HYPERCALL_OP_QUERY_CAP 0x8001
617/** Query guest physical address range that has zero'd filled memory. */
618#define GIM_HV_EXT_HYPERCALL_OP_GET_BOOT_ZEROED_MEM 0x8002
619/** @} */
620
621
622/** @name Hyper-V Extended hypercall - HvExtCallQueryCapabilities.
623 * @{
624 */
625/** Boot time zeroed pages. */
626#define GIM_HV_EXT_HYPERCALL_CAP_ZERO_MEM RT_BIT_64(0)
627/** Whether boot time zeroed pages capability is enabled. */
628#define GIM_HV_EXT_HYPERCALL_CAP_IS_ZERO_MEM_ENABLED(a) RT_BOOL((a) & GIM_HV_EXT_HYPERCALL_CAP_ZERO_MEM)
629/** @} */
630
631
632/** @name Hyper-V hypercall inputs.
633 * @{
634 */
635/** The hypercall call operation code. */
636#define GIM_HV_HYPERCALL_IN_CALL_CODE(a) ((a) & UINT64_C(0xffff))
637/** Whether it's a fast (register based) hypercall or not (memory-based). */
638#define GIM_HV_HYPERCALL_IN_IS_FAST(a) RT_BOOL((a) & RT_BIT_64(16))
639/** Total number of reps for a rep hypercall. */
640#define GIM_HV_HYPERCALL_IN_REP_COUNT(a) (((a) << 32) & UINT64_C(0xfff))
641/** Rep start index for a rep hypercall. */
642#define GIM_HV_HYPERCALL_IN_REP_START_IDX(a) (((a) << 48) & UINT64_C(0xfff))
643/** Reserved bits range 1. */
644#define GIM_HV_HYPERCALL_IN_RSVD_1(a) (((a) << 17) & UINT64_C(0x7fff))
645/** Reserved bits range 2. */
646#define GIM_HV_HYPERCALL_IN_RSVD_2(a) (((a) << 44) & UINT64_C(0xf))
647/** Reserved bits range 3. */
648#define GIM_HV_HYPERCALL_IN_RSVD_3(a) (((a) << 60) & UINT64_C(0x7))
649/** @} */
650
651
652/** @name Hyper-V hypercall status codes.
653 * @{
654 */
655/** Success. */
656#define GIM_HV_STATUS_SUCCESS 0x00
657/** Unrecognized hypercall. */
658#define GIM_HV_STATUS_INVALID_HYPERCALL_CODE 0x02
659/** Invalid hypercall input (rep count, rsvd bits). */
660#define GIM_HV_STATUS_INVALID_HYPERCALL_INPUT 0x03
661/** Hypercall guest-physical address not 8-byte aligned or crosses page boundary. */
662#define GIM_HV_STATUS_INVALID_ALIGNMENT 0x04
663/** Invalid hypercall parameters. */
664#define GIM_HV_STATUS_INVALID_PARAMETER 0x05
665/** Access denied. */
666#define GIM_HV_STATUS_ACCESS_DENIED 0x06
667/** The partition state not valid for specified op. */
668#define GIM_HV_STATUS_INVALID_PARTITION_STATE 0x07
669/** The hypercall operation could not be performed. */
670#define GIM_HV_STATUS_OPERATION_DENIED 0x08
671/** Specified partition property ID not recognized. */
672#define GIM_HV_STATUS_UNKNOWN_PROPERTY 0x09
673/** Specified partition property value not within range. */
674#define GIM_HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0x0a
675/** Insufficient memory for performing the hypercall. */
676#define GIM_HV_STATUS_INSUFFICIENT_MEMORY 0x0b
677/** Maximum partition depth has been exceeded for the partition hierarchy. */
678#define GIM_HV_STATUS_PARTITION_TOO_DEEP 0x0c
679/** The specified partition ID is not valid. */
680#define GIM_HV_STATUS_INVALID_PARTITION_ID 0x0d
681/** The specified virtual processor index in invalid. */
682#define GIM_HV_STATUS_INVALID_VP_INDEX 0x0e
683/** The specified port ID is not unique or doesn't exist. */
684#define GIM_HV_STATUS_INVALID_PORT_ID 0x11
685/** The specified connection ID is not unique or doesn't exist. */
686#define GIM_HV_STATUS_INVALID_CONNECTION_ID 0x12
687/** The target port doesn't have sufficient buffers for the caller to post a message. */
688#define GIM_HV_STATUS_INSUFFICIENT_BUFFERS 0x13
689/** External interrupt not acknowledged.*/
690#define GIM_HV_STATUS_NOT_ACKNOWLEDGED 0x14
691/** External interrupt acknowledged. */
692#define GIM_HV_STATUS_ACKNOWLEDGED 0x16
693/** Invalid state due to misordering Hv[Save|Restore]PartitionState. */
694#define GIM_HV_STATUS_INVALID_SAVE_RESTORE_STATE 0x17
695/** Operation not perform due to a required feature of SynIc was disabled. */
696#define GIM_HV_STATUS_INVALID_SYNIC_STATE 0x18
697/** Object or value already in use. */
698#define GIM_HV_STATUS_OBJECT_IN_USE 0x19
699/** Invalid proximity domain information. */
700#define GIM_HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO 0x1A
701/** Attempt to retrieve data failed. */
702#define GIM_HV_STATUS_NO_DATA 0x1B
703/** Debug connection has not recieved any new data since the last time. */
704#define GIM_HV_STATUS_INACTIVE 0x1C
705/** A resource is unavailable for allocation. */
706#define GIM_HV_STATUS_NO_RESOURCES 0x1D
707/** A hypervisor feature is not available to the caller. */
708#define GIM_HV_STATUS_FEATURE_UNAVAILABLE 0x1E
709/** The debug packet returned is partial due to an I/O error. */
710#define GIM_HV_STATUS_PARTIAL_PACKET 0x1F
711/** Processor feature SSE3 unsupported. */
712#define GIM_HV_STATUS_PROC_FEAT_SSE3_NOT_SUPPORTED 0x20
713/** Processor feature LAHSAHF unsupported. */
714#define GIM_HV_STATUS_PROC_FEAT_LAHSAHF_NOT_SUPPORTED 0x21
715/** Processor feature SSSE3 unsupported. */
716#define GIM_HV_STATUS_PROC_FEAT_SSSE3_NOT_SUPPORTED 0x22
717/** Processor feature SSE4.1 unsupported. */
718#define GIM_HV_STATUS_PROC_FEAT_SSE4_1_NOT_SUPPORTED 0x23
719/** Processor feature SSE4.2 unsupported. */
720#define GIM_HV_STATUS_PROC_FEAT_SSE4_2_NOT_SUPPORTED 0x24
721/** Processor feature SSE4A unsupported. */
722#define GIM_HV_STATUS_PROC_FEAT_SSE4A_NOT_SUPPORTED 0x25
723/** Processor feature XOP unsupported. */
724#define GIM_HV_STATUS_PROC_FEAT_XOP_NOT_SUPPORTED 0x26
725/** Processor feature POPCNT unsupported. */
726#define GIM_HV_STATUS_PROC_FEAT_POPCNT_NOT_SUPPORTED 0x27
727/** Processor feature CMPXCHG16B unsupported. */
728#define GIM_HV_STATUS_PROC_FEAT_CMPXCHG16B_NOT_SUPPORTED 0x28
729/** Processor feature ALTMOVCR8 unsupported. */
730#define GIM_HV_STATUS_PROC_FEAT_ALTMOVCR8_NOT_SUPPORTED 0x29
731/** Processor feature LZCNT unsupported. */
732#define GIM_HV_STATUS_PROC_FEAT_LZCNT_NOT_SUPPORTED 0x2A
733/** Processor feature misaligned SSE unsupported. */
734#define GIM_HV_STATUS_PROC_FEAT_MISALIGNED_SSE_NOT_SUPPORTED 0x2B
735/** Processor feature MMX extensions unsupported. */
736#define GIM_HV_STATUS_PROC_FEAT_MMX_EXT_NOT_SUPPORTED 0x2C
737/** Processor feature 3DNow! unsupported. */
738#define GIM_HV_STATUS_PROC_FEAT_3DNOW_NOT_SUPPORTED 0x2D
739/** Processor feature Extended 3DNow! unsupported. */
740#define GIM_HV_STATUS_PROC_FEAT_EXTENDED_3DNOW_NOT_SUPPORTED 0x2E
741/** Processor feature 1GB large page unsupported. */
742#define GIM_HV_STATUS_PROC_FEAT_PAGE_1GB_NOT_SUPPORTED 0x2F
743/** Processor cache line flush size incompatible. */
744#define GIM_HV_STATUS_PROC_CACHE_LINE_FLUSH_SIZE_INCOMPATIBLE 0x30
745/** Processor feature XSAVE unsupported. */
746#define GIM_HV_STATUS_PROC_FEAT_XSAVE_NOT_SUPPORTED 0x31
747/** Processor feature XSAVEOPT unsupported. */
748#define GIM_HV_STATUS_PROC_FEAT_XSAVEOPT_NOT_SUPPORTED 0x32
749/** The specified buffer was too small for all requested data. */
750#define GIM_HV_STATUS_INSUFFICIENT_BUFFER 0x33
751/** Processor feature XSAVEOPT unsupported. */
752#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX_NOT_SUPPORTED 0x34
753/** Processor feature XSAVEOPT unsupported. */
754#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEAT_NOT_SUPPORTED 0x35 /** Huh, isn't this same as 0x31? */
755/** Processor feature XSAVEOPT unsupported. */
756#define GIM_HV_STATUS_PROC_FEAT_PAGE_XSAVE_SAVE_AREA_INCOMPATIBLE 0x36
757/** Processor architecture unsupoorted. */
758#define GIM_HV_STATUS_INCOMPATIBLE_PROCESSOR 0x37
759/** Max. domains for platform I/O remapping reached. */
760#define GIM_HV_STATUS_INSUFFICIENT_DEVICE_DOMAINS 0x38
761/** Processor feature AES unsupported. */
762#define GIM_HV_STATUS_PROC_FEAT_AES_NOT_SUPPORTED 0x39
763/** Processor feature PCMULQDQ unsupported. */
764#define GIM_HV_STATUS_PROC_FEAT_PCMULQDQ_NOT_SUPPORTED 0x3A
765/** Processor feature XSAVE features unsupported. */
766#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEATURES_INCOMPATIBLE 0x3B
767/** Generic CPUID validation error. */
768#define GIM_HV_STATUS_CPUID_FEAT_VALIDATION_ERROR 0x3C
769/** XSAVE CPUID validation error. */
770#define GIM_HV_STATUS_CPUID_XSAVE_FEAT_VALIDATION_ERROR 0x3D
771/** Processor startup timed out. */
772#define GIM_HV_STATUS_PROCESSOR_STARTUP_TIMEOUT 0x3E
773/** SMX enabled by the BIOS. */
774#define GIM_HV_STATUS_SMX_ENABLED 0x3F
775/** Processor feature PCID unsupported. */
776#define GIM_HV_STATUS_PROC_FEAT_PCID_NOT_SUPPORTED 0x40
777/** Invalid LP index. */
778#define GIM_HV_STATUS_INVALID_LP_INDEX 0x41
779/** Processor feature PCID unsupported. */
780#define GIM_HV_STATUS_FEAT_FMA4_NOT_SUPPORTED 0x42
781/** Processor feature PCID unsupported. */
782#define GIM_HV_STATUS_FEAT_F16C_NOT_SUPPORTED 0x43
783/** Processor feature PCID unsupported. */
784#define GIM_HV_STATUS_PROC_FEAT_RDRAND_NOT_SUPPORTED 0x44
785/** Processor feature RDWRFSGS unsupported. */
786#define GIM_HV_STATUS_PROC_FEAT_RDWRFSGS_NOT_SUPPORTED 0x45
787/** Processor feature SMEP unsupported. */
788#define GIM_HV_STATUS_PROC_FEAT_SMEP_NOT_SUPPORTED 0x46
789/** Processor feature enhanced fast string unsupported. */
790#define GIM_HV_STATUS_PROC_FEAT_ENHANCED_FAST_STRING_NOT_SUPPORTED 0x47
791/** Processor feature MOVBE unsupported. */
792#define GIM_HV_STATUS_PROC_FEAT_MOVBE_NOT_SUPPORTED 0x48
793/** Processor feature BMI1 unsupported. */
794#define GIM_HV_STATUS_PROC_FEAT_BMI1_NOT_SUPPORTED 0x49
795/** Processor feature BMI2 unsupported. */
796#define GIM_HV_STATUS_PROC_FEAT_BMI2_NOT_SUPPORTED 0x4A
797/** Processor feature HLE unsupported. */
798#define GIM_HV_STATUS_PROC_FEAT_HLE_NOT_SUPPORTED 0x4B
799/** Processor feature RTM unsupported. */
800#define GIM_HV_STATUS_PROC_FEAT_RTM_NOT_SUPPORTED 0x4C
801/** Processor feature XSAVE FMA unsupported. */
802#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FMA_NOT_SUPPORTED 0x4D
803/** Processor feature XSAVE AVX2 unsupported. */
804#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX2_NOT_SUPPORTED 0x4E
805/** Processor feature NPIEP1 unsupported. */
806#define GIM_HV_STATUS_PROC_FEAT_NPIEP1_NOT_SUPPORTED 0x4F
807/** @} */
808
809
810/** @name Hyper-V MSR - Debug control (MSR_GIM_HV_SYNTH_DEBUG_CONTROL).
811 * @{
812 */
813/** Perform debug write. */
814#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(a) RT_BOOL((a) & RT_BIT_64(0))
815/** Perform debug read. */
816#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(a) RT_BOOL((a) & RT_BIT_64(1))
817/** Returns length of the debug write buffer. */
818#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(a) (((a) & UINT64_C(0xffff0000)) >> 16)
819/** @} */
820
821
822/** @name Hyper-V MSR - Debug status (MSR_GIM_HV_SYNTH_DEBUG_STATUS).
823 * @{
824 */
825/** Debug send buffer operation success. */
826#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS RT_BIT_64(0)
827/** Debug receive buffer operation success. */
828#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS RT_BIT_64(2)
829/** Debug connection was reset. */
830#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_CONN_RESET RT_BIT_64(3)
831/** @} */
832
833
834/** @name Hyper-V MSR - synthetic interrupt (MSR_GIM_HV_SINTx).
835 * @{
836 */
837/** The interrupt masked mask. */
838#define MSR_GIM_HV_SINT_MASKED RT_BIT_64(16)
839/** Whether the interrupt source is masked. */
840#define MSR_GIM_HV_SINT_IS_MASKED(a) RT_BOOL((a) & MSR_GIM_HV_SINT_MASKED)
841/** Gets the interrupt vector. */
842#define MSR_GIM_HV_SINT_GET_VECTOR(a) ((a) & UINT64_C(0xff))
843/** The AutoEoi mask. */
844#define MSR_GIM_HV_SINT_AUTOEOI RT_BIT_64(17)
845/** Gets whether AutoEoi is enabled for the synthetic interrupt. */
846#define MSR_GIM_HV_SINT_IS_AUTOEOI(a) RT_BOOL((a) & MSR_GIM_HV_SINT_AUTOEOI)
847/** @} */
848
849
850/** @name Hyper-V MSR - synthetic interrupt message page (MSR_GIM_HV_SIMP).
851 * @{
852 */
853/** The SIMP enable mask. */
854#define MSR_GIM_HV_SIMP_ENABLE RT_BIT_64(0)
855/** Whether the SIMP is enabled. */
856#define MSR_GIM_HV_SIMP_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIMP_ENABLE)
857/** The SIMP guest-physical address. */
858#define MSR_GIM_HV_SIMP_GPA(a) ((a) & UINT64_C(0xfffffffffffff000))
859/** @} */
860
861
862/** @name Hyper-V hypercall debug options.
863 * @{ */
864/** Maximum debug data payload size in bytes. */
865#define GIM_HV_DEBUG_MAX_DATA_SIZE 4088
866
867/** The undocumented bit for MSR_GIM_HV_DEBUG_OPTIONS_MSR that makes it all
868 * work. */
869#define GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS RT_BIT(2)
870
871/** Guest will perform the HvPostDebugData hypercall until completion. */
872#define GIM_HV_DEBUG_POST_LOOP RT_BIT_32(0)
873/** Mask of valid HvPostDebugData options. */
874#define GIM_HV_DEBUG_POST_OPTIONS_MASK RT_BIT_32(0)
875
876/** Guest will perform the HvRetrieveDebugData hypercall until completion. */
877#define GIM_HV_DEBUG_RETREIVE_LOOP RT_BIT_32(0)
878/** Guest checks if any global debug session is active. */
879#define GIM_HV_DEBUG_RETREIVE_TEST_ACTIVITY RT_BIT_32(1)
880/** Mask of valid HvRetrieveDebugData options. */
881#define GIM_HV_DEBUG_RETREIVE_OPTIONS_MASK RT_BIT_32(0) | RT_BIT_32(1)
882
883/** Guest requests purging of incoming debug data. */
884#define GIM_HV_DEBUG_PURGE_INCOMING_DATA RT_BIT_32(0)
885/** Guest requests purging of outgoing debug data. */
886#define GIM_HV_DEBUG_PURGE_OUTGOING_DATA RT_BIT_32(1)
887/** @} */
888
889
890/** @name VMBus.
891 * These are just arbitrary definitions made up by Microsoft without
892 * any publicly available specification behind it.
893 * @{ */
894/** VMBus connection ID. */
895#define GIM_HV_VMBUS_MSG_CONNECTION_ID 1
896/** VMBus synthetic interrupt source (see VMBUS_MESSAGE_SINT in linux
897 * sources). */
898#define GIM_HV_VMBUS_MSG_SINT 2
899/** @} */
900
901/** @name SynIC.
902 * Synthetic Interrupt Controller definitions.
903 * @{ */
904/** SynIC version register. */
905#define GIM_HV_SVERSION 1
906/** Number of synthetic interrupt sources (warning, fixed in saved-states!). */
907#define GIM_HV_SINT_COUNT 16
908/** Lowest valid vector for synthetic interrupt. */
909#define GIM_HV_SINT_VECTOR_VALID_MIN 16
910/** Highest valid vector for synthetic interrupt. */
911#define GIM_HV_SINT_VECTOR_VALID_MAX 255
912/** Number of synthetic timers. */
913#define GIM_HV_STIMER_COUNT 4
914/** @} */
915
916/** @name Hyper-V synthetic interrupt message type.
917 * See 14.8.2 "SynIC Message Types"
918 * @{
919 */
920typedef enum GIMHVMSGTYPE
921{
922 GIMHVMSGTYPE_NONE = 0, /* Common messages */
923 GIMHVMSGTYPE_VMBUS = 1, /* Guest messages */
924 GIMHVMSGTYPE_UNMAPPEDGPA = 0x80000000, /* Hypervisor messages */
925 GIMHVMSGTYPE_GPAINTERCEPT = 0x80000001,
926 GIMHVMSGTYPE_TIMEREXPIRED = 0x80000010,
927 GIMHVMSGTYPE_INVALIDVPREGVAL = 0x80000020,
928 GIMHVMSGTYPE_UNRECOVERABLEXCPT = 0x80000021,
929 GIMHVMSGTYPE_UNSUPPORTEDFEAT = 0x80000022,
930 GIMHVMSGTYPE_APICEOI = 0x80000030,
931 GIMHVMSGTYPE_X64LEGACYFPERROR = 0x80000031,
932 GIMHVMSGTYPE_EVENTLOGBUFSCOMPLETE = 0x80000040,
933 GIMHVMSGTYPE_X64IOPORTINTERCEPT = 0x80010000,
934 GIMHVMSGTYPE_X64MSRINTERCEPT = 0x80010001,
935 GIMHVMSGTYPE_X64CPUIDINTERCEPT = 0x80010002,
936 GIMHVMSGTYPE_X64XCPTINTERCEPT = 0x80010003
937} GIMHVMSGTYPE;
938AssertCompileSize(GIMHVMSGTYPE, 4);
939/** @} */
940
941
942/** @name Hyper-V synthetic interrupt message format.
943 * @{ */
944#define GIM_HV_MSG_SIZE 256
945#define GIM_HV_MSG_MAX_PAYLOAD_SIZE 240
946#define GIM_HV_MSG_MAX_PAYLOAD_UNITS 30
947
948/**
949 * Synthetic interrupt message flags.
950 */
951typedef union GIMHVMSGFLAGS
952{
953 struct
954 {
955 uint8_t u1Pending : 1;
956 uint8_t u7Reserved : 7;
957 } n;
958 uint8_t u;
959} GIMHVMSGFLAGS;
960AssertCompileSize(GIMHVMSGFLAGS, sizeof(uint8_t));
961
962/**
963 * Synthetic interrupt message header.
964 *
965 * @remarks The layout of this structure differs from
966 * the Hyper-V spec. Aug 8, 2013 v4.0a. Layout
967 * in accordance w/ VMBus client expectations.
968 */
969typedef struct GIMHVMSGHDR
970{
971 GIMHVMSGTYPE enmMessageType;
972 uint8_t cbPayload;
973 GIMHVMSGFLAGS MessageFlags;
974 uint16_t uRsvd;
975 union
976 {
977 uint64_t uOriginatorId;
978 uint64_t uPartitionId;
979 uint64_t uPortId;
980 } msgid;
981} GIMHVMSGHDR;
982/** Pointer to a synthetic interrupt message header. */
983typedef GIMHVMSGHDR *PGIMHVMSGHDR;
984AssertCompileMemberOffset(GIMHVMSGHDR, cbPayload, 4);
985AssertCompileMemberOffset(GIMHVMSGHDR, MessageFlags, 5);
986AssertCompileMemberOffset(GIMHVMSGHDR, msgid, 8);
987AssertCompileSize(GIMHVMSGHDR, GIM_HV_MSG_SIZE - GIM_HV_MSG_MAX_PAYLOAD_SIZE);
988
989/**
990 * Synthetic interrupt message.
991 */
992typedef struct GIMHVMSG
993{
994 GIMHVMSGHDR MsgHdr;
995 uint64_t aPayload[GIM_HV_MSG_MAX_PAYLOAD_UNITS];
996} GIMHVMSG;
997/** Pointer to a synthetic interrupt message. */
998typedef GIMHVMSG *PGIMHVMSG;
999AssertCompileSize(GIMHVMSG, GIM_HV_MSG_SIZE);
1000/** @} */
1001
1002
1003/** @name Hyper-V hypercall parameters.
1004 * @{ */
1005/**
1006 * HvPostMessage hypercall input.
1007 */
1008typedef struct GIMHVPOSTMESSAGEIN
1009{
1010 uint32_t uConnectionId;
1011 uint32_t uPadding;
1012 GIMHVMSGTYPE enmMessageType;
1013 uint32_t cbPayload;
1014} GIMHVPOSTMESSAGEIN;
1015/** Pointer to a HvPostMessage input struct. */
1016typedef GIMHVPOSTMESSAGEIN *PGIMHVPOSTMESSAGEIN;
1017AssertCompileSize(GIMHVPOSTMESSAGEIN, 16);
1018
1019/**
1020 * HvResetDebugData hypercall input.
1021 */
1022typedef struct GIMHVDEBUGRESETIN
1023{
1024 uint32_t fFlags;
1025 uint32_t uPadding;
1026} GIMHVDEBUGRESETIN;
1027/** Pointer to a HvResetDebugData input struct. */
1028typedef GIMHVDEBUGRESETIN *PGIMHVDEBUGRESETIN;
1029AssertCompileSize(GIMHVDEBUGRESETIN, 8);
1030
1031/**
1032 * HvPostDebugData hypercall input.
1033 */
1034typedef struct GIMHVDEBUGPOSTIN
1035{
1036 uint32_t cbWrite;
1037 uint32_t fFlags;
1038} GIMHVDEBUGPOSTIN;
1039/** Pointer to a HvPostDebugData input struct. */
1040typedef GIMHVDEBUGPOSTIN *PGIMHVDEBUGPOSTIN;
1041AssertCompileSize(GIMHVDEBUGPOSTIN, 8);
1042
1043/**
1044 * HvPostDebugData hypercall output.
1045 */
1046typedef struct GIMHVDEBUGPOSTOUT
1047{
1048 uint32_t cbPending;
1049 uint32_t uPadding;
1050} GIMHVDEBUGPOSTOUT;
1051/** Pointer to a HvPostDebugData output struct. */
1052typedef GIMHVDEBUGPOSTOUT *PGIMHVDEBUGPOSTOUT;
1053AssertCompileSize(GIMHVDEBUGPOSTOUT, 8);
1054
1055/**
1056 * HvRetrieveDebugData hypercall input.
1057 */
1058typedef struct GIMHVDEBUGRETRIEVEIN
1059{
1060 uint32_t cbRead;
1061 uint32_t fFlags;
1062 uint64_t u64Timeout;
1063} GIMHVDEBUGRETRIEVEIN;
1064/** Pointer to a HvRetrieveDebugData input struct. */
1065typedef GIMHVDEBUGRETRIEVEIN *PGIMHVDEBUGRETRIEVEIN;
1066AssertCompileSize(GIMHVDEBUGRETRIEVEIN, 16);
1067
1068/**
1069 * HvRetriveDebugData hypercall output.
1070 */
1071typedef struct GIMHVDEBUGRETRIEVEOUT
1072{
1073 uint32_t cbRead;
1074 uint32_t cbRemaining;
1075} GIMHVDEBUGRETRIEVEOUT;
1076/** Pointer to a HvRetrieveDebugData output struct. */
1077typedef GIMHVDEBUGRETRIEVEOUT *PGIMHVDEBUGRETRIEVEOUT;
1078AssertCompileSize(GIMHVDEBUGRETRIEVEOUT, 8);
1079
1080/**
1081 * HvExtCallQueryCapabilities hypercall output.
1082 */
1083typedef struct GIMHVEXTQUERYCAP
1084{
1085 uint64_t fCapabilities;
1086} GIMHVEXTQUERYCAP;
1087/** Pointer to a HvExtCallQueryCapabilities output struct. */
1088typedef GIMHVEXTQUERYCAP *PGIMHVEXTQUERYCAP;
1089AssertCompileSize(GIMHVEXTQUERYCAP, 8);
1090
1091/**
1092 * Hyper-V memory range for HvExtCallGetBootZeroedMemory.
1093 */
1094typedef struct GIMHVEXTMEMRANGE
1095{
1096 RTGCPHYS GCPhysStart;
1097 uint64_t cPages;
1098} GIMHVEXTMEMRANGE;
1099
1100/** Maximum number of zeroed memory ranges supported by Hyper-V. */
1101#define GIM_HV_MAX_BOOT_ZEROED_MEM_RANGES 255
1102
1103/**
1104 * HvExtCallGetBootZeroedMemory hypercall output.
1105 */
1106typedef struct GIMHVEXTGETBOOTZEROMEM
1107{
1108 uint64_t cRanges;
1109 GIMHVEXTMEMRANGE aRanges[GIM_HV_MAX_BOOT_ZEROED_MEM_RANGES];
1110} GIMHVEXTGETBOOTZEROMEM;
1111/** Pointer to a HvExtCallGetBootZeroedMemory output struct. */
1112typedef GIMHVEXTGETBOOTZEROMEM *PGIMHVEXTGETBOOTZEROMEM;
1113/** Pointer to a const HvExtCallGetBootZeroedMemory output struct. */
1114typedef GIMHVEXTGETBOOTZEROMEM const *PCGIMHVEXTGETBOOTZEROMEM;
1115AssertCompileSize(GIMHVEXTGETBOOTZEROMEM, 4088);
1116AssertCompile(sizeof(GIMHVEXTGETBOOTZEROMEM) <= GIM_HV_PAGE_SIZE);
1117/** @} */
1118
1119
1120/**
1121 * MMIO2 region indices.
1122 */
1123/** The hypercall page region. */
1124#define GIM_HV_HYPERCALL_PAGE_REGION_IDX UINT8_C(0)
1125/** The TSC page region. */
1126#define GIM_HV_REF_TSC_PAGE_REGION_IDX UINT8_C(1)
1127/** The maximum region index (must be <= UINT8_MAX). */
1128#define GIM_HV_REGION_IDX_MAX GIM_HV_REF_TSC_PAGE_REGION_IDX
1129
1130/**
1131 * Hyper-V TSC (HV_REFERENCE_TSC_PAGE) structure placed in the TSC reference
1132 * page.
1133 */
1134typedef struct GIMHVREFTSC
1135{
1136 uint32_t u32TscSequence;
1137 uint32_t uReserved0;
1138 uint64_t u64TscScale;
1139 int64_t i64TscOffset;
1140} GIMHVTSCPAGE;
1141/** Pointer to Hyper-V reference TSC. */
1142typedef GIMHVREFTSC *PGIMHVREFTSC;
1143/** Pointer to a const Hyper-V reference TSC. */
1144typedef GIMHVREFTSC const *PCGIMHVREFTSC;
1145
1146/**
1147 * Type of the next reply to be sent to the debug connection of the guest.
1148 *
1149 * @remarks This is saved as part of saved-state, so don't re-order or
1150 * alter the size!
1151 */
1152typedef enum GIMHVDEBUGREPLY
1153{
1154 /** Send UDP packet. */
1155 GIMHVDEBUGREPLY_UDP = 0,
1156 /** Send DHCP offer for DHCP discover. */
1157 GIMHVDEBUGREPLY_DHCP_OFFER,
1158 /** DHCP offer sent. */
1159 GIMHVDEBUGREPLY_DHCP_OFFER_SENT,
1160 /** Send DHCP acknowledgement for DHCP request. */
1161 GIMHVDEBUGREPLY_DHCP_ACK,
1162 /** DHCP acknowledgement sent. */
1163 GIMHVDEBUGREPLY_DHCP_ACK_SENT,
1164 /** Sent ARP reply. */
1165 GIMHVDEBUGREPLY_ARP_REPLY,
1166 /** ARP reply sent. */
1167 GIMHVDEBUGREPLY_ARP_REPLY_SENT,
1168 /** Customary 32-bit type hack. */
1169 GIMHVDEBUGREPLY_32BIT_HACK = 0x7fffffff
1170} GIMHVDEBUGREPLY;
1171AssertCompileSize(GIMHVDEBUGREPLY, sizeof(uint32_t));
1172
1173/**
1174 * GIM Hyper-V VM instance data.
1175 * Changes to this must checked against the padding of the gim union in VM!
1176 */
1177typedef struct GIMHV
1178{
1179 /** @name Primary MSRs.
1180 * @{ */
1181 /** Guest OS identity MSR. */
1182 uint64_t u64GuestOsIdMsr;
1183 /** Hypercall MSR. */
1184 uint64_t u64HypercallMsr;
1185 /** Reference TSC page MSR. */
1186 uint64_t u64TscPageMsr;
1187 /** @} */
1188
1189 /** @name CPUID features.
1190 * @{ */
1191 /** Basic features. */
1192 uint32_t uBaseFeat;
1193 /** Partition flags. */
1194 uint32_t uPartFlags;
1195 /** Power management. */
1196 uint32_t uPowMgmtFeat;
1197 /** Miscellaneous. */
1198 uint32_t uMiscFeat;
1199 /** Hypervisor hints to the guest. */
1200 uint32_t uHyperHints;
1201 /** Hypervisor capabilities. */
1202 uint32_t uHyperCaps;
1203 /** @} */
1204
1205 /** @name Guest Crash MSRs.
1206 * @{
1207 */
1208 /** Guest crash control MSR. */
1209 uint64_t uCrashCtlMsr;
1210 /** Guest crash parameter 0 MSR. */
1211 uint64_t uCrashP0Msr;
1212 /** Guest crash parameter 1 MSR. */
1213 uint64_t uCrashP1Msr;
1214 /** Guest crash parameter 2 MSR. */
1215 uint64_t uCrashP2Msr;
1216 /** Guest crash parameter 3 MSR. */
1217 uint64_t uCrashP3Msr;
1218 /** Guest crash parameter 4 MSR. */
1219 uint64_t uCrashP4Msr;
1220 /** @} */
1221
1222 /** @name Time management.
1223 * @{ */
1224 /** Per-VM R0 Spinlock for protecting EMT writes to the TSC page. */
1225 RTSPINLOCK hSpinlockR0;
1226 /** The TSC frequency (in HZ) reported to the guest. */
1227 uint64_t cTscTicksPerSecond;
1228 /** @} */
1229
1230 /** @name Hypercalls.
1231 * @{ */
1232 /** Guest address of the hypercall input parameter page. */
1233 RTGCPHYS GCPhysHypercallIn;
1234 /** Guest address of the hypercall output parameter page. */
1235 RTGCPHYS GCPhysHypercallOut;
1236 /** Pointer to the hypercall input parameter page - R3. */
1237 R3PTRTYPE(uint8_t *) pbHypercallIn;
1238 /** Pointer to the hypercall output parameter page - R3. */
1239 R3PTRTYPE(uint8_t *) pbHypercallOut;
1240 /** @} */
1241
1242 /** @name Guest debugging.
1243 * @{ */
1244 /** Whether we're posing as the Microsoft vendor. */
1245 bool fIsVendorMsHv;
1246 /** Whether we're posing as the Microsoft virtualization service. */
1247 bool fIsInterfaceVs;
1248 /** Whether debugging support is enabled. */
1249 bool fDbgEnabled;
1250 /** Whether we should suggest a hypercall-based debug interface to the guest. */
1251 bool fDbgHypercallInterface;
1252 bool afAlignment0[4];
1253 /** The action to take while sending replies. */
1254 GIMHVDEBUGREPLY enmDbgReply;
1255 /** The IP address chosen by/assigned to the guest. */
1256 RTNETADDRIPV4 DbgGuestIp4Addr;
1257 /** Transaction ID for the BOOTP+DHCP sequence. */
1258 uint32_t uDbgBootpXId;
1259 /** The source UDP port used by the guest while sending debug packets. */
1260 uint16_t uUdpGuestSrcPort;
1261 /** The destination UDP port used by the guest while sending debug packets. */
1262 uint16_t uUdpGuestDstPort;
1263 /** Debug send buffer MSR. */
1264 uint64_t uDbgSendBufferMsr;
1265 /** Debug receive buffer MSR. */
1266 uint64_t uDbgRecvBufferMsr;
1267 /** Debug pending buffer MSR. */
1268 uint64_t uDbgPendingBufferMsr;
1269 /** Debug status MSR. */
1270 uint64_t uDbgStatusMsr;
1271 /** Intermediate debug I/O buffer (GIM_HV_PAGE_SIZE). */
1272 R3PTRTYPE(void *) pvDbgBuffer;
1273 R3PTRTYPE(void *) pvAlignment0;
1274 /** @} */
1275
1276 /** Array of MMIO2 regions. */
1277 GIMMMIO2REGION aMmio2Regions[GIM_HV_REGION_IDX_MAX + 1];
1278} GIMHV;
1279/** Pointer to per-VM GIM Hyper-V instance data. */
1280typedef GIMHV *PGIMHV;
1281/** Pointer to const per-VM GIM Hyper-V instance data. */
1282typedef GIMHV const *PCGIMHV;
1283AssertCompileMemberAlignment(GIMHV, aMmio2Regions, 8);
1284AssertCompileMemberAlignment(GIMHV, hSpinlockR0, sizeof(uintptr_t));
1285
1286/**
1287 * Hyper-V per-VCPU synthetic timer.
1288 */
1289typedef struct GIMHVSTIMER
1290{
1291 /** Synthetic timer handle. */
1292 TMTIMERHANDLE hTimer;
1293 /** Virtual CPU ID this timer belongs to (for reverse mapping). */
1294 VMCPUID idCpu;
1295 /** The index of this timer in the auStimers array (for reverse mapping). */
1296 uint32_t idxStimer;
1297 /** Synthetic timer config MSR. */
1298 uint64_t uStimerConfigMsr;
1299 /** Synthetic timer count MSR. */
1300 uint64_t uStimerCountMsr;
1301} GIMHVSTIMER;
1302/** Pointer to per-VCPU Hyper-V synthetic timer. */
1303typedef GIMHVSTIMER *PGIMHVSTIMER;
1304/** Pointer to a const per-VCPU Hyper-V synthetic timer. */
1305typedef GIMHVSTIMER const *PCGIMHVSTIMER;
1306AssertCompileSizeAlignment(GIMHVSTIMER, 8);
1307
1308/**
1309 * Hyper-V VCPU instance data.
1310 * Changes to this must checked against the padding of the gim union in VMCPU!
1311 */
1312typedef struct GIMHVCPU
1313{
1314 /** @name Synthetic interrupt MSRs.
1315 * @{ */
1316 /** Synthetic interrupt message page MSR. */
1317 uint64_t uSimpMsr;
1318 /** Interrupt source MSRs. */
1319 uint64_t auSintMsrs[GIM_HV_SINT_COUNT];
1320 /** Synethtic interrupt events flag page MSR. */
1321 uint64_t uSiefpMsr;
1322 /** APIC-assist page MSR. */
1323 uint64_t uApicAssistPageMsr;
1324 /** Synthetic interrupt control MSR. */
1325 uint64_t uSControlMsr;
1326 /** Synthetic timers. */
1327 GIMHVSTIMER aStimers[GIM_HV_STIMER_COUNT];
1328 /** @} */
1329
1330 /** @name Statistics.
1331 * @{ */
1332 STAMCOUNTER aStatStimerFired[GIM_HV_STIMER_COUNT];
1333 /** @} */
1334} GIMHVCPU;
1335/** Pointer to per-VCPU GIM Hyper-V instance data. */
1336typedef GIMHVCPU *PGIMHVCPU;
1337/** Pointer to const per-VCPU GIM Hyper-V instance data. */
1338typedef GIMHVCPU const *PCGIMHVCPU;
1339
1340
1341RT_C_DECLS_BEGIN
1342
1343#ifdef IN_RING0
1344VMMR0_INT_DECL(int) gimR0HvInitVM(PVMCC pVM);
1345VMMR0_INT_DECL(int) gimR0HvTermVM(PVMCC pVM);
1346VMMR0_INT_DECL(int) gimR0HvUpdateParavirtTsc(PVMCC pVM, uint64_t u64Offset);
1347#endif /* IN_RING0 */
1348
1349#ifdef IN_RING3
1350VMMR3_INT_DECL(int) gimR3HvInit(PVM pVM, PCFGMNODE pGimCfg);
1351VMMR3_INT_DECL(int) gimR3HvInitCompleted(PVM pVM);
1352VMMR3_INT_DECL(int) gimR3HvTerm(PVM pVM);
1353VMMR3_INT_DECL(void) gimR3HvRelocate(PVM pVM, RTGCINTPTR offDelta);
1354VMMR3_INT_DECL(void) gimR3HvReset(PVM pVM);
1355VMMR3_INT_DECL(int) gimR3HvSave(PVM pVM, PSSMHANDLE pSSM);
1356VMMR3_INT_DECL(int) gimR3HvLoad(PVM pVM, PSSMHANDLE pSSM);
1357VMMR3_INT_DECL(int) gimR3HvLoadDone(PVM pVM, PSSMHANDLE pSSM);
1358VMMR3_INT_DECL(int) gimR3HvGetDebugSetup(PVM pVM, PGIMDEBUGSETUP pDbgSetup);
1359
1360VMMR3_INT_DECL(int) gimR3HvDisableSiefPage(PVMCPU pVCpu);
1361VMMR3_INT_DECL(int) gimR3HvEnableSiefPage(PVMCPU pVCpu, RTGCPHYS GCPhysSiefPage);
1362VMMR3_INT_DECL(int) gimR3HvEnableSimPage(PVMCPU pVCpu, RTGCPHYS GCPhysSimPage);
1363VMMR3_INT_DECL(int) gimR3HvDisableSimPage(PVMCPU pVCpu);
1364VMMR3_INT_DECL(int) gimR3HvDisableApicAssistPage(PVMCPU pVCpu);
1365VMMR3_INT_DECL(int) gimR3HvEnableApicAssistPage(PVMCPU pVCpu, RTGCPHYS GCPhysTscPage);
1366VMMR3_INT_DECL(int) gimR3HvDisableTscPage(PVM pVM);
1367VMMR3_INT_DECL(int) gimR3HvEnableTscPage(PVM pVM, RTGCPHYS GCPhysTscPage, bool fUseThisTscSeq, uint32_t uTscSeq);
1368VMMR3_INT_DECL(int) gimR3HvDisableHypercallPage(PVM pVM);
1369VMMR3_INT_DECL(int) gimR3HvEnableHypercallPage(PVM pVM, RTGCPHYS GCPhysHypercallPage);
1370
1371VMMR3_INT_DECL(int) gimR3HvHypercallPostDebugData(PVM pVM, int *prcHv);
1372VMMR3_INT_DECL(int) gimR3HvHypercallRetrieveDebugData(PVM pVM, int *prcHv);
1373VMMR3_INT_DECL(int) gimR3HvDebugWrite(PVM pVM, void *pvData, uint32_t cbWrite, uint32_t *pcbWritten, bool fUdpPkt);
1374VMMR3_INT_DECL(int) gimR3HvDebugRead(PVM pVM, void *pvBuf, uint32_t cbBuf, uint32_t cbRead, uint32_t *pcbRead,
1375 uint32_t cMsTimeout, bool fUdpPkt);
1376VMMR3_INT_DECL(int) gimR3HvHypercallExtQueryCap(PVM pVM, int *prcHv);
1377VMMR3_INT_DECL(int) gimR3HvHypercallExtGetBootZeroedMem(PVM pVM, int *prcHv);
1378
1379#endif /* IN_RING3 */
1380
1381VMM_INT_DECL(PGIMMMIO2REGION) gimHvGetMmio2Regions(PVM pVM, uint32_t *pcRegions);
1382VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM);
1383VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PCVM pVM);
1384VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu);
1385VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPUCC pVCpu, PCPUMCTX pCtx, PDISSTATE pDis, uint8_t *pcbInstr);
1386VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPUCC pVCpu, PCPUMCTX pCtx);
1387VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercallEx(PVMCPUCC pVCpu, PCPUMCTX pCtx, unsigned uDisOpcode, uint8_t cbInstr);
1388#if !defined(VBOX_VMM_TARGET_ARMV8)
1389VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
1390VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
1391#endif
1392
1393VMM_INT_DECL(void) gimHvStartStimer(PVMCPUCC pVCpu, PCGIMHVSTIMER pHvStimer);
1394
1395RT_C_DECLS_END
1396
1397#endif /* !VMM_INCLUDED_SRC_include_GIMHvInternal_h */
1398
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