| 1 | /* $Id: EMHandleRCTmpl.h 93115 2022-01-01 11:31:46Z vboxsync $ */
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| 2 | /** @file
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| 3 | * EM - emR3[Raw|Hm|Nem]HandleRC template.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2022 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 | #ifndef VMM_INCLUDED_SRC_include_EMHandleRCTmpl_h
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| 19 | #define VMM_INCLUDED_SRC_include_EMHandleRCTmpl_h
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| 20 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 21 | # pragma once
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| 22 | #endif
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| 23 |
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| 24 | #if defined(EMHANDLERC_WITH_PATM) + defined(EMHANDLERC_WITH_HM) + defined(EMHANDLERC_WITH_NEM) != 1
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| 25 | # error "Exactly one of these must be defined: EMHANDLERC_WITH_PATM, EMHANDLERC_WITH_HM, EMHANDLERC_WITH_NEM"
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| 26 | #endif
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| 27 |
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| 28 |
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| 29 | /**
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| 30 | * Process a subset of the raw-mode, HM and NEM return codes.
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| 31 | *
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| 32 | * Since we have to share this with raw-mode single stepping, this inline
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| 33 | * function has been created to avoid code duplication.
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| 34 | *
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| 35 | * @returns VINF_SUCCESS if it's ok to continue raw mode.
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| 36 | * @returns VBox status code to return to the EM main loop.
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| 37 | *
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| 38 | * @param pVM The cross context VM structure.
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| 39 | * @param pVCpu The cross context virtual CPU structure.
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| 40 | * @param rc The return code.
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| 41 | */
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| 42 | #if defined(EMHANDLERC_WITH_HM) || defined(DOXYGEN_RUNNING)
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| 43 | int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, int rc)
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| 44 | #elif defined(EMHANDLERC_WITH_NEM)
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| 45 | int emR3NemHandleRC(PVM pVM, PVMCPU pVCpu, int rc)
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| 46 | #endif
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| 47 | {
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| 48 | switch (rc)
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| 49 | {
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| 50 | /*
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| 51 | * Common & simple ones.
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| 52 | */
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| 53 | case VINF_SUCCESS:
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| 54 | break;
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| 55 | case VINF_EM_RESCHEDULE_RAW:
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| 56 | case VINF_EM_RESCHEDULE_HM:
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| 57 | case VINF_EM_RAW_INTERRUPT:
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| 58 | case VINF_EM_RAW_TO_R3:
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| 59 | case VINF_EM_RAW_TIMER_PENDING:
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| 60 | case VINF_EM_PENDING_REQUEST:
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| 61 | rc = VINF_SUCCESS;
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| 62 | break;
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| 63 |
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| 64 | #ifndef EMHANDLERC_WITH_NEM
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| 65 | /*
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| 66 | * Conflict or out of page tables.
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| 67 | *
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| 68 | * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
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| 69 | * do here is to execute the pending forced actions.
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| 70 | */
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| 71 | case VINF_PGM_SYNC_CR3:
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| 72 | AssertMsg(VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
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| 73 | ("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
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| 74 | rc = VINF_SUCCESS;
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| 75 | break;
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| 76 |
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| 77 | /*
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| 78 | * PGM pool flush pending (guest SMP only).
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| 79 | */
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| 80 | /** @todo jumping back and forth between ring 0 and 3 can burn a lot of cycles
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| 81 | * if the EMT thread that's supposed to handle the flush is currently not active
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| 82 | * (e.g. waiting to be scheduled) -> fix this properly!
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| 83 | *
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| 84 | * bird: Since the clearing is global and done via a rendezvous any CPU can do
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| 85 | * it. They would have to choose who to call VMMR3EmtRendezvous and send
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| 86 | * the rest to VMMR3EmtRendezvousFF ... Hmm ... that's not going to work
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| 87 | * all that well since the latter will race the setup done by the
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| 88 | * first. Guess that means we need some new magic in that area for
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| 89 | * handling this case. :/
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| 90 | */
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| 91 | case VINF_PGM_POOL_FLUSH_PENDING:
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| 92 | rc = VINF_SUCCESS;
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| 93 | break;
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| 94 | #endif /* !EMHANDLERC_WITH_NEM */
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| 95 |
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| 96 | /*
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| 97 | * I/O Port access - emulate the instruction.
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| 98 | */
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| 99 | case VINF_IOM_R3_IOPORT_READ:
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| 100 | case VINF_IOM_R3_IOPORT_WRITE:
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| 101 | case VINF_EM_RESUME_R3_HISTORY_EXEC: /* Resume EMHistoryExec after VMCPU_FF_IOM. */
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| 102 | rc = emR3ExecuteIOInstruction(pVM, pVCpu);
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| 103 | break;
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| 104 |
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| 105 | /*
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| 106 | * Execute pending I/O Port access.
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| 107 | */
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| 108 | case VINF_EM_PENDING_R3_IOPORT_WRITE:
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| 109 | rc = VBOXSTRICTRC_TODO(emR3ExecutePendingIoPortWrite(pVM, pVCpu));
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| 110 | break;
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| 111 | case VINF_EM_PENDING_R3_IOPORT_READ:
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| 112 | rc = VBOXSTRICTRC_TODO(emR3ExecutePendingIoPortRead(pVM, pVCpu));
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| 113 | break;
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| 114 |
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| 115 | /*
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| 116 | * Memory mapped I/O access - emulate the instruction.
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| 117 | */
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| 118 | case VINF_IOM_R3_MMIO_READ:
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| 119 | case VINF_IOM_R3_MMIO_WRITE:
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| 120 | case VINF_IOM_R3_MMIO_READ_WRITE:
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| 121 | rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
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| 122 | break;
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| 123 |
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| 124 | /*
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| 125 | * Machine specific register access - emulate the instruction.
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| 126 | */
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| 127 | case VINF_CPUM_R3_MSR_READ:
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| 128 | case VINF_CPUM_R3_MSR_WRITE:
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| 129 | rc = emR3ExecuteInstruction(pVM, pVCpu, "MSR");
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| 130 | break;
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| 131 |
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| 132 | /*
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| 133 | * GIM hypercall.
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| 134 | */
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| 135 | case VINF_GIM_R3_HYPERCALL:
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| 136 | rc = emR3ExecuteInstruction(pVM, pVCpu, "Hypercall");
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| 137 | break;
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| 138 |
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| 139 | #ifdef EMHANDLERC_WITH_HM
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| 140 | case VINF_EM_HM_PATCH_TPR_INSTR:
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| 141 | rc = HMR3PatchTprInstr(pVM, pVCpu);
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| 142 | break;
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| 143 | #endif
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| 144 |
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| 145 | case VINF_EM_RAW_GUEST_TRAP:
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| 146 | case VINF_EM_RAW_EMULATE_INSTR:
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| 147 | Assert(!TRPMHasTrap(pVCpu)); /* We're directly executing instructions below without respecting any pending traps! */
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| 148 | rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
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| 149 | break;
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| 150 |
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| 151 | case VINF_EM_RAW_INJECT_TRPM_EVENT:
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| 152 | CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
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| 153 | rc = VBOXSTRICTRC_VAL(IEMInjectTrpmEvent(pVCpu));
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| 154 | /* The following condition should be removed when IEM_IMPLEMENTS_TASKSWITCH becomes true. */
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| 155 | if (rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
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| 156 | rc = emR3ExecuteInstruction(pVM, pVCpu, "EVENT: ");
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| 157 | break;
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| 158 |
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| 159 | case VINF_EM_EMULATE_SPLIT_LOCK:
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| 160 | rc = VBOXSTRICTRC_TODO(emR3ExecuteSplitLockInstruction(pVM, pVCpu));
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| 161 | break;
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| 162 |
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| 163 |
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| 164 | /*
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| 165 | * Up a level.
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| 166 | */
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| 167 | case VINF_EM_TERMINATE:
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| 168 | case VINF_EM_OFF:
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| 169 | case VINF_EM_RESET:
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| 170 | case VINF_EM_SUSPEND:
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| 171 | case VINF_EM_HALT:
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| 172 | case VINF_EM_RESUME:
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| 173 | case VINF_EM_NO_MEMORY:
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| 174 | case VINF_EM_RESCHEDULE:
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| 175 | case VINF_EM_RESCHEDULE_REM:
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| 176 | case VINF_EM_WAIT_SIPI:
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| 177 | break;
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| 178 |
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| 179 | /*
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| 180 | * Up a level and invoke the debugger.
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| 181 | */
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| 182 | case VINF_EM_DBG_STEPPED:
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| 183 | case VINF_EM_DBG_BREAKPOINT:
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| 184 | case VINF_EM_DBG_STEP:
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| 185 | case VINF_EM_DBG_HYPER_BREAKPOINT:
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| 186 | case VINF_EM_DBG_HYPER_STEPPED:
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| 187 | case VINF_EM_DBG_HYPER_ASSERTION:
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| 188 | case VINF_EM_DBG_STOP:
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| 189 | case VINF_EM_DBG_EVENT:
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| 190 | break;
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| 191 |
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| 192 | /*
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| 193 | * Up a level, dump and debug.
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| 194 | */
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| 195 | case VERR_TRPM_DONT_PANIC:
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| 196 | case VERR_TRPM_PANIC:
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| 197 | case VERR_VMM_RING0_ASSERTION:
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| 198 | case VINF_EM_TRIPLE_FAULT:
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| 199 | case VERR_VMM_HYPER_CR3_MISMATCH:
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| 200 | case VERR_VMM_RING3_CALL_DISABLED:
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| 201 | case VERR_IEM_INSTR_NOT_IMPLEMENTED:
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| 202 | case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
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| 203 | case VERR_EM_GUEST_CPU_HANG:
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| 204 | break;
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| 205 |
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| 206 | #ifdef EMHANDLERC_WITH_HM
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| 207 | /*
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| 208 | * Up a level, after Hm have done some release logging.
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| 209 | */
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| 210 | case VERR_VMX_INVALID_VMCS_FIELD:
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| 211 | case VERR_VMX_INVALID_VMCS_PTR:
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| 212 | case VERR_VMX_INVALID_VMXON_PTR:
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| 213 | case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
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| 214 | case VERR_VMX_UNEXPECTED_EXCEPTION:
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| 215 | case VERR_VMX_UNEXPECTED_EXIT:
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| 216 | case VERR_VMX_INVALID_GUEST_STATE:
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| 217 | case VERR_VMX_UNABLE_TO_START_VM:
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| 218 | case VERR_SVM_UNKNOWN_EXIT:
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| 219 | case VERR_SVM_UNEXPECTED_EXIT:
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| 220 | case VERR_SVM_UNEXPECTED_PATCH_TYPE:
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| 221 | case VERR_SVM_UNEXPECTED_XCPT_EXIT:
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| 222 | HMR3CheckError(pVM, rc);
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| 223 | break;
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| 224 |
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| 225 | /* Up a level; fatal */
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| 226 | case VERR_VMX_IN_VMX_ROOT_MODE:
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| 227 | case VERR_SVM_IN_USE:
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| 228 | case VERR_SVM_UNABLE_TO_START_VM:
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| 229 | break;
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| 230 | #endif
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| 231 |
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| 232 | #ifdef EMHANDLERC_WITH_NEM
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| 233 | /* Fatal stuff, up a level. */
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| 234 | case VERR_NEM_IPE_0:
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| 235 | case VERR_NEM_IPE_1:
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| 236 | case VERR_NEM_IPE_2:
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| 237 | case VERR_NEM_IPE_3:
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| 238 | case VERR_NEM_IPE_4:
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| 239 | case VERR_NEM_IPE_5:
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| 240 | case VERR_NEM_IPE_6:
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| 241 | case VERR_NEM_IPE_7:
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| 242 | case VERR_NEM_IPE_8:
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| 243 | case VERR_NEM_IPE_9:
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| 244 | break;
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| 245 | #endif
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| 246 |
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| 247 | /*
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| 248 | * These two should be handled via the force flag already, but just in
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| 249 | * case they end up here deal with it.
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| 250 | */
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| 251 | case VINF_IOM_R3_IOPORT_COMMIT_WRITE:
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| 252 | case VINF_IOM_R3_MMIO_COMMIT_WRITE:
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| 253 | AssertFailed();
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| 254 | rc = VBOXSTRICTRC_TODO(IOMR3ProcessForceFlag(pVM, pVCpu, rc));
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| 255 | break;
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| 256 |
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| 257 | /*
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| 258 | * Anything which is not known to us means an internal error
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| 259 | * and the termination of the VM!
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| 260 | */
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| 261 | default:
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| 262 | AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
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| 263 | break;
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| 264 | }
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| 265 | return rc;
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| 266 | }
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| 267 |
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| 268 | #endif /* !VMM_INCLUDED_SRC_include_EMHandleRCTmpl_h */
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| 269 |
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