| 1 | ; $Id: CPUMInternal.mac 91266 2021-09-15 22:26:50Z vboxsync $
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| 2 | ;; @file
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| 3 | ; CPUM - Internal header file (asm).
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2006-2020 Oracle Corporation
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 |
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| 18 | %include "VBox/asmdefs.mac"
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| 19 | %include "VBox/vmm/cpum.mac"
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| 20 |
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| 21 | ;; Check sanity.
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| 22 | %ifdef VBOX_WITH_KERNEL_USING_XMM
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| 23 | %ifndef IN_RING0
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| 24 | %error "What? We've got code assuming VBOX_WITH_KERNEL_USING_XMM is only defined in ring-0!"
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| 25 | %endif
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| 26 | %endif
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| 27 |
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| 28 | ;; For numeric expressions
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| 29 | %ifdef RT_ARCH_AMD64
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| 30 | %define CPUM_IS_AMD64 1
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| 31 | %else
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| 32 | %define CPUM_IS_AMD64 0
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| 33 | %endif
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| 34 |
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| 35 |
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| 36 | ;;
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| 37 | ; CPU info
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| 38 | struc CPUMINFO
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| 39 | .cMsrRanges resd 1 ; uint32_t
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| 40 | .fMsrMask resd 1 ; uint32_t
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| 41 | .fMxCsrMask resd 1 ; uint32_t
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| 42 | .cCpuIdLeaves resd 1 ; uint32_t
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| 43 | .iFirstExtCpuIdLeaf resd 1 ; uint32_t
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| 44 | .enmUnknownCpuIdMethod resd 1 ; CPUMUNKNOWNCPUID
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| 45 | .DefCpuId resb CPUMCPUID_size ; CPUMCPUID
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| 46 | .uScalableBusFreq resq 1 ; uint64_t
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| 47 | .paMsrRangesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMMSRRANGE)
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| 48 | .paCpuIdLeavesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMCPUIDLEAF)
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| 49 | .aCpuIdLeaves resb 256*32
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| 50 | .aMsrRanges resb 8192*128
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| 51 | endstruc
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| 52 |
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| 53 |
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| 54 | %define CPUM_USED_FPU_HOST RT_BIT(0)
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| 55 | %define CPUM_USED_FPU_GUEST RT_BIT(10)
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| 56 | %define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
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| 57 | %define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
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| 58 | %define CPUM_USE_SYSENTER RT_BIT(3)
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| 59 | %define CPUM_USE_SYSCALL RT_BIT(4)
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| 60 | %define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
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| 61 | %define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
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| 62 | %define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
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| 63 | %define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
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| 64 | %define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
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| 65 | %define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
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| 66 | %define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
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| 67 |
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| 68 | %define CPUM_HANDLER_DS 1
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| 69 | %define CPUM_HANDLER_ES 2
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| 70 | %define CPUM_HANDLER_FS 3
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| 71 | %define CPUM_HANDLER_GS 4
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| 72 | %define CPUM_HANDLER_IRET 5
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| 73 | %define CPUM_HANDLER_TYPEMASK 0ffh
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| 74 | %define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
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| 75 |
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| 76 |
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| 77 | struc CPUM
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| 78 | ;...
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| 79 | .fHostUseFlags resd 1
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| 80 |
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| 81 | ; CR4 masks
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| 82 | .CR4.AndMask resd 1
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| 83 | .CR4.OrMask resd 1
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| 84 | .u8PortableCpuIdLevel resb 1
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| 85 | .fPendingRestore resb 1
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| 86 |
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| 87 | alignb 8
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| 88 | .fXStateGuestMask resq 1
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| 89 | .fXStateHostMask resq 1
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| 90 |
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| 91 | alignb 64
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| 92 | .HostFeatures resb 48
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| 93 | .GuestFeatures resb 48
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| 94 | .GuestInfo resb CPUMINFO_size
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| 95 |
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| 96 | ; Patch manager saved state compatability CPUID leaf arrays
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| 97 | .aGuestCpuIdPatmStd resb 16*6
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| 98 | .aGuestCpuIdPatmExt resb 16*10
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| 99 | .aGuestCpuIdPatmCentaur resb 16*4
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| 100 |
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| 101 | alignb 8
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| 102 | .cMsrWrites resq 1
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| 103 | .cMsrWritesToIgnoredBits resq 1
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| 104 | .cMsrWritesRaiseGp resq 1
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| 105 | .cMsrWritesUnknown resq 1
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| 106 | .cMsrReads resq 1
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| 107 | .cMsrReadsRaiseGp resq 1
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| 108 | .cMsrReadsUnknown resq 1
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| 109 | endstruc
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| 110 |
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| 111 | struc CPUMCPU
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| 112 | ;
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| 113 | ; Guest context state
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| 114 | ; (Identical to the .Hyper chunk below and to CPUMCTX in cpum.mac.)
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| 115 | ;
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| 116 | .Guest resq 0
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| 117 | .Guest.eax resq 1
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| 118 | .Guest.ecx resq 1
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| 119 | .Guest.edx resq 1
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| 120 | .Guest.ebx resq 1
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| 121 | .Guest.esp resq 1
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| 122 | .Guest.ebp resq 1
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| 123 | .Guest.esi resq 1
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| 124 | .Guest.edi resq 1
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| 125 | .Guest.r8 resq 1
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| 126 | .Guest.r9 resq 1
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| 127 | .Guest.r10 resq 1
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| 128 | .Guest.r11 resq 1
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| 129 | .Guest.r12 resq 1
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| 130 | .Guest.r13 resq 1
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| 131 | .Guest.r14 resq 1
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| 132 | .Guest.r15 resq 1
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| 133 | .Guest.es.Sel resw 1
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| 134 | .Guest.es.PaddingSel resw 1
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| 135 | .Guest.es.ValidSel resw 1
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| 136 | .Guest.es.fFlags resw 1
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| 137 | .Guest.es.u64Base resq 1
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| 138 | .Guest.es.u32Limit resd 1
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| 139 | .Guest.es.Attr resd 1
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| 140 | .Guest.cs.Sel resw 1
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| 141 | .Guest.cs.PaddingSel resw 1
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| 142 | .Guest.cs.ValidSel resw 1
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| 143 | .Guest.cs.fFlags resw 1
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| 144 | .Guest.cs.u64Base resq 1
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| 145 | .Guest.cs.u32Limit resd 1
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| 146 | .Guest.cs.Attr resd 1
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| 147 | .Guest.ss.Sel resw 1
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| 148 | .Guest.ss.PaddingSel resw 1
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| 149 | .Guest.ss.ValidSel resw 1
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| 150 | .Guest.ss.fFlags resw 1
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| 151 | .Guest.ss.u64Base resq 1
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| 152 | .Guest.ss.u32Limit resd 1
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| 153 | .Guest.ss.Attr resd 1
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| 154 | .Guest.ds.Sel resw 1
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| 155 | .Guest.ds.PaddingSel resw 1
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| 156 | .Guest.ds.ValidSel resw 1
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| 157 | .Guest.ds.fFlags resw 1
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| 158 | .Guest.ds.u64Base resq 1
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| 159 | .Guest.ds.u32Limit resd 1
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| 160 | .Guest.ds.Attr resd 1
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| 161 | .Guest.fs.Sel resw 1
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| 162 | .Guest.fs.PaddingSel resw 1
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| 163 | .Guest.fs.ValidSel resw 1
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| 164 | .Guest.fs.fFlags resw 1
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| 165 | .Guest.fs.u64Base resq 1
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| 166 | .Guest.fs.u32Limit resd 1
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| 167 | .Guest.fs.Attr resd 1
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| 168 | .Guest.gs.Sel resw 1
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| 169 | .Guest.gs.PaddingSel resw 1
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| 170 | .Guest.gs.ValidSel resw 1
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| 171 | .Guest.gs.fFlags resw 1
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| 172 | .Guest.gs.u64Base resq 1
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| 173 | .Guest.gs.u32Limit resd 1
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| 174 | .Guest.gs.Attr resd 1
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| 175 | .Guest.eip resq 1
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| 176 | .Guest.eflags resq 1
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| 177 | .Guest.cr0 resq 1
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| 178 | .Guest.cr2 resq 1
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| 179 | .Guest.cr3 resq 1
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| 180 | .Guest.cr4 resq 1
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| 181 | .Guest.dr resq 8
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| 182 | .Guest.gdtrPadding resw 3
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| 183 | .Guest.gdtr resw 0
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| 184 | .Guest.gdtr.cbGdt resw 1
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| 185 | .Guest.gdtr.pGdt resq 1
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| 186 | .Guest.idtrPadding resw 3
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| 187 | .Guest.idtr resw 0
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| 188 | .Guest.idtr.cbIdt resw 1
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| 189 | .Guest.idtr.pIdt resq 1
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| 190 | .Guest.ldtr.Sel resw 1
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| 191 | .Guest.ldtr.PaddingSel resw 1
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| 192 | .Guest.ldtr.ValidSel resw 1
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| 193 | .Guest.ldtr.fFlags resw 1
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| 194 | .Guest.ldtr.u64Base resq 1
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| 195 | .Guest.ldtr.u32Limit resd 1
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| 196 | .Guest.ldtr.Attr resd 1
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| 197 | .Guest.tr.Sel resw 1
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| 198 | .Guest.tr.PaddingSel resw 1
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| 199 | .Guest.tr.ValidSel resw 1
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| 200 | .Guest.tr.fFlags resw 1
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| 201 | .Guest.tr.u64Base resq 1
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| 202 | .Guest.tr.u32Limit resd 1
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| 203 | .Guest.tr.Attr resd 1
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| 204 | .Guest.SysEnter.cs resb 8
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| 205 | .Guest.SysEnter.eip resb 8
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| 206 | .Guest.SysEnter.esp resb 8
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| 207 | .Guest.msrEFER resb 8
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| 208 | .Guest.msrSTAR resb 8
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| 209 | .Guest.msrPAT resb 8
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| 210 | .Guest.msrLSTAR resb 8
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| 211 | .Guest.msrCSTAR resb 8
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| 212 | .Guest.msrSFMASK resb 8
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| 213 | .Guest.msrKERNELGSBASE resb 8
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| 214 | .Guest.uMsrPadding0 resb 8
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| 215 | alignb 8
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| 216 | .Guest.aXcr resq 2
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| 217 | .Guest.fXStateMask resq 1
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| 218 | .Guest.pXStateR0 RTR0PTR_RES 1
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| 219 | alignb 8
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| 220 | .Guest.pXStateR3 RTR3PTR_RES 1
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| 221 | alignb 8
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| 222 | .Guest.aoffXState resw 64
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| 223 | .Guest.fUsedFpuGuest resb 1
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| 224 | alignb 8
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| 225 | .Guest.fExtrn resq 1
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| 226 | alignb 8
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| 227 | .Guest.hwvirt.svm.uMsrHSavePa resq 1
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| 228 | .Guest.hwvirt.svm.GCPhysVmcb resq 1
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| 229 | .Guest.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1
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| 230 | alignb 8
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| 231 | .Guest.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1
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| 232 | alignb 8
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| 233 | .Guest.hwvirt.svm.HostState resb 184
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| 234 | .Guest.hwvirt.svm.uPrevPauseTick resq 1
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| 235 | .Guest.hwvirt.svm.cPauseFilter resw 1
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| 236 | .Guest.hwvirt.svm.cPauseFilterThreshold resw 1
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| 237 | .Guest.hwvirt.svm.fInterceptEvents resb 1
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| 238 | alignb 8
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| 239 | .Guest.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1
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| 240 | alignb 8
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| 241 | .Guest.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1
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| 242 | alignb 8
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| 243 | .Guest.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1
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| 244 | alignb 8
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| 245 | .Guest.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1
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| 246 | alignb 8
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| 247 | .Guest.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1
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| 248 | .Guest.hwvirt.svm.abPadding0 resb 272
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| 249 | .Guest.hwvirt.enmHwvirt resd 1
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| 250 | .Guest.hwvirt.fGif resb 1
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| 251 | alignb 8
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| 252 | .Guest.hwvirt.fLocalForcedActions resd 1
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| 253 | alignb 64
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| 254 |
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| 255 | .GuestMsrs resq 0
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| 256 | .GuestMsrs.au64 resq 64
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| 257 |
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| 258 | ;
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| 259 | ; Other stuff.
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| 260 | ;
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| 261 | .hNestedVmxPreemptTimer resq 1
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| 262 |
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| 263 | .fUseFlags resd 1
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| 264 | .fChanged resd 1
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| 265 | .u32RetCode resd 1
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| 266 |
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| 267 | %ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
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| 268 | .fApicDisVectors resd 1
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| 269 | .pvApicBase RTR0PTR_RES 1
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| 270 | .fX2Apic resb 1
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| 271 | %else
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| 272 | .abPadding3 resb (4 + RTR0PTR_CB + 1)
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| 273 | %endif
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| 274 |
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| 275 | .fCpuIdApicFeatureVisible resb 1
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| 276 |
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| 277 | ;
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| 278 | ; Host context state
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| 279 | ;
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| 280 | alignb 64
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| 281 | .Host resb 0
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| 282 | ;.Host.rax resq 1 - scratch
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| 283 | .Host.rbx resq 1
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| 284 | ;.Host.rcx resq 1 - scratch
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| 285 | ;.Host.rdx resq 1 - scratch
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| 286 | .Host.rdi resq 1
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| 287 | .Host.rsi resq 1
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| 288 | .Host.rbp resq 1
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| 289 | .Host.rsp resq 1
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| 290 | ;.Host.r8 resq 1 - scratch
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| 291 | ;.Host.r9 resq 1 - scratch
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| 292 | .Host.r10 resq 1
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| 293 | .Host.r11 resq 1
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| 294 | .Host.r12 resq 1
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| 295 | .Host.r13 resq 1
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| 296 | .Host.r14 resq 1
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| 297 | .Host.r15 resq 1
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| 298 | ;.Host.rip resd 1 - scratch
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| 299 | .Host.rflags resq 1
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| 300 | .Host.ss resw 1
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| 301 | .Host.ssPadding resw 1
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| 302 | .Host.gs resw 1
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| 303 | .Host.gsPadding resw 1
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| 304 | .Host.fs resw 1
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| 305 | .Host.fsPadding resw 1
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| 306 | .Host.es resw 1
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| 307 | .Host.esPadding resw 1
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| 308 | .Host.ds resw 1
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| 309 | .Host.dsPadding resw 1
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| 310 | .Host.cs resw 1
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| 311 | .Host.csPadding resw 1
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| 312 |
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| 313 | .Host.cr0Fpu:
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| 314 | .Host.cr0 resq 1
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| 315 | ;.Host.cr2 resq 1 - scratch
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| 316 | .Host.cr3 resq 1
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| 317 | .Host.cr4 resq 1
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| 318 | .Host.cr8 resq 1
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| 319 |
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| 320 | .Host.dr0 resq 1
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| 321 | .Host.dr1 resq 1
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| 322 | .Host.dr2 resq 1
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| 323 | .Host.dr3 resq 1
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| 324 | .Host.dr6 resq 1
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| 325 | .Host.dr7 resq 1
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| 326 |
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| 327 | .Host.gdtr resb 10 ; GDT limit + linear address
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| 328 | .Host.gdtrPadding resw 1
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| 329 | .Host.idtr resb 10 ; IDT limit + linear address
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| 330 | .Host.idtrPadding resw 1
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| 331 | .Host.ldtr resw 1
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| 332 | .Host.ldtrPadding resw 1
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| 333 | .Host.tr resw 1
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| 334 | .Host.trPadding resw 1
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| 335 |
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| 336 | .Host.SysEnter.cs resq 1
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| 337 | .Host.SysEnter.eip resq 1
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| 338 | .Host.SysEnter.esp resq 1
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| 339 | .Host.FSbase resq 1
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| 340 | .Host.GSbase resq 1
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| 341 | .Host.efer resq 1
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| 342 | .Host.auPadding resb 4
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| 343 | alignb RTR0PTR_CB
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| 344 | .Host.pXStateR0 RTR0PTR_RES 1
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| 345 | .Host.pXStateR3 RTR3PTR_RES 1
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| 346 | alignb 8
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| 347 | .Host.xcr0 resq 1
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| 348 | .Host.fXStateMask resq 1
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| 349 |
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| 350 | ;
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| 351 | ; Hypervisor Context.
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| 352 | ;
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| 353 | alignb 64
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| 354 | .Hyper resq 0
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| 355 | .Hyper.dr resq 8
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| 356 | .Hyper.cr3 resq 1
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| 357 | alignb 64
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| 358 |
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| 359 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 360 | .aMagic resb 56
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| 361 | .uMagic resq 1
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| 362 | %endif
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| 363 | endstruc
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| 364 |
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| 365 |
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| 366 |
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| 367 | %if 0 ; Currently not used anywhere.
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| 368 | ;;
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| 369 | ; Macro for FXSAVE/FXRSTOR leaky behaviour on AMD CPUs, see cpumR3CheckLeakyFpu().
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| 370 | ;
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| 371 | ; Cleans the FPU state, if necessary, before restoring the FPU.
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| 372 | ;
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| 373 | ; This macro ASSUMES CR0.TS is not set!
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| 374 | ;
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| 375 | ; @param xDX Pointer to CPUMCPU.
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| 376 | ; @uses xAX, EFLAGS
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| 377 | ;
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| 378 | ; Changes here should also be reflected in CPUMRCA.asm's copy!
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| 379 | ;
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| 380 | %macro CLEANFPU 0
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| 381 | test dword [xDX + CPUMCPU.fUseFlags], CPUM_USE_FFXSR_LEAKY
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| 382 | jz .nothing_to_clean
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| 383 |
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| 384 | xor eax, eax
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| 385 | fnstsw ax ; FSW -> AX.
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| 386 | test eax, RT_BIT(7) ; If FSW.ES (bit 7) is set, clear it to not cause FPU exceptions
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| 387 | ; while clearing & loading the FPU bits in 'clean_fpu' below.
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| 388 | jz .clean_fpu
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| 389 | fnclex
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| 390 |
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| 391 | .clean_fpu:
|
|---|
| 392 | ffree st7 ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs.
|
|---|
| 393 | ; for the upcoming push (load)
|
|---|
| 394 | fild dword [g_r32_Zero xWrtRIP] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
|
|---|
| 395 | .nothing_to_clean:
|
|---|
| 396 | %endmacro
|
|---|
| 397 | %endif ; Unused.
|
|---|
| 398 |
|
|---|
| 399 |
|
|---|
| 400 | ;;
|
|---|
| 401 | ; Makes sure we don't trap (#NM) accessing the FPU.
|
|---|
| 402 | ;
|
|---|
| 403 | ; In ring-0 this is a bit of work since we may have try convince the host kernel
|
|---|
| 404 | ; to do the work for us, also, we must report any CR0 changes back to HMR0VMX
|
|---|
| 405 | ; via the VINF_CPUM_HOST_CR0_MODIFIED status code.
|
|---|
| 406 | ;
|
|---|
| 407 | ; If we end up clearing CR0.TS/EM ourselves in ring-0, we'll save the original
|
|---|
| 408 | ; value in CPUMCPU.Host.cr0Fpu. If we don't, we'll store zero there. (See also
|
|---|
| 409 | ; CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET.)
|
|---|
| 410 | ;
|
|---|
| 411 | ; In raw-mode we will always have to clear TS and it will be recalculated
|
|---|
| 412 | ; elsewhere and thus needs no saving.
|
|---|
| 413 | ;
|
|---|
| 414 | ; @param %1 Register to return the return status code in.
|
|---|
| 415 | ; @param %2 Temporary scratch register.
|
|---|
| 416 | ; @param %3 Ring-0 only, register pointing to the CPUMCPU structure
|
|---|
| 417 | ; of the EMT we're on.
|
|---|
| 418 | ; @uses EFLAGS, CR0, %1, %2
|
|---|
| 419 | ;
|
|---|
| 420 | %macro CPUMRZ_TOUCH_FPU_CLEAR_CR0_FPU_TRAPS_SET_RC 3
|
|---|
| 421 | ;
|
|---|
| 422 | ; ring-0 - slightly complicated (than old raw-mode).
|
|---|
| 423 | ;
|
|---|
| 424 | xor %1, %1 ; 0 / VINF_SUCCESS. Wishing for no CR0 changes.
|
|---|
| 425 | mov [%3 + CPUMCPU.Host.cr0Fpu], %1
|
|---|
| 426 |
|
|---|
| 427 | mov %2, cr0
|
|---|
| 428 | test %2, X86_CR0_TS | X86_CR0_EM ; Make sure its safe to access the FPU state.
|
|---|
| 429 | jz %%no_cr0_change
|
|---|
| 430 |
|
|---|
| 431 | %ifdef VMM_R0_TOUCH_FPU
|
|---|
| 432 | ; Touch the state and check that the kernel updated CR0 for us.
|
|---|
| 433 | movdqa xmm0, xmm0
|
|---|
| 434 | mov %2, cr0
|
|---|
| 435 | test %2, X86_CR0_TS | X86_CR0_EM
|
|---|
| 436 | jz %%cr0_changed
|
|---|
| 437 | %endif
|
|---|
| 438 |
|
|---|
| 439 | ; Save CR0 and clear them flags ourselves.
|
|---|
| 440 | mov [%3 + CPUMCPU.Host.cr0Fpu], %2
|
|---|
| 441 | and %2, ~(X86_CR0_TS | X86_CR0_EM)
|
|---|
| 442 | mov cr0, %2
|
|---|
| 443 |
|
|---|
| 444 | %%cr0_changed:
|
|---|
| 445 | mov %1, VINF_CPUM_HOST_CR0_MODIFIED
|
|---|
| 446 | %%no_cr0_change:
|
|---|
| 447 | %endmacro
|
|---|
| 448 |
|
|---|
| 449 |
|
|---|
| 450 | ;;
|
|---|
| 451 | ; Restore CR0 if CR0.TS or CR0.EM were non-zero in the original state.
|
|---|
| 452 | ;
|
|---|
| 453 | ; @param %1 The original state to restore (or zero).
|
|---|
| 454 | ;
|
|---|
| 455 | %macro CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET 1
|
|---|
| 456 | test %1, X86_CR0_TS | X86_CR0_EM
|
|---|
| 457 | jz %%skip_cr0_restore
|
|---|
| 458 | mov cr0, %1
|
|---|
| 459 | %%skip_cr0_restore:
|
|---|
| 460 | %endmacro
|
|---|
| 461 |
|
|---|
| 462 |
|
|---|
| 463 | ;;
|
|---|
| 464 | ; Saves the host state.
|
|---|
| 465 | ;
|
|---|
| 466 | ; @uses rax, rdx
|
|---|
| 467 | ; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
|
|---|
| 468 | ; @param pXState Define for the register containing the extended state pointer.
|
|---|
| 469 | ;
|
|---|
| 470 | %macro CPUMR0_SAVE_HOST 0
|
|---|
| 471 | ;
|
|---|
| 472 | ; Load a couple of registers we'll use later in all branches.
|
|---|
| 473 | ;
|
|---|
| 474 | %ifdef IN_RING0
|
|---|
| 475 | mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
|
|---|
| 476 | %else
|
|---|
| 477 | %error "Unsupported context!"
|
|---|
| 478 | %endif
|
|---|
| 479 | mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
|
|---|
| 480 |
|
|---|
| 481 | ;
|
|---|
| 482 | ; XSAVE or FXSAVE?
|
|---|
| 483 | ;
|
|---|
| 484 | or eax, eax
|
|---|
| 485 | jz %%host_fxsave
|
|---|
| 486 |
|
|---|
| 487 | ; XSAVE
|
|---|
| 488 | mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
|
|---|
| 489 | %ifdef RT_ARCH_AMD64
|
|---|
| 490 | o64 xsave [pXState]
|
|---|
| 491 | %else
|
|---|
| 492 | xsave [pXState]
|
|---|
| 493 | %endif
|
|---|
| 494 | jmp %%host_done
|
|---|
| 495 |
|
|---|
| 496 | ; FXSAVE
|
|---|
| 497 | %%host_fxsave:
|
|---|
| 498 | %ifdef RT_ARCH_AMD64
|
|---|
| 499 | o64 fxsave [pXState] ; Use explicit REX prefix. See @bugref{6398}.
|
|---|
| 500 | %else
|
|---|
| 501 | fxsave [pXState]
|
|---|
| 502 | %endif
|
|---|
| 503 |
|
|---|
| 504 | %%host_done:
|
|---|
| 505 | %endmacro ; CPUMR0_SAVE_HOST
|
|---|
| 506 |
|
|---|
| 507 |
|
|---|
| 508 | ;;
|
|---|
| 509 | ; Loads the host state.
|
|---|
| 510 | ;
|
|---|
| 511 | ; @uses rax, rdx
|
|---|
| 512 | ; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
|
|---|
| 513 | ; @param pXState Define for the register containing the extended state pointer.
|
|---|
| 514 | ;
|
|---|
| 515 | %macro CPUMR0_LOAD_HOST 0
|
|---|
| 516 | ;
|
|---|
| 517 | ; Load a couple of registers we'll use later in all branches.
|
|---|
| 518 | ;
|
|---|
| 519 | %ifdef IN_RING0
|
|---|
| 520 | mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
|
|---|
| 521 | %else
|
|---|
| 522 | %error "Unsupported context!"
|
|---|
| 523 | %endif
|
|---|
| 524 | mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
|
|---|
| 525 |
|
|---|
| 526 | ;
|
|---|
| 527 | ; XRSTOR or FXRSTOR?
|
|---|
| 528 | ;
|
|---|
| 529 | or eax, eax
|
|---|
| 530 | jz %%host_fxrstor
|
|---|
| 531 |
|
|---|
| 532 | ; XRSTOR
|
|---|
| 533 | mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
|
|---|
| 534 | %ifdef RT_ARCH_AMD64
|
|---|
| 535 | o64 xrstor [pXState]
|
|---|
| 536 | %else
|
|---|
| 537 | xrstor [pXState]
|
|---|
| 538 | %endif
|
|---|
| 539 | jmp %%host_done
|
|---|
| 540 |
|
|---|
| 541 | ; FXRSTOR
|
|---|
| 542 | %%host_fxrstor:
|
|---|
| 543 | %ifdef RT_ARCH_AMD64
|
|---|
| 544 | o64 fxrstor [pXState] ; Use explicit REX prefix. See @bugref{6398}.
|
|---|
| 545 | %else
|
|---|
| 546 | fxrstor [pXState]
|
|---|
| 547 | %endif
|
|---|
| 548 |
|
|---|
| 549 | %%host_done:
|
|---|
| 550 | %endmacro ; CPUMR0_LOAD_HOST
|
|---|
| 551 |
|
|---|
| 552 |
|
|---|
| 553 |
|
|---|
| 554 | ;; Macro for XSAVE/FXSAVE for the guest FPU but tries to figure out whether to
|
|---|
| 555 | ; save the 32-bit FPU state or 64-bit FPU state.
|
|---|
| 556 | ;
|
|---|
| 557 | ; @param %1 Pointer to CPUMCPU.
|
|---|
| 558 | ; @param %2 Pointer to XState.
|
|---|
| 559 | ; @param %3 Force AMD64
|
|---|
| 560 | ; @param %4 The instruction to use (xsave or fxsave)
|
|---|
| 561 | ; @uses xAX, xDX, EFLAGS, 20h of stack.
|
|---|
| 562 | ;
|
|---|
| 563 | %macro SAVE_32_OR_64_FPU 4
|
|---|
| 564 | %if CPUM_IS_AMD64 || %3
|
|---|
| 565 | ; Save the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
|
|---|
| 566 | test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
|
|---|
| 567 | jnz short %%save_long_mode_guest
|
|---|
| 568 | %endif
|
|---|
| 569 | %4 [pXState]
|
|---|
| 570 | %if CPUM_IS_AMD64 || %3
|
|---|
| 571 | jmp %%save_done_32bit_cs_ds
|
|---|
| 572 |
|
|---|
| 573 | %%save_long_mode_guest:
|
|---|
| 574 | o64 %4 [pXState]
|
|---|
| 575 |
|
|---|
| 576 | xor edx, edx
|
|---|
| 577 | cmp dword [pXState + X86FXSTATE.FPUCS], 0
|
|---|
| 578 | jne short %%save_done
|
|---|
| 579 |
|
|---|
| 580 | sub rsp, 20h ; Only need 1ch bytes but keep stack aligned otherwise we #GP(0).
|
|---|
| 581 | fnstenv [rsp]
|
|---|
| 582 | movzx eax, word [rsp + 10h]
|
|---|
| 583 | mov [pXState + X86FXSTATE.FPUCS], eax
|
|---|
| 584 | movzx eax, word [rsp + 18h]
|
|---|
| 585 | add rsp, 20h
|
|---|
| 586 | mov [pXState + X86FXSTATE.FPUDS], eax
|
|---|
| 587 | %endif
|
|---|
| 588 | %%save_done_32bit_cs_ds:
|
|---|
| 589 | mov edx, X86_FXSTATE_RSVD_32BIT_MAGIC
|
|---|
| 590 | %%save_done:
|
|---|
| 591 | mov dword [pXState + X86_OFF_FXSTATE_RSVD], edx
|
|---|
| 592 | %endmacro ; SAVE_32_OR_64_FPU
|
|---|
| 593 |
|
|---|
| 594 |
|
|---|
| 595 | ;;
|
|---|
| 596 | ; Save the guest state.
|
|---|
| 597 | ;
|
|---|
| 598 | ; @uses rax, rdx
|
|---|
| 599 | ; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
|
|---|
| 600 | ; @param pXState Define for the register containing the extended state pointer.
|
|---|
| 601 | ;
|
|---|
| 602 | %macro CPUMR0_SAVE_GUEST 0
|
|---|
| 603 | ;
|
|---|
| 604 | ; Load a couple of registers we'll use later in all branches.
|
|---|
| 605 | ;
|
|---|
| 606 | %ifdef IN_RING0
|
|---|
| 607 | mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
|
|---|
| 608 | %else
|
|---|
| 609 | %error "Unsupported context!"
|
|---|
| 610 | %endif
|
|---|
| 611 | mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
|
|---|
| 612 |
|
|---|
| 613 | ;
|
|---|
| 614 | ; XSAVE or FXSAVE?
|
|---|
| 615 | ;
|
|---|
| 616 | or eax, eax
|
|---|
| 617 | jz %%guest_fxsave
|
|---|
| 618 |
|
|---|
| 619 | ; XSAVE
|
|---|
| 620 | mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
|
|---|
| 621 | %ifdef VBOX_WITH_KERNEL_USING_XMM
|
|---|
| 622 | and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Already saved in HMR0A.asm.
|
|---|
| 623 | %endif
|
|---|
| 624 | SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, xsave
|
|---|
| 625 | jmp %%guest_done
|
|---|
| 626 |
|
|---|
| 627 | ; FXSAVE
|
|---|
| 628 | %%guest_fxsave:
|
|---|
| 629 | SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, fxsave
|
|---|
| 630 |
|
|---|
| 631 | %%guest_done:
|
|---|
| 632 | %endmacro ; CPUMR0_SAVE_GUEST
|
|---|
| 633 |
|
|---|
| 634 |
|
|---|
| 635 | ;;
|
|---|
| 636 | ; Wrapper for selecting 32-bit or 64-bit XRSTOR/FXRSTOR according to what SAVE_32_OR_64_FPU did.
|
|---|
| 637 | ;
|
|---|
| 638 | ; @param %1 Pointer to CPUMCPU.
|
|---|
| 639 | ; @param %2 Pointer to XState.
|
|---|
| 640 | ; @param %3 Force AMD64.
|
|---|
| 641 | ; @param %4 The instruction to use (xrstor or fxrstor).
|
|---|
| 642 | ; @uses xAX, xDX, EFLAGS
|
|---|
| 643 | ;
|
|---|
| 644 | %macro RESTORE_32_OR_64_FPU 4
|
|---|
| 645 | %if CPUM_IS_AMD64 || %3
|
|---|
| 646 | ; Restore the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
|
|---|
| 647 | test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
|
|---|
| 648 | jz %%restore_32bit_fpu
|
|---|
| 649 | cmp dword [pXState + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
|
|---|
| 650 | jne short %%restore_64bit_fpu
|
|---|
| 651 | %%restore_32bit_fpu:
|
|---|
| 652 | %endif
|
|---|
| 653 | %4 [pXState]
|
|---|
| 654 | %if CPUM_IS_AMD64 || %3
|
|---|
| 655 | ; TODO: Restore XMM8-XMM15!
|
|---|
| 656 | jmp short %%restore_fpu_done
|
|---|
| 657 | %%restore_64bit_fpu:
|
|---|
| 658 | o64 %4 [pXState]
|
|---|
| 659 | %%restore_fpu_done:
|
|---|
| 660 | %endif
|
|---|
| 661 | %endmacro ; RESTORE_32_OR_64_FPU
|
|---|
| 662 |
|
|---|
| 663 |
|
|---|
| 664 | ;;
|
|---|
| 665 | ; Loads the guest state.
|
|---|
| 666 | ;
|
|---|
| 667 | ; @uses rax, rdx
|
|---|
| 668 | ; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
|
|---|
| 669 | ; @param pXState Define for the register containing the extended state pointer.
|
|---|
| 670 | ;
|
|---|
| 671 | %macro CPUMR0_LOAD_GUEST 0
|
|---|
| 672 | ;
|
|---|
| 673 | ; Load a couple of registers we'll use later in all branches.
|
|---|
| 674 | ;
|
|---|
| 675 | %ifdef IN_RING0
|
|---|
| 676 | mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
|
|---|
| 677 | %else
|
|---|
| 678 | %error "Unsupported context!"
|
|---|
| 679 | %endif
|
|---|
| 680 | mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
|
|---|
| 681 |
|
|---|
| 682 | ;
|
|---|
| 683 | ; XRSTOR or FXRSTOR?
|
|---|
| 684 | ;
|
|---|
| 685 | or eax, eax
|
|---|
| 686 | jz %%guest_fxrstor
|
|---|
| 687 |
|
|---|
| 688 | ; XRSTOR
|
|---|
| 689 | mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
|
|---|
| 690 | %ifdef VBOX_WITH_KERNEL_USING_XMM
|
|---|
| 691 | and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Will be loaded by HMR0A.asm.
|
|---|
| 692 | %endif
|
|---|
| 693 | RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, xrstor
|
|---|
| 694 | jmp %%guest_done
|
|---|
| 695 |
|
|---|
| 696 | ; FXRSTOR
|
|---|
| 697 | %%guest_fxrstor:
|
|---|
| 698 | RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, fxrstor
|
|---|
| 699 |
|
|---|
| 700 | %%guest_done:
|
|---|
| 701 | %endmacro ; CPUMR0_LOAD_GUEST
|
|---|
| 702 |
|
|---|
