VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.mac@ 87815

Last change on this file since 87815 was 87766, checked in by vboxsync, 4 years ago

VMM/TM,VMM/*: Refactored the TM timer APIs to use 'handles' and take a pVM parameter. Only internal callbacks have been updated with a hTimer parameter, so far. bugref:9943
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1; $Id: CPUMInternal.mac 87766 2021-02-16 14:27:43Z vboxsync $
2;; @file
3; CPUM - Internal header file (asm).
4;
5
6;
7; Copyright (C) 2006-2020 Oracle Corporation
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17
18%include "VBox/asmdefs.mac"
19%include "VBox/vmm/cpum.mac"
20
21;; Check sanity.
22%ifdef VBOX_WITH_KERNEL_USING_XMM
23 %ifndef IN_RING0
24 %error "What? We've got code assuming VBOX_WITH_KERNEL_USING_XMM is only defined in ring-0!"
25 %endif
26%endif
27
28;; For numeric expressions
29%ifdef RT_ARCH_AMD64
30 %define CPUM_IS_AMD64 1
31%else
32 %define CPUM_IS_AMD64 0
33%endif
34
35
36;;
37; CPU info
38struc CPUMINFO
39 .cMsrRanges resd 1 ; uint32_t
40 .fMsrMask resd 1 ; uint32_t
41 .fMxCsrMask resd 1 ; uint32_t
42 .cCpuIdLeaves resd 1 ; uint32_t
43 .iFirstExtCpuIdLeaf resd 1 ; uint32_t
44 .enmUnknownCpuIdMethod resd 1 ; CPUMUNKNOWNCPUID
45 .DefCpuId resb CPUMCPUID_size ; CPUMCPUID
46 .uScalableBusFreq resq 1 ; uint64_t
47 .paMsrRangesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMMSRRANGE)
48 .paCpuIdLeavesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMCPUIDLEAF)
49 .paMsrRangesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMMSRRANGE)
50 .paCpuIdLeavesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMCPUIDLEAF)
51endstruc
52
53
54%define CPUM_USED_FPU_HOST RT_BIT(0)
55%define CPUM_USED_FPU_GUEST RT_BIT(10)
56%define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
57%define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
58%define CPUM_USE_SYSENTER RT_BIT(3)
59%define CPUM_USE_SYSCALL RT_BIT(4)
60%define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
61%define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
62%define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
63%define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
64%define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
65%define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
66%define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
67
68%define CPUM_HANDLER_DS 1
69%define CPUM_HANDLER_ES 2
70%define CPUM_HANDLER_FS 3
71%define CPUM_HANDLER_GS 4
72%define CPUM_HANDLER_IRET 5
73%define CPUM_HANDLER_TYPEMASK 0ffh
74%define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
75
76
77struc CPUM
78 ;...
79 .fHostUseFlags resd 1
80
81 ; CR4 masks
82 .CR4.AndMask resd 1
83 .CR4.OrMask resd 1
84 .u8PortableCpuIdLevel resb 1
85 .fPendingRestore resb 1
86
87 alignb 8
88 .fXStateGuestMask resq 1
89 .fXStateHostMask resq 1
90
91 alignb 64
92 .HostFeatures resb 48
93 .GuestFeatures resb 48
94 .GuestInfo resb RTHCPTR_CB*4 + 4*12
95
96 ; Patch manager saved state compatability CPUID leaf arrays
97 .aGuestCpuIdPatmStd resb 16*6
98 .aGuestCpuIdPatmExt resb 16*10
99 .aGuestCpuIdPatmCentaur resb 16*4
100
101 alignb 8
102 .cMsrWrites resq 1
103 .cMsrWritesToIgnoredBits resq 1
104 .cMsrWritesRaiseGp resq 1
105 .cMsrWritesUnknown resq 1
106 .cMsrReads resq 1
107 .cMsrReadsRaiseGp resq 1
108 .cMsrReadsUnknown resq 1
109endstruc
110
111struc CPUMCPU
112 ;
113 ; Guest context state
114 ; (Identical to the .Hyper chunk below and to CPUMCTX in cpum.mac.)
115 ;
116 .Guest resq 0
117 .Guest.eax resq 1
118 .Guest.ecx resq 1
119 .Guest.edx resq 1
120 .Guest.ebx resq 1
121 .Guest.esp resq 1
122 .Guest.ebp resq 1
123 .Guest.esi resq 1
124 .Guest.edi resq 1
125 .Guest.r8 resq 1
126 .Guest.r9 resq 1
127 .Guest.r10 resq 1
128 .Guest.r11 resq 1
129 .Guest.r12 resq 1
130 .Guest.r13 resq 1
131 .Guest.r14 resq 1
132 .Guest.r15 resq 1
133 .Guest.es.Sel resw 1
134 .Guest.es.PaddingSel resw 1
135 .Guest.es.ValidSel resw 1
136 .Guest.es.fFlags resw 1
137 .Guest.es.u64Base resq 1
138 .Guest.es.u32Limit resd 1
139 .Guest.es.Attr resd 1
140 .Guest.cs.Sel resw 1
141 .Guest.cs.PaddingSel resw 1
142 .Guest.cs.ValidSel resw 1
143 .Guest.cs.fFlags resw 1
144 .Guest.cs.u64Base resq 1
145 .Guest.cs.u32Limit resd 1
146 .Guest.cs.Attr resd 1
147 .Guest.ss.Sel resw 1
148 .Guest.ss.PaddingSel resw 1
149 .Guest.ss.ValidSel resw 1
150 .Guest.ss.fFlags resw 1
151 .Guest.ss.u64Base resq 1
152 .Guest.ss.u32Limit resd 1
153 .Guest.ss.Attr resd 1
154 .Guest.ds.Sel resw 1
155 .Guest.ds.PaddingSel resw 1
156 .Guest.ds.ValidSel resw 1
157 .Guest.ds.fFlags resw 1
158 .Guest.ds.u64Base resq 1
159 .Guest.ds.u32Limit resd 1
160 .Guest.ds.Attr resd 1
161 .Guest.fs.Sel resw 1
162 .Guest.fs.PaddingSel resw 1
163 .Guest.fs.ValidSel resw 1
164 .Guest.fs.fFlags resw 1
165 .Guest.fs.u64Base resq 1
166 .Guest.fs.u32Limit resd 1
167 .Guest.fs.Attr resd 1
168 .Guest.gs.Sel resw 1
169 .Guest.gs.PaddingSel resw 1
170 .Guest.gs.ValidSel resw 1
171 .Guest.gs.fFlags resw 1
172 .Guest.gs.u64Base resq 1
173 .Guest.gs.u32Limit resd 1
174 .Guest.gs.Attr resd 1
175 .Guest.eip resq 1
176 .Guest.eflags resq 1
177 .Guest.cr0 resq 1
178 .Guest.cr2 resq 1
179 .Guest.cr3 resq 1
180 .Guest.cr4 resq 1
181 .Guest.dr resq 8
182 .Guest.gdtrPadding resw 3
183 .Guest.gdtr resw 0
184 .Guest.gdtr.cbGdt resw 1
185 .Guest.gdtr.pGdt resq 1
186 .Guest.idtrPadding resw 3
187 .Guest.idtr resw 0
188 .Guest.idtr.cbIdt resw 1
189 .Guest.idtr.pIdt resq 1
190 .Guest.ldtr.Sel resw 1
191 .Guest.ldtr.PaddingSel resw 1
192 .Guest.ldtr.ValidSel resw 1
193 .Guest.ldtr.fFlags resw 1
194 .Guest.ldtr.u64Base resq 1
195 .Guest.ldtr.u32Limit resd 1
196 .Guest.ldtr.Attr resd 1
197 .Guest.tr.Sel resw 1
198 .Guest.tr.PaddingSel resw 1
199 .Guest.tr.ValidSel resw 1
200 .Guest.tr.fFlags resw 1
201 .Guest.tr.u64Base resq 1
202 .Guest.tr.u32Limit resd 1
203 .Guest.tr.Attr resd 1
204 .Guest.SysEnter.cs resb 8
205 .Guest.SysEnter.eip resb 8
206 .Guest.SysEnter.esp resb 8
207 .Guest.msrEFER resb 8
208 .Guest.msrSTAR resb 8
209 .Guest.msrPAT resb 8
210 .Guest.msrLSTAR resb 8
211 .Guest.msrCSTAR resb 8
212 .Guest.msrSFMASK resb 8
213 .Guest.msrKERNELGSBASE resb 8
214 .Guest.uMsrPadding0 resb 8
215 alignb 8
216 .Guest.aXcr resq 2
217 .Guest.fXStateMask resq 1
218 .Guest.pXStateR0 RTR0PTR_RES 1
219 alignb 8
220 .Guest.pXStateR3 RTR3PTR_RES 1
221 alignb 8
222 .Guest.aoffXState resw 64
223 .Guest.fUsedFpuGuest resb 1
224 alignb 8
225 .Guest.fExtrn resq 1
226 alignb 8
227 .Guest.hwvirt.svm.uMsrHSavePa resq 1
228 .Guest.hwvirt.svm.GCPhysVmcb resq 1
229 .Guest.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1
230 alignb 8
231 .Guest.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1
232 alignb 8
233 .Guest.hwvirt.svm.HostState resb 184
234 .Guest.hwvirt.svm.uPrevPauseTick resq 1
235 .Guest.hwvirt.svm.cPauseFilter resw 1
236 .Guest.hwvirt.svm.cPauseFilterThreshold resw 1
237 .Guest.hwvirt.svm.fInterceptEvents resb 1
238 alignb 8
239 .Guest.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1
240 alignb 8
241 .Guest.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1
242 alignb 8
243 .Guest.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1
244 alignb 8
245 .Guest.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1
246 alignb 8
247 .Guest.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1
248 .Guest.hwvirt.svm.abPadding0 resb 272
249 .Guest.hwvirt.enmHwvirt resd 1
250 .Guest.hwvirt.fGif resb 1
251 alignb 8
252 .Guest.hwvirt.fLocalForcedActions resd 1
253 alignb 64
254
255 .GuestMsrs resq 0
256 .GuestMsrs.au64 resq 64
257
258 ;
259 ; Other stuff.
260 ;
261 .hNestedVmxPreemptTimer resq 1
262
263 .fUseFlags resd 1
264 .fChanged resd 1
265 .u32RetCode resd 1
266
267%ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
268 .fApicDisVectors resd 1
269 .pvApicBase RTR0PTR_RES 1
270 .fX2Apic resb 1
271%else
272 .abPadding3 resb (4 + RTR0PTR_CB + 1)
273%endif
274
275 .fCpuIdApicFeatureVisible resb 1
276
277 ;
278 ; Host context state
279 ;
280 alignb 64
281 .Host resb 0
282 ;.Host.rax resq 1 - scratch
283 .Host.rbx resq 1
284 ;.Host.rcx resq 1 - scratch
285 ;.Host.rdx resq 1 - scratch
286 .Host.rdi resq 1
287 .Host.rsi resq 1
288 .Host.rbp resq 1
289 .Host.rsp resq 1
290 ;.Host.r8 resq 1 - scratch
291 ;.Host.r9 resq 1 - scratch
292 .Host.r10 resq 1
293 .Host.r11 resq 1
294 .Host.r12 resq 1
295 .Host.r13 resq 1
296 .Host.r14 resq 1
297 .Host.r15 resq 1
298 ;.Host.rip resd 1 - scratch
299 .Host.rflags resq 1
300 .Host.ss resw 1
301 .Host.ssPadding resw 1
302 .Host.gs resw 1
303 .Host.gsPadding resw 1
304 .Host.fs resw 1
305 .Host.fsPadding resw 1
306 .Host.es resw 1
307 .Host.esPadding resw 1
308 .Host.ds resw 1
309 .Host.dsPadding resw 1
310 .Host.cs resw 1
311 .Host.csPadding resw 1
312
313 .Host.cr0Fpu:
314 .Host.cr0 resq 1
315 ;.Host.cr2 resq 1 - scratch
316 .Host.cr3 resq 1
317 .Host.cr4 resq 1
318 .Host.cr8 resq 1
319
320 .Host.dr0 resq 1
321 .Host.dr1 resq 1
322 .Host.dr2 resq 1
323 .Host.dr3 resq 1
324 .Host.dr6 resq 1
325 .Host.dr7 resq 1
326
327 .Host.gdtr resb 10 ; GDT limit + linear address
328 .Host.gdtrPadding resw 1
329 .Host.idtr resb 10 ; IDT limit + linear address
330 .Host.idtrPadding resw 1
331 .Host.ldtr resw 1
332 .Host.ldtrPadding resw 1
333 .Host.tr resw 1
334 .Host.trPadding resw 1
335
336 .Host.SysEnter.cs resq 1
337 .Host.SysEnter.eip resq 1
338 .Host.SysEnter.esp resq 1
339 .Host.FSbase resq 1
340 .Host.GSbase resq 1
341 .Host.efer resq 1
342 .Host.auPadding resb 4
343 alignb RTR0PTR_CB
344 .Host.pXStateR0 RTR0PTR_RES 1
345 .Host.pXStateR3 RTR3PTR_RES 1
346 alignb 8
347 .Host.xcr0 resq 1
348 .Host.fXStateMask resq 1
349
350 ;
351 ; Hypervisor Context.
352 ;
353 alignb 64
354 .Hyper resq 0
355 .Hyper.dr resq 8
356 .Hyper.cr3 resq 1
357 alignb 64
358
359%ifdef VBOX_WITH_CRASHDUMP_MAGIC
360 .aMagic resb 56
361 .uMagic resq 1
362%endif
363endstruc
364
365
366
367%if 0 ; Currently not used anywhere.
368;;
369; Macro for FXSAVE/FXRSTOR leaky behaviour on AMD CPUs, see cpumR3CheckLeakyFpu().
370;
371; Cleans the FPU state, if necessary, before restoring the FPU.
372;
373; This macro ASSUMES CR0.TS is not set!
374;
375; @param xDX Pointer to CPUMCPU.
376; @uses xAX, EFLAGS
377;
378; Changes here should also be reflected in CPUMRCA.asm's copy!
379;
380%macro CLEANFPU 0
381 test dword [xDX + CPUMCPU.fUseFlags], CPUM_USE_FFXSR_LEAKY
382 jz .nothing_to_clean
383
384 xor eax, eax
385 fnstsw ax ; FSW -> AX.
386 test eax, RT_BIT(7) ; If FSW.ES (bit 7) is set, clear it to not cause FPU exceptions
387 ; while clearing & loading the FPU bits in 'clean_fpu' below.
388 jz .clean_fpu
389 fnclex
390
391.clean_fpu:
392 ffree st7 ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs.
393 ; for the upcoming push (load)
394 fild dword [g_r32_Zero xWrtRIP] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
395.nothing_to_clean:
396%endmacro
397%endif ; Unused.
398
399
400;;
401; Makes sure we don't trap (#NM) accessing the FPU.
402;
403; In ring-0 this is a bit of work since we may have try convince the host kernel
404; to do the work for us, also, we must report any CR0 changes back to HMR0VMX
405; via the VINF_CPUM_HOST_CR0_MODIFIED status code.
406;
407; If we end up clearing CR0.TS/EM ourselves in ring-0, we'll save the original
408; value in CPUMCPU.Host.cr0Fpu. If we don't, we'll store zero there. (See also
409; CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET.)
410;
411; In raw-mode we will always have to clear TS and it will be recalculated
412; elsewhere and thus needs no saving.
413;
414; @param %1 Register to return the return status code in.
415; @param %2 Temporary scratch register.
416; @param %3 Ring-0 only, register pointing to the CPUMCPU structure
417; of the EMT we're on.
418; @uses EFLAGS, CR0, %1, %2
419;
420%macro CPUMRZ_TOUCH_FPU_CLEAR_CR0_FPU_TRAPS_SET_RC 3
421 ;
422 ; ring-0 - slightly complicated (than old raw-mode).
423 ;
424 xor %1, %1 ; 0 / VINF_SUCCESS. Wishing for no CR0 changes.
425 mov [%3 + CPUMCPU.Host.cr0Fpu], %1
426
427 mov %2, cr0
428 test %2, X86_CR0_TS | X86_CR0_EM ; Make sure its safe to access the FPU state.
429 jz %%no_cr0_change
430
431 %ifdef VMM_R0_TOUCH_FPU
432 ; Touch the state and check that the kernel updated CR0 for us.
433 movdqa xmm0, xmm0
434 mov %2, cr0
435 test %2, X86_CR0_TS | X86_CR0_EM
436 jz %%cr0_changed
437 %endif
438
439 ; Save CR0 and clear them flags ourselves.
440 mov [%3 + CPUMCPU.Host.cr0Fpu], %2
441 and %2, ~(X86_CR0_TS | X86_CR0_EM)
442 mov cr0, %2
443
444%%cr0_changed:
445 mov %1, VINF_CPUM_HOST_CR0_MODIFIED
446%%no_cr0_change:
447%endmacro
448
449
450;;
451; Restore CR0 if CR0.TS or CR0.EM were non-zero in the original state.
452;
453; @param %1 The original state to restore (or zero).
454;
455%macro CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET 1
456 test %1, X86_CR0_TS | X86_CR0_EM
457 jz %%skip_cr0_restore
458 mov cr0, %1
459%%skip_cr0_restore:
460%endmacro
461
462
463;;
464; Saves the host state.
465;
466; @uses rax, rdx
467; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
468; @param pXState Define for the register containing the extended state pointer.
469;
470%macro CPUMR0_SAVE_HOST 0
471 ;
472 ; Load a couple of registers we'll use later in all branches.
473 ;
474 %ifdef IN_RING0
475 mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
476 %else
477 %error "Unsupported context!"
478 %endif
479 mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
480
481 ;
482 ; XSAVE or FXSAVE?
483 ;
484 or eax, eax
485 jz %%host_fxsave
486
487 ; XSAVE
488 mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
489 %ifdef RT_ARCH_AMD64
490 o64 xsave [pXState]
491 %else
492 xsave [pXState]
493 %endif
494 jmp %%host_done
495
496 ; FXSAVE
497%%host_fxsave:
498 %ifdef RT_ARCH_AMD64
499 o64 fxsave [pXState] ; Use explicit REX prefix. See @bugref{6398}.
500 %else
501 fxsave [pXState]
502 %endif
503
504%%host_done:
505%endmacro ; CPUMR0_SAVE_HOST
506
507
508;;
509; Loads the host state.
510;
511; @uses rax, rdx
512; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
513; @param pXState Define for the register containing the extended state pointer.
514;
515%macro CPUMR0_LOAD_HOST 0
516 ;
517 ; Load a couple of registers we'll use later in all branches.
518 ;
519 %ifdef IN_RING0
520 mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
521 %else
522 %error "Unsupported context!"
523 %endif
524 mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
525
526 ;
527 ; XRSTOR or FXRSTOR?
528 ;
529 or eax, eax
530 jz %%host_fxrstor
531
532 ; XRSTOR
533 mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
534 %ifdef RT_ARCH_AMD64
535 o64 xrstor [pXState]
536 %else
537 xrstor [pXState]
538 %endif
539 jmp %%host_done
540
541 ; FXRSTOR
542%%host_fxrstor:
543 %ifdef RT_ARCH_AMD64
544 o64 fxrstor [pXState] ; Use explicit REX prefix. See @bugref{6398}.
545 %else
546 fxrstor [pXState]
547 %endif
548
549%%host_done:
550%endmacro ; CPUMR0_LOAD_HOST
551
552
553
554;; Macro for XSAVE/FXSAVE for the guest FPU but tries to figure out whether to
555; save the 32-bit FPU state or 64-bit FPU state.
556;
557; @param %1 Pointer to CPUMCPU.
558; @param %2 Pointer to XState.
559; @param %3 Force AMD64
560; @param %4 The instruction to use (xsave or fxsave)
561; @uses xAX, xDX, EFLAGS, 20h of stack.
562;
563%macro SAVE_32_OR_64_FPU 4
564%if CPUM_IS_AMD64 || %3
565 ; Save the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
566 test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
567 jnz short %%save_long_mode_guest
568%endif
569 %4 [pXState]
570%if CPUM_IS_AMD64 || %3
571 jmp %%save_done_32bit_cs_ds
572
573%%save_long_mode_guest:
574 o64 %4 [pXState]
575
576 xor edx, edx
577 cmp dword [pXState + X86FXSTATE.FPUCS], 0
578 jne short %%save_done
579
580 sub rsp, 20h ; Only need 1ch bytes but keep stack aligned otherwise we #GP(0).
581 fnstenv [rsp]
582 movzx eax, word [rsp + 10h]
583 mov [pXState + X86FXSTATE.FPUCS], eax
584 movzx eax, word [rsp + 18h]
585 add rsp, 20h
586 mov [pXState + X86FXSTATE.FPUDS], eax
587%endif
588%%save_done_32bit_cs_ds:
589 mov edx, X86_FXSTATE_RSVD_32BIT_MAGIC
590%%save_done:
591 mov dword [pXState + X86_OFF_FXSTATE_RSVD], edx
592%endmacro ; SAVE_32_OR_64_FPU
593
594
595;;
596; Save the guest state.
597;
598; @uses rax, rdx
599; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
600; @param pXState Define for the register containing the extended state pointer.
601;
602%macro CPUMR0_SAVE_GUEST 0
603 ;
604 ; Load a couple of registers we'll use later in all branches.
605 ;
606 %ifdef IN_RING0
607 mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
608 %else
609 %error "Unsupported context!"
610 %endif
611 mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
612
613 ;
614 ; XSAVE or FXSAVE?
615 ;
616 or eax, eax
617 jz %%guest_fxsave
618
619 ; XSAVE
620 mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
621 %ifdef VBOX_WITH_KERNEL_USING_XMM
622 and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Already saved in HMR0A.asm.
623 %endif
624 SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, xsave
625 jmp %%guest_done
626
627 ; FXSAVE
628%%guest_fxsave:
629 SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, fxsave
630
631%%guest_done:
632%endmacro ; CPUMR0_SAVE_GUEST
633
634
635;;
636; Wrapper for selecting 32-bit or 64-bit XRSTOR/FXRSTOR according to what SAVE_32_OR_64_FPU did.
637;
638; @param %1 Pointer to CPUMCPU.
639; @param %2 Pointer to XState.
640; @param %3 Force AMD64.
641; @param %4 The instruction to use (xrstor or fxrstor).
642; @uses xAX, xDX, EFLAGS
643;
644%macro RESTORE_32_OR_64_FPU 4
645%if CPUM_IS_AMD64 || %3
646 ; Restore the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
647 test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
648 jz %%restore_32bit_fpu
649 cmp dword [pXState + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
650 jne short %%restore_64bit_fpu
651%%restore_32bit_fpu:
652%endif
653 %4 [pXState]
654%if CPUM_IS_AMD64 || %3
655 ; TODO: Restore XMM8-XMM15!
656 jmp short %%restore_fpu_done
657%%restore_64bit_fpu:
658 o64 %4 [pXState]
659%%restore_fpu_done:
660%endif
661%endmacro ; RESTORE_32_OR_64_FPU
662
663
664;;
665; Loads the guest state.
666;
667; @uses rax, rdx
668; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
669; @param pXState Define for the register containing the extended state pointer.
670;
671%macro CPUMR0_LOAD_GUEST 0
672 ;
673 ; Load a couple of registers we'll use later in all branches.
674 ;
675 %ifdef IN_RING0
676 mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
677 %else
678 %error "Unsupported context!"
679 %endif
680 mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
681
682 ;
683 ; XRSTOR or FXRSTOR?
684 ;
685 or eax, eax
686 jz %%guest_fxrstor
687
688 ; XRSTOR
689 mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
690 %ifdef VBOX_WITH_KERNEL_USING_XMM
691 and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Will be loaded by HMR0A.asm.
692 %endif
693 RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, xrstor
694 jmp %%guest_done
695
696 ; FXRSTOR
697%%guest_fxrstor:
698 RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, fxrstor
699
700%%guest_done:
701%endmacro ; CPUMR0_LOAD_GUEST
702
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