VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.mac@ 47705

Last change on this file since 47705 was 47660, checked in by vboxsync, 11 years ago

VMM: Debug register handling redo. (only partly tested on AMD-V so far.)

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File size: 15.6 KB
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1; $Id: CPUMInternal.mac 47660 2013-08-12 00:37:34Z vboxsync $
2;; @file
3; CPUM - Internal header file (asm).
4;
5
6;
7; Copyright (C) 2006-2012 Oracle Corporation
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17
18%include "VBox/asmdefs.mac"
19
20
21%define CPUM_USED_FPU RT_BIT(0)
22%define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
23%define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
24%define CPUM_USE_SYSENTER RT_BIT(3)
25%define CPUM_USE_SYSCALL RT_BIT(4)
26%define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
27%define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
28%define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
29%define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
30%define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
31%define CPUM_SYNC_FPU_STATE RT_BIT(16)
32%define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
33%define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
34
35
36%define CPUM_HANDLER_DS 1
37%define CPUM_HANDLER_ES 2
38%define CPUM_HANDLER_FS 3
39%define CPUM_HANDLER_GS 4
40%define CPUM_HANDLER_IRET 5
41%define CPUM_HANDLER_TYPEMASK 0ffh
42%define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
43
44%define VMMGCRET_USED_FPU 040000000h
45
46%define FPUSTATE_SIZE 512
47
48;; if anyone figures how to do %if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) in
49; nasm please tell / fix this hack.
50%ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
51 %define fVBOX_WITH_HYBRID_32BIT_KERNEL 1
52%else
53 %define fVBOX_WITH_HYBRID_32BIT_KERNEL 0
54%endif
55
56struc CPUM
57 ;...
58 .offCPUMCPU0 resd 1
59 .fHostUseFlags resd 1
60
61 ; CPUID eax=1
62 .CPUFeatures.edx resd 1
63 .CPUFeatures.ecx resd 1
64
65 ; CPUID eax=0x80000001
66 .CPUFeaturesExt.edx resd 1
67 .CPUFeaturesExt.ecx resd 1
68
69 .enmHostCpuVendor resd 1
70 .enmGuestCpuVendor resd 1
71
72 ; CR4 masks
73 .CR4.AndMask resd 1
74 .CR4.OrMask resd 1
75 ; entered rawmode?
76 .fSyntheticCpu resb 1
77 .u8PortableCpuIdLevel resb 1
78 .fPendingRestore resb 1
79%if RTHCPTR_CB == 8
80 .abPadding resb 5
81%else
82 .abPadding resb 1
83%endif
84
85 ; CPUID leafs
86 .aGuestCpuIdStd resb 16*6
87 .aGuestCpuIdExt resb 16*10
88 .aGuestCpuIdCentaur resb 16*4
89 .aGuestCpuIdHyper resb 16*4
90 .GuestCpuIdDef resb 16
91
92%if HC_ARCH_BITS == 32
93 .abPadding2 resb 4
94%endif
95
96%ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
97 .pvApicBase RTR0PTR_RES 1
98 .fApicDisVectors resd 1
99 .abPadding3 resb 4
100%endif
101endstruc
102
103struc CPUMCPU
104 ;
105 ; Hypervisor Context.
106 ;
107 .Hyper.fpu resb 512
108 .Hyper.eax resq 1
109 .Hyper.ecx resq 1
110 .Hyper.edx resq 1
111 .Hyper.ebx resq 1
112 .Hyper.esp resq 1
113 .Hyper.ebp resq 1
114 .Hyper.esi resq 1
115 .Hyper.edi resq 1
116 .Hyper.r8 resq 1
117 .Hyper.r9 resq 1
118 .Hyper.r10 resq 1
119 .Hyper.r11 resq 1
120 .Hyper.r12 resq 1
121 .Hyper.r13 resq 1
122 .Hyper.r14 resq 1
123 .Hyper.r15 resq 1
124 .Hyper.es.Sel resw 1
125 .Hyper.es.PaddingSel resw 1
126 .Hyper.es.ValidSel resw 1
127 .Hyper.es.fFlags resw 1
128 .Hyper.es.u64Base resq 1
129 .Hyper.es.u32Limit resd 1
130 .Hyper.es.Attr resd 1
131 .Hyper.cs.Sel resw 1
132 .Hyper.cs.PaddingSel resw 1
133 .Hyper.cs.ValidSel resw 1
134 .Hyper.cs.fFlags resw 1
135 .Hyper.cs.u64Base resq 1
136 .Hyper.cs.u32Limit resd 1
137 .Hyper.cs.Attr resd 1
138 .Hyper.ss.Sel resw 1
139 .Hyper.ss.PaddingSel resw 1
140 .Hyper.ss.ValidSel resw 1
141 .Hyper.ss.fFlags resw 1
142 .Hyper.ss.u64Base resq 1
143 .Hyper.ss.u32Limit resd 1
144 .Hyper.ss.Attr resd 1
145 .Hyper.ds.Sel resw 1
146 .Hyper.ds.PaddingSel resw 1
147 .Hyper.ds.ValidSel resw 1
148 .Hyper.ds.fFlags resw 1
149 .Hyper.ds.u64Base resq 1
150 .Hyper.ds.u32Limit resd 1
151 .Hyper.ds.Attr resd 1
152 .Hyper.fs.Sel resw 1
153 .Hyper.fs.PaddingSel resw 1
154 .Hyper.fs.ValidSel resw 1
155 .Hyper.fs.fFlags resw 1
156 .Hyper.fs.u64Base resq 1
157 .Hyper.fs.u32Limit resd 1
158 .Hyper.fs.Attr resd 1
159 .Hyper.gs.Sel resw 1
160 .Hyper.gs.PaddingSel resw 1
161 .Hyper.gs.ValidSel resw 1
162 .Hyper.gs.fFlags resw 1
163 .Hyper.gs.u64Base resq 1
164 .Hyper.gs.u32Limit resd 1
165 .Hyper.gs.Attr resd 1
166 .Hyper.eip resq 1
167 .Hyper.eflags resq 1
168 .Hyper.cr0 resq 1
169 .Hyper.cr2 resq 1
170 .Hyper.cr3 resq 1
171 .Hyper.cr4 resq 1
172 .Hyper.dr resq 8
173 .Hyper.gdtrPadding resw 3
174 .Hyper.gdtr resw 0
175 .Hyper.gdtr.cbGdt resw 1
176 .Hyper.gdtr.pGdt resq 1
177 .Hyper.idtrPadding resw 3
178 .Hyper.idtr resw 0
179 .Hyper.idtr.cbIdt resw 1
180 .Hyper.idtr.pIdt resq 1
181 .Hyper.ldtr.Sel resw 1
182 .Hyper.ldtr.PaddingSel resw 1
183 .Hyper.ldtr.ValidSel resw 1
184 .Hyper.ldtr.fFlags resw 1
185 .Hyper.ldtr.u64Base resq 1
186 .Hyper.ldtr.u32Limit resd 1
187 .Hyper.ldtr.Attr resd 1
188 .Hyper.tr.Sel resw 1
189 .Hyper.tr.PaddingSel resw 1
190 .Hyper.tr.ValidSel resw 1
191 .Hyper.tr.fFlags resw 1
192 .Hyper.tr.u64Base resq 1
193 .Hyper.tr.u32Limit resd 1
194 .Hyper.tr.Attr resd 1
195 .Hyper.SysEnter.cs resb 8
196 .Hyper.SysEnter.eip resb 8
197 .Hyper.SysEnter.esp resb 8
198 .Hyper.msrEFER resb 8
199 .Hyper.msrSTAR resb 8
200 .Hyper.msrPAT resb 8
201 .Hyper.msrLSTAR resb 8
202 .Hyper.msrCSTAR resb 8
203 .Hyper.msrSFMASK resb 8
204 .Hyper.msrKERNELGSBASE resb 8
205 .Hyper.msrApicBase resb 8
206
207 ;
208 ; Host context state
209 ;
210 alignb 64
211 .Host.fpu resb FPUSTATE_SIZE
212
213%if HC_ARCH_BITS == 64 || fVBOX_WITH_HYBRID_32BIT_KERNEL
214 ;.Host.rax resq 1 - scratch
215 .Host.rbx resq 1
216 ;.Host.rcx resq 1 - scratch
217 ;.Host.rdx resq 1 - scratch
218 .Host.rdi resq 1
219 .Host.rsi resq 1
220 .Host.rbp resq 1
221 .Host.rsp resq 1
222 ;.Host.r8 resq 1 - scratch
223 ;.Host.r9 resq 1 - scratch
224 .Host.r10 resq 1
225 .Host.r11 resq 1
226 .Host.r12 resq 1
227 .Host.r13 resq 1
228 .Host.r14 resq 1
229 .Host.r15 resq 1
230 ;.Host.rip resd 1 - scratch
231 .Host.rflags resq 1
232%endif
233%if HC_ARCH_BITS == 32
234 ;.Host.eax resd 1 - scratch
235 .Host.ebx resd 1
236 ;.Host.edx resd 1 - scratch
237 ;.Host.ecx resd 1 - scratch
238 .Host.edi resd 1
239 .Host.esi resd 1
240 .Host.ebp resd 1
241 .Host.eflags resd 1
242 ;.Host.eip resd 1 - scratch
243 ; lss pair!
244 .Host.esp resd 1
245%endif
246 .Host.ss resw 1
247 .Host.ssPadding resw 1
248 .Host.gs resw 1
249 .Host.gsPadding resw 1
250 .Host.fs resw 1
251 .Host.fsPadding resw 1
252 .Host.es resw 1
253 .Host.esPadding resw 1
254 .Host.ds resw 1
255 .Host.dsPadding resw 1
256 .Host.cs resw 1
257 .Host.csPadding resw 1
258
259%if HC_ARCH_BITS == 32 && fVBOX_WITH_HYBRID_32BIT_KERNEL == 0
260 .Host.cr0 resd 1
261 ;.Host.cr2 resd 1 - scratch
262 .Host.cr3 resd 1
263 .Host.cr4 resd 1
264
265 .Host.dr0 resd 1
266 .Host.dr1 resd 1
267 .Host.dr2 resd 1
268 .Host.dr3 resd 1
269 .Host.dr6 resd 1
270 .Host.dr7 resd 1
271
272 .Host.gdtr resb 6 ; GDT limit + linear address
273 .Host.gdtrPadding resw 1
274 .Host.idtr resb 6 ; IDT limit + linear address
275 .Host.idtrPadding resw 1
276 .Host.ldtr resw 1
277 .Host.ldtrPadding resw 1
278 .Host.tr resw 1
279 .Host.trPadding resw 1
280
281 .Host.SysEnterPadding resd 1
282 .Host.SysEnter.cs resq 1
283 .Host.SysEnter.eip resq 1
284 .Host.SysEnter.esp resq 1
285 .Host.efer resq 1
286
287%else ; 64-bit
288
289 .Host.cr0 resq 1
290 ;.Host.cr2 resq 1 - scratch
291 .Host.cr3 resq 1
292 .Host.cr4 resq 1
293 .Host.cr8 resq 1
294
295 .Host.dr0 resq 1
296 .Host.dr1 resq 1
297 .Host.dr2 resq 1
298 .Host.dr3 resq 1
299 .Host.dr6 resq 1
300 .Host.dr7 resq 1
301
302 .Host.gdtr resb 10 ; GDT limit + linear address
303 .Host.gdtrPadding resw 1
304 .Host.idtr resb 10 ; IDT limit + linear address
305 .Host.idtrPadding resw 1
306 .Host.ldtr resw 1
307 .Host.ldtrPadding resw 1
308 .Host.tr resw 1
309 .Host.trPadding resw 1
310
311 .Host.SysEnter.cs resq 1
312 .Host.SysEnter.eip resq 1
313 .Host.SysEnter.esp resq 1
314 .Host.FSbase resq 1
315 .Host.GSbase resq 1
316 .Host.efer resq 1
317%endif ; 64-bit
318
319%ifdef VBOX_WITH_CRASHDUMP_MAGIC
320 .aMagic resb 56
321 .uMagic resq 1
322%endif
323 ;
324 ; Guest context state
325 ; (Identical to the .Hyper chunk above.)
326 ;
327 alignb 64
328 .Guest.fpu resb 512
329 .Guest.eax resq 1
330 .Guest.ecx resq 1
331 .Guest.edx resq 1
332 .Guest.ebx resq 1
333 .Guest.esp resq 1
334 .Guest.ebp resq 1
335 .Guest.esi resq 1
336 .Guest.edi resq 1
337 .Guest.r8 resq 1
338 .Guest.r9 resq 1
339 .Guest.r10 resq 1
340 .Guest.r11 resq 1
341 .Guest.r12 resq 1
342 .Guest.r13 resq 1
343 .Guest.r14 resq 1
344 .Guest.r15 resq 1
345 .Guest.es.Sel resw 1
346 .Guest.es.PaddingSel resw 1
347 .Guest.es.ValidSel resw 1
348 .Guest.es.fFlags resw 1
349 .Guest.es.u64Base resq 1
350 .Guest.es.u32Limit resd 1
351 .Guest.es.Attr resd 1
352 .Guest.cs.Sel resw 1
353 .Guest.cs.PaddingSel resw 1
354 .Guest.cs.ValidSel resw 1
355 .Guest.cs.fFlags resw 1
356 .Guest.cs.u64Base resq 1
357 .Guest.cs.u32Limit resd 1
358 .Guest.cs.Attr resd 1
359 .Guest.ss.Sel resw 1
360 .Guest.ss.PaddingSel resw 1
361 .Guest.ss.ValidSel resw 1
362 .Guest.ss.fFlags resw 1
363 .Guest.ss.u64Base resq 1
364 .Guest.ss.u32Limit resd 1
365 .Guest.ss.Attr resd 1
366 .Guest.ds.Sel resw 1
367 .Guest.ds.PaddingSel resw 1
368 .Guest.ds.ValidSel resw 1
369 .Guest.ds.fFlags resw 1
370 .Guest.ds.u64Base resq 1
371 .Guest.ds.u32Limit resd 1
372 .Guest.ds.Attr resd 1
373 .Guest.fs.Sel resw 1
374 .Guest.fs.PaddingSel resw 1
375 .Guest.fs.ValidSel resw 1
376 .Guest.fs.fFlags resw 1
377 .Guest.fs.u64Base resq 1
378 .Guest.fs.u32Limit resd 1
379 .Guest.fs.Attr resd 1
380 .Guest.gs.Sel resw 1
381 .Guest.gs.PaddingSel resw 1
382 .Guest.gs.ValidSel resw 1
383 .Guest.gs.fFlags resw 1
384 .Guest.gs.u64Base resq 1
385 .Guest.gs.u32Limit resd 1
386 .Guest.gs.Attr resd 1
387 .Guest.eip resq 1
388 .Guest.eflags resq 1
389 .Guest.cr0 resq 1
390 .Guest.cr2 resq 1
391 .Guest.cr3 resq 1
392 .Guest.cr4 resq 1
393 .Guest.dr resq 8
394 .Guest.gdtrPadding resw 3
395 .Guest.gdtr resw 0
396 .Guest.gdtr.cbGdt resw 1
397 .Guest.gdtr.pGdt resq 1
398 .Guest.idtrPadding resw 3
399 .Guest.idtr resw 0
400 .Guest.idtr.cbIdt resw 1
401 .Guest.idtr.pIdt resq 1
402 .Guest.ldtr.Sel resw 1
403 .Guest.ldtr.PaddingSel resw 1
404 .Guest.ldtr.ValidSel resw 1
405 .Guest.ldtr.fFlags resw 1
406 .Guest.ldtr.u64Base resq 1
407 .Guest.ldtr.u32Limit resd 1
408 .Guest.ldtr.Attr resd 1
409 .Guest.tr.Sel resw 1
410 .Guest.tr.PaddingSel resw 1
411 .Guest.tr.ValidSel resw 1
412 .Guest.tr.fFlags resw 1
413 .Guest.tr.u64Base resq 1
414 .Guest.tr.u32Limit resd 1
415 .Guest.tr.Attr resd 1
416 .Guest.SysEnter.cs resb 8
417 .Guest.SysEnter.eip resb 8
418 .Guest.SysEnter.esp resb 8
419 .Guest.msrEFER resb 8
420 .Guest.msrSTAR resb 8
421 .Guest.msrPAT resb 8
422 .Guest.msrLSTAR resb 8
423 .Guest.msrCSTAR resb 8
424 .Guest.msrSFMASK resb 8
425 .Guest.msrKERNELGSBASE resb 8
426 .Guest.msrApicBase resb 8
427
428
429 alignb 64
430 .GuestMsrs.au64 resq 64
431
432 ;
433 ; Other stuff.
434 ;
435 .fUseFlags resd 1
436 .fChanged resd 1
437 .offCPUM resd 1
438 .u32RetCode resd 1
439 .fRawEntered resb 1
440 .fRemEntered resb 1
441 .abPadding2 resb (64 - 16 - 2)
442endstruc
443
444
445;;
446; Converts the CPUM pointer to CPUMCPU
447; @param %1 register name
448%macro CPUMCPU_FROM_CPUM 1
449 add %1, dword [%1 + CPUM.offCPUMCPU0]
450%endmacro
451
452;;
453; Converts the CPUM pointer to CPUMCPU
454; @param %1 register name (PVM)
455; @param %2 register name (CPUMCPU offset)
456%macro CPUMCPU_FROM_CPUM_WITH_OFFSET 2
457 add %1, %2
458%endmacro
459
460;;
461; Converts the CPUMCPU pointer to CPUM
462; @param %1 register name
463%macro CPUM_FROM_CPUMCPU 1
464 sub %1, dword [%1 + CPUMCPU.offCPUM]
465%endmacro
466
467;;
468; Converts the CPUMCPU pointer to CPUM
469; @param %1 register name (PVM)
470; @param %2 register name (CPUMCPU offset)
471%macro CPUM_FROM_CPUMCPU_WITH_OFFSET 2
472 sub %1, %2
473%endmacro
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