CPUMInternal.h@ 98122

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1	/* $Id: CPUMInternal.h 98103 2023-01-17 14:15:46Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
29	#define VMM_INCLUDED_SRC_include_CPUMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef VBOX_FOR_DTRACE_LIB
35	# include <VBox/cdefs.h>
36	# include <VBox/types.h>
37	# include <VBox/vmm/stam.h>
38	# include <iprt/x86.h>
39	# include <VBox/vmm/pgm.h>
40	#else
41	# pragma D depends_on library x86.d
42	# pragma D depends_on library cpumctx.d
43	# pragma D depends_on library cpum.d
44
45	/* Some fudging. */
46	typedef uint64_t STAMCOUNTER;
47	#endif
48
49
50
51
52	/** @defgroup grp_cpum_int Internals
53	* @ingroup grp_cpum
54	* @internal
55	* @{
56	*/
57
58	/** Use flags (CPUM::fUseFlags).
59	* (Don't forget to sync this with CPUMInternal.mac !)
60	* @note Was part of saved state (6.1 and earlier).
61	* @{ */
62	/** Indicates that we've saved the host FPU, SSE, whatever state and that it
63	* needs to be restored. */
64	#define CPUM_USED_FPU_HOST RT_BIT(0)
65	/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
66	* needs to be saved.
67	* @note Mirrored in CPUMCTX::fUsedFpuGuest for the HM switcher code. */
68	#define CPUM_USED_FPU_GUEST RT_BIT(10)
69	/** Used the guest FPU, SSE or such stuff since last we were in REM.
70	* REM syncing is clearing this, lazy FPU is setting it. */
71	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
72	/** The XMM state was manually restored. (AMD only) */
73	#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
74
75	/** Host OS is using SYSENTER and we must NULL the CS. */
76	#define CPUM_USE_SYSENTER RT_BIT(3)
77	/** Host OS is using SYSENTER and we must NULL the CS. */
78	#define CPUM_USE_SYSCALL RT_BIT(4)
79
80	/** Debug registers are used by host and that DR7 and DR6 must be saved and
81	* disabled when switching to raw-mode. */
82	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
83	/** Records that we've saved the host DRx registers.
84	* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
85	* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
86	#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
87	/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
88	* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
89	#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
90	/** Used in ring-0 to indicate that we have loaded the hypervisor debug
91	* registers. */
92	#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
93	/** Used in ring-0 to indicate that we have loaded the guest debug
94	* registers (DR0-3 and maybe DR6) for direct use by the guest.
95	* DR7 (and AMD-V DR6) are handled via the VMCB. */
96	#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
97
98	/** Host CPU requires fxsave/fxrstor leaky bit handling. */
99	#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
100	/** Set if the VM supports long-mode. */
101	#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
102	/** @} */
103
104
105	/** @name CPUM Saved State Version.
106	* @{ */
107	/** The current saved state version. */
108	#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3
109	/** The saved state version with more virtual VMCS fields (HLAT prefix size,
110	* PCONFIG-exiting bitmap, HLAT ptr, VM-exit ctls2) and a CPUMCTX field (VM-exit
111	* ctls2 MSR). */
112	#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3 22
113	/** The saved state version with PAE PDPEs added. */
114	#define CPUM_SAVED_STATE_VERSION_PAE_PDPES 21
115	/** The saved state version with more virtual VMCS fields and CPUMCTX VMX fields. */
116	#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2 20
117	/** The saved state version including VMX hardware virtualization state. */
118	#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX 19
119	/** The saved state version including SVM hardware virtualization state. */
120	#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
121	/** The saved state version including XSAVE state. */
122	#define CPUM_SAVED_STATE_VERSION_XSAVE 17
123	/** The saved state version with good CPUID leaf count. */
124	#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
125	/** CPUID changes with explode forgetting to update the leaf count on
126	* restore, resulting in garbage being saved restoring+saving old states). */
127	#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
128	/** The saved state version before the CPUIDs changes. */
129	#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
130	/** The saved state version before using SSMR3PutStruct. */
131	#define CPUM_SAVED_STATE_VERSION_MEM 13
132	/** The saved state version before introducing the MSR size field. */
133	#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
134	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
135	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
136	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
137	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
138	* changes. */
139	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
140	/** The saved state version for the 2.1 trunk before the MSR changes. */
141	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
142	/** The saved state version of 2.0, used for backwards compatibility. */
143	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
144	/** The saved state version of 1.6, used for backwards compatibility. */
145	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
146	/** @} */
147
148
149	/** @name XSAVE limits.
150	* @{ */
151	/** Max size we accept for the XSAVE area.
152	* @see CPUMCTX::abXSave */
153	#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
154	/* Min size we accept for the XSAVE area. */
155	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
156	/** @} */
157
158
159	/**
160	* CPU info
161	*/
162	typedef struct CPUMINFO
163	{
164	/** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
165	uint32_t cMsrRanges;
166	/** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
167	* instruction. Older hardware has been observed to ignore higher bits. */
168	uint32_t fMsrMask;
169
170	/** MXCSR mask. */
171	uint32_t fMxCsrMask;
172
173	/** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
174	uint32_t cCpuIdLeaves;
175	/** The index of the first extended CPUID leaf in the array.
176	* Set to cCpuIdLeaves if none present. */
177	uint32_t iFirstExtCpuIdLeaf;
178	/** How to handle unknown CPUID leaves. */
179	CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
180	/** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
181	* CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
182	CPUMCPUID DefCpuId;
183
184	/** Scalable bus frequency used for reporting other frequencies. */
185	uint64_t uScalableBusFreq;
186
187	/** Pointer to the MSR ranges (for compatibility with old hyper heap code). */
188	R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
189	/** Pointer to the CPUID leaves (for compatibility with old hyper heap code). */
190	R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
191
192	/** CPUID leaves. */
193	CPUMCPUIDLEAF aCpuIdLeaves[256];
194	/** MSR ranges.
195	* @todo This is insane, so might want to move this into a separate
196	* allocation. The insanity is mainly for more recent AMD CPUs. */
197	CPUMMSRRANGE aMsrRanges[8192];
198	} CPUMINFO;
199	/** Pointer to a CPU info structure. */
200	typedef CPUMINFO *PCPUMINFO;
201	/** Pointer to a const CPU info structure. */
202	typedef CPUMINFO const *CPCPUMINFO;
203
204
205	/**
206	* The saved host CPU state.
207	*/
208	typedef struct CPUMHOSTCTX
209	{
210	/** The extended state (FPU/SSE/AVX/AVX-2/XXXX). Must be aligned on 64 bytes. */
211	union /* no tag */
212	{
213	X86XSAVEAREA XState;
214	/** Byte view for simple indexing and space allocation.
215	* @note Must match or exceed the size of CPUMCTX::abXState. */
216	uint8_t abXState[0x4000 - 0x300];
217	} CPUM_UNION_NM(u);
218
219	/** General purpose register, selectors, flags and more
220	* @{ */
221	/** General purpose register ++
222	* { */
223	/uint64_t rax; - scratch/
224	uint64_t rbx;
225	/uint64_t rcx; - scratch/
226	/uint64_t rdx; - scratch/
227	uint64_t rdi;
228	uint64_t rsi;
229	uint64_t rbp;
230	uint64_t rsp;
231	/uint64_t r8; - scratch/
232	/uint64_t r9; - scratch/
233	uint64_t r10;
234	uint64_t r11;
235	uint64_t r12;
236	uint64_t r13;
237	uint64_t r14;
238	uint64_t r15;
239	/uint64_t rip; - scratch/
240	uint64_t rflags;
241	/** @} */
242
243	/** Selector registers
244	* @{ */
245	RTSEL ss;
246	RTSEL ssPadding;
247	RTSEL gs;
248	RTSEL gsPadding;
249	RTSEL fs;
250	RTSEL fsPadding;
251	RTSEL es;
252	RTSEL esPadding;
253	RTSEL ds;
254	RTSEL dsPadding;
255	RTSEL cs;
256	RTSEL csPadding;
257	/** @} */
258
259	/** Control registers.
260	* @{ */
261	/** The CR0 FPU state in HM mode. */
262	uint64_t cr0;
263	/uint64_t cr2; - scratch/
264	uint64_t cr3;
265	uint64_t cr4;
266	uint64_t cr8;
267	/** @} */
268
269	/** Debug registers.
270	* @{ */
271	uint64_t dr0;
272	uint64_t dr1;
273	uint64_t dr2;
274	uint64_t dr3;
275	uint64_t dr6;
276	uint64_t dr7;
277	/** @} */
278
279	/** Global Descriptor Table register. */
280	X86XDTR64 gdtr;
281	uint16_t gdtrPadding;
282	/** Interrupt Descriptor Table register. */
283	X86XDTR64 idtr;
284	uint16_t idtrPadding;
285	/** The task register. */
286	RTSEL ldtr;
287	RTSEL ldtrPadding;
288	/** The task register. */
289	RTSEL tr;
290	RTSEL trPadding;
291
292	/** MSRs
293	* @{ */
294	CPUMSYSENTER SysEnter;
295	uint64_t FSbase;
296	uint64_t GSbase;
297	uint64_t efer;
298	/** @} */
299
300	/** The XCR0 register. */
301	uint64_t xcr0;
302	/** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
303	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
304	uint64_t fXStateMask;
305
306	/* padding to get 64byte aligned size */
307	uint8_t auPadding[24];
308	#if HC_ARCH_BITS != 64
309	# error HC_ARCH_BITS not defined or unsupported
310	#endif
311	} CPUMHOSTCTX;
312	#ifndef VBOX_FOR_DTRACE_LIB
313	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
314	#endif
315	/** Pointer to the saved host CPU state. */
316	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
317
318
319	/**
320	* The hypervisor context CPU state (just DRx left now).
321	*/
322	typedef struct CPUMHYPERCTX
323	{
324	/** Debug registers.
325	* @remarks DR4 and DR5 should not be used since they are aliases for
326	* DR6 and DR7 respectively on both AMD and Intel CPUs.
327	* @remarks DR8-15 are currently not supported by AMD or Intel, so
328	* neither do we.
329	*/
330	uint64_t dr[8];
331	/** @todo eliminiate the rest. */
332	uint64_t cr3;
333	uint64_t au64Padding[7];
334	} CPUMHYPERCTX;
335	#ifndef VBOX_FOR_DTRACE_LIB
336	AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
337	#endif
338	/** Pointer to the hypervisor context CPU state. */
339	typedef CPUMHYPERCTX *PCPUMHYPERCTX;
340
341
342	/**
343	* CPUM Data (part of VM)
344	*/
345	typedef struct CPUM
346	{
347	/** Use flags.
348	* These flags indicates which CPU features the host uses.
349	*/
350	uint32_t fHostUseFlags;
351
352	/** CR4 mask
353	* @todo obsolete? */
354	struct
355	{
356	uint32_t AndMask; /*< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! /
357	uint32_t OrMask;
358	} CR4;
359
360	/** The (more) portable CPUID level. */
361	uint8_t u8PortableCpuIdLevel;
362	/** Indicates that a state restore is pending.
363	* This is used to verify load order dependencies (PGM). */
364	bool fPendingRestore;
365	uint8_t abPadding0[2];
366
367	/** XSAVE/XRTOR components we can expose to the guest mask. */
368	uint64_t fXStateGuestMask;
369	/** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
370	* to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
371	uint64_t fXStateHostMask;
372
373	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
374	/** The host MXCSR mask (determined at init). */
375	uint32_t fHostMxCsrMask;
376	#else
377	uint32_t u32UnusedOnNonX86;
378	#endif
379	uint8_t abPadding1[4];
380
381	/** Random value we store in the reserved RFLAGS bits we don't use ourselves so
382	* we can detect corruption. */
383	uint64_t fReservedRFlagsCookie;
384
385	/** Align to 64-byte boundary. */
386	uint8_t abPadding2[16];
387
388	/** Host CPU feature information.
389	* Externaly visible via the VM structure, aligned on 64-byte boundrary. */
390	CPUMFEATURES HostFeatures;
391	/** Guest CPU feature information.
392	* Externaly visible via that VM structure, aligned with HostFeatures. */
393	CPUMFEATURES GuestFeatures;
394	/** Guest CPU info. */
395	CPUMINFO GuestInfo;
396
397	/** The standard set of CpuId leaves. */
398	CPUMCPUID aGuestCpuIdPatmStd[6];
399	/** The extended set of CpuId leaves. */
400	CPUMCPUID aGuestCpuIdPatmExt[10];
401	/** The centaur set of CpuId leaves. */
402	CPUMCPUID aGuestCpuIdPatmCentaur[4];
403
404	/** @name MSR statistics.
405	* @{ */
406	STAMCOUNTER cMsrWrites;
407	STAMCOUNTER cMsrWritesToIgnoredBits;
408	STAMCOUNTER cMsrWritesRaiseGp;
409	STAMCOUNTER cMsrWritesUnknown;
410	STAMCOUNTER cMsrReads;
411	STAMCOUNTER cMsrReadsRaiseGp;
412	STAMCOUNTER cMsrReadsUnknown;
413	/** @} */
414	} CPUM;
415	#ifndef VBOX_FOR_DTRACE_LIB
416	AssertCompileMemberOffset(CPUM, HostFeatures, 64);
417	AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
418	#endif
419	/** Pointer to the CPUM instance data residing in the shared VM structure. */
420	typedef CPUM *PCPUM;
421
422	/**
423	* CPUM Data (part of VMCPU)
424	*/
425	typedef struct CPUMCPU
426	{
427	/** Guest context.
428	* Aligned on a 64-byte boundary. */
429	CPUMCTX Guest;
430	/** Guest context - misc MSRs
431	* Aligned on a 64-byte boundary. */
432	CPUMCTXMSRS GuestMsrs;
433
434	/** Nested VMX: VMX-preemption timer. */
435	TMTIMERHANDLE hNestedVmxPreemptTimer;
436
437	/** Use flags.
438	* These flags indicates both what is to be used and what has been used. */
439	uint32_t fUseFlags;
440
441	/** Changed flags.
442	* These flags indicates to REM (and others) which important guest
443	* registers which has been changed since last time the flags were cleared.
444	* See the CPUM_CHANGED_* defines for what we keep track of.
445	*
446	* @todo Obsolete, but will probably be refactored so keep it for reference. */
447	uint32_t fChanged;
448
449	/** Temporary storage for the return code of the function called in the
450	* 32-64 switcher. */
451	uint32_t u32RetCode;
452
453	/** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
454	* (?) bits are visible or not. (The APIC is responsible for setting this
455	* when loading state, so we won't save it.) */
456	bool fCpuIdApicFeatureVisible;
457
458	/** Align the next member on a 64-byte boundary. */
459	uint8_t abPadding2[64 - 8 - 4*3 - 1];
460
461	/** Saved host context. Only valid while inside RC or HM contexts.
462	* Must be aligned on a 64-byte boundary. */
463	CPUMHOSTCTX Host;
464	/** Old hypervisor context, only used for combined DRx values now.
465	* Must be aligned on a 64-byte boundary. */
466	CPUMHYPERCTX Hyper;
467
468	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
469	uint8_t aMagic[56];
470	uint64_t uMagic;
471	#endif
472	} CPUMCPU;
473	#ifndef VBOX_FOR_DTRACE_LIB
474	AssertCompileMemberAlignment(CPUMCPU, Host, 64);
475	#endif
476	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
477	typedef CPUMCPU *PCPUMCPU;
478
479	#ifndef VBOX_FOR_DTRACE_LIB
480	RT_C_DECLS_BEGIN
481
482	PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
483	PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
484	PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
485	PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves);
486	# ifdef VBOX_STRICT
487	void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves);
488	# endif
489	int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs,
490	PCPUMFEATURES pFeatures);
491
492	# ifdef IN_RING3
493	int cpumR3DbgInit(PVM pVM);
494	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
495	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCVMXMSRS pHostVmxMsrs,
496	PVMXMSRS pGuestVmxMsrs);
497	void cpumR3CpuIdRing3InitDone(PVM pVM);
498	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
499	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
500	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
501	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
502
503	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
504	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange);
505	int cpumR3MsrReconcileWithCpuId(PVM pVM);
506	int cpumR3MsrApplyFudge(PVM pVM);
507	int cpumR3MsrRegStats(PVM pVM);
508	int cpumR3MsrStrictInitChecks(void);
509	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
510	# endif
511
512	# ifdef IN_RC
513	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
514	# endif
515
516	# ifdef IN_RING0
517	DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
518	DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
519	# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
520	DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
521	# endif
522	# endif
523
524	# if defined(IN_RC) \|\| defined(IN_RING0)
525	DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
526	DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
527	DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
528	DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
529	# endif
530
531	RT_C_DECLS_END
532	#endif /* !VBOX_FOR_DTRACE_LIB */
533
534	/** @} */
535
536	#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
537

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