CPUMInternal.h@ 97213

Last change on this file since 97213 was 97213, checked in by vboxsync, 2 years ago
VMM,VBox/types.h: Removed the CPUMCTXCORE type.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 19.1 KB

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1	/* $Id: CPUMInternal.h 97213 2022-10-18 15:00:16Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
29	#define VMM_INCLUDED_SRC_include_CPUMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef VBOX_FOR_DTRACE_LIB
35	# include <VBox/cdefs.h>
36	# include <VBox/types.h>
37	# include <VBox/vmm/stam.h>
38	# include <iprt/x86.h>
39	# include <VBox/vmm/pgm.h>
40	#else
41	# pragma D depends_on library x86.d
42	# pragma D depends_on library cpumctx.d
43	# pragma D depends_on library cpum.d
44
45	/* Some fudging. */
46	typedef uint64_t STAMCOUNTER;
47	#endif
48
49
50
51
52	/** @defgroup grp_cpum_int Internals
53	* @ingroup grp_cpum
54	* @internal
55	* @{
56	*/
57
58	/** Use flags (CPUM::fUseFlags).
59	* (Don't forget to sync this with CPUMInternal.mac !)
60	* @note Was part of saved state (6.1 and earlier).
61	* @{ */
62	/** Indicates that we've saved the host FPU, SSE, whatever state and that it
63	* needs to be restored. */
64	#define CPUM_USED_FPU_HOST RT_BIT(0)
65	/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
66	* needs to be saved.
67	* @note Mirrored in CPUMCTX::fUsedFpuGuest for the HM switcher code. */
68	#define CPUM_USED_FPU_GUEST RT_BIT(10)
69	/** Used the guest FPU, SSE or such stuff since last we were in REM.
70	* REM syncing is clearing this, lazy FPU is setting it. */
71	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
72	/** The XMM state was manually restored. (AMD only) */
73	#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
74
75	/** Host OS is using SYSENTER and we must NULL the CS. */
76	#define CPUM_USE_SYSENTER RT_BIT(3)
77	/** Host OS is using SYSENTER and we must NULL the CS. */
78	#define CPUM_USE_SYSCALL RT_BIT(4)
79
80	/** Debug registers are used by host and that DR7 and DR6 must be saved and
81	* disabled when switching to raw-mode. */
82	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
83	/** Records that we've saved the host DRx registers.
84	* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
85	* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
86	#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
87	/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
88	* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
89	#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
90	/** Used in ring-0 to indicate that we have loaded the hypervisor debug
91	* registers. */
92	#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
93	/** Used in ring-0 to indicate that we have loaded the guest debug
94	* registers (DR0-3 and maybe DR6) for direct use by the guest.
95	* DR7 (and AMD-V DR6) are handled via the VMCB. */
96	#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
97
98	/** Host CPU requires fxsave/fxrstor leaky bit handling. */
99	#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
100	/** Set if the VM supports long-mode. */
101	#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
102	/** @} */
103
104
105	/** @name CPUM Saved State Version.
106	* @{ */
107	/** The current saved state version. */
108	#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_PAE_PDPES
109	/** The saved state version with PAE PDPEs added. */
110	#define CPUM_SAVED_STATE_VERSION_PAE_PDPES 21
111	/** The saved state version with more virtual VMCS fields and CPUMCTX VMX fields. */
112	#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2 20
113	/** The saved state version including VMX hardware virtualization state. */
114	#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX 19
115	/** The saved state version including SVM hardware virtualization state. */
116	#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
117	/** The saved state version including XSAVE state. */
118	#define CPUM_SAVED_STATE_VERSION_XSAVE 17
119	/** The saved state version with good CPUID leaf count. */
120	#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
121	/** CPUID changes with explode forgetting to update the leaf count on
122	* restore, resulting in garbage being saved restoring+saving old states). */
123	#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
124	/** The saved state version before the CPUIDs changes. */
125	#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
126	/** The saved state version before using SSMR3PutStruct. */
127	#define CPUM_SAVED_STATE_VERSION_MEM 13
128	/** The saved state version before introducing the MSR size field. */
129	#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
130	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
131	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
132	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
133	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
134	* changes. */
135	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
136	/** The saved state version for the 2.1 trunk before the MSR changes. */
137	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
138	/** The saved state version of 2.0, used for backwards compatibility. */
139	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
140	/** The saved state version of 1.6, used for backwards compatibility. */
141	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
142	/** @} */
143
144
145	/** @name XSAVE limits.
146	* @{ */
147	/** Max size we accept for the XSAVE area.
148	* @see CPUMCTX::abXSave */
149	#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
150	/* Min size we accept for the XSAVE area. */
151	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
152	/** @} */
153
154
155	/**
156	* CPU info
157	*/
158	typedef struct CPUMINFO
159	{
160	/** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
161	uint32_t cMsrRanges;
162	/** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
163	* instruction. Older hardware has been observed to ignore higher bits. */
164	uint32_t fMsrMask;
165
166	/** MXCSR mask. */
167	uint32_t fMxCsrMask;
168
169	/** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
170	uint32_t cCpuIdLeaves;
171	/** The index of the first extended CPUID leaf in the array.
172	* Set to cCpuIdLeaves if none present. */
173	uint32_t iFirstExtCpuIdLeaf;
174	/** How to handle unknown CPUID leaves. */
175	CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
176	/** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
177	* CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
178	CPUMCPUID DefCpuId;
179
180	/** Scalable bus frequency used for reporting other frequencies. */
181	uint64_t uScalableBusFreq;
182
183	/** Pointer to the MSR ranges (for compatibility with old hyper heap code). */
184	R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
185	/** Pointer to the CPUID leaves (for compatibility with old hyper heap code). */
186	R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
187
188	/** CPUID leaves. */
189	CPUMCPUIDLEAF aCpuIdLeaves[256];
190	/** MSR ranges.
191	* @todo This is insane, so might want to move this into a separate
192	* allocation. The insanity is mainly for more recent AMD CPUs. */
193	CPUMMSRRANGE aMsrRanges[8192];
194	} CPUMINFO;
195	/** Pointer to a CPU info structure. */
196	typedef CPUMINFO *PCPUMINFO;
197	/** Pointer to a const CPU info structure. */
198	typedef CPUMINFO const *CPCPUMINFO;
199
200
201	/**
202	* The saved host CPU state.
203	*/
204	typedef struct CPUMHOSTCTX
205	{
206	/** The extended state (FPU/SSE/AVX/AVX-2/XXXX). Must be aligned on 64 bytes. */
207	union /* no tag */
208	{
209	X86XSAVEAREA XState;
210	/** Byte view for simple indexing and space allocation.
211	* @note Must match or exceed the size of CPUMCTX::abXState. */
212	uint8_t abXState[0x4000 - 0x300];
213	} CPUM_UNION_NM(u);
214
215	/** General purpose register, selectors, flags and more
216	* @{ */
217	/** General purpose register ++
218	* { */
219	/uint64_t rax; - scratch/
220	uint64_t rbx;
221	/uint64_t rcx; - scratch/
222	/uint64_t rdx; - scratch/
223	uint64_t rdi;
224	uint64_t rsi;
225	uint64_t rbp;
226	uint64_t rsp;
227	/uint64_t r8; - scratch/
228	/uint64_t r9; - scratch/
229	uint64_t r10;
230	uint64_t r11;
231	uint64_t r12;
232	uint64_t r13;
233	uint64_t r14;
234	uint64_t r15;
235	/uint64_t rip; - scratch/
236	uint64_t rflags;
237	/** @} */
238
239	/** Selector registers
240	* @{ */
241	RTSEL ss;
242	RTSEL ssPadding;
243	RTSEL gs;
244	RTSEL gsPadding;
245	RTSEL fs;
246	RTSEL fsPadding;
247	RTSEL es;
248	RTSEL esPadding;
249	RTSEL ds;
250	RTSEL dsPadding;
251	RTSEL cs;
252	RTSEL csPadding;
253	/** @} */
254
255	/** Control registers.
256	* @{ */
257	/** The CR0 FPU state in HM mode. */
258	uint64_t cr0;
259	/uint64_t cr2; - scratch/
260	uint64_t cr3;
261	uint64_t cr4;
262	uint64_t cr8;
263	/** @} */
264
265	/** Debug registers.
266	* @{ */
267	uint64_t dr0;
268	uint64_t dr1;
269	uint64_t dr2;
270	uint64_t dr3;
271	uint64_t dr6;
272	uint64_t dr7;
273	/** @} */
274
275	/** Global Descriptor Table register. */
276	X86XDTR64 gdtr;
277	uint16_t gdtrPadding;
278	/** Interrupt Descriptor Table register. */
279	X86XDTR64 idtr;
280	uint16_t idtrPadding;
281	/** The task register. */
282	RTSEL ldtr;
283	RTSEL ldtrPadding;
284	/** The task register. */
285	RTSEL tr;
286	RTSEL trPadding;
287
288	/** MSRs
289	* @{ */
290	CPUMSYSENTER SysEnter;
291	uint64_t FSbase;
292	uint64_t GSbase;
293	uint64_t efer;
294	/** @} */
295
296	/** The XCR0 register. */
297	uint64_t xcr0;
298	/** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
299	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
300	uint64_t fXStateMask;
301
302	/* padding to get 64byte aligned size */
303	uint8_t auPadding[24];
304	#if HC_ARCH_BITS != 64
305	# error HC_ARCH_BITS not defined or unsupported
306	#endif
307	} CPUMHOSTCTX;
308	#ifndef VBOX_FOR_DTRACE_LIB
309	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
310	#endif
311	/** Pointer to the saved host CPU state. */
312	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
313
314
315	/**
316	* The hypervisor context CPU state (just DRx left now).
317	*/
318	typedef struct CPUMHYPERCTX
319	{
320	/** Debug registers.
321	* @remarks DR4 and DR5 should not be used since they are aliases for
322	* DR6 and DR7 respectively on both AMD and Intel CPUs.
323	* @remarks DR8-15 are currently not supported by AMD or Intel, so
324	* neither do we.
325	*/
326	uint64_t dr[8];
327	/** @todo eliminiate the rest. */
328	uint64_t cr3;
329	uint64_t au64Padding[7];
330	} CPUMHYPERCTX;
331	#ifndef VBOX_FOR_DTRACE_LIB
332	AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
333	#endif
334	/** Pointer to the hypervisor context CPU state. */
335	typedef CPUMHYPERCTX *PCPUMHYPERCTX;
336
337
338	/**
339	* CPUM Data (part of VM)
340	*/
341	typedef struct CPUM
342	{
343	/** Use flags.
344	* These flags indicates which CPU features the host uses.
345	*/
346	uint32_t fHostUseFlags;
347
348	/** CR4 mask
349	* @todo obsolete? */
350	struct
351	{
352	uint32_t AndMask; /*< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! /
353	uint32_t OrMask;
354	} CR4;
355
356	/** The (more) portable CPUID level. */
357	uint8_t u8PortableCpuIdLevel;
358	/** Indicates that a state restore is pending.
359	* This is used to verify load order dependencies (PGM). */
360	bool fPendingRestore;
361	uint8_t abPadding0[2];
362
363	/** XSAVE/XRTOR components we can expose to the guest mask. */
364	uint64_t fXStateGuestMask;
365	/** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
366	* to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
367	uint64_t fXStateHostMask;
368
369	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
370	/** The host MXCSR mask (determined at init). */
371	uint32_t fHostMxCsrMask;
372	#else
373	uint32_t u32UnusedOnNonX86;
374	#endif
375	/** Nested VMX: Whether to expose VMX-preemption timer to the guest. */
376	bool fNestedVmxPreemptTimer;
377	/** Nested VMX: Whether to expose EPT to the guest. If this is disabled make sure
378	* to also disable fNestedVmxUnrestrictedGuest. */
379	bool fNestedVmxEpt;
380	/** Nested VMX: Whether to expose "unrestricted guest" to the guest. */
381	bool fNestedVmxUnrestrictedGuest;
382	uint8_t abPadding1[1];
383
384	/** Align to 64-byte boundary. */
385	uint8_t abPadding2[20+4];
386
387	/** Host CPU feature information.
388	* Externaly visible via the VM structure, aligned on 64-byte boundrary. */
389	CPUMFEATURES HostFeatures;
390	/** Guest CPU feature information.
391	* Externaly visible via that VM structure, aligned with HostFeatures. */
392	CPUMFEATURES GuestFeatures;
393	/** Guest CPU info. */
394	CPUMINFO GuestInfo;
395
396	/** The standard set of CpuId leaves. */
397	CPUMCPUID aGuestCpuIdPatmStd[6];
398	/** The extended set of CpuId leaves. */
399	CPUMCPUID aGuestCpuIdPatmExt[10];
400	/** The centaur set of CpuId leaves. */
401	CPUMCPUID aGuestCpuIdPatmCentaur[4];
402
403	/** @name MSR statistics.
404	* @{ */
405	STAMCOUNTER cMsrWrites;
406	STAMCOUNTER cMsrWritesToIgnoredBits;
407	STAMCOUNTER cMsrWritesRaiseGp;
408	STAMCOUNTER cMsrWritesUnknown;
409	STAMCOUNTER cMsrReads;
410	STAMCOUNTER cMsrReadsRaiseGp;
411	STAMCOUNTER cMsrReadsUnknown;
412	/** @} */
413	} CPUM;
414	#ifndef VBOX_FOR_DTRACE_LIB
415	AssertCompileMemberOffset(CPUM, HostFeatures, 64);
416	AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
417	#endif
418	/** Pointer to the CPUM instance data residing in the shared VM structure. */
419	typedef CPUM *PCPUM;
420
421	/**
422	* CPUM Data (part of VMCPU)
423	*/
424	typedef struct CPUMCPU
425	{
426	/** Guest context.
427	* Aligned on a 64-byte boundary. */
428	CPUMCTX Guest;
429	/** Guest context - misc MSRs
430	* Aligned on a 64-byte boundary. */
431	CPUMCTXMSRS GuestMsrs;
432
433	/** Nested VMX: VMX-preemption timer. */
434	TMTIMERHANDLE hNestedVmxPreemptTimer;
435
436	/** Use flags.
437	* These flags indicates both what is to be used and what has been used. */
438	uint32_t fUseFlags;
439
440	/** Changed flags.
441	* These flags indicates to REM (and others) which important guest
442	* registers which has been changed since last time the flags were cleared.
443	* See the CPUM_CHANGED_* defines for what we keep track of.
444	*
445	* @todo Obsolete, but will probably be refactored so keep it for reference. */
446	uint32_t fChanged;
447
448	/** Temporary storage for the return code of the function called in the
449	* 32-64 switcher. */
450	uint32_t u32RetCode;
451
452	/** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
453	* (?) bits are visible or not. (The APIC is responsible for setting this
454	* when loading state, so we won't save it.) */
455	bool fCpuIdApicFeatureVisible;
456
457	/** Align the next member on a 64-byte boundary. */
458	uint8_t abPadding2[64 - 8 - 4*3 - 1];
459
460	/** Saved host context. Only valid while inside RC or HM contexts.
461	* Must be aligned on a 64-byte boundary. */
462	CPUMHOSTCTX Host;
463	/** Old hypervisor context, only used for combined DRx values now.
464	* Must be aligned on a 64-byte boundary. */
465	CPUMHYPERCTX Hyper;
466
467	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
468	uint8_t aMagic[56];
469	uint64_t uMagic;
470	#endif
471	} CPUMCPU;
472	#ifndef VBOX_FOR_DTRACE_LIB
473	AssertCompileMemberAlignment(CPUMCPU, Host, 64);
474	#endif
475	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
476	typedef CPUMCPU *PCPUMCPU;
477
478	#ifndef VBOX_FOR_DTRACE_LIB
479	RT_C_DECLS_BEGIN
480
481	PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
482	PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
483	PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
484	PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves);
485	# ifdef VBOX_STRICT
486	void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves);
487	# endif
488	int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs,
489	PCPUMFEATURES pFeatures);
490
491	# ifdef IN_RING3
492	int cpumR3DbgInit(PVM pVM);
493	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
494	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs);
495	void cpumR3CpuIdRing3InitDone(PVM pVM);
496	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
497	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
498	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
499	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
500
501	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
502	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange);
503	int cpumR3MsrReconcileWithCpuId(PVM pVM);
504	int cpumR3MsrApplyFudge(PVM pVM);
505	int cpumR3MsrRegStats(PVM pVM);
506	int cpumR3MsrStrictInitChecks(void);
507	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
508	# endif
509
510	# ifdef IN_RC
511	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
512	# endif
513
514	# ifdef IN_RING0
515	DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
516	DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
517	# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
518	DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
519	# endif
520	# endif
521
522	# if defined(IN_RC) \|\| defined(IN_RING0)
523	DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
524	DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
525	DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
526	DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
527	# endif
528
529	RT_C_DECLS_END
530	#endif /* !VBOX_FOR_DTRACE_LIB */
531
532	/** @} */
533
534	#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
535

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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 97213

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