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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 96622

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1/* $Id: CPUMInternal.h 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
29#define VMM_INCLUDED_SRC_include_CPUMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <VBox/cdefs.h>
36# include <VBox/types.h>
37# include <VBox/vmm/stam.h>
38# include <iprt/x86.h>
39# include <VBox/vmm/pgm.h>
40#else
41# pragma D depends_on library x86.d
42# pragma D depends_on library cpumctx.d
43# pragma D depends_on library cpum.d
44
45/* Some fudging. */
46typedef uint64_t STAMCOUNTER;
47#endif
48
49
50
51
52/** @defgroup grp_cpum_int Internals
53 * @ingroup grp_cpum
54 * @internal
55 * @{
56 */
57
58/** Flags and types for CPUM fault handlers
59 * @{ */
60/** Type: Load DS */
61#define CPUM_HANDLER_DS 1
62/** Type: Load ES */
63#define CPUM_HANDLER_ES 2
64/** Type: Load FS */
65#define CPUM_HANDLER_FS 3
66/** Type: Load GS */
67#define CPUM_HANDLER_GS 4
68/** Type: IRET */
69#define CPUM_HANDLER_IRET 5
70/** Type mask. */
71#define CPUM_HANDLER_TYPEMASK 0xff
72/** If set EBP points to the CPUMCTXCORE that's being used. */
73#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
74/** @} */
75
76
77/** Use flags (CPUM::fUseFlags).
78 * (Don't forget to sync this with CPUMInternal.mac !)
79 * @note Was part of saved state (6.1 and earlier).
80 * @{ */
81/** Indicates that we've saved the host FPU, SSE, whatever state and that it
82 * needs to be restored. */
83#define CPUM_USED_FPU_HOST RT_BIT(0)
84/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
85 * needs to be saved.
86 * @note Mirrored in CPUMCTX::fUsedFpuGuest for the HM switcher code. */
87#define CPUM_USED_FPU_GUEST RT_BIT(10)
88/** Used the guest FPU, SSE or such stuff since last we were in REM.
89 * REM syncing is clearing this, lazy FPU is setting it. */
90#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
91/** The XMM state was manually restored. (AMD only) */
92#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
93
94/** Host OS is using SYSENTER and we must NULL the CS. */
95#define CPUM_USE_SYSENTER RT_BIT(3)
96/** Host OS is using SYSENTER and we must NULL the CS. */
97#define CPUM_USE_SYSCALL RT_BIT(4)
98
99/** Debug registers are used by host and that DR7 and DR6 must be saved and
100 * disabled when switching to raw-mode. */
101#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
102/** Records that we've saved the host DRx registers.
103 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
104 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
105#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
106/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
107 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
108#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
109/** Used in ring-0 to indicate that we have loaded the hypervisor debug
110 * registers. */
111#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
112/** Used in ring-0 to indicate that we have loaded the guest debug
113 * registers (DR0-3 and maybe DR6) for direct use by the guest.
114 * DR7 (and AMD-V DR6) are handled via the VMCB. */
115#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
116
117/** Host CPU requires fxsave/fxrstor leaky bit handling. */
118#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
119/** Set if the VM supports long-mode. */
120#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
121/** @} */
122
123
124/** @name CPUM Saved State Version.
125 * @{ */
126/** The current saved state version. */
127#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_PAE_PDPES
128/** The saved state version with PAE PDPEs added. */
129#define CPUM_SAVED_STATE_VERSION_PAE_PDPES 21
130/** The saved state version with more virtual VMCS fields and CPUMCTX VMX fields. */
131#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2 20
132/** The saved state version including VMX hardware virtualization state. */
133#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX 19
134/** The saved state version including SVM hardware virtualization state. */
135#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
136/** The saved state version including XSAVE state. */
137#define CPUM_SAVED_STATE_VERSION_XSAVE 17
138/** The saved state version with good CPUID leaf count. */
139#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
140/** CPUID changes with explode forgetting to update the leaf count on
141 * restore, resulting in garbage being saved restoring+saving old states). */
142#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
143/** The saved state version before the CPUIDs changes. */
144#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
145/** The saved state version before using SSMR3PutStruct. */
146#define CPUM_SAVED_STATE_VERSION_MEM 13
147/** The saved state version before introducing the MSR size field. */
148#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
149/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
150 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
151#define CPUM_SAVED_STATE_VERSION_VER3_2 11
152/** The saved state version of 3.0 and 3.1 trunk before the teleportation
153 * changes. */
154#define CPUM_SAVED_STATE_VERSION_VER3_0 10
155/** The saved state version for the 2.1 trunk before the MSR changes. */
156#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
157/** The saved state version of 2.0, used for backwards compatibility. */
158#define CPUM_SAVED_STATE_VERSION_VER2_0 8
159/** The saved state version of 1.6, used for backwards compatibility. */
160#define CPUM_SAVED_STATE_VERSION_VER1_6 6
161/** @} */
162
163
164/** @name XSAVE limits.
165 * @{ */
166/** Max size we accept for the XSAVE area.
167 * @see CPUMCTX::abXSave */
168#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
169/* Min size we accept for the XSAVE area. */
170#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
171/** @} */
172
173
174/**
175 * CPU info
176 */
177typedef struct CPUMINFO
178{
179 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
180 uint32_t cMsrRanges;
181 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
182 * instruction. Older hardware has been observed to ignore higher bits. */
183 uint32_t fMsrMask;
184
185 /** MXCSR mask. */
186 uint32_t fMxCsrMask;
187
188 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
189 uint32_t cCpuIdLeaves;
190 /** The index of the first extended CPUID leaf in the array.
191 * Set to cCpuIdLeaves if none present. */
192 uint32_t iFirstExtCpuIdLeaf;
193 /** How to handle unknown CPUID leaves. */
194 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
195 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
196 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
197 CPUMCPUID DefCpuId;
198
199 /** Scalable bus frequency used for reporting other frequencies. */
200 uint64_t uScalableBusFreq;
201
202 /** Pointer to the MSR ranges (for compatibility with old hyper heap code). */
203 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
204 /** Pointer to the CPUID leaves (for compatibility with old hyper heap code). */
205 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
206
207 /** CPUID leaves. */
208 CPUMCPUIDLEAF aCpuIdLeaves[256];
209 /** MSR ranges.
210 * @todo This is insane, so might want to move this into a separate
211 * allocation. The insanity is mainly for more recent AMD CPUs. */
212 CPUMMSRRANGE aMsrRanges[8192];
213} CPUMINFO;
214/** Pointer to a CPU info structure. */
215typedef CPUMINFO *PCPUMINFO;
216/** Pointer to a const CPU info structure. */
217typedef CPUMINFO const *CPCPUMINFO;
218
219
220/**
221 * The saved host CPU state.
222 */
223typedef struct CPUMHOSTCTX
224{
225 /** The extended state (FPU/SSE/AVX/AVX-2/XXXX). Must be aligned on 64 bytes. */
226 union /* no tag */
227 {
228 X86XSAVEAREA XState;
229 /** Byte view for simple indexing and space allocation.
230 * @note Must match or exceed the size of CPUMCTX::abXState. */
231 uint8_t abXState[0x4000 - 0x300];
232 } CPUM_UNION_NM(u);
233
234 /** General purpose register, selectors, flags and more
235 * @{ */
236 /** General purpose register ++
237 * { */
238 /*uint64_t rax; - scratch*/
239 uint64_t rbx;
240 /*uint64_t rcx; - scratch*/
241 /*uint64_t rdx; - scratch*/
242 uint64_t rdi;
243 uint64_t rsi;
244 uint64_t rbp;
245 uint64_t rsp;
246 /*uint64_t r8; - scratch*/
247 /*uint64_t r9; - scratch*/
248 uint64_t r10;
249 uint64_t r11;
250 uint64_t r12;
251 uint64_t r13;
252 uint64_t r14;
253 uint64_t r15;
254 /*uint64_t rip; - scratch*/
255 uint64_t rflags;
256 /** @} */
257
258 /** Selector registers
259 * @{ */
260 RTSEL ss;
261 RTSEL ssPadding;
262 RTSEL gs;
263 RTSEL gsPadding;
264 RTSEL fs;
265 RTSEL fsPadding;
266 RTSEL es;
267 RTSEL esPadding;
268 RTSEL ds;
269 RTSEL dsPadding;
270 RTSEL cs;
271 RTSEL csPadding;
272 /** @} */
273
274 /** Control registers.
275 * @{ */
276 /** The CR0 FPU state in HM mode. */
277 uint64_t cr0;
278 /*uint64_t cr2; - scratch*/
279 uint64_t cr3;
280 uint64_t cr4;
281 uint64_t cr8;
282 /** @} */
283
284 /** Debug registers.
285 * @{ */
286 uint64_t dr0;
287 uint64_t dr1;
288 uint64_t dr2;
289 uint64_t dr3;
290 uint64_t dr6;
291 uint64_t dr7;
292 /** @} */
293
294 /** Global Descriptor Table register. */
295 X86XDTR64 gdtr;
296 uint16_t gdtrPadding;
297 /** Interrupt Descriptor Table register. */
298 X86XDTR64 idtr;
299 uint16_t idtrPadding;
300 /** The task register. */
301 RTSEL ldtr;
302 RTSEL ldtrPadding;
303 /** The task register. */
304 RTSEL tr;
305 RTSEL trPadding;
306
307 /** MSRs
308 * @{ */
309 CPUMSYSENTER SysEnter;
310 uint64_t FSbase;
311 uint64_t GSbase;
312 uint64_t efer;
313 /** @} */
314
315 /** The XCR0 register. */
316 uint64_t xcr0;
317 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
318 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
319 uint64_t fXStateMask;
320
321 /* padding to get 64byte aligned size */
322 uint8_t auPadding[24];
323#if HC_ARCH_BITS != 64
324# error HC_ARCH_BITS not defined or unsupported
325#endif
326} CPUMHOSTCTX;
327#ifndef VBOX_FOR_DTRACE_LIB
328AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
329#endif
330/** Pointer to the saved host CPU state. */
331typedef CPUMHOSTCTX *PCPUMHOSTCTX;
332
333
334/**
335 * The hypervisor context CPU state (just DRx left now).
336 */
337typedef struct CPUMHYPERCTX
338{
339 /** Debug registers.
340 * @remarks DR4 and DR5 should not be used since they are aliases for
341 * DR6 and DR7 respectively on both AMD and Intel CPUs.
342 * @remarks DR8-15 are currently not supported by AMD or Intel, so
343 * neither do we.
344 */
345 uint64_t dr[8];
346 /** @todo eliminiate the rest. */
347 uint64_t cr3;
348 uint64_t au64Padding[7];
349} CPUMHYPERCTX;
350#ifndef VBOX_FOR_DTRACE_LIB
351AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
352#endif
353/** Pointer to the hypervisor context CPU state. */
354typedef CPUMHYPERCTX *PCPUMHYPERCTX;
355
356
357/**
358 * CPUM Data (part of VM)
359 */
360typedef struct CPUM
361{
362 /** Use flags.
363 * These flags indicates which CPU features the host uses.
364 */
365 uint32_t fHostUseFlags;
366
367 /** CR4 mask
368 * @todo obsolete? */
369 struct
370 {
371 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
372 uint32_t OrMask;
373 } CR4;
374
375 /** The (more) portable CPUID level. */
376 uint8_t u8PortableCpuIdLevel;
377 /** Indicates that a state restore is pending.
378 * This is used to verify load order dependencies (PGM). */
379 bool fPendingRestore;
380 uint8_t abPadding0[2];
381
382 /** XSAVE/XRTOR components we can expose to the guest mask. */
383 uint64_t fXStateGuestMask;
384 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
385 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
386 uint64_t fXStateHostMask;
387
388#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
389 /** The host MXCSR mask (determined at init). */
390 uint32_t fHostMxCsrMask;
391#else
392 uint32_t u32UnusedOnNonX86;
393#endif
394 /** Nested VMX: Whether to expose VMX-preemption timer to the guest. */
395 bool fNestedVmxPreemptTimer;
396 /** Nested VMX: Whether to expose EPT to the guest. If this is disabled make sure
397 * to also disable fNestedVmxUnrestrictedGuest. */
398 bool fNestedVmxEpt;
399 /** Nested VMX: Whether to expose "unrestricted guest" to the guest. */
400 bool fNestedVmxUnrestrictedGuest;
401 uint8_t abPadding1[1];
402
403 /** Align to 64-byte boundary. */
404 uint8_t abPadding2[20+4];
405
406 /** Host CPU feature information.
407 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
408 CPUMFEATURES HostFeatures;
409 /** Guest CPU feature information.
410 * Externaly visible via that VM structure, aligned with HostFeatures. */
411 CPUMFEATURES GuestFeatures;
412 /** Guest CPU info. */
413 CPUMINFO GuestInfo;
414
415 /** The standard set of CpuId leaves. */
416 CPUMCPUID aGuestCpuIdPatmStd[6];
417 /** The extended set of CpuId leaves. */
418 CPUMCPUID aGuestCpuIdPatmExt[10];
419 /** The centaur set of CpuId leaves. */
420 CPUMCPUID aGuestCpuIdPatmCentaur[4];
421
422 /** @name MSR statistics.
423 * @{ */
424 STAMCOUNTER cMsrWrites;
425 STAMCOUNTER cMsrWritesToIgnoredBits;
426 STAMCOUNTER cMsrWritesRaiseGp;
427 STAMCOUNTER cMsrWritesUnknown;
428 STAMCOUNTER cMsrReads;
429 STAMCOUNTER cMsrReadsRaiseGp;
430 STAMCOUNTER cMsrReadsUnknown;
431 /** @} */
432} CPUM;
433#ifndef VBOX_FOR_DTRACE_LIB
434AssertCompileMemberOffset(CPUM, HostFeatures, 64);
435AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
436#endif
437/** Pointer to the CPUM instance data residing in the shared VM structure. */
438typedef CPUM *PCPUM;
439
440/**
441 * CPUM Data (part of VMCPU)
442 */
443typedef struct CPUMCPU
444{
445 /** Guest context.
446 * Aligned on a 64-byte boundary. */
447 CPUMCTX Guest;
448 /** Guest context - misc MSRs
449 * Aligned on a 64-byte boundary. */
450 CPUMCTXMSRS GuestMsrs;
451
452 /** Nested VMX: VMX-preemption timer. */
453 TMTIMERHANDLE hNestedVmxPreemptTimer;
454
455 /** Use flags.
456 * These flags indicates both what is to be used and what has been used. */
457 uint32_t fUseFlags;
458
459 /** Changed flags.
460 * These flags indicates to REM (and others) which important guest
461 * registers which has been changed since last time the flags were cleared.
462 * See the CPUM_CHANGED_* defines for what we keep track of.
463 *
464 * @todo Obsolete, but will probably be refactored so keep it for reference. */
465 uint32_t fChanged;
466
467 /** Temporary storage for the return code of the function called in the
468 * 32-64 switcher. */
469 uint32_t u32RetCode;
470
471 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
472 * (?) bits are visible or not. (The APIC is responsible for setting this
473 * when loading state, so we won't save it.) */
474 bool fCpuIdApicFeatureVisible;
475
476 /** Align the next member on a 64-byte boundary. */
477 uint8_t abPadding2[64 - 8 - 4*3 - 1];
478
479 /** Saved host context. Only valid while inside RC or HM contexts.
480 * Must be aligned on a 64-byte boundary. */
481 CPUMHOSTCTX Host;
482 /** Old hypervisor context, only used for combined DRx values now.
483 * Must be aligned on a 64-byte boundary. */
484 CPUMHYPERCTX Hyper;
485
486#ifdef VBOX_WITH_CRASHDUMP_MAGIC
487 uint8_t aMagic[56];
488 uint64_t uMagic;
489#endif
490} CPUMCPU;
491#ifndef VBOX_FOR_DTRACE_LIB
492AssertCompileMemberAlignment(CPUMCPU, Host, 64);
493#endif
494/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
495typedef CPUMCPU *PCPUMCPU;
496
497#ifndef VBOX_FOR_DTRACE_LIB
498RT_C_DECLS_BEGIN
499
500PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
501PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
502PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
503PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves);
504# ifdef VBOX_STRICT
505void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves);
506# endif
507int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs,
508 PCPUMFEATURES pFeatures);
509
510# ifdef IN_RING3
511int cpumR3DbgInit(PVM pVM);
512int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
513void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs);
514void cpumR3CpuIdRing3InitDone(PVM pVM);
515void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
516int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
517int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
518DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
519
520int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
521int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
522int cpumR3MsrReconcileWithCpuId(PVM pVM);
523int cpumR3MsrApplyFudge(PVM pVM);
524int cpumR3MsrRegStats(PVM pVM);
525int cpumR3MsrStrictInitChecks(void);
526PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
527# endif
528
529# ifdef IN_RC
530DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
531# endif
532
533# ifdef IN_RING0
534DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
535DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
536# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
537DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
538# endif
539# endif
540
541# if defined(IN_RC) || defined(IN_RING0)
542DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
543DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
544DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
545DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
546# endif
547
548RT_C_DECLS_END
549#endif /* !VBOX_FOR_DTRACE_LIB */
550
551/** @} */
552
553#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
554
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