VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 87815

Last change on this file since 87815 was 87766, checked in by vboxsync, 4 years ago

VMM/TM,VMM/*: Refactored the TM timer APIs to use 'handles' and take a pVM parameter. Only internal callbacks have been updated with a hTimer parameter, so far. bugref:9943
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1/* $Id: CPUMInternal.h 87766 2021-02-16 14:27:43Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
19#define VMM_INCLUDED_SRC_include_CPUMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#ifndef VBOX_FOR_DTRACE_LIB
25# include <VBox/cdefs.h>
26# include <VBox/types.h>
27# include <VBox/vmm/stam.h>
28# include <iprt/x86.h>
29# include <VBox/vmm/pgm.h>
30#else
31# pragma D depends_on library x86.d
32# pragma D depends_on library cpumctx.d
33# pragma D depends_on library cpum.d
34
35/* Some fudging. */
36typedef uint64_t STAMCOUNTER;
37#endif
38
39
40
41
42/** @defgroup grp_cpum_int Internals
43 * @ingroup grp_cpum
44 * @internal
45 * @{
46 */
47
48/** Flags and types for CPUM fault handlers
49 * @{ */
50/** Type: Load DS */
51#define CPUM_HANDLER_DS 1
52/** Type: Load ES */
53#define CPUM_HANDLER_ES 2
54/** Type: Load FS */
55#define CPUM_HANDLER_FS 3
56/** Type: Load GS */
57#define CPUM_HANDLER_GS 4
58/** Type: IRET */
59#define CPUM_HANDLER_IRET 5
60/** Type mask. */
61#define CPUM_HANDLER_TYPEMASK 0xff
62/** If set EBP points to the CPUMCTXCORE that's being used. */
63#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
64/** @} */
65
66
67/** Use flags (CPUM::fUseFlags).
68 * (Don't forget to sync this with CPUMInternal.mac !)
69 * @note Was part of saved state (6.1 and earlier).
70 * @{ */
71/** Indicates that we've saved the host FPU, SSE, whatever state and that it
72 * needs to be restored. */
73#define CPUM_USED_FPU_HOST RT_BIT(0)
74/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
75 * needs to be saved.
76 * @note Mirrored in CPUMCTX::fUsedFpuGuest for the HM switcher code. */
77#define CPUM_USED_FPU_GUEST RT_BIT(10)
78/** Used the guest FPU, SSE or such stuff since last we were in REM.
79 * REM syncing is clearing this, lazy FPU is setting it. */
80#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
81/** The XMM state was manually restored. (AMD only) */
82#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
83
84/** Host OS is using SYSENTER and we must NULL the CS. */
85#define CPUM_USE_SYSENTER RT_BIT(3)
86/** Host OS is using SYSENTER and we must NULL the CS. */
87#define CPUM_USE_SYSCALL RT_BIT(4)
88
89/** Debug registers are used by host and that DR7 and DR6 must be saved and
90 * disabled when switching to raw-mode. */
91#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
92/** Records that we've saved the host DRx registers.
93 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
94 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
95#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
96/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
97 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
98#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
99/** Used in ring-0 to indicate that we have loaded the hypervisor debug
100 * registers. */
101#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
102/** Used in ring-0 to indicate that we have loaded the guest debug
103 * registers (DR0-3 and maybe DR6) for direct use by the guest.
104 * DR7 (and AMD-V DR6) are handled via the VMCB. */
105#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
106
107/** Host CPU requires fxsave/fxrstor leaky bit handling. */
108#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
109/** Set if the VM supports long-mode. */
110#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
111/** @} */
112
113
114/** @name CPUM Saved State Version.
115 * @{ */
116/** The current saved state version. */
117#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM
118/** The saved state version including VMX hardware virtualization state (IEM only
119 * execution). */
120#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM 19
121/** The saved state version including SVM hardware virtualization state. */
122#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
123/** The saved state version including XSAVE state. */
124#define CPUM_SAVED_STATE_VERSION_XSAVE 17
125/** The saved state version with good CPUID leaf count. */
126#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
127/** CPUID changes with explode forgetting to update the leaf count on
128 * restore, resulting in garbage being saved restoring+saving old states). */
129#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
130/** The saved state version before the CPUIDs changes. */
131#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
132/** The saved state version before using SSMR3PutStruct. */
133#define CPUM_SAVED_STATE_VERSION_MEM 13
134/** The saved state version before introducing the MSR size field. */
135#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
136/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
137 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
138#define CPUM_SAVED_STATE_VERSION_VER3_2 11
139/** The saved state version of 3.0 and 3.1 trunk before the teleportation
140 * changes. */
141#define CPUM_SAVED_STATE_VERSION_VER3_0 10
142/** The saved state version for the 2.1 trunk before the MSR changes. */
143#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
144/** The saved state version of 2.0, used for backwards compatibility. */
145#define CPUM_SAVED_STATE_VERSION_VER2_0 8
146/** The saved state version of 1.6, used for backwards compatibility. */
147#define CPUM_SAVED_STATE_VERSION_VER1_6 6
148/** @} */
149
150
151/**
152 * CPU info
153 */
154typedef struct CPUMINFO
155{
156 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
157 uint32_t cMsrRanges;
158 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
159 * instruction. Older hardware has been observed to ignore higher bits. */
160 uint32_t fMsrMask;
161
162 /** MXCSR mask. */
163 uint32_t fMxCsrMask;
164
165 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
166 uint32_t cCpuIdLeaves;
167 /** The index of the first extended CPUID leaf in the array.
168 * Set to cCpuIdLeaves if none present. */
169 uint32_t iFirstExtCpuIdLeaf;
170 /** How to handle unknown CPUID leaves. */
171 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
172 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
173 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
174 CPUMCPUID DefCpuId;
175
176 /** Scalable bus frequency used for reporting other frequencies. */
177 uint64_t uScalableBusFreq;
178
179 /** Pointer to the MSR ranges (ring-0 pointer). */
180 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
181 /** Pointer to the CPUID leaves (ring-0 pointer). */
182 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
183
184 /** Pointer to the MSR ranges (ring-3 pointer). */
185 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
186 /** Pointer to the CPUID leaves (ring-3 pointer). */
187 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
188} CPUMINFO;
189/** Pointer to a CPU info structure. */
190typedef CPUMINFO *PCPUMINFO;
191/** Pointer to a const CPU info structure. */
192typedef CPUMINFO const *CPCPUMINFO;
193
194
195/**
196 * The saved host CPU state.
197 */
198typedef struct CPUMHOSTCTX
199{
200 /** General purpose register, selectors, flags and more
201 * @{ */
202 /** General purpose register ++
203 * { */
204 /*uint64_t rax; - scratch*/
205 uint64_t rbx;
206 /*uint64_t rcx; - scratch*/
207 /*uint64_t rdx; - scratch*/
208 uint64_t rdi;
209 uint64_t rsi;
210 uint64_t rbp;
211 uint64_t rsp;
212 /*uint64_t r8; - scratch*/
213 /*uint64_t r9; - scratch*/
214 uint64_t r10;
215 uint64_t r11;
216 uint64_t r12;
217 uint64_t r13;
218 uint64_t r14;
219 uint64_t r15;
220 /*uint64_t rip; - scratch*/
221 uint64_t rflags;
222 /** @} */
223
224 /** Selector registers
225 * @{ */
226 RTSEL ss;
227 RTSEL ssPadding;
228 RTSEL gs;
229 RTSEL gsPadding;
230 RTSEL fs;
231 RTSEL fsPadding;
232 RTSEL es;
233 RTSEL esPadding;
234 RTSEL ds;
235 RTSEL dsPadding;
236 RTSEL cs;
237 RTSEL csPadding;
238 /** @} */
239
240 /** Control registers.
241 * @{ */
242 /** The CR0 FPU state in HM mode. */
243 uint64_t cr0;
244 /*uint64_t cr2; - scratch*/
245 uint64_t cr3;
246 uint64_t cr4;
247 uint64_t cr8;
248 /** @} */
249
250 /** Debug registers.
251 * @{ */
252 uint64_t dr0;
253 uint64_t dr1;
254 uint64_t dr2;
255 uint64_t dr3;
256 uint64_t dr6;
257 uint64_t dr7;
258 /** @} */
259
260 /** Global Descriptor Table register. */
261 X86XDTR64 gdtr;
262 uint16_t gdtrPadding;
263 /** Interrupt Descriptor Table register. */
264 X86XDTR64 idtr;
265 uint16_t idtrPadding;
266 /** The task register. */
267 RTSEL ldtr;
268 RTSEL ldtrPadding;
269 /** The task register. */
270 RTSEL tr;
271 RTSEL trPadding;
272
273 /** MSRs
274 * @{ */
275 CPUMSYSENTER SysEnter;
276 uint64_t FSbase;
277 uint64_t GSbase;
278 uint64_t efer;
279 /** @} */
280
281 /* padding to get 64byte aligned size */
282 uint8_t auPadding[8];
283
284#if HC_ARCH_BITS != 64
285# error HC_ARCH_BITS not defined or unsupported
286#endif
287
288 /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
289 R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
290 /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
291 R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
292 /** The XCR0 register. */
293 uint64_t xcr0;
294 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
295 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
296 uint64_t fXStateMask;
297} CPUMHOSTCTX;
298#ifndef VBOX_FOR_DTRACE_LIB
299AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
300#endif
301/** Pointer to the saved host CPU state. */
302typedef CPUMHOSTCTX *PCPUMHOSTCTX;
303
304
305/**
306 * The hypervisor context CPU state (just DRx left now).
307 */
308typedef struct CPUMHYPERCTX
309{
310 /** Debug registers.
311 * @remarks DR4 and DR5 should not be used since they are aliases for
312 * DR6 and DR7 respectively on both AMD and Intel CPUs.
313 * @remarks DR8-15 are currently not supported by AMD or Intel, so
314 * neither do we.
315 */
316 uint64_t dr[8];
317 /** @todo eliminiate the rest. */
318 uint64_t cr3;
319 uint64_t au64Padding[7];
320} CPUMHYPERCTX;
321#ifndef VBOX_FOR_DTRACE_LIB
322AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
323#endif
324/** Pointer to the hypervisor context CPU state. */
325typedef CPUMHYPERCTX *PCPUMHYPERCTX;
326
327
328/**
329 * CPUM Data (part of VM)
330 */
331typedef struct CPUM
332{
333 /** Use flags.
334 * These flags indicates which CPU features the host uses.
335 */
336 uint32_t fHostUseFlags;
337
338 /** CR4 mask
339 * @todo obsolete? */
340 struct
341 {
342 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
343 uint32_t OrMask;
344 } CR4;
345
346 /** The (more) portable CPUID level. */
347 uint8_t u8PortableCpuIdLevel;
348 /** Indicates that a state restore is pending.
349 * This is used to verify load order dependencies (PGM). */
350 bool fPendingRestore;
351 uint8_t abPadding0[2];
352
353 /** XSAVE/XRTOR components we can expose to the guest mask. */
354 uint64_t fXStateGuestMask;
355 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
356 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
357 uint64_t fXStateHostMask;
358
359 /** The host MXCSR mask (determined at init). */
360 uint32_t fHostMxCsrMask;
361 /** Nested VMX: Whether to expose VMX-preemption timer to the guest. */
362 bool fNestedVmxPreemptTimer;
363 uint8_t abPadding1[3];
364
365 /** Align to 64-byte boundary. */
366 uint8_t abPadding2[20+4];
367
368 /** Host CPU feature information.
369 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
370 CPUMFEATURES HostFeatures;
371 /** Guest CPU feature information.
372 * Externaly visible via that VM structure, aligned with HostFeatures. */
373 CPUMFEATURES GuestFeatures;
374 /** Guest CPU info. */
375 CPUMINFO GuestInfo;
376
377 /** The standard set of CpuId leaves. */
378 CPUMCPUID aGuestCpuIdPatmStd[6];
379 /** The extended set of CpuId leaves. */
380 CPUMCPUID aGuestCpuIdPatmExt[10];
381 /** The centaur set of CpuId leaves. */
382 CPUMCPUID aGuestCpuIdPatmCentaur[4];
383
384 /** @name MSR statistics.
385 * @{ */
386 STAMCOUNTER cMsrWrites;
387 STAMCOUNTER cMsrWritesToIgnoredBits;
388 STAMCOUNTER cMsrWritesRaiseGp;
389 STAMCOUNTER cMsrWritesUnknown;
390 STAMCOUNTER cMsrReads;
391 STAMCOUNTER cMsrReadsRaiseGp;
392 STAMCOUNTER cMsrReadsUnknown;
393 /** @} */
394} CPUM;
395#ifndef VBOX_FOR_DTRACE_LIB
396AssertCompileMemberOffset(CPUM, HostFeatures, 64);
397AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
398#endif
399/** Pointer to the CPUM instance data residing in the shared VM structure. */
400typedef CPUM *PCPUM;
401
402/**
403 * CPUM Data (part of VMCPU)
404 */
405typedef struct CPUMCPU
406{
407 /**
408 * Guest context.
409 * Aligned on a 64-byte boundary.
410 */
411 CPUMCTX Guest;
412
413 /**
414 * Guest context - misc MSRs
415 * Aligned on a 64-byte boundary.
416 */
417 CPUMCTXMSRS GuestMsrs;
418
419 /** Nested VMX: VMX-preemption timer. */
420 TMTIMERHANDLE hNestedVmxPreemptTimer;
421
422 /** Use flags.
423 * These flags indicates both what is to be used and what has been used.
424 */
425 uint32_t fUseFlags;
426
427 /** Changed flags.
428 * These flags indicates to REM (and others) which important guest
429 * registers which has been changed since last time the flags were cleared.
430 * See the CPUM_CHANGED_* defines for what we keep track of.
431 *
432 * @todo Obsolete, but will probably refactored so keep it for reference. */
433 uint32_t fChanged;
434
435 /** Temporary storage for the return code of the function called in the
436 * 32-64 switcher. */
437 uint32_t u32RetCode;
438
439#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
440 /** Used by the world switcher code to store which vectors needs restoring on
441 * the way back. */
442 uint32_t fApicDisVectors;
443 /** The address of the APIC mapping, NULL if no APIC.
444 * Call CPUMR0SetLApic to update this before doing a world switch. */
445 RTHCPTR pvApicBase;
446 /** Set if the CPU has the X2APIC mode enabled.
447 * Call CPUMR0SetLApic to update this before doing a world switch. */
448 bool fX2Apic;
449#else
450 uint8_t abPadding3[4 + sizeof(RTHCPTR) + 1];
451#endif
452
453 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
454 * (?) bits are visible or not. (The APIC is responsible for setting this
455 * when loading state, so we won't save it.) */
456 bool fCpuIdApicFeatureVisible;
457
458 /** Align the next member on a 64-byte boundary. */
459 uint8_t abPadding2[64 - (8 + 12 + 4 + 8 + 1 + 1)];
460
461 /** Saved host context. Only valid while inside RC or HM contexts.
462 * Must be aligned on a 64-byte boundary. */
463 CPUMHOSTCTX Host;
464 /** Old hypervisor context, only used for combined DRx values now.
465 * Must be aligned on a 64-byte boundary. */
466 CPUMHYPERCTX Hyper;
467
468#ifdef VBOX_WITH_CRASHDUMP_MAGIC
469 uint8_t aMagic[56];
470 uint64_t uMagic;
471#endif
472} CPUMCPU;
473/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
474typedef CPUMCPU *PCPUMCPU;
475
476#ifndef VBOX_FOR_DTRACE_LIB
477RT_C_DECLS_BEGIN
478
479PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
480PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
481
482# ifdef IN_RING3
483int cpumR3DbgInit(PVM pVM);
484int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures);
485int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
486void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs);
487void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
488int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
489int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
490DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
491
492int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
493int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
494int cpumR3MsrReconcileWithCpuId(PVM pVM);
495int cpumR3MsrApplyFudge(PVM pVM);
496int cpumR3MsrRegStats(PVM pVM);
497int cpumR3MsrStrictInitChecks(void);
498PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
499# endif
500
501# ifdef IN_RC
502DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
503# endif
504
505# ifdef IN_RING0
506DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
507DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
508# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
509DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
510# endif
511# endif
512
513# if defined(IN_RC) || defined(IN_RING0)
514DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
515DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
516DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
517DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
518# endif
519
520RT_C_DECLS_END
521#endif /* !VBOX_FOR_DTRACE_LIB */
522
523/** @} */
524
525#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
526
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