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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 86647

Last change on this file since 86647 was 86218, checked in by vboxsync, 4 years ago

VMM/CPUMInternal.h: TODO
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1/* $Id: CPUMInternal.h 86218 2020-09-22 12:36:57Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
19#define VMM_INCLUDED_SRC_include_CPUMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#ifndef VBOX_FOR_DTRACE_LIB
25# include <VBox/cdefs.h>
26# include <VBox/types.h>
27# include <VBox/vmm/stam.h>
28# include <iprt/x86.h>
29# include <VBox/vmm/pgm.h>
30#else
31# pragma D depends_on library x86.d
32# pragma D depends_on library cpumctx.d
33# pragma D depends_on library cpum.d
34
35/* Some fudging. */
36typedef uint64_t STAMCOUNTER;
37#endif
38
39
40
41
42/** @defgroup grp_cpum_int Internals
43 * @ingroup grp_cpum
44 * @internal
45 * @{
46 */
47
48/** Flags and types for CPUM fault handlers
49 * @{ */
50/** Type: Load DS */
51#define CPUM_HANDLER_DS 1
52/** Type: Load ES */
53#define CPUM_HANDLER_ES 2
54/** Type: Load FS */
55#define CPUM_HANDLER_FS 3
56/** Type: Load GS */
57#define CPUM_HANDLER_GS 4
58/** Type: IRET */
59#define CPUM_HANDLER_IRET 5
60/** Type mask. */
61#define CPUM_HANDLER_TYPEMASK 0xff
62/** If set EBP points to the CPUMCTXCORE that's being used. */
63#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
64/** @} */
65
66
67/** Use flags (CPUM::fUseFlags).
68 * (Don't forget to sync this with CPUMInternal.mac !)
69 * @note Part of saved state.
70 * @{ */
71/** Indicates that we've saved the host FPU, SSE, whatever state and that it
72 * needs to be restored. */
73#define CPUM_USED_FPU_HOST RT_BIT(0)
74/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
75 * needs to be saved. */
76#define CPUM_USED_FPU_GUEST RT_BIT(10)
77/** Used the guest FPU, SSE or such stuff since last we were in REM.
78 * REM syncing is clearing this, lazy FPU is setting it. */
79#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
80/** The XMM state was manually restored. (AMD only) */
81#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
82
83/** Host OS is using SYSENTER and we must NULL the CS. */
84#define CPUM_USE_SYSENTER RT_BIT(3)
85/** Host OS is using SYSENTER and we must NULL the CS. */
86#define CPUM_USE_SYSCALL RT_BIT(4)
87
88/** Debug registers are used by host and that DR7 and DR6 must be saved and
89 * disabled when switching to raw-mode. */
90#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
91/** Records that we've saved the host DRx registers.
92 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
93 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
94#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
95/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
96 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
97#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
98/** Used in ring-0 to indicate that we have loaded the hypervisor debug
99 * registers. */
100#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
101/** Used in ring-0 to indicate that we have loaded the guest debug
102 * registers (DR0-3 and maybe DR6) for direct use by the guest.
103 * DR7 (and AMD-V DR6) are handled via the VMCB. */
104#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
105
106/** Sync the FPU state on next entry (32->64 switcher only). */
107#define CPUM_SYNC_FPU_STATE RT_BIT(16)
108/** Sync the debug state on next entry (32->64 switcher only). */
109#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
110/** Sync the debug state on next entry (32->64 switcher only).
111 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
112#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
113/** Host CPU requires fxsave/fxrstor leaky bit handling. */
114#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
115/** Set if the VM supports long-mode. */
116#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
117/** @} */
118
119
120/** @name CPUM Saved State Version.
121 * @{ */
122/** The current saved state version. */
123#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM
124/** The saved state version including VMX hardware virtualization state (IEM only
125 * execution). */
126#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM 19
127/** The saved state version including SVM hardware virtualization state. */
128#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
129/** The saved state version including XSAVE state. */
130#define CPUM_SAVED_STATE_VERSION_XSAVE 17
131/** The saved state version with good CPUID leaf count. */
132#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
133/** CPUID changes with explode forgetting to update the leaf count on
134 * restore, resulting in garbage being saved restoring+saving old states). */
135#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
136/** The saved state version before the CPUIDs changes. */
137#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
138/** The saved state version before using SSMR3PutStruct. */
139#define CPUM_SAVED_STATE_VERSION_MEM 13
140/** The saved state version before introducing the MSR size field. */
141#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
142/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
143 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
144#define CPUM_SAVED_STATE_VERSION_VER3_2 11
145/** The saved state version of 3.0 and 3.1 trunk before the teleportation
146 * changes. */
147#define CPUM_SAVED_STATE_VERSION_VER3_0 10
148/** The saved state version for the 2.1 trunk before the MSR changes. */
149#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
150/** The saved state version of 2.0, used for backwards compatibility. */
151#define CPUM_SAVED_STATE_VERSION_VER2_0 8
152/** The saved state version of 1.6, used for backwards compatibility. */
153#define CPUM_SAVED_STATE_VERSION_VER1_6 6
154/** @} */
155
156
157/**
158 * CPU info
159 */
160typedef struct CPUMINFO
161{
162 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
163 uint32_t cMsrRanges;
164 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
165 * instruction. Older hardware has been observed to ignore higher bits. */
166 uint32_t fMsrMask;
167
168 /** MXCSR mask. */
169 uint32_t fMxCsrMask;
170
171 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
172 uint32_t cCpuIdLeaves;
173 /** The index of the first extended CPUID leaf in the array.
174 * Set to cCpuIdLeaves if none present. */
175 uint32_t iFirstExtCpuIdLeaf;
176 /** How to handle unknown CPUID leaves. */
177 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
178 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
179 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
180 CPUMCPUID DefCpuId;
181
182 /** Scalable bus frequency used for reporting other frequencies. */
183 uint64_t uScalableBusFreq;
184
185 /** Pointer to the MSR ranges (ring-0 pointer). */
186 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
187 /** Pointer to the CPUID leaves (ring-0 pointer). */
188 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
189
190 /** Pointer to the MSR ranges (ring-3 pointer). */
191 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
192 /** Pointer to the CPUID leaves (ring-3 pointer). */
193 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
194} CPUMINFO;
195/** Pointer to a CPU info structure. */
196typedef CPUMINFO *PCPUMINFO;
197/** Pointer to a const CPU info structure. */
198typedef CPUMINFO const *CPCPUMINFO;
199
200
201/**
202 * The saved host CPU state.
203 */
204typedef struct CPUMHOSTCTX
205{
206 /** General purpose register, selectors, flags and more
207 * @{ */
208 /** General purpose register ++
209 * { */
210 /*uint64_t rax; - scratch*/
211 uint64_t rbx;
212 /*uint64_t rcx; - scratch*/
213 /*uint64_t rdx; - scratch*/
214 uint64_t rdi;
215 uint64_t rsi;
216 uint64_t rbp;
217 uint64_t rsp;
218 /*uint64_t r8; - scratch*/
219 /*uint64_t r9; - scratch*/
220 uint64_t r10;
221 uint64_t r11;
222 uint64_t r12;
223 uint64_t r13;
224 uint64_t r14;
225 uint64_t r15;
226 /*uint64_t rip; - scratch*/
227 uint64_t rflags;
228 /** @} */
229
230 /** Selector registers
231 * @{ */
232 RTSEL ss;
233 RTSEL ssPadding;
234 RTSEL gs;
235 RTSEL gsPadding;
236 RTSEL fs;
237 RTSEL fsPadding;
238 RTSEL es;
239 RTSEL esPadding;
240 RTSEL ds;
241 RTSEL dsPadding;
242 RTSEL cs;
243 RTSEL csPadding;
244 /** @} */
245
246 /** Control registers.
247 * @{ */
248 /** The CR0 FPU state in HM mode. */
249 uint64_t cr0;
250 /*uint64_t cr2; - scratch*/
251 uint64_t cr3;
252 uint64_t cr4;
253 uint64_t cr8;
254 /** @} */
255
256 /** Debug registers.
257 * @{ */
258 uint64_t dr0;
259 uint64_t dr1;
260 uint64_t dr2;
261 uint64_t dr3;
262 uint64_t dr6;
263 uint64_t dr7;
264 /** @} */
265
266 /** Global Descriptor Table register. */
267 X86XDTR64 gdtr;
268 uint16_t gdtrPadding;
269 /** Interrupt Descriptor Table register. */
270 X86XDTR64 idtr;
271 uint16_t idtrPadding;
272 /** The task register. */
273 RTSEL ldtr;
274 RTSEL ldtrPadding;
275 /** The task register. */
276 RTSEL tr;
277 RTSEL trPadding;
278
279 /** MSRs
280 * @{ */
281 CPUMSYSENTER SysEnter;
282 uint64_t FSbase;
283 uint64_t GSbase;
284 uint64_t efer;
285 /** @} */
286
287 /* padding to get 64byte aligned size */
288 uint8_t auPadding[8];
289
290#if HC_ARCH_BITS != 64
291# error HC_ARCH_BITS not defined or unsupported
292#endif
293
294 /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
295 R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
296 /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
297 R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
298 /** The XCR0 register. */
299 uint64_t xcr0;
300 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
301 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
302 uint64_t fXStateMask;
303} CPUMHOSTCTX;
304#ifndef VBOX_FOR_DTRACE_LIB
305AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
306#endif
307/** Pointer to the saved host CPU state. */
308typedef CPUMHOSTCTX *PCPUMHOSTCTX;
309
310
311/**
312 * The hypervisor context CPU state (just DRx left now).
313 */
314typedef struct CPUMHYPERCTX
315{
316 /** Debug registers.
317 * @remarks DR4 and DR5 should not be used since they are aliases for
318 * DR6 and DR7 respectively on both AMD and Intel CPUs.
319 * @remarks DR8-15 are currently not supported by AMD or Intel, so
320 * neither do we.
321 */
322 uint64_t dr[8];
323 /** @todo eliminiate the rest. */
324 uint64_t cr3;
325 uint64_t au64Padding[7];
326} CPUMHYPERCTX;
327#ifndef VBOX_FOR_DTRACE_LIB
328AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
329#endif
330/** Pointer to the hypervisor context CPU state. */
331typedef CPUMHYPERCTX *PCPUMHYPERCTX;
332
333
334/**
335 * CPUM Data (part of VM)
336 */
337typedef struct CPUM
338{
339 /** Use flags.
340 * These flags indicates which CPU features the host uses.
341 */
342 uint32_t fHostUseFlags;
343
344 /** CR4 mask
345 * @todo obsolete? */
346 struct
347 {
348 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
349 uint32_t OrMask;
350 } CR4;
351
352 /** The (more) portable CPUID level. */
353 uint8_t u8PortableCpuIdLevel;
354 /** Indicates that a state restore is pending.
355 * This is used to verify load order dependencies (PGM). */
356 bool fPendingRestore;
357 uint8_t abPadding0[2];
358
359 /** XSAVE/XRTOR components we can expose to the guest mask. */
360 uint64_t fXStateGuestMask;
361 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
362 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
363 uint64_t fXStateHostMask;
364
365 /** The host MXCSR mask (determined at init). */
366 uint32_t fHostMxCsrMask;
367 /** Nested VMX: Whether to expose VMX-preemption timer to the guest. */
368 bool fNestedVmxPreemptTimer;
369 uint8_t abPadding1[3];
370
371 /** Align to 64-byte boundary. */
372 uint8_t abPadding2[20+4];
373
374 /** Host CPU feature information.
375 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
376 CPUMFEATURES HostFeatures;
377 /** Guest CPU feature information.
378 * Externaly visible via that VM structure, aligned with HostFeatures. */
379 CPUMFEATURES GuestFeatures;
380 /** Guest CPU info. */
381 CPUMINFO GuestInfo;
382
383 /** The standard set of CpuId leaves. */
384 CPUMCPUID aGuestCpuIdPatmStd[6];
385 /** The extended set of CpuId leaves. */
386 CPUMCPUID aGuestCpuIdPatmExt[10];
387 /** The centaur set of CpuId leaves. */
388 CPUMCPUID aGuestCpuIdPatmCentaur[4];
389
390 /** @name MSR statistics.
391 * @{ */
392 STAMCOUNTER cMsrWrites;
393 STAMCOUNTER cMsrWritesToIgnoredBits;
394 STAMCOUNTER cMsrWritesRaiseGp;
395 STAMCOUNTER cMsrWritesUnknown;
396 STAMCOUNTER cMsrReads;
397 STAMCOUNTER cMsrReadsRaiseGp;
398 STAMCOUNTER cMsrReadsUnknown;
399 /** @} */
400} CPUM;
401#ifndef VBOX_FOR_DTRACE_LIB
402AssertCompileMemberOffset(CPUM, HostFeatures, 64);
403AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
404#endif
405/** Pointer to the CPUM instance data residing in the shared VM structure. */
406typedef CPUM *PCPUM;
407
408/**
409 * CPUM Data (part of VMCPU)
410 */
411typedef struct CPUMCPU
412{
413 /**
414 * Guest context.
415 * Aligned on a 64-byte boundary.
416 */
417 CPUMCTX Guest;
418
419 /**
420 * Guest context - misc MSRs
421 * Aligned on a 64-byte boundary.
422 */
423 CPUMCTXMSRS GuestMsrs;
424
425 /** Nested VMX: VMX-preemption timer - R0 ptr. */
426 PTMTIMERR0 pNestedVmxPreemptTimerR0;
427 /** Nested VMX: VMX-preemption timer - R3 ptr. */
428 PTMTIMERR3 pNestedVmxPreemptTimerR3;
429
430 /** Use flags.
431 * These flags indicates both what is to be used and what has been used.
432 */
433 uint32_t fUseFlags;
434
435 /** Changed flags.
436 * These flags indicates to REM (and others) which important guest
437 * registers which has been changed since last time the flags were cleared.
438 * See the CPUM_CHANGED_* defines for what we keep track of.
439 */
440 uint32_t fChanged;
441
442 /** Temporary storage for the return code of the function called in the
443 * 32-64 switcher. */
444 uint32_t u32RetCode;
445
446#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
447 /** Used by the world switcher code to store which vectors needs restoring on
448 * the way back. */
449 uint32_t fApicDisVectors;
450 /** The address of the APIC mapping, NULL if no APIC.
451 * Call CPUMR0SetLApic to update this before doing a world switch. */
452 RTHCPTR pvApicBase;
453 /** Set if the CPU has the X2APIC mode enabled.
454 * Call CPUMR0SetLApic to update this before doing a world switch. */
455 bool fX2Apic;
456#else
457 uint8_t abPadding3[4 + sizeof(RTHCPTR) + 1];
458#endif
459
460 /** Have we entered the recompiler? */
461 bool fRemEntered;
462 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
463 * (?) bits are visible or not. (The APIC is responsible for setting this
464 * when loading state, so we won't save it.) */
465 bool fCpuIdApicFeatureVisible;
466
467 /** Align the next member on a 64-byte boundary. */
468 uint8_t abPadding2[64 - (16 + 12 + 4 + 8 + 1 + 2)];
469
470 /** Saved host context. Only valid while inside RC or HM contexts.
471 * Must be aligned on a 64-byte boundary. */
472 CPUMHOSTCTX Host;
473 /** Old hypervisor context, only used for combined DRx values now.
474 * Must be aligned on a 64-byte boundary. */
475 CPUMHYPERCTX Hyper;
476
477#ifdef VBOX_WITH_CRASHDUMP_MAGIC
478 uint8_t aMagic[56];
479 uint64_t uMagic;
480#endif
481} CPUMCPU;
482/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
483typedef CPUMCPU *PCPUMCPU;
484
485#ifndef VBOX_FOR_DTRACE_LIB
486RT_C_DECLS_BEGIN
487
488PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
489PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
490
491# ifdef IN_RING3
492int cpumR3DbgInit(PVM pVM);
493int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures);
494int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
495void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs);
496void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
497int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
498int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
499DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
500
501int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
502int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
503int cpumR3MsrReconcileWithCpuId(PVM pVM);
504int cpumR3MsrApplyFudge(PVM pVM);
505int cpumR3MsrRegStats(PVM pVM);
506int cpumR3MsrStrictInitChecks(void);
507PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
508# endif
509
510# ifdef IN_RC
511DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
512# endif
513
514# ifdef IN_RING0
515DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
516DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
517# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
518DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
519# endif
520# endif
521
522# if defined(IN_RC) || defined(IN_RING0)
523DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
524DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
525DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
526DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
527# endif
528
529RT_C_DECLS_END
530#endif /* !VBOX_FOR_DTRACE_LIB */
531
532/** @} */
533
534#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
535
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