1 | /* $Id: CPUMInternal.h 55466 2015-04-28 00:10:51Z vboxsync $ */
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2 | /** @file
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3 | * CPUM - Internal header file.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2015 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 | #ifndef ___CPUMInternal_h
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19 | #define ___CPUMInternal_h
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20 |
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21 | #ifndef VBOX_FOR_DTRACE_LIB
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22 | # include <VBox/cdefs.h>
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23 | # include <VBox/types.h>
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24 | # include <VBox/vmm/stam.h>
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25 | # include <iprt/x86.h>
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26 | #else
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27 | # pragma D depends_on library x86.d
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28 | # pragma D depends_on library cpumctx.d
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29 |
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30 | /* Some fudging. */
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31 | typedef uint32_t CPUMMICROARCH;
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32 | typedef uint32_t CPUMUNKNOWNCPUID;
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33 | typedef struct CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
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34 | typedef struct CPUMMSRRANGE *PCPUMMSRRANGE;
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35 | typedef uint64_t STAMCOUNTER;
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36 | #endif
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37 |
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38 |
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39 |
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40 |
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41 | /** @defgroup grp_cpum_int Internals
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42 | * @ingroup grp_cpum
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43 | * @internal
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44 | * @{
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45 | */
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46 |
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47 | /** Flags and types for CPUM fault handlers
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48 | * @{ */
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49 | /** Type: Load DS */
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50 | #define CPUM_HANDLER_DS 1
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51 | /** Type: Load ES */
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52 | #define CPUM_HANDLER_ES 2
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53 | /** Type: Load FS */
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54 | #define CPUM_HANDLER_FS 3
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55 | /** Type: Load GS */
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56 | #define CPUM_HANDLER_GS 4
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57 | /** Type: IRET */
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58 | #define CPUM_HANDLER_IRET 5
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59 | /** Type mask. */
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60 | #define CPUM_HANDLER_TYPEMASK 0xff
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61 | /** If set EBP points to the CPUMCTXCORE that's being used. */
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62 | #define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
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63 | /** @} */
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64 |
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65 |
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66 | /** Use flags (CPUM::fUseFlags).
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67 | * (Don't forget to sync this with CPUMInternal.mac !)
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68 | * @{ */
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69 | /** Used the FPU, SSE or such stuff. */
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70 | #define CPUM_USED_FPU RT_BIT(0)
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71 | /** Used the FPU, SSE or such stuff since last we were in REM.
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72 | * REM syncing is clearing this, lazy FPU is setting it. */
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73 | #define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
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74 | /** The XMM state was manually restored. (AMD only) */
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75 | #define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
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76 |
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77 | /** Host OS is using SYSENTER and we must NULL the CS. */
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78 | #define CPUM_USE_SYSENTER RT_BIT(3)
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79 | /** Host OS is using SYSENTER and we must NULL the CS. */
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80 | #define CPUM_USE_SYSCALL RT_BIT(4)
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81 |
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82 | /** Debug registers are used by host and that DR7 and DR6 must be saved and
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83 | * disabled when switching to raw-mode. */
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84 | #define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
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85 | /** Records that we've saved the host DRx registers.
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86 | * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
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87 | * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
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88 | #define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
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89 | /** Set to indicate that we should save host DR0-7 and load the hypervisor debug
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90 | * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
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91 | #define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
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92 | /** Used in ring-0 to indicate that we have loaded the hypervisor debug
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93 | * registers. */
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94 | #define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
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95 | /** Used in ring-0 to indicate that we have loaded the guest debug
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96 | * registers (DR0-3 and maybe DR6) for direct use by the guest.
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97 | * DR7 (and AMD-V DR6) are handled via the VMCB. */
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98 | #define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
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99 |
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100 |
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101 | /** Sync the FPU state on next entry (32->64 switcher only). */
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102 | #define CPUM_SYNC_FPU_STATE RT_BIT(16)
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103 | /** Sync the debug state on next entry (32->64 switcher only). */
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104 | #define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
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105 | /** Sync the debug state on next entry (32->64 switcher only).
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106 | * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
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107 | #define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
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108 | /** Host CPU requires fxsave/fxrstor leaky bit handling. */
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109 | #define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
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110 | /** Set if the VM supports long-mode. */
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111 | #define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
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112 | /** @} */
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113 |
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114 | /* Sanity check. */
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115 | #ifndef VBOX_FOR_DTRACE_LIB
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116 | #if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 || R0_ARCH_BITS != 32)
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117 | # error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
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118 | #endif
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119 | #endif
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120 |
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121 |
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122 | /** @name CPUM Saved State Version.
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123 | * @{ */
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124 | /** The current saved state version. */
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125 | #define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_XSAVE
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126 | /** The saved state version including XSAVE state. */
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127 | #define CPUM_SAVED_STATE_VERSION_XSAVE 17
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128 | /** The saved state version with good CPUID leaf count. */
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129 | #define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
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130 | /** CPUID changes with explode forgetting to update the leaf count on
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131 | * restore, resulting in garbage being saved restoring+saving old states). */
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132 | #define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
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133 | /** The saved state version before the CPUIDs changes. */
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134 | #define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
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135 | /** The saved state version before using SSMR3PutStruct. */
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136 | #define CPUM_SAVED_STATE_VERSION_MEM 13
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137 | /** The saved state version before introducing the MSR size field. */
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138 | #define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
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139 | /** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
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140 | * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
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141 | #define CPUM_SAVED_STATE_VERSION_VER3_2 11
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142 | /** The saved state version of 3.0 and 3.1 trunk before the teleportation
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143 | * changes. */
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144 | #define CPUM_SAVED_STATE_VERSION_VER3_0 10
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145 | /** The saved state version for the 2.1 trunk before the MSR changes. */
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146 | #define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
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147 | /** The saved state version of 2.0, used for backwards compatibility. */
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148 | #define CPUM_SAVED_STATE_VERSION_VER2_0 8
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149 | /** The saved state version of 1.6, used for backwards compatibility. */
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150 | #define CPUM_SAVED_STATE_VERSION_VER1_6 6
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151 | /** @} */
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152 |
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153 |
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154 | /**
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155 | * CPU info
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156 | */
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157 | typedef struct CPUMINFO
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158 | {
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159 | /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
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160 | uint32_t cMsrRanges;
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161 | /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
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162 | * instruction. Older hardware has been observed to ignore higher bits. */
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163 | uint32_t fMsrMask;
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164 |
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165 | /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
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166 | uint32_t cCpuIdLeaves;
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167 | /** The index of the first extended CPUID leaf in the array.
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168 | * Set to cCpuIdLeaves if none present. */
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169 | uint32_t iFirstExtCpuIdLeaf;
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170 | /** Alignment padding. */
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171 | uint32_t uPadding;
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172 | /** How to handle unknown CPUID leaves. */
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173 | CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
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174 | /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
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175 | * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
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176 | CPUMCPUID DefCpuId;
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177 |
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178 | /** Scalable bus frequency used for reporting other frequencies. */
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179 | uint64_t uScalableBusFreq;
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180 |
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181 | /** Pointer to the MSR ranges (ring-0 pointer). */
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182 | R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
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183 | /** Pointer to the CPUID leaves (ring-0 pointer). */
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184 | R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
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185 |
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186 | /** Pointer to the MSR ranges (ring-3 pointer). */
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187 | R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
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188 | /** Pointer to the CPUID leaves (ring-3 pointer). */
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189 | R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
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190 |
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191 | /** Pointer to the MSR ranges (raw-mode context pointer). */
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192 | RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
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193 | /** Pointer to the CPUID leaves (raw-mode context pointer). */
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194 | RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
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195 | } CPUMINFO;
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196 | /** Pointer to a CPU info structure. */
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197 | typedef CPUMINFO *PCPUMINFO;
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198 | /** Pointer to a const CPU info structure. */
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199 | typedef CPUMINFO const *CPCPUMINFO;
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200 |
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201 |
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202 | /**
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203 | * The saved host CPU state.
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204 | *
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205 | * @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
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206 | * of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
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207 | */
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208 | typedef struct CPUMHOSTCTX
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209 | {
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210 | /** General purpose register, selectors, flags and more
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211 | * @{ */
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212 | #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
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213 | /** General purpose register ++
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214 | * { */
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215 | /*uint64_t rax; - scratch*/
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216 | uint64_t rbx;
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217 | /*uint64_t rcx; - scratch*/
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218 | /*uint64_t rdx; - scratch*/
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219 | uint64_t rdi;
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220 | uint64_t rsi;
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221 | uint64_t rbp;
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222 | uint64_t rsp;
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223 | /*uint64_t r8; - scratch*/
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224 | /*uint64_t r9; - scratch*/
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225 | uint64_t r10;
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226 | uint64_t r11;
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227 | uint64_t r12;
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228 | uint64_t r13;
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229 | uint64_t r14;
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230 | uint64_t r15;
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231 | /*uint64_t rip; - scratch*/
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232 | uint64_t rflags;
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233 | #endif
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234 |
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235 | #if HC_ARCH_BITS == 32
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236 | /*uint32_t eax; - scratch*/
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237 | uint32_t ebx;
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238 | /*uint32_t ecx; - scratch*/
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239 | /*uint32_t edx; - scratch*/
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240 | uint32_t edi;
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241 | uint32_t esi;
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242 | uint32_t ebp;
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243 | X86EFLAGS eflags;
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244 | /*uint32_t eip; - scratch*/
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245 | /* lss pair! */
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246 | uint32_t esp;
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247 | #endif
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248 | /** @} */
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249 |
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250 | /** Selector registers
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251 | * @{ */
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252 | RTSEL ss;
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253 | RTSEL ssPadding;
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254 | RTSEL gs;
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255 | RTSEL gsPadding;
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256 | RTSEL fs;
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257 | RTSEL fsPadding;
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258 | RTSEL es;
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259 | RTSEL esPadding;
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260 | RTSEL ds;
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261 | RTSEL dsPadding;
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262 | RTSEL cs;
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263 | RTSEL csPadding;
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264 | /** @} */
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265 |
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266 | #if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
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267 | /** Control registers.
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268 | * @{ */
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269 | uint32_t cr0;
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270 | /*uint32_t cr2; - scratch*/
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271 | uint32_t cr3;
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272 | uint32_t cr4;
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273 | /** @} */
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274 |
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275 | /** Debug registers.
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276 | * @{ */
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277 | uint32_t dr0;
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278 | uint32_t dr1;
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279 | uint32_t dr2;
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280 | uint32_t dr3;
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281 | uint32_t dr6;
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282 | uint32_t dr7;
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283 | /** @} */
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284 |
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285 | /** Global Descriptor Table register. */
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286 | X86XDTR32 gdtr;
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287 | uint16_t gdtrPadding;
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288 | /** Interrupt Descriptor Table register. */
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289 | X86XDTR32 idtr;
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290 | uint16_t idtrPadding;
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291 | /** The task register. */
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292 | RTSEL ldtr;
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293 | RTSEL ldtrPadding;
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294 | /** The task register. */
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295 | RTSEL tr;
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296 | RTSEL trPadding;
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297 | uint32_t SysEnterPadding;
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298 |
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299 | /** The sysenter msr registers.
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300 | * This member is not used by the hypervisor context. */
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301 | CPUMSYSENTER SysEnter;
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302 |
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303 | /** MSRs
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304 | * @{ */
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305 | uint64_t efer;
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306 | /** @} */
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307 |
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308 | /* padding to get 64byte aligned size */
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309 | uint8_t auPadding[20];
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310 |
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311 | #elif HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
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312 |
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313 | /** Control registers.
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314 | * @{ */
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315 | uint64_t cr0;
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316 | /*uint64_t cr2; - scratch*/
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317 | uint64_t cr3;
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318 | uint64_t cr4;
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319 | uint64_t cr8;
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320 | /** @} */
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321 |
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322 | /** Debug registers.
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323 | * @{ */
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324 | uint64_t dr0;
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325 | uint64_t dr1;
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326 | uint64_t dr2;
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327 | uint64_t dr3;
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328 | uint64_t dr6;
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329 | uint64_t dr7;
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330 | /** @} */
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331 |
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332 | /** Global Descriptor Table register. */
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333 | X86XDTR64 gdtr;
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334 | uint16_t gdtrPadding;
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335 | /** Interrupt Descriptor Table register. */
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336 | X86XDTR64 idtr;
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337 | uint16_t idtrPadding;
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338 | /** The task register. */
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339 | RTSEL ldtr;
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340 | RTSEL ldtrPadding;
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341 | /** The task register. */
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342 | RTSEL tr;
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343 | RTSEL trPadding;
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344 |
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345 | /** MSRs
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346 | * @{ */
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347 | CPUMSYSENTER SysEnter;
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348 | uint64_t FSbase;
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349 | uint64_t GSbase;
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350 | uint64_t efer;
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351 | /** @} */
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352 |
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353 | /* padding to get 32byte aligned size */
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354 | # ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
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355 | uint8_t auPadding[52];
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356 | # else
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357 | uint8_t auPadding[4];
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358 | # endif
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359 |
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360 | #else
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361 | # error HC_ARCH_BITS not defined
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362 | #endif
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363 |
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364 | /** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
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365 | RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
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366 | /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
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367 | R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
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368 | /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
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369 | R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
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370 | /** The XCR0 register. */
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371 | uint64_t xcr0;
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372 | /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
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373 | * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
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374 | uint64_t fXStateMask;
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375 | } CPUMHOSTCTX;
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376 | AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
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377 | /** Pointer to the saved host CPU state. */
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378 | typedef CPUMHOSTCTX *PCPUMHOSTCTX;
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379 |
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380 |
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381 | /**
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382 | * CPUM Data (part of VM)
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383 | */
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384 | typedef struct CPUM
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385 | {
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386 | /** Offset from CPUM to CPUMCPU for the first CPU. */
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387 | uint32_t offCPUMCPU0;
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388 |
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389 | /** Use flags.
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390 | * These flags indicates which CPU features the host uses.
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391 | */
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392 | uint32_t fHostUseFlags;
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393 |
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394 | /** CR4 mask */
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395 | struct
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396 | {
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397 | uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
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398 | uint32_t OrMask;
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399 | } CR4;
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400 |
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401 | /** The (more) portable CPUID level. */
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402 | uint8_t u8PortableCpuIdLevel;
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403 | /** Indicates that a state restore is pending.
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404 | * This is used to verify load order dependencies (PGM). */
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405 | bool fPendingRestore;
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406 | uint8_t abPadding0[6];
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407 |
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408 | /** XSAVE/XRTOR components we can expose to the guest mask. */
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409 | uint64_t fXStateGuestMask;
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410 | /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
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411 | * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
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412 | uint64_t fXStateHostMask;
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413 | uint8_t abPadding1[24];
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414 |
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415 | /** Host CPU feature information.
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416 | * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
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417 | CPUMFEATURES HostFeatures;
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418 | /** Guest CPU feature information.
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419 | * Externaly visible via that VM structure, aligned with HostFeatures. */
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420 | CPUMFEATURES GuestFeatures;
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421 | /** Guest CPU info. */
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422 | CPUMINFO GuestInfo;
|
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423 |
|
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424 |
|
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425 | /** The standard set of CpuId leaves. */
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426 | CPUMCPUID aGuestCpuIdPatmStd[6];
|
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427 | /** The extended set of CpuId leaves. */
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428 | CPUMCPUID aGuestCpuIdPatmExt[10];
|
---|
429 | /** The centaur set of CpuId leaves. */
|
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430 | CPUMCPUID aGuestCpuIdPatmCentaur[4];
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431 |
|
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432 | /** @name MSR statistics.
|
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433 | * @{ */
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434 | STAMCOUNTER cMsrWrites;
|
---|
435 | STAMCOUNTER cMsrWritesToIgnoredBits;
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436 | STAMCOUNTER cMsrWritesRaiseGp;
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437 | STAMCOUNTER cMsrWritesUnknown;
|
---|
438 | STAMCOUNTER cMsrReads;
|
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439 | STAMCOUNTER cMsrReadsRaiseGp;
|
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440 | STAMCOUNTER cMsrReadsUnknown;
|
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441 | /** @} */
|
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442 | } CPUM;
|
---|
443 | AssertCompileMemberOffset(CPUM, HostFeatures, 64);
|
---|
444 | AssertCompileMemberOffset(CPUM, GuestFeatures, 96);
|
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445 | /** Pointer to the CPUM instance data residing in the shared VM structure. */
|
---|
446 | typedef CPUM *PCPUM;
|
---|
447 |
|
---|
448 | /**
|
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449 | * CPUM Data (part of VMCPU)
|
---|
450 | */
|
---|
451 | typedef struct CPUMCPU
|
---|
452 | {
|
---|
453 | /**
|
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454 | * Guest context.
|
---|
455 | * Aligned on a 64-byte boundary.
|
---|
456 | */
|
---|
457 | CPUMCTX Guest;
|
---|
458 |
|
---|
459 | /**
|
---|
460 | * Guest context - misc MSRs
|
---|
461 | * Aligned on a 64-byte boundary.
|
---|
462 | */
|
---|
463 | CPUMCTXMSRS GuestMsrs;
|
---|
464 |
|
---|
465 | /** Use flags.
|
---|
466 | * These flags indicates both what is to be used and what has been used.
|
---|
467 | */
|
---|
468 | uint32_t fUseFlags;
|
---|
469 |
|
---|
470 | /** Changed flags.
|
---|
471 | * These flags indicates to REM (and others) which important guest
|
---|
472 | * registers which has been changed since last time the flags were cleared.
|
---|
473 | * See the CPUM_CHANGED_* defines for what we keep track of.
|
---|
474 | */
|
---|
475 | uint32_t fChanged;
|
---|
476 |
|
---|
477 | /** Offset from CPUM to CPUMCPU. */
|
---|
478 | uint32_t offCPUM;
|
---|
479 |
|
---|
480 | /** Temporary storage for the return code of the function called in the
|
---|
481 | * 32-64 switcher. */
|
---|
482 | uint32_t u32RetCode;
|
---|
483 |
|
---|
484 | #ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
|
---|
485 | /** The address of the APIC mapping, NULL if no APIC.
|
---|
486 | * Call CPUMR0SetLApic to update this before doing a world switch. */
|
---|
487 | RTHCPTR pvApicBase;
|
---|
488 | /** Used by the world switcher code to store which vectors needs restoring on
|
---|
489 | * the way back. */
|
---|
490 | uint32_t fApicDisVectors;
|
---|
491 | /** Set if the CPU has the X2APIC mode enabled.
|
---|
492 | * Call CPUMR0SetLApic to update this before doing a world switch. */
|
---|
493 | bool fX2Apic;
|
---|
494 | #else
|
---|
495 | uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
|
---|
496 | #endif
|
---|
497 |
|
---|
498 | /** Have we entered raw-mode? */
|
---|
499 | bool fRawEntered;
|
---|
500 | /** Have we entered the recompiler? */
|
---|
501 | bool fRemEntered;
|
---|
502 |
|
---|
503 | /** Align the next member on a 64-bit boundrary. */
|
---|
504 | uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
|
---|
505 |
|
---|
506 | /** Saved host context. Only valid while inside RC or HM contexts.
|
---|
507 | * Must be aligned on a 64-byte boundary. */
|
---|
508 | CPUMHOSTCTX Host;
|
---|
509 | /** Hypervisor context. Must be aligned on a 64-byte boundary. */
|
---|
510 | CPUMCTX Hyper;
|
---|
511 |
|
---|
512 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
---|
513 | uint8_t aMagic[56];
|
---|
514 | uint64_t uMagic;
|
---|
515 | #endif
|
---|
516 | } CPUMCPU;
|
---|
517 | /** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
|
---|
518 | typedef CPUMCPU *PCPUMCPU;
|
---|
519 |
|
---|
520 | #ifndef VBOX_FOR_DTRACE_LIB
|
---|
521 | RT_C_DECLS_BEGIN
|
---|
522 |
|
---|
523 | PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
|
---|
524 | PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
|
---|
525 |
|
---|
526 | #ifdef IN_RING3
|
---|
527 | int cpumR3DbgInit(PVM pVM);
|
---|
528 | int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
|
---|
529 | int cpumR3InitCpuIdAndMsrs(PVM pVM);
|
---|
530 | void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
|
---|
531 | int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
|
---|
532 | int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
|
---|
533 | DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
|
---|
534 |
|
---|
535 | int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
|
---|
536 | int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
|
---|
537 | int cpumR3MsrApplyFudge(PVM pVM);
|
---|
538 | int cpumR3MsrRegStats(PVM pVM);
|
---|
539 | int cpumR3MsrStrictInitChecks(void);
|
---|
540 | PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
|
---|
541 | #endif
|
---|
542 |
|
---|
543 | #ifdef IN_RC
|
---|
544 | DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
|
---|
545 | #endif
|
---|
546 |
|
---|
547 | #ifdef IN_RING0
|
---|
548 | DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
|
---|
549 | DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
|
---|
550 | DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
|
---|
551 | DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
|
---|
552 | DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
|
---|
553 | DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
|
---|
554 | DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
|
---|
555 | DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
|
---|
556 | DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
|
---|
557 | DECLASM(uint16_t) cpumR0GetFCW(void);
|
---|
558 | DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
|
---|
559 | DECLASM(uint32_t) cpumR0GetMXCSR(void);
|
---|
560 | DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
|
---|
561 | DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
|
---|
562 | #endif
|
---|
563 |
|
---|
564 | RT_C_DECLS_END
|
---|
565 | #endif /* !VBOX_FOR_DTRACE_LIB */
|
---|
566 |
|
---|
567 | /** @} */
|
---|
568 |
|
---|
569 | #endif
|
---|
570 |
|
---|