CPUMInternal.h@ 47786

Last change on this file since 47786 was 47660, checked in by vboxsync, 11 years ago
VMM: Debug register handling redo. (only partly tested on AMD-V so far.)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 12.8 KB

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1	/* $Id: CPUMInternal.h 47660 2013-08-12 00:37:34Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___CPUMInternal_h
19	#define ___CPUMInternal_h
20
21	#ifndef VBOX_FOR_DTRACE_LIB
22	# include <VBox/cdefs.h>
23	# include <VBox/types.h>
24	# include <iprt/x86.h>
25	#else
26	# pragma D depends_on library x86.d
27	# pragma D depends_on library cpumctx.d
28	#endif
29
30
31
32
33	/** @defgroup grp_cpum_int Internals
34	* @ingroup grp_cpum
35	* @internal
36	* @{
37	*/
38
39	/** Flags and types for CPUM fault handlers
40	* @{ */
41	/** Type: Load DS */
42	#define CPUM_HANDLER_DS 1
43	/** Type: Load ES */
44	#define CPUM_HANDLER_ES 2
45	/** Type: Load FS */
46	#define CPUM_HANDLER_FS 3
47	/** Type: Load GS */
48	#define CPUM_HANDLER_GS 4
49	/** Type: IRET */
50	#define CPUM_HANDLER_IRET 5
51	/** Type mask. */
52	#define CPUM_HANDLER_TYPEMASK 0xff
53	/** If set EBP points to the CPUMCTXCORE that's being used. */
54	#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
55	/** @} */
56
57
58	/** Use flags (CPUM::fUseFlags).
59	* (Don't forget to sync this with CPUMInternal.mac !)
60	* @{ */
61	/** Used the FPU, SSE or such stuff. */
62	#define CPUM_USED_FPU RT_BIT(0)
63	/** Used the FPU, SSE or such stuff since last we were in REM.
64	* REM syncing is clearing this, lazy FPU is setting it. */
65	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
66	/** The XMM state was manually restored. (AMD only) */
67	#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
68
69	/** Host OS is using SYSENTER and we must NULL the CS. */
70	#define CPUM_USE_SYSENTER RT_BIT(3)
71	/** Host OS is using SYSENTER and we must NULL the CS. */
72	#define CPUM_USE_SYSCALL RT_BIT(4)
73
74	/** Debug registers are used by host and that DR7 and DR6 must be saved and
75	* disabled when switching to raw-mode. */
76	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
77	/** Records that we've saved the host DRx registers.
78	* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
79	* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
80	#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
81	/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
82	* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
83	#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
84	/** Used in ring-0 to indicate that we have loaded the hypervisor debug
85	* registers. */
86	#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
87	/** Used in ring-0 to indicate that we have loaded the guest debug
88	* registers (DR0-3 and maybe DR6) for direct use by the guest.
89	* DR7 (and AMD-V DR6) are handled via the VMCB. */
90	#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
91
92
93	/** Sync the FPU state on next entry (32->64 switcher only). */
94	#define CPUM_SYNC_FPU_STATE RT_BIT(16)
95	/** Sync the debug state on next entry (32->64 switcher only). */
96	#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
97	/** Sync the debug state on next entry (32->64 switcher only).
98	* Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
99	#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
100	/** @} */
101
102	/* Sanity check. */
103	#ifndef VBOX_FOR_DTRACE_LIB
104	#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 \|\| R0_ARCH_BITS != 32)
105	# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
106	#endif
107	#endif
108
109
110	/**
111	* The saved host CPU state.
112	*
113	* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
114	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
115	*/
116	typedef struct CPUMHOSTCTX
117	{
118	/** FPU state. (16-byte alignment)
119	* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
120	X86FXSTATE fpu;
121
122	/** General purpose register, selectors, flags and more
123	* @{ */
124	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
125	/** General purpose register ++
126	* { */
127	/uint64_t rax; - scratch/
128	uint64_t rbx;
129	/uint64_t rcx; - scratch/
130	/uint64_t rdx; - scratch/
131	uint64_t rdi;
132	uint64_t rsi;
133	uint64_t rbp;
134	uint64_t rsp;
135	/uint64_t r8; - scratch/
136	/uint64_t r9; - scratch/
137	uint64_t r10;
138	uint64_t r11;
139	uint64_t r12;
140	uint64_t r13;
141	uint64_t r14;
142	uint64_t r15;
143	/uint64_t rip; - scratch/
144	uint64_t rflags;
145	#endif
146
147	#if HC_ARCH_BITS == 32
148	/uint32_t eax; - scratch/
149	uint32_t ebx;
150	/uint32_t ecx; - scratch/
151	/uint32_t edx; - scratch/
152	uint32_t edi;
153	uint32_t esi;
154	uint32_t ebp;
155	X86EFLAGS eflags;
156	/uint32_t eip; - scratch/
157	/* lss pair! */
158	uint32_t esp;
159	#endif
160	/** @} */
161
162	/** Selector registers
163	* @{ */
164	RTSEL ss;
165	RTSEL ssPadding;
166	RTSEL gs;
167	RTSEL gsPadding;
168	RTSEL fs;
169	RTSEL fsPadding;
170	RTSEL es;
171	RTSEL esPadding;
172	RTSEL ds;
173	RTSEL dsPadding;
174	RTSEL cs;
175	RTSEL csPadding;
176	/** @} */
177
178	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
179	/** Control registers.
180	* @{ */
181	uint32_t cr0;
182	/uint32_t cr2; - scratch/
183	uint32_t cr3;
184	uint32_t cr4;
185	/** @} */
186
187	/** Debug registers.
188	* @{ */
189	uint32_t dr0;
190	uint32_t dr1;
191	uint32_t dr2;
192	uint32_t dr3;
193	uint32_t dr6;
194	uint32_t dr7;
195	/** @} */
196
197	/** Global Descriptor Table register. */
198	X86XDTR32 gdtr;
199	uint16_t gdtrPadding;
200	/** Interrupt Descriptor Table register. */
201	X86XDTR32 idtr;
202	uint16_t idtrPadding;
203	/** The task register. */
204	RTSEL ldtr;
205	RTSEL ldtrPadding;
206	/** The task register. */
207	RTSEL tr;
208	RTSEL trPadding;
209	uint32_t SysEnterPadding;
210
211	/** The sysenter msr registers.
212	* This member is not used by the hypervisor context. */
213	CPUMSYSENTER SysEnter;
214
215	/** MSRs
216	* @{ */
217	uint64_t efer;
218	/** @} */
219
220	/* padding to get 64byte aligned size */
221	uint8_t auPadding[16+32];
222
223	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
224
225	/** Control registers.
226	* @{ */
227	uint64_t cr0;
228	/uint64_t cr2; - scratch/
229	uint64_t cr3;
230	uint64_t cr4;
231	uint64_t cr8;
232	/** @} */
233
234	/** Debug registers.
235	* @{ */
236	uint64_t dr0;
237	uint64_t dr1;
238	uint64_t dr2;
239	uint64_t dr3;
240	uint64_t dr6;
241	uint64_t dr7;
242	/** @} */
243
244	/** Global Descriptor Table register. */
245	X86XDTR64 gdtr;
246	uint16_t gdtrPadding;
247	/** Interrupt Descriptor Table register. */
248	X86XDTR64 idtr;
249	uint16_t idtrPadding;
250	/** The task register. */
251	RTSEL ldtr;
252	RTSEL ldtrPadding;
253	/** The task register. */
254	RTSEL tr;
255	RTSEL trPadding;
256
257	/** MSRs
258	* @{ */
259	CPUMSYSENTER SysEnter;
260	uint64_t FSbase;
261	uint64_t GSbase;
262	uint64_t efer;
263	/** @} */
264
265	/* padding to get 32byte aligned size */
266	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
267	uint8_t auPadding[16];
268	# else
269	uint8_t auPadding[8+32];
270	# endif
271
272	#else
273	# error HC_ARCH_BITS not defined
274	#endif
275	} CPUMHOSTCTX;
276	/** Pointer to the saved host CPU state. */
277	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
278
279
280	/**
281	* CPUM Data (part of VM)
282	*/
283	typedef struct CPUM
284	{
285	/** Offset from CPUM to CPUMCPU for the first CPU. */
286	uint32_t offCPUMCPU0;
287
288	/** Use flags.
289	* These flags indicates which CPU features the host uses.
290	*/
291	uint32_t fHostUseFlags;
292
293	/** Host CPU Features - ECX */
294	struct
295	{
296	/** edx part */
297	X86CPUIDFEATEDX edx;
298	/** ecx part */
299	X86CPUIDFEATECX ecx;
300	} CPUFeatures;
301	/** Host extended CPU features. */
302	struct
303	{
304	/** edx part */
305	uint32_t edx;
306	/** ecx part */
307	uint32_t ecx;
308	} CPUFeaturesExt;
309
310	/** Host CPU manufacturer. */
311	CPUMCPUVENDOR enmHostCpuVendor;
312	/** Guest CPU manufacturer. */
313	CPUMCPUVENDOR enmGuestCpuVendor;
314
315	/** CR4 mask */
316	struct
317	{
318	uint32_t AndMask;
319	uint32_t OrMask;
320	} CR4;
321
322	/** Synthetic CPU type? */
323	bool fSyntheticCpu;
324	/** The (more) portable CPUID level. */
325	uint8_t u8PortableCpuIdLevel;
326	/** Indicates that a state restore is pending.
327	* This is used to verify load order dependencies (PGM). */
328	bool fPendingRestore;
329	uint8_t abPadding[HC_ARCH_BITS == 64 ? 5 : 1];
330
331	/** The standard set of CpuId leaves. */
332	CPUMCPUID aGuestCpuIdStd[6];
333	/** The extended set of CpuId leaves. */
334	CPUMCPUID aGuestCpuIdExt[10];
335	/** The centaur set of CpuId leaves. */
336	CPUMCPUID aGuestCpuIdCentaur[4];
337	/** The hypervisor specific set of CpuId leaves. */
338	CPUMCPUID aGuestCpuIdHyper[4];
339	/** The default set of CpuId leaves. */
340	CPUMCPUID GuestCpuIdDef;
341
342	#if HC_ARCH_BITS == 32
343	uint8_t abPadding2[4];
344	#endif
345
346	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
347	RTHCPTR pvApicBase;
348	uint32_t fApicDisVectors;
349	uint8_t abPadding3[4];
350	#endif
351	} CPUM;
352	/** Pointer to the CPUM instance data residing in the shared VM structure. */
353	typedef CPUM *PCPUM;
354
355	/**
356	* CPUM Data (part of VMCPU)
357	*/
358	typedef struct CPUMCPU
359	{
360	/**
361	* Hypervisor context.
362	* Aligned on a 64-byte boundary.
363	*/
364	CPUMCTX Hyper;
365
366	/**
367	* Saved host context. Only valid while inside GC.
368	* Aligned on a 64-byte boundary.
369	*/
370	CPUMHOSTCTX Host;
371
372	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
373	uint8_t aMagic[56];
374	uint64_t uMagic;
375	#endif
376
377	/**
378	* Guest context.
379	* Aligned on a 64-byte boundary.
380	*/
381	CPUMCTX Guest;
382
383	/**
384	* Guest context - misc MSRs
385	* Aligned on a 64-byte boundary.
386	*/
387	CPUMCTXMSRS GuestMsrs;
388
389	/** Use flags.
390	* These flags indicates both what is to be used and what has been used.
391	*/
392	uint32_t fUseFlags;
393
394	/** Changed flags.
395	* These flags indicates to REM (and others) which important guest
396	* registers which has been changed since last time the flags were cleared.
397	* See the CPUM_CHANGED_* defines for what we keep track of.
398	*/
399	uint32_t fChanged;
400
401	/** Offset from CPUM to CPUMCPU. */
402	uint32_t offCPUM;
403
404	/** Temporary storage for the return code of the function called in the
405	* 32-64 switcher. */
406	uint32_t u32RetCode;
407
408	/** Have we entered raw-mode? */
409	bool fRawEntered;
410	/** Have we entered the recompiler? */
411	bool fRemEntered;
412
413	/** Align the structure on a 64-byte boundary. */
414	uint8_t abPadding2[64 - 16 - 2];
415	} CPUMCPU;
416	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
417	typedef CPUMCPU *PCPUMCPU;
418
419	#ifndef VBOX_FOR_DTRACE_LIB
420	RT_C_DECLS_BEGIN
421
422	#ifdef IN_RING3
423	int cpumR3DbgInit(PVM pVM);
424	#endif
425
426	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
427
428	#ifdef IN_RING0
429	DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
430	DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
431	DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
432	DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
433	DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
434	DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
435	DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
436	DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
437	DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
438	DECLASM(uint16_t) cpumR0GetFCW(void);
439	DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
440	DECLASM(uint32_t) cpumR0GetMXCSR(void);
441	DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
442	DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
443	#endif
444
445	RT_C_DECLS_END
446	#endif /* !VBOX_FOR_DTRACE_LIB */
447
448	/** @} */
449
450	#endif
451

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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 47786

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