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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 69288

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1/* $Id: CPUMInternal.h 69111 2017-10-17 14:26:02Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___CPUMInternal_h
19#define ___CPUMInternal_h
20
21#ifndef VBOX_FOR_DTRACE_LIB
22# include <VBox/cdefs.h>
23# include <VBox/types.h>
24# include <VBox/vmm/stam.h>
25# include <iprt/x86.h>
26#else
27# pragma D depends_on library x86.d
28# pragma D depends_on library cpumctx.d
29# pragma D depends_on library cpum.d
30
31/* Some fudging. */
32typedef uint64_t STAMCOUNTER;
33#endif
34
35
36
37
38/** @defgroup grp_cpum_int Internals
39 * @ingroup grp_cpum
40 * @internal
41 * @{
42 */
43
44/** Flags and types for CPUM fault handlers
45 * @{ */
46/** Type: Load DS */
47#define CPUM_HANDLER_DS 1
48/** Type: Load ES */
49#define CPUM_HANDLER_ES 2
50/** Type: Load FS */
51#define CPUM_HANDLER_FS 3
52/** Type: Load GS */
53#define CPUM_HANDLER_GS 4
54/** Type: IRET */
55#define CPUM_HANDLER_IRET 5
56/** Type mask. */
57#define CPUM_HANDLER_TYPEMASK 0xff
58/** If set EBP points to the CPUMCTXCORE that's being used. */
59#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
60/** @} */
61
62
63/** Use flags (CPUM::fUseFlags).
64 * (Don't forget to sync this with CPUMInternal.mac !)
65 * @note Part of saved state.
66 * @{ */
67/** Indicates that we've saved the host FPU, SSE, whatever state and that it
68 * needs to be restored. */
69#define CPUM_USED_FPU_HOST RT_BIT(0)
70/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
71 * needs to be saved. */
72#define CPUM_USED_FPU_GUEST RT_BIT(10)
73/** Used the guest FPU, SSE or such stuff since last we were in REM.
74 * REM syncing is clearing this, lazy FPU is setting it. */
75#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
76/** The XMM state was manually restored. (AMD only) */
77#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
78
79/** Host OS is using SYSENTER and we must NULL the CS. */
80#define CPUM_USE_SYSENTER RT_BIT(3)
81/** Host OS is using SYSENTER and we must NULL the CS. */
82#define CPUM_USE_SYSCALL RT_BIT(4)
83
84/** Debug registers are used by host and that DR7 and DR6 must be saved and
85 * disabled when switching to raw-mode. */
86#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
87/** Records that we've saved the host DRx registers.
88 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
89 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
90#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
91/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
92 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
93#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
94/** Used in ring-0 to indicate that we have loaded the hypervisor debug
95 * registers. */
96#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
97/** Used in ring-0 to indicate that we have loaded the guest debug
98 * registers (DR0-3 and maybe DR6) for direct use by the guest.
99 * DR7 (and AMD-V DR6) are handled via the VMCB. */
100#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
101
102/** Sync the FPU state on next entry (32->64 switcher only). */
103#define CPUM_SYNC_FPU_STATE RT_BIT(16)
104/** Sync the debug state on next entry (32->64 switcher only). */
105#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
106/** Sync the debug state on next entry (32->64 switcher only).
107 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
108#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
109/** Host CPU requires fxsave/fxrstor leaky bit handling. */
110#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
111/** Set if the VM supports long-mode. */
112#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
113/** @} */
114
115
116/** @name CPUM Saved State Version.
117 * @{ */
118/** The current saved state version. */
119#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_XSAVE
120/** The saved state version including XSAVE state. */
121#define CPUM_SAVED_STATE_VERSION_XSAVE 17
122/** The saved state version with good CPUID leaf count. */
123#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
124/** CPUID changes with explode forgetting to update the leaf count on
125 * restore, resulting in garbage being saved restoring+saving old states). */
126#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
127/** The saved state version before the CPUIDs changes. */
128#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
129/** The saved state version before using SSMR3PutStruct. */
130#define CPUM_SAVED_STATE_VERSION_MEM 13
131/** The saved state version before introducing the MSR size field. */
132#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
133/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
134 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
135#define CPUM_SAVED_STATE_VERSION_VER3_2 11
136/** The saved state version of 3.0 and 3.1 trunk before the teleportation
137 * changes. */
138#define CPUM_SAVED_STATE_VERSION_VER3_0 10
139/** The saved state version for the 2.1 trunk before the MSR changes. */
140#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
141/** The saved state version of 2.0, used for backwards compatibility. */
142#define CPUM_SAVED_STATE_VERSION_VER2_0 8
143/** The saved state version of 1.6, used for backwards compatibility. */
144#define CPUM_SAVED_STATE_VERSION_VER1_6 6
145/** @} */
146
147
148/**
149 * CPU info
150 */
151typedef struct CPUMINFO
152{
153 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
154 uint32_t cMsrRanges;
155 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
156 * instruction. Older hardware has been observed to ignore higher bits. */
157 uint32_t fMsrMask;
158
159 /** MXCSR mask. */
160 uint32_t fMxCsrMask;
161
162 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
163 uint32_t cCpuIdLeaves;
164 /** The index of the first extended CPUID leaf in the array.
165 * Set to cCpuIdLeaves if none present. */
166 uint32_t iFirstExtCpuIdLeaf;
167 /** How to handle unknown CPUID leaves. */
168 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
169 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
170 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
171 CPUMCPUID DefCpuId;
172
173 /** Scalable bus frequency used for reporting other frequencies. */
174 uint64_t uScalableBusFreq;
175
176 /** Pointer to the MSR ranges (ring-0 pointer). */
177 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
178 /** Pointer to the CPUID leaves (ring-0 pointer). */
179 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
180
181 /** Pointer to the MSR ranges (ring-3 pointer). */
182 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
183 /** Pointer to the CPUID leaves (ring-3 pointer). */
184 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
185
186 /** Pointer to the MSR ranges (raw-mode context pointer). */
187 RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
188 /** Pointer to the CPUID leaves (raw-mode context pointer). */
189 RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
190} CPUMINFO;
191/** Pointer to a CPU info structure. */
192typedef CPUMINFO *PCPUMINFO;
193/** Pointer to a const CPU info structure. */
194typedef CPUMINFO const *CPCPUMINFO;
195
196
197/**
198 * The saved host CPU state.
199 */
200typedef struct CPUMHOSTCTX
201{
202 /** General purpose register, selectors, flags and more
203 * @{ */
204#if HC_ARCH_BITS == 64
205 /** General purpose register ++
206 * { */
207 /*uint64_t rax; - scratch*/
208 uint64_t rbx;
209 /*uint64_t rcx; - scratch*/
210 /*uint64_t rdx; - scratch*/
211 uint64_t rdi;
212 uint64_t rsi;
213 uint64_t rbp;
214 uint64_t rsp;
215 /*uint64_t r8; - scratch*/
216 /*uint64_t r9; - scratch*/
217 uint64_t r10;
218 uint64_t r11;
219 uint64_t r12;
220 uint64_t r13;
221 uint64_t r14;
222 uint64_t r15;
223 /*uint64_t rip; - scratch*/
224 uint64_t rflags;
225#endif
226
227#if HC_ARCH_BITS == 32
228 /*uint32_t eax; - scratch*/
229 uint32_t ebx;
230 /*uint32_t ecx; - scratch*/
231 /*uint32_t edx; - scratch*/
232 uint32_t edi;
233 uint32_t esi;
234 uint32_t ebp;
235 X86EFLAGS eflags;
236 /*uint32_t eip; - scratch*/
237 /* lss pair! */
238 uint32_t esp;
239#endif
240 /** @} */
241
242 /** Selector registers
243 * @{ */
244 RTSEL ss;
245 RTSEL ssPadding;
246 RTSEL gs;
247 RTSEL gsPadding;
248 RTSEL fs;
249 RTSEL fsPadding;
250 RTSEL es;
251 RTSEL esPadding;
252 RTSEL ds;
253 RTSEL dsPadding;
254 RTSEL cs;
255 RTSEL csPadding;
256 /** @} */
257
258#if HC_ARCH_BITS == 32
259 /** Control registers.
260 * @{ */
261 uint32_t cr0;
262 /*uint32_t cr2; - scratch*/
263 uint32_t cr3;
264 uint32_t cr4;
265 /** The CR0 FPU state in HM mode. Can't use cr0 here because the
266 * 64-bit-on-32-bit-host world switches is using it. */
267 uint32_t cr0Fpu;
268 /** @} */
269
270 /** Debug registers.
271 * @{ */
272 uint32_t dr0;
273 uint32_t dr1;
274 uint32_t dr2;
275 uint32_t dr3;
276 uint32_t dr6;
277 uint32_t dr7;
278 /** @} */
279
280 /** Global Descriptor Table register. */
281 X86XDTR32 gdtr;
282 uint16_t gdtrPadding;
283 /** Interrupt Descriptor Table register. */
284 X86XDTR32 idtr;
285 uint16_t idtrPadding;
286 /** The task register. */
287 RTSEL ldtr;
288 RTSEL ldtrPadding;
289 /** The task register. */
290 RTSEL tr;
291 RTSEL trPadding;
292
293 /** The sysenter msr registers.
294 * This member is not used by the hypervisor context. */
295 CPUMSYSENTER SysEnter;
296
297 /** MSRs
298 * @{ */
299 uint64_t efer;
300 /** @} */
301
302 /* padding to get 64byte aligned size */
303 uint8_t auPadding[20];
304
305#elif HC_ARCH_BITS == 64
306
307 /** Control registers.
308 * @{ */
309 /** The CR0 FPU state in HM mode. */
310 uint64_t cr0;
311 /*uint64_t cr2; - scratch*/
312 uint64_t cr3;
313 uint64_t cr4;
314 uint64_t cr8;
315 /** @} */
316
317 /** Debug registers.
318 * @{ */
319 uint64_t dr0;
320 uint64_t dr1;
321 uint64_t dr2;
322 uint64_t dr3;
323 uint64_t dr6;
324 uint64_t dr7;
325 /** @} */
326
327 /** Global Descriptor Table register. */
328 X86XDTR64 gdtr;
329 uint16_t gdtrPadding;
330 /** Interrupt Descriptor Table register. */
331 X86XDTR64 idtr;
332 uint16_t idtrPadding;
333 /** The task register. */
334 RTSEL ldtr;
335 RTSEL ldtrPadding;
336 /** The task register. */
337 RTSEL tr;
338 RTSEL trPadding;
339
340 /** MSRs
341 * @{ */
342 CPUMSYSENTER SysEnter;
343 uint64_t FSbase;
344 uint64_t GSbase;
345 uint64_t efer;
346 /** @} */
347
348 /* padding to get 64byte aligned size */
349 uint8_t auPadding[4];
350
351#else
352# error HC_ARCH_BITS not defined or unsupported
353#endif
354
355 /** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
356 RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
357 /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
358 R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
359 /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
360 R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
361 /** The XCR0 register. */
362 uint64_t xcr0;
363 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
364 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
365 uint64_t fXStateMask;
366} CPUMHOSTCTX;
367#ifndef VBOX_FOR_DTRACE_LIB
368AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
369#endif
370/** Pointer to the saved host CPU state. */
371typedef CPUMHOSTCTX *PCPUMHOSTCTX;
372
373
374/**
375 * CPUM Data (part of VM)
376 */
377typedef struct CPUM
378{
379 /** Offset from CPUM to CPUMCPU for the first CPU. */
380 uint32_t offCPUMCPU0;
381
382 /** Use flags.
383 * These flags indicates which CPU features the host uses.
384 */
385 uint32_t fHostUseFlags;
386
387 /** CR4 mask */
388 struct
389 {
390 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
391 uint32_t OrMask;
392 } CR4;
393
394 /** The (more) portable CPUID level. */
395 uint8_t u8PortableCpuIdLevel;
396 /** Indicates that a state restore is pending.
397 * This is used to verify load order dependencies (PGM). */
398 bool fPendingRestore;
399 uint8_t abPadding0[6];
400
401 /** XSAVE/XRTOR components we can expose to the guest mask. */
402 uint64_t fXStateGuestMask;
403 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
404 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
405 uint64_t fXStateHostMask;
406
407 /** The host MXCSR mask (determined at init). */
408 uint32_t fHostMxCsrMask;
409 uint8_t abPadding1[20];
410
411 /** Host CPU feature information.
412 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
413 CPUMFEATURES HostFeatures;
414 /** Guest CPU feature information.
415 * Externaly visible via that VM structure, aligned with HostFeatures. */
416 CPUMFEATURES GuestFeatures;
417 /** Guest CPU info. */
418 CPUMINFO GuestInfo;
419
420
421 /** The standard set of CpuId leaves. */
422 CPUMCPUID aGuestCpuIdPatmStd[6];
423 /** The extended set of CpuId leaves. */
424 CPUMCPUID aGuestCpuIdPatmExt[10];
425 /** The centaur set of CpuId leaves. */
426 CPUMCPUID aGuestCpuIdPatmCentaur[4];
427
428 /** @name MSR statistics.
429 * @{ */
430 STAMCOUNTER cMsrWrites;
431 STAMCOUNTER cMsrWritesToIgnoredBits;
432 STAMCOUNTER cMsrWritesRaiseGp;
433 STAMCOUNTER cMsrWritesUnknown;
434 STAMCOUNTER cMsrReads;
435 STAMCOUNTER cMsrReadsRaiseGp;
436 STAMCOUNTER cMsrReadsUnknown;
437 /** @} */
438} CPUM;
439#ifndef VBOX_FOR_DTRACE_LIB
440AssertCompileMemberOffset(CPUM, HostFeatures, 64);
441AssertCompileMemberOffset(CPUM, GuestFeatures, 96);
442#endif
443/** Pointer to the CPUM instance data residing in the shared VM structure. */
444typedef CPUM *PCPUM;
445
446/**
447 * CPUM Data (part of VMCPU)
448 */
449typedef struct CPUMCPU
450{
451 /**
452 * Guest context.
453 * Aligned on a 64-byte boundary.
454 */
455 CPUMCTX Guest;
456
457 /**
458 * Guest context - misc MSRs
459 * Aligned on a 64-byte boundary.
460 */
461 CPUMCTXMSRS GuestMsrs;
462
463 /** Use flags.
464 * These flags indicates both what is to be used and what has been used.
465 */
466 uint32_t fUseFlags;
467
468 /** Changed flags.
469 * These flags indicates to REM (and others) which important guest
470 * registers which has been changed since last time the flags were cleared.
471 * See the CPUM_CHANGED_* defines for what we keep track of.
472 */
473 uint32_t fChanged;
474
475 /** Offset from CPUM to CPUMCPU. */
476 uint32_t offCPUM;
477
478 /** Temporary storage for the return code of the function called in the
479 * 32-64 switcher. */
480 uint32_t u32RetCode;
481
482#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
483 /** The address of the APIC mapping, NULL if no APIC.
484 * Call CPUMR0SetLApic to update this before doing a world switch. */
485 RTHCPTR pvApicBase;
486 /** Used by the world switcher code to store which vectors needs restoring on
487 * the way back. */
488 uint32_t fApicDisVectors;
489 /** Set if the CPU has the X2APIC mode enabled.
490 * Call CPUMR0SetLApic to update this before doing a world switch. */
491 bool fX2Apic;
492#else
493 uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
494#endif
495
496 /** Have we entered raw-mode? */
497 bool fRawEntered;
498 /** Have we entered the recompiler? */
499 bool fRemEntered;
500 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
501 * (?) bits are visible or not. (The APIC is responsible for setting this
502 * when loading state, so we won't save it.) */
503 bool fCpuIdApicFeatureVisible;
504
505 /** Align the next member on a 64-byte boundrary. */
506 uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 3];
507
508 /** Saved host context. Only valid while inside RC or HM contexts.
509 * Must be aligned on a 64-byte boundary. */
510 CPUMHOSTCTX Host;
511 /** Hypervisor context. Must be aligned on a 64-byte boundary. */
512 CPUMCTX Hyper;
513
514#ifdef VBOX_WITH_CRASHDUMP_MAGIC
515 uint8_t aMagic[56];
516 uint64_t uMagic;
517#endif
518} CPUMCPU;
519/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
520typedef CPUMCPU *PCPUMCPU;
521
522#ifndef VBOX_FOR_DTRACE_LIB
523RT_C_DECLS_BEGIN
524
525PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
526PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
527
528# ifdef IN_RING3
529int cpumR3DbgInit(PVM pVM);
530int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
531int cpumR3InitCpuIdAndMsrs(PVM pVM);
532void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
533int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
534int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
535DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
536
537int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
538int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
539int cpumR3MsrApplyFudge(PVM pVM);
540int cpumR3MsrRegStats(PVM pVM);
541int cpumR3MsrStrictInitChecks(void);
542PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
543# endif
544
545# ifdef IN_RC
546DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
547# endif
548
549# ifdef IN_RING0
550DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
551DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
552# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
553DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
554# endif
555# endif
556
557# if defined(IN_RC) || defined(IN_RING0)
558DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
559DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
560DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
561DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
562# endif
563
564RT_C_DECLS_END
565#endif /* !VBOX_FOR_DTRACE_LIB */
566
567/** @} */
568
569#endif
570
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