VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMTests.cpp@ 32131

Last change on this file since 32131 was 29250, checked in by vboxsync, 15 years ago

iprt/asm*.h: split out asm-math.h, don't include asm-*.h from asm.h, don't include asm.h from sup.h. Fixed a couple file headers.

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1/* $Id: VMMTests.cpp 29250 2010-05-09 17:53:58Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core, Tests.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18//#define NO_SUPCALLR0VMM
19
20/*******************************************************************************
21* Header Files *
22*******************************************************************************/
23#define LOG_GROUP LOG_GROUP_VMM
24#include <iprt/asm-amd64-x86.h> /* for SUPGetCpuHzFromGIP */
25#include <VBox/vmm.h>
26#include <VBox/pdmapi.h>
27#include <VBox/cpum.h>
28#include <VBox/dbg.h>
29#include <VBox/mm.h>
30#include <VBox/trpm.h>
31#include <VBox/selm.h>
32#include "VMMInternal.h"
33#include <VBox/vm.h>
34#include <VBox/err.h>
35#include <VBox/param.h>
36#include <VBox/x86.h>
37#include <VBox/hwaccm.h>
38
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/time.h>
42#include <iprt/stream.h>
43#include <iprt/string.h>
44
45
46/**
47 * Performs a testcase.
48 *
49 * @returns return value from the test.
50 * @param pVM The VM handle.
51 * @param enmTestcase The testcase operation to perform.
52 * @param uVariation The testcase variation id.
53 */
54static int vmmR3DoGCTest(PVM pVM, VMMGCOPERATION enmTestcase, unsigned uVariation)
55{
56 PVMCPU pVCpu = &pVM->aCpus[0];
57
58 RTRCPTR RCPtrEP;
59 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
60 if (RT_FAILURE(rc))
61 return rc;
62
63 CPUMHyperSetCtxCore(pVCpu, NULL);
64 memset(pVCpu->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE);
65 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
66 CPUMPushHyper(pVCpu, uVariation);
67 CPUMPushHyper(pVCpu, enmTestcase);
68 CPUMPushHyper(pVCpu, pVM->pVMRC);
69 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
70 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
71 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
72 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
73 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
74 if (RT_LIKELY(rc == VINF_SUCCESS))
75 rc = pVCpu->vmm.s.iLastGZRc;
76 return rc;
77}
78
79
80/**
81 * Performs a trap test.
82 *
83 * @returns Return value from the trap test.
84 * @param pVM The VM handle.
85 * @param u8Trap The trap number to test.
86 * @param uVariation The testcase variation.
87 * @param rcExpect The expected result.
88 * @param u32Eax The expected eax value.
89 * @param pszFaultEIP The fault address. Pass NULL if this isn't available or doesn't apply.
90 * @param pszDesc The test description.
91 */
92static int vmmR3DoTrapTest(PVM pVM, uint8_t u8Trap, unsigned uVariation, int rcExpect, uint32_t u32Eax, const char *pszFaultEIP, const char *pszDesc)
93{
94 PVMCPU pVCpu = &pVM->aCpus[0];
95
96 RTPrintf("VMM: testing 0%x / %d - %s\n", u8Trap, uVariation, pszDesc);
97
98 RTRCPTR RCPtrEP;
99 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
100 if (RT_FAILURE(rc))
101 return rc;
102
103 CPUMHyperSetCtxCore(pVCpu, NULL);
104 memset(pVCpu->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE);
105 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
106 CPUMPushHyper(pVCpu, uVariation);
107 CPUMPushHyper(pVCpu, u8Trap + VMMGC_DO_TESTCASE_TRAP_FIRST);
108 CPUMPushHyper(pVCpu, pVM->pVMRC);
109 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
110 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
111 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
112 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
113 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
114 if (RT_LIKELY(rc == VINF_SUCCESS))
115 rc = pVCpu->vmm.s.iLastGZRc;
116 bool fDump = false;
117 if (rc != rcExpect)
118 {
119 RTPrintf("VMM: FAILURE - rc=%Rrc expected %Rrc\n", rc, rcExpect);
120 if (rc != VERR_NOT_IMPLEMENTED)
121 fDump = true;
122 }
123 else if ( rcExpect != VINF_SUCCESS
124 && u8Trap != 8 /* double fault doesn't dare set TrapNo. */
125 && u8Trap != 3 /* guest only, we're not in guest. */
126 && u8Trap != 1 /* guest only, we're not in guest. */
127 && u8Trap != TRPMGetTrapNo(pVCpu))
128 {
129 RTPrintf("VMM: FAILURE - Trap %#x expected %#x\n", TRPMGetTrapNo(pVCpu), u8Trap);
130 fDump = true;
131 }
132 else if (pszFaultEIP)
133 {
134 RTRCPTR RCPtrFault;
135 int rc2 = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, pszFaultEIP, &RCPtrFault);
136 if (RT_FAILURE(rc2))
137 RTPrintf("VMM: FAILURE - Failed to resolve symbol '%s', %Rrc!\n", pszFaultEIP, rc);
138 else if (RCPtrFault != CPUMGetHyperEIP(pVCpu))
139 {
140 RTPrintf("VMM: FAILURE - EIP=%08RX32 expected %RRv (%s)\n", CPUMGetHyperEIP(pVCpu), RCPtrFault, pszFaultEIP);
141 fDump = true;
142 }
143 }
144 else if (rcExpect != VINF_SUCCESS)
145 {
146 if (CPUMGetHyperSS(pVCpu) == SELMGetHyperDS(pVM))
147 RTPrintf("VMM: FAILURE - ss=%x expected %x\n", CPUMGetHyperSS(pVCpu), SELMGetHyperDS(pVM));
148 if (CPUMGetHyperES(pVCpu) == SELMGetHyperDS(pVM))
149 RTPrintf("VMM: FAILURE - es=%x expected %x\n", CPUMGetHyperES(pVCpu), SELMGetHyperDS(pVM));
150 if (CPUMGetHyperDS(pVCpu) == SELMGetHyperDS(pVM))
151 RTPrintf("VMM: FAILURE - ds=%x expected %x\n", CPUMGetHyperDS(pVCpu), SELMGetHyperDS(pVM));
152 if (CPUMGetHyperFS(pVCpu) == SELMGetHyperDS(pVM))
153 RTPrintf("VMM: FAILURE - fs=%x expected %x\n", CPUMGetHyperFS(pVCpu), SELMGetHyperDS(pVM));
154 if (CPUMGetHyperGS(pVCpu) == SELMGetHyperDS(pVM))
155 RTPrintf("VMM: FAILURE - gs=%x expected %x\n", CPUMGetHyperGS(pVCpu), SELMGetHyperDS(pVM));
156 if (CPUMGetHyperEDI(pVCpu) == 0x01234567)
157 RTPrintf("VMM: FAILURE - edi=%x expected %x\n", CPUMGetHyperEDI(pVCpu), 0x01234567);
158 if (CPUMGetHyperESI(pVCpu) == 0x42000042)
159 RTPrintf("VMM: FAILURE - esi=%x expected %x\n", CPUMGetHyperESI(pVCpu), 0x42000042);
160 if (CPUMGetHyperEBP(pVCpu) == 0xffeeddcc)
161 RTPrintf("VMM: FAILURE - ebp=%x expected %x\n", CPUMGetHyperEBP(pVCpu), 0xffeeddcc);
162 if (CPUMGetHyperEBX(pVCpu) == 0x89abcdef)
163 RTPrintf("VMM: FAILURE - ebx=%x expected %x\n", CPUMGetHyperEBX(pVCpu), 0x89abcdef);
164 if (CPUMGetHyperECX(pVCpu) == 0xffffaaaa)
165 RTPrintf("VMM: FAILURE - ecx=%x expected %x\n", CPUMGetHyperECX(pVCpu), 0xffffaaaa);
166 if (CPUMGetHyperEDX(pVCpu) == 0x77778888)
167 RTPrintf("VMM: FAILURE - edx=%x expected %x\n", CPUMGetHyperEDX(pVCpu), 0x77778888);
168 if (CPUMGetHyperEAX(pVCpu) == u32Eax)
169 RTPrintf("VMM: FAILURE - eax=%x expected %x\n", CPUMGetHyperEAX(pVCpu), u32Eax);
170 }
171 if (fDump)
172 VMMR3FatalDump(pVM, pVCpu, rc);
173 return rc;
174}
175
176
177/* execute the switch. */
178VMMR3DECL(int) VMMDoTest(PVM pVM)
179{
180#if 1
181 PVMCPU pVCpu = &pVM->aCpus[0];
182
183#ifdef NO_SUPCALLR0VMM
184 RTPrintf("NO_SUPCALLR0VMM\n");
185 return VINF_SUCCESS;
186#endif
187
188 /*
189 * Setup stack for calling VMMGCEntry().
190 */
191 RTRCPTR RCPtrEP;
192 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
193 if (RT_SUCCESS(rc))
194 {
195 RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
196
197 /*
198 * Test various crashes which we must be able to recover from.
199 */
200 vmmR3DoTrapTest(pVM, 0x3, 0, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3");
201 vmmR3DoTrapTest(pVM, 0x3, 1, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3 WP");
202
203#if defined(DEBUG_bird) /* guess most people would like to skip these since they write to com1. */
204 vmmR3DoTrapTest(pVM, 0x8, 0, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG]");
205 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
206 bool f;
207 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "DoubleFault", &f);
208#if !defined(DEBUG_bird)
209 if (RT_SUCCESS(rc) && f)
210#endif
211 {
212 /* see tripple fault warnings in SELM and VMMGC.cpp. */
213 vmmR3DoTrapTest(pVM, 0x8, 1, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG] WP");
214 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
215 }
216#endif
217
218 vmmR3DoTrapTest(pVM, 0xd, 0, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP");
219 ///@todo find a better \#GP case, on intel ltr will \#PF (busy update?) and not \#GP.
220 //vmmR3DoTrapTest(pVM, 0xd, 1, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP WP");
221
222 vmmR3DoTrapTest(pVM, 0xe, 0, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL)");
223 vmmR3DoTrapTest(pVM, 0xe, 1, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL) WP");
224 vmmR3DoTrapTest(pVM, 0xe, 2, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler");
225 vmmR3DoTrapTest(pVM, 0xe, 4, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler and bad fs");
226
227 /*
228 * Set a debug register and perform a context switch.
229 */
230 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
231 if (rc != VINF_SUCCESS)
232 {
233 RTPrintf("VMM: Nop test failed, rc=%Rrc not VINF_SUCCESS\n", rc);
234 return rc;
235 }
236
237 /* a harmless breakpoint */
238 RTPrintf("VMM: testing hardware bp at 0x10000 (not hit)\n");
239 DBGFADDRESS Addr;
240 DBGFR3AddrFromFlat(pVM, &Addr, 0x10000);
241 RTUINT iBp0;
242 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp0);
243 AssertReleaseRC(rc);
244 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
245 if (rc != VINF_SUCCESS)
246 {
247 RTPrintf("VMM: DR0=0x10000 test failed with rc=%Rrc!\n", rc);
248 return rc;
249 }
250
251 /* a bad one at VMMGCEntry */
252 RTPrintf("VMM: testing hardware bp at VMMGCEntry (hit)\n");
253 DBGFR3AddrFromFlat(pVM, &Addr, RCPtrEP);
254 RTUINT iBp1;
255 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp1);
256 AssertReleaseRC(rc);
257 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
258 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
259 {
260 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
261 return rc;
262 }
263
264 /* resume the breakpoint */
265 RTPrintf("VMM: resuming hyper after breakpoint\n");
266 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
267 rc = VMMR3ResumeHyper(pVM, pVCpu);
268 if (rc != VINF_SUCCESS)
269 {
270 RTPrintf("VMM: failed to resume on hyper breakpoint, rc=%Rrc\n", rc);
271 return rc;
272 }
273
274 /* engage the breakpoint again and try single stepping. */
275 RTPrintf("VMM: testing hardware bp at VMMGCEntry + stepping\n");
276 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
277 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
278 {
279 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
280 return rc;
281 }
282
283 RTGCUINTREG OldPc = CPUMGetHyperEIP(pVCpu);
284 RTPrintf("%RGr=>", OldPc);
285 unsigned i;
286 for (i = 0; i < 8; i++)
287 {
288 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
289 rc = VMMR3ResumeHyper(pVM, pVCpu);
290 if (rc != VINF_EM_DBG_HYPER_STEPPED)
291 {
292 RTPrintf("\nVMM: failed to step on hyper breakpoint, rc=%Rrc\n", rc);
293 return rc;
294 }
295 RTGCUINTREG Pc = CPUMGetHyperEIP(pVCpu);
296 RTPrintf("%RGr=>", Pc);
297 if (Pc == OldPc)
298 {
299 RTPrintf("\nVMM: step failed, PC: %RGr -> %RGr\n", OldPc, Pc);
300 return VERR_GENERAL_FAILURE;
301 }
302 OldPc = Pc;
303 }
304 RTPrintf("ok\n");
305
306 /* done, clear it */
307 if ( RT_FAILURE(DBGFR3BpClear(pVM, iBp0))
308 || RT_FAILURE(DBGFR3BpClear(pVM, iBp1)))
309 {
310 RTPrintf("VMM: Failed to clear breakpoints!\n");
311 return VERR_GENERAL_FAILURE;
312 }
313 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
314 if (rc != VINF_SUCCESS)
315 {
316 RTPrintf("VMM: NOP failed, rc=%Rrc\n", rc);
317 return rc;
318 }
319
320 /*
321 * Interrupt masking.
322 */
323 RTPrintf("VMM: interrupt masking...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
324 for (i = 0; i < 10000; i++)
325 {
326 uint64_t StartTick = ASMReadTSC();
327 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_INTERRUPT_MASKING, 0);
328 if (rc != VINF_SUCCESS)
329 {
330 RTPrintf("VMM: Interrupt masking failed: rc=%Rrc\n", rc);
331 return rc;
332 }
333 uint64_t Ticks = ASMReadTSC() - StartTick;
334 if (Ticks < (SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000))
335 RTPrintf("Warning: Ticks=%RU64 (< %RU64)\n", Ticks, SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000);
336 }
337
338 /*
339 * Interrupt forwarding.
340 */
341 CPUMHyperSetCtxCore(pVCpu, NULL);
342 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
343 CPUMPushHyper(pVCpu, 0);
344 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HYPER_INTERRUPT);
345 CPUMPushHyper(pVCpu, pVM->pVMRC);
346 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
347 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
348 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
349 Log(("trampoline=%x\n", pVM->vmm.s.pfnCallTrampolineRC));
350
351 /*
352 * Switch and do da thing.
353 */
354 RTPrintf("VMM: interrupt forwarding...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
355 i = 0;
356 uint64_t tsBegin = RTTimeNanoTS();
357 uint64_t TickStart = ASMReadTSC();
358 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
359 do
360 {
361 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
362 if (RT_LIKELY(rc == VINF_SUCCESS))
363 rc = pVCpu->vmm.s.iLastGZRc;
364 if (RT_FAILURE(rc))
365 {
366 Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
367 VMMR3FatalDump(pVM, pVCpu, rc);
368 return rc;
369 }
370 i++;
371 if (!(i % 32))
372 Log(("VMM: iteration %d, esi=%08x edi=%08x ebx=%08x\n",
373 i, CPUMGetHyperESI(pVCpu), CPUMGetHyperEDI(pVCpu), CPUMGetHyperEBX(pVCpu)));
374 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
375 uint64_t TickEnd = ASMReadTSC();
376 uint64_t tsEnd = RTTimeNanoTS();
377
378 uint64_t Elapsed = tsEnd - tsBegin;
379 uint64_t PerIteration = Elapsed / (uint64_t)i;
380 uint64_t cTicksElapsed = TickEnd - TickStart;
381 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
382
383 RTPrintf("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
384 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration);
385 Log(("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
386 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration));
387
388 /*
389 * These forced actions are not necessary for the test and trigger breakpoints too.
390 */
391 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
392 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
393
394 /*
395 * Profile switching.
396 */
397 RTPrintf("VMM: profiling switcher...\n");
398 Log(("VMM: profiling switcher...\n"));
399 uint64_t TickMin = ~0;
400 tsBegin = RTTimeNanoTS();
401 TickStart = ASMReadTSC();
402 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
403 for (i = 0; i < 1000000; i++)
404 {
405 CPUMHyperSetCtxCore(pVCpu, NULL);
406 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
407 CPUMPushHyper(pVCpu, 0);
408 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_NOP);
409 CPUMPushHyper(pVCpu, pVM->pVMRC);
410 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
411 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
412 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
413
414 uint64_t TickThisStart = ASMReadTSC();
415 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
416 if (RT_LIKELY(rc == VINF_SUCCESS))
417 rc = pVCpu->vmm.s.iLastGZRc;
418 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
419 if (RT_FAILURE(rc))
420 {
421 Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
422 VMMR3FatalDump(pVM, pVCpu, rc);
423 return rc;
424 }
425 if (TickThisElapsed < TickMin)
426 TickMin = TickThisElapsed;
427 }
428 TickEnd = ASMReadTSC();
429 tsEnd = RTTimeNanoTS();
430
431 Elapsed = tsEnd - tsBegin;
432 PerIteration = Elapsed / (uint64_t)i;
433 cTicksElapsed = TickEnd - TickStart;
434 cTicksPerIteration = cTicksElapsed / (uint64_t)i;
435
436 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
437 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
438 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
439 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
440
441 rc = VINF_SUCCESS;
442 }
443 else
444 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
445#endif
446 return rc;
447}
448
449#define SYNC_SEL(pHyperCtx, reg) \
450 if (pHyperCtx->reg) \
451 { \
452 DBGFSELINFO selInfo; \
453 int rc2 = SELMR3GetShadowSelectorInfo(pVM, pHyperCtx->reg, &selInfo); \
454 AssertRC(rc2); \
455 \
456 pHyperCtx->reg##Hid.u64Base = selInfo.GCPtrBase; \
457 pHyperCtx->reg##Hid.u32Limit = selInfo.cbLimit; \
458 pHyperCtx->reg##Hid.Attr.n.u1Present = selInfo.u.Raw.Gen.u1Present; \
459 pHyperCtx->reg##Hid.Attr.n.u1DefBig = selInfo.u.Raw.Gen.u1DefBig; \
460 pHyperCtx->reg##Hid.Attr.n.u1Granularity = selInfo.u.Raw.Gen.u1Granularity; \
461 pHyperCtx->reg##Hid.Attr.n.u4Type = selInfo.u.Raw.Gen.u4Type; \
462 pHyperCtx->reg##Hid.Attr.n.u2Dpl = selInfo.u.Raw.Gen.u2Dpl; \
463 pHyperCtx->reg##Hid.Attr.n.u1DescType = selInfo.u.Raw.Gen.u1DescType; \
464 pHyperCtx->reg##Hid.Attr.n.u1Long = selInfo.u.Raw.Gen.u1Long; \
465 }
466
467/* execute the switch. */
468VMMR3DECL(int) VMMDoHwAccmTest(PVM pVM)
469{
470 uint32_t i;
471 int rc;
472 PCPUMCTX pHyperCtx, pGuestCtx;
473 RTGCPHYS CR3Phys = 0x0; /* fake address */
474 PVMCPU pVCpu = &pVM->aCpus[0];
475
476 if (!HWACCMR3IsAllowed(pVM))
477 {
478 RTPrintf("VMM: Hardware accelerated test not available!\n");
479 return VERR_ACCESS_DENIED;
480 }
481
482 /*
483 * These forced actions are not necessary for the test and trigger breakpoints too.
484 */
485 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
486 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
487
488 /* Enable mapping of the hypervisor into the shadow page table. */
489 uint32_t cb;
490 rc = PGMR3MappingsSize(pVM, &cb);
491 AssertRCReturn(rc, rc);
492
493 /* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
494 rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
495 AssertRCReturn(rc, rc);
496
497 CPUMQueryHyperCtxPtr(pVCpu, &pHyperCtx);
498
499 pHyperCtx->cr0 = X86_CR0_PE | X86_CR0_WP | X86_CR0_PG | X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
500 pHyperCtx->cr4 = X86_CR4_PGE | X86_CR4_OSFSXR | X86_CR4_OSXMMEEXCPT;
501 PGMChangeMode(pVCpu, pHyperCtx->cr0, pHyperCtx->cr4, pHyperCtx->msrEFER);
502 PGMSyncCR3(pVCpu, pHyperCtx->cr0, CR3Phys, pHyperCtx->cr4, true);
503
504 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
505 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
506 VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
507 VM_FF_CLEAR(pVM, VM_FF_REQUEST);
508
509 /*
510 * Setup stack for calling VMMGCEntry().
511 */
512 RTRCPTR RCPtrEP;
513 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
514 if (RT_SUCCESS(rc))
515 {
516 RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
517
518 CPUMQueryHyperCtxPtr(pVCpu, &pHyperCtx);
519
520 /* Fill in hidden selector registers for the hypervisor state. */
521 SYNC_SEL(pHyperCtx, cs);
522 SYNC_SEL(pHyperCtx, ds);
523 SYNC_SEL(pHyperCtx, es);
524 SYNC_SEL(pHyperCtx, fs);
525 SYNC_SEL(pHyperCtx, gs);
526 SYNC_SEL(pHyperCtx, ss);
527 SYNC_SEL(pHyperCtx, tr);
528
529 /*
530 * Profile switching.
531 */
532 RTPrintf("VMM: profiling switcher...\n");
533 Log(("VMM: profiling switcher...\n"));
534 uint64_t TickMin = ~0;
535 uint64_t tsBegin = RTTimeNanoTS();
536 uint64_t TickStart = ASMReadTSC();
537 for (i = 0; i < 1000000; i++)
538 {
539 CPUMHyperSetCtxCore(pVCpu, NULL);
540
541 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
542 CPUMPushHyper(pVCpu, 0);
543 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HWACCM_NOP);
544 CPUMPushHyper(pVCpu, pVM->pVMRC);
545 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
546 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
547 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
548
549 CPUMQueryHyperCtxPtr(pVCpu, &pHyperCtx);
550 pGuestCtx = CPUMQueryGuestCtxPtr(pVCpu);
551
552 /* Copy the hypervisor context to make sure we have a valid guest context. */
553 *pGuestCtx = *pHyperCtx;
554 pGuestCtx->cr3 = CR3Phys;
555
556 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
557 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
558 VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
559
560 uint64_t TickThisStart = ASMReadTSC();
561 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN, 0);
562 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
563 if (RT_FAILURE(rc))
564 {
565 Log(("VMM: R0 returned fatal %Rrc in iteration %d\n", rc, i));
566 VMMR3FatalDump(pVM, pVCpu, rc);
567 return rc;
568 }
569 if (TickThisElapsed < TickMin)
570 TickMin = TickThisElapsed;
571 }
572 uint64_t TickEnd = ASMReadTSC();
573 uint64_t tsEnd = RTTimeNanoTS();
574
575 uint64_t Elapsed = tsEnd - tsBegin;
576 uint64_t PerIteration = Elapsed / (uint64_t)i;
577 uint64_t cTicksElapsed = TickEnd - TickStart;
578 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
579
580 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
581 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
582 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
583 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
584
585 rc = VINF_SUCCESS;
586 }
587 else
588 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
589
590 return rc;
591}
592
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